2 /* From: NetBSD: alpha_cpu.h,v 1.15 1997/09/20 19:02:34 mjacob Exp */
5 * Copyright (c) 1996 Carnegie-Mellon University.
8 * Author: Chris G. Demetriou
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
20 * Carnegie Mellon requests users of this software to return to
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
31 #ifndef __ALPHA_ALPHA_CPU_H__
32 #define __ALPHA_ALPHA_CPU_H__
35 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
39 * Process Control Block
40 * Interrupt/Exception/Syscall Stack Frame
41 * Processor Status Register
42 * Machine Check Error Summary Register
43 * Machine Check Logout Area
44 * Virtual Memory Management
45 * Kernel Entry Vectors
46 * MMCSR Fault Type Codes
47 * Translation Buffer Invalidation
49 * and miscellaneous PALcode operations.
54 * Process Control Block definitions [OSF/1 PALcode Specific]
58 unsigned long apcb_ksp; /* kernel stack ptr */
59 unsigned long apcb_usp; /* user stack ptr */
60 unsigned long apcb_ptbr; /* page table base reg */
61 unsigned int apcb_cpc; /* charged process cycles */
62 unsigned int apcb_asn; /* address space number */
63 unsigned long apcb_unique; /* process unique value */
64 unsigned long apcb_flags; /* flags; see below */
65 unsigned long apcb_decrsv0; /* DEC reserved */
66 unsigned long apcb_decrsv1; /* DEC reserved */
69 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001
70 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000
73 * Interrupt/Exception/Syscall "Hardware" (really PALcode)
74 * Stack Frame definitions
76 * These are quadword offsets from the sp on kernel entry, i.e.
77 * to get to the value in question you access (sp + (offset * 8)).
79 * On syscall entry, A0-A2 aren't written to memory but space
80 * _is_ reserved for them.
83 #define ALPHA_HWFRAME_PS 0 /* processor status register */
84 #define ALPHA_HWFRAME_PC 1 /* program counter */
85 #define ALPHA_HWFRAME_GP 2 /* global pointer */
86 #define ALPHA_HWFRAME_A0 3 /* a0 */
87 #define ALPHA_HWFRAME_A1 4 /* a1 */
88 #define ALPHA_HWFRAME_A2 5 /* a2 */
90 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */
93 * Processor Status Register [OSF/1 PALcode Specific]
95 * Includes user/kernel mode bit, interrupt priority levels, etc.
98 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */
99 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */
101 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */
102 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */
103 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */
104 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */
105 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */
107 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
109 /* Convenience constants: what must be set/clear in user mode */
110 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE
111 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
114 * Interrupt Type Code Definitions [OSF/1 PALcode Specific]
117 #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */
118 #define ALPHA_INTR_CLOCK 1 /* clock interrupt */
119 #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */
120 #define ALPHA_INTR_DEVICE 3 /* device interrupt */
121 #define ALPHA_INTR_PERF 4 /* performance counter */
122 #define ALPHA_INTR_PASSIVE 5 /* passive release */
125 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
127 * The following bits are values as read. On write, _PCE, _SCE, and
128 * _MIP are "write 1 to clear."
131 #define ALPHA_MCES_IMP \
132 0xffffffff00000000 /* impl. dependent */
133 #define ALPHA_MCES_RSVD \
134 0x00000000ffffffe0 /* reserved */
135 #define ALPHA_MCES_DSC \
136 0x0000000000000010 /* disable system correctable error reporting */
137 #define ALPHA_MCES_DPC \
138 0x0000000000000008 /* disable processor correctable error reporting */
139 #define ALPHA_MCES_PCE \
140 0x0000000000000004 /* processor correctable error in progress */
141 #define ALPHA_MCES_SCE \
142 0x0000000000000002 /* system correctable error in progress */
143 #define ALPHA_MCES_MIP \
144 0x0000000000000001 /* machine check in progress */
147 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
150 struct alpha_logout_area {
151 unsigned int la_frame_size; /* frame size */
152 unsigned int la_flags; /* flags; see below */
153 unsigned int la_cpu_offset; /* offset to cpu area */
154 unsigned int la_system_offset; /* offset to system area */
157 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */
158 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */
159 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */
161 #define ALPHA_LOGOUT_NOT_BUILT \
162 (struct alpha_logout_area *)0xffffffffffffffff)
164 #define ALPHA_LOGOUT_PAL_AREA(lap) \
165 (unsigned long *)((unsigned char *)(lap) + 16)
166 #define ALPHA_LOGOUT_PAL_SIZE(lap) \
167 ((lap)->la_cpu_offset - 16)
168 #define ALPHA_LOGOUT_CPU_AREA(lap) \
169 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
170 #define ALPHA_LOGOUT_CPU_SIZE(lap) \
171 ((lap)->la_system_offset - (lap)->la_cpu_offset)
172 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \
173 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
174 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \
175 ((lap)->la_frame_size - (lap)->la_system_offset)
178 * Virtual Memory Management definitions [OSF/1 PALcode Specific]
180 * Includes user and kernel space addresses and information,
181 * page table entry definitions, etc.
183 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
186 #define ALPHA_PGSHIFT 13 /* bits that index within page */
187 #define ALPHA_PTSHIFT 10 /* bits that index within page tables */
188 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT)
189 #define ALPHA_L3SHIFT ALPHA_PGSHIFT
190 #define ALPHA_L2SHIFT (ALPHA_L3SHIFT+ALPHA_PTSHIFT)
191 #define ALPHA_L1SHIFT (ALPHA_L2SHIFT+ALPHA_PTSHIFT)
193 #define ALPHA_USEG_BASE 0 /* virtual */
194 #define ALPHA_USEG_END 0x000003ffffffffffLL
196 #define ALPHA_K0SEG_BASE 0xfffffc0000000000LL /* direct-mapped */
197 #define ALPHA_K0SEG_END 0xfffffdffffffffffLL
198 #define ALPHA_K1SEG_BASE 0xfffffe0000000000LL /* virtual */
199 #define ALPHA_K1SEG_END 0xffffffffffffffffLL
201 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE)
202 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE)
204 #define ALPHA_PTE_VALID 0x0001
206 #define ALPHA_PTE_FAULT_ON_READ 0x0002
207 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004
208 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008
210 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */
211 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */
213 #define ALPHA_PTE_PROT 0xff00
214 #define ALPHA_PTE_KR 0x0100
215 #define ALPHA_PTE_UR 0x0200
216 #define ALPHA_PTE_KW 0x1000
217 #define ALPHA_PTE_UW 0x2000
219 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW)
221 #define ALPHA_PTE_SOFTWARE 0xffff0000
223 #define ALPHA_PTE_PFN 0xffffffff00000000
225 #define ALPHA_PTE_TO_PFN(pte) ((u_long)(pte) >> 32)
226 #define ALPHA_PTE_FROM_PFN(pfn) ((u_long)(pfn) << 32)
228 typedef unsigned long alpha_pt_entry_t;
231 * Kernel Entry Vectors. [OSF/1 PALcode Specific]
234 #define ALPHA_KENTRY_INT 0
235 #define ALPHA_KENTRY_ARITH 1
236 #define ALPHA_KENTRY_MM 2
237 #define ALPHA_KENTRY_IF 3
238 #define ALPHA_KENTRY_UNA 4
239 #define ALPHA_KENTRY_SYS 5
242 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
245 #define ALPHA_MMCSR_INVALTRANS 0
246 #define ALPHA_MMCSR_ACCESS 1
247 #define ALPHA_MMCSR_FOR 2
248 #define ALPHA_MMCSR_FOE 3
249 #define ALPHA_MMCSR_FOW 4
252 * Instruction Fault Type Codes. [OSF/1 PALcode Specific]
255 #define ALPHA_IF_CODE_BPT 0
256 #define ALPHA_IF_CODE_BUGCHK 1
257 #define ALPHA_IF_CODE_GENTRAP 2
258 #define ALPHA_IF_CODE_FEN 3
259 #define ALPHA_IF_CODE_OPDEC 4
262 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
265 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */
266 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */
267 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */
268 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */
269 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */
272 * Bits used in the amask instruction [EV56 and later]
275 #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */
276 #define ALPHA_AMASK_FIX 0x0002 /* sqrt and f <-> i conversion extension */
277 #define ALPHA_AMASK_CIX 0x0004 /* count extension */
278 #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */
279 #define ALPHA_AMASK_PRECISE 0x0200 /* Precise arithmetic traps */
282 * Chip family IDs returned by implver instruction
285 #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */
286 #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */
287 #define ALPHA_IMPLVER_EV6 2 /* EV6 */
291 * Stubs for Alpha instructions normally inaccessible from C.
293 unsigned long alpha_amask __P((unsigned long));
294 unsigned long alpha_implver __P((void));
295 unsigned long alpha_rpcc __P((void));
296 void alpha_mb __P((void));
297 void alpha_wmb __P((void));
299 u_int8_t alpha_ldbu __P((volatile u_int8_t *));
300 u_int16_t alpha_ldwu __P((volatile u_int16_t *));
301 void alpha_stb __P((volatile u_int8_t *, u_int8_t));
302 void alpha_stw __P((volatile u_int16_t *, u_int16_t));
303 u_int8_t alpha_sextb __P((u_int8_t));
304 u_int16_t alpha_sextw __P((u_int16_t));
307 * Stubs for OSF/1 PALcode operations.
309 void alpha_pal_imb __P((void));
310 void alpha_pal_cflush __P((unsigned long));
311 void alpha_pal_draina __P((void));
312 void alpha_pal_halt __P((void)) __attribute__((__noreturn__));
313 unsigned long alpha_pal_rdmces __P((void));
314 unsigned long alpha_pal_rdps __P((void));
315 unsigned long alpha_pal_rdusp __P((void));
316 unsigned long alpha_pal_rdval __P((void));
317 unsigned long alpha_pal_swpctx __P((unsigned long));
318 unsigned long alpha_pal_swpipl __P((unsigned long));
319 unsigned long _alpha_pal_swpipl __P((unsigned long)); /* for profiling */
320 void alpha_pal_tbi __P((unsigned long, vm_offset_t));
321 unsigned long alpha_pal_whami __P((void));
322 void alpha_pal_wrent __P((void *, unsigned long));
323 void alpha_pal_wrfen __P((unsigned long));
324 void alpha_pal_wripir __P((unsigned long));
325 void alpha_pal_wrusp __P((unsigned long));
326 void alpha_pal_wrvptptr __P((unsigned long));
327 void alpha_pal_wrmces __P((unsigned long));
328 void alpha_pal_wrval __P((unsigned long));
329 unsigned long alpha_pal_wrperfmon __P((unsigned long, unsigned long));
331 #endif /* __ALPHA_ALPHA_CPU_H__ */