2 /* $NetBSD: ciareg.h,v 1.22 1998/06/06 20:40:14 thorpej Exp $ */
5 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
8 * Authors: Chris G. Demetriou, Jason R. Thorpe
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
20 * Carnegie Mellon requests users of this software to return to
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
32 * 21171 Chipset registers and constants.
34 * Taken from EC-QE18B-TE.
37 #define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
38 #define REGVAL64(r) (*(volatile u_int64_t *)ALPHA_PHYS_TO_K0SEG(r))
43 #define CIA_PCI_SMEM1 0x8000000000UL
44 #define CIA_PCI_SMEM2 0x8400000000UL
45 #define CIA_PCI_SMEM3 0x8500000000UL
46 #define CIA_PCI_SIO1 0x8580000000UL
47 #define CIA_PCI_SIO2 0x85c0000000UL
48 #define CIA_PCI_DENSE 0x8600000000UL
49 #define CIA_PCI_CONF 0x8700000000UL
50 #define CIA_PCI_IACK 0x8720000000UL
51 #define CIA_CSRS 0x8740000000UL
52 #define CIA_PCI_MC_CSRS 0x8750000000UL
53 #define CIA_PCI_ATRANS 0x8760000000UL
54 #define CIA_PCI_TBIA 0x8760000100UL
55 #define CIA_EV56_BWMEM 0x8800000000UL
56 #define CIA_EV56_BWIO 0x8900000000UL
57 #define CIA_EV56_BWCONF0 0x8a00000000UL
58 #define CIA_EV56_BWCONF1 0x8b00000000UL
60 #define CIA_PCI_W0BASE 0x8760000400UL
61 #define CIA_PCI_W0MASK 0x8760000440UL
62 #define CIA_PCI_T0BASE 0x8760000480UL
64 #define CIA_PCI_W1BASE 0x8760000500UL
65 #define CIA_PCI_W1MASK 0x8760000540UL
66 #define CIA_PCI_T1BASE 0x8760000580UL
68 #define CIA_PCI_W2BASE 0x8760000600UL
69 #define CIA_PCI_W2MASK 0x8760000640UL
70 #define CIA_PCI_T2BASE 0x8760000680UL
72 #define CIA_PCI_W3BASE 0x8760000700UL
73 #define CIA_PCI_W3MASK 0x8760000740UL
74 #define CIA_PCI_T3BASE 0x8760000780UL
76 #define PYXIS_INT_REQ 0x87a0000000UL
77 #define PYXIS_INT_MASK 0x87a0000040UL
78 #define PYXIS_GPO 0x87a0000180UL
81 * Values for CIA_PCI_TBIA
83 #define CIA_PCI_TBIA_NOOP 0 /* no operation */
84 #define CIA_PCI_TBIA_LOCKED 1 /* invalidate and unlock locked tags */
85 #define CIA_PCI_TBIA_UNLOCKED 2 /* invalidate unlocked tags */
86 #define CIA_PCI_TBIA_ALL 3 /* invalidate and unlock all tags */
88 #define CIA_TLB_NTAGS 8 /* number of TLB entries */
91 * Values for CIA_PCI_WnBASE
93 #define CIA_PCI_WnBASE_W_BASE 0xfff00000
94 #define CIA_PCI_WnBASE_DAC_EN 0x00000008 /* W3BASE only */
95 #define CIA_PCI_WnBASE_MEMCS_EN 0x00000004 /* W0BASE only */
96 #define CIA_PCI_WnBASE_SG_EN 0x00000002
97 #define CIA_PCI_WnBASE_W_EN 0x00000001
100 * Values for CIA_PCI_WnMASK
102 #define CIA_PCI_WnMASK_W_MASK 0xfff00000
103 #define CIA_PCI_WnMASK_1M 0x00000000
104 #define CIA_PCI_WnMASK_2M 0x00100000
105 #define CIA_PCI_WnMASK_4M 0x00300000
106 #define CIA_PCI_WnMASK_8M 0x00700000
107 #define CIA_PCI_WnMASK_16M 0x00f00000
108 #define CIA_PCI_WnMASK_32M 0x01f00000
109 #define CIA_PCI_WnMASK_64M 0x03f00000
110 #define CIA_PCI_WnMASK_128M 0x07f00000
111 #define CIA_PCI_WnMASK_256M 0x0ff00000
112 #define CIA_PCI_WnMASK_512M 0x1ff00000
113 #define CIA_PCI_WnMASK_1G 0x3ff00000
114 #define CIA_PCI_WnMASK_2G 0x7ff00000
115 #define CIA_PCI_WnMASK_4G 0xfff00000
118 * Values for CIA_PCI_TnBASE
120 #define CIA_PCI_TnBASE_MASK 0xfffffff0
121 #define CIA_PCI_TnBASE_SHIFT 2
127 #define CIA_CSR_REV (CIA_CSRS + 0x80)
129 #define REV_MASK 0x000000ff
130 #define REV_ALT_MEM 0x00000100 /* not on Pyxis */
132 #define REV_PYXIS_ID_MASK 0x0000ff00
133 #define REV_PYXIS_ID_21174 0x00000100
135 #define CIA_CSR_CTRL (CIA_CSRS + 0x100)
137 #define CTRL_RCI_EN 0x00000001
138 #define CTRL_PCI_LOCK_EN 0x00000002
139 #define CTRL_PCI_LOOP_EN 0x00000004
140 #define CTRL_FST_BB_EN 0x00000008
141 #define CTRL_PCI_MST_EN 0x00000010
142 #define CTRL_PCI_MEM_EN 0x00000020
143 #define CTRL_PCI_REQ64_EN 0x00000040
144 #define CTRL_PCI_ACK64_EN 0x00000080
145 #define CTRL_ADDR_PE_EN 0x00000100
146 #define CTRL_PERR_EN 0x00000200
147 #define CTRL_FILL_ERR_EN 0x00000400
148 #define CTRL_ECC_CHK_EN 0x00001000
149 #define CTRL_CACK_EN_PE 0x00002000
150 #define CTRL_CON_IDLE_BC 0x00004000
151 #define CTRL_CSR_IOA_BYPASS 0x00008000
152 #define CTRL_IO_FLUSHREQ_EN 0x00010000
153 #define CTRL_CPU_CLUSHREQ_EN 0x00020000
154 #define CTRL_ARB_EV5_EN 0x00040000
155 #define CTRL_EN_ARB_LINK 0x00080000
156 #define CTRL_RD_TYPE 0x00300000
157 #define CTRL_RL_TYPE 0x03000000
158 #define CTRL_RM_TYPE 0x30000000
160 /* a.k.a. CIA_CSR_PYXIS_CTRL1 */
161 #define CIA_CSR_CNFG (CIA_CSRS + 0x140)
163 #define CNFG_BWEN 0x00000001
164 #define CNFG_MWEN 0x00000010
165 #define CNFG_DWEN 0x00000020
166 #define CNFG_WLEN 0x00000100
168 #define CIA_CSR_CNFG_BITS "\20\11WLEN\6DWEN\5MWEN\1BWEN"
170 #define CIA_CSR_HAE_MEM (CIA_CSRS + 0x400)
172 #define HAE_MEM_REG1_START(x) (((u_int32_t)(x) & 0xe0000000UL) << 0)
173 #define HAE_MEM_REG1_MASK 0x1fffffffUL
174 #define HAE_MEM_REG2_START(x) (((u_int32_t)(x) & 0x0000f800UL) << 16)
175 #define HAE_MEM_REG2_MASK 0x07ffffffUL
176 #define HAE_MEM_REG3_START(x) (((u_int32_t)(x) & 0x000000fcUL) << 24)
177 #define HAE_MEM_REG3_MASK 0x03ffffffUL
179 #define CIA_CSR_HAE_IO (CIA_CSRS + 0x440)
181 #define HAE_IO_REG1_START(x) 0UL
182 #define HAE_IO_REG1_MASK 0x01ffffffUL
183 #define HAE_IO_REG2_START(x) (((u_int32_t)(x) & 0xfe000000UL) << 0)
184 #define HAE_IO_REG2_MASK 0x01ffffffUL
186 #define CIA_CSR_CFG (CIA_CSRS + 0x480)
188 #define CFG_CFG_MASK 0x00000003UL
190 #define CIA_CSR_CIA_ERR (CIA_CSRS + 0x8200)
192 #define CIA_ERR_COR_ERR 0x00000001
193 #define CIA_ERR_UN_COR_ERR 0x00000002
194 #define CIA_ERR_CPU_PE 0x00000004
195 #define CIA_ERR_MEM_NEM 0x00000008
196 #define CIA_ERR_PCI_SERR 0x00000010
197 #define CIA_ERR_PERR 0x00000020
198 #define CIA_ERR_PCI_ADDR_PE 0x00000040
199 #define CIA_ERR_RCVD_MAS_ABT 0x00000080
200 #define CIA_ERR_RCVD_TAR_ABT 0x00000100
201 #define CIA_ERR_PA_PTE_INV 0x00000200
202 #define CIA_ERR_FROM_WRT_ERR 0x00000400
203 #define CIA_ERR_IOA_TIMEOUT 0x00000800
204 #define CIA_ERR_LOST_COR_ERR 0x00010000
205 #define CIA_ERR_LOST_UN_COR_ERR 0x00020000
206 #define CIA_ERR_LOST_CPU_PE 0x00040000
207 #define CIA_ERR_LOST_MEM_NEM 0x00080000
208 #define CIA_ERR_LOST_PERR 0x00200000
209 #define CIA_ERR_LOST_PCI_ADDR_PE 0x00400000
210 #define CIA_ERR_LOST_RCVD_MAS_ABT 0x00800000
211 #define CIA_ERR_LOST_RCVD_TAR_ABT 0x01000000
212 #define CIA_ERR_LOST_PA_PTE_INV 0x02000000
213 #define CIA_ERR_LOST_FROM_WRT_ERR 0x04000000
214 #define CIA_ERR_LOST_IOA_TIMEOUT 0x08000000
215 #define CIA_ERR_VALID 0x80000000