2 * Copyright (c) 2000 Andrew Gallatin & Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Portions of this file were obtained from Compaq intellectual
27 * property which was made available under the following copyright:
29 * *****************************************************************
31 * * Copyright Compaq Computer Corporation, 2000 *
33 * * Permission to use, copy, modify, distribute, and sell *
34 * * this software and its documentation for any purpose is *
35 * * hereby granted without fee, provided that the above *
36 * * copyright notice appear in all copies and that both *
37 * * that copyright notice and this permission notice appear *
38 * * in supporting documentation, and that the name of *
39 * * Compaq Computer Corporation not be used in advertising *
40 * * or publicity pertaining to distribution of the software *
41 * * without specific, written prior permission. Compaq *
42 * * makes no representations about the suitability of this *
43 * * software for any purpose. It is provided "AS IS" *
44 * * without express or implied warranty. *
46 * *****************************************************************
52 * T2 CBUS to PCI bridge
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/kernel.h>
58 #include <sys/module.h>
59 #include <sys/malloc.h>
61 #include <machine/bus.h>
64 #include <sys/interrupt.h>
66 #include <alpha/pci/t2reg.h>
67 #include <alpha/pci/t2var.h>
68 #include <alpha/isa/isavar.h>
69 #include <machine/intr.h>
70 #include <machine/resource.h>
71 #include <machine/intrcnt.h>
72 #include <machine/cpuconf.h>
73 #include <machine/swiz.h>
74 #include <machine/sgmap.h>
75 #include <pci/pcivar.h>
78 #include <vm/vm_page.h>
80 #define KV(pa) ALPHA_PHYS_TO_K0SEG(pa + sable_lynx_base)
82 vm_offset_t sable_lynx_base = 0UL;
84 volatile t2_csr_t *t2_csr[2];
85 static int pci_int_type[2];
87 static devclass_t t2_devclass;
88 static device_t t2_0; /* XXX only one for now */
94 #define T2_SOFTC(dev) (struct t2_softc*) device_get_softc(dev)
96 static alpha_chipset_read_hae_t t2_read_hae;
97 static alpha_chipset_write_hae_t t2_write_hae;
99 static alpha_chipset_t t2_chipset = {
104 static u_int32_t t2_hae_mem[2];
106 #define REG1 (1UL << 24)
109 t2_set_hae_mem(void *arg, u_int32_t pa)
118 msb = pa & 0xf8000000;
120 msb >>= 27; /* t2 puts high bits in the bottom of the register */
121 s = cpu_critical_enter();
122 if (msb != t2_hae_mem[hose]) {
123 t2_hae_mem[hose] = msb;
124 t2_csr[hose]->hae0_1 = t2_hae_mem[hose];
126 t2_hae_mem[hose] = t2_csr[hose]->hae0_1;
128 cpu_critical_exit(s);
136 return t2_hae_mem[0] << 27;
140 t2_write_hae(u_int64_t hae)
143 t2_set_hae_mem(0, pa);
146 static int t2_probe(device_t dev);
147 static int t2_attach(device_t dev);
148 static int t2_setup_intr(device_t dev, device_t child,
149 struct resource *irq, int flags,
150 void *intr, void *arg, void **cookiep);
151 static int t2_teardown_intr(device_t dev, device_t child,
152 struct resource *irq, void *cookie);
154 t2_dispatch_intr(void *frame, unsigned long vector);
156 t2_machine_check(unsigned long mces, struct trapframe *framep,
157 unsigned long vector, unsigned long param);
160 static device_method_t t2_methods[] = {
161 /* Device interface */
162 DEVMETHOD(device_probe, t2_probe),
163 DEVMETHOD(device_attach, t2_attach),
166 DEVMETHOD(bus_setup_intr, t2_setup_intr),
167 DEVMETHOD(bus_teardown_intr, t2_teardown_intr),
172 static driver_t t2_driver = {
175 sizeof(struct t2_softc),
179 #define T2_SGMAP_BASE (8*1024*1024)
180 #define T2_SGMAP_SIZE (8*1024*1024)
183 t2_sgmap_invalidate(void)
188 val = REGVAL64(T2_IOCSR);
189 val |= T2_IOCSRL_ITLB;
190 REGVAL64(T2_IOCSR) = val;
193 val = REGVAL64(T2_IOCSR);
194 val &= ~T2_IOCSRL_ITLB;
195 REGVAL64(T2_IOCSR) = val;
201 t2_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
203 u_int64_t *sgtable = arg;
204 int index = alpha_btop(ba - T2_SGMAP_BASE);
208 panic("t2_sgmap_map: can't map address 0x%lx", pa);
209 sgtable[index] = ((pa >> 13) << 1) | 1;
214 t2_sgmap_invalidate();
224 * First setup Window 2 to map 8Mb to 16Mb with an
225 * sgmap. Allocate the map aligned to a 32 boundary.
227 * bits 31..20 of WBASE represent the pci start address
228 * (in units of 1Mb), and bits 11..0 represent the pci
231 t2_csr[h]->wbase2 = T2_WSIZE_8M|T2_WINDOW_ENABLE|T2_WINDOW_SG
232 | ((T2_SGMAP_BASE >> 20) << 20)
233 | ((T2_SGMAP_BASE + T2_SGMAP_SIZE) >> 20);
234 t2_csr[h]->wmask2 = T2_WMASK_8M;
237 sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
241 panic("t2_init_sgmap: can't allocate page table");
244 (pmap_kextract((vm_offset_t) sgtable) >> T2_TBASE_SHIFT);
246 chipset.sgmap = sgmap_map_create(T2_SGMAP_BASE,
247 T2_SGMAP_BASE + T2_SGMAP_SIZE,
248 t2_sgmap_map, sgtable);
255 * initialize the DMA windows
257 t2_csr[h]->wbase1 = T2_WSIZE_1G|T2_WINDOW_ENABLE|T2_WINDOW_DIRECT|0x7ff;
258 t2_csr[h]->wmask1 = T2_WMASK_1G;
259 t2_csr[h]->tbase1 = 0x0;
261 t2_csr[h]->wbase2 = 0x0;
264 * enable the PCI "Hole" for ISA devices which use memory in
265 * the 512k - 1MB range
267 t2_csr[h]->hbase = 1 << 13;
270 /* initialize the HAEs */
271 t2_csr[h]->hae0_1 = 0x0;
273 t2_csr[h]->hae0_2 = 0x0;
275 t2_csr[h]->hae0_3 = 0x0;
281 * Perform basic chipset init/fixup. Called by various early
282 * consumers to ensure that the system will work before the
283 * bus methods are invoked.
290 static int initted = 0;
291 static struct swiz_space io_space, mem_space;
296 swiz_init_space(&io_space, KV(T2_PCI_SIO));
297 swiz_init_space_hae(&mem_space, KV(T2_PCI_SPARSE),
300 busspace_isa_io = (struct alpha_busspace *) &io_space;
301 busspace_isa_mem = (struct alpha_busspace *) &mem_space;
303 chipset = t2_chipset;
308 t2_probe(device_t dev)
310 int h, t2_num_hoses = 1;
317 device_set_desc(dev, "T2 Core Logic chipset");
318 t2_csr[0] = (t2_csr_t *)
319 ALPHA_PHYS_TO_K0SEG(sable_lynx_base + PCI0_BASE);
320 t2_csr[1] = (t2_csr_t *)
321 ALPHA_PHYS_TO_K0SEG(sable_lynx_base + PCI1_BASE);
323 /* Look at the rev of the chip. If the high bit is set in the
324 * rev field then we have either a T3 or a T4 chip, so use the
325 * new interrupt structure. If it is clear, then we have a T2
326 * so use the old way */
328 platform.mcheck_handler = t2_machine_check;
330 if (((t2_csr[0]->iocsr) >> 35) & 1)
335 device_printf(dev, "using interrupt type %d on pci bus 0\n",
338 if (!badaddr((void *)&t2_csr[1]->tlbbr, sizeof(long))) {
339 pci_int_type[1] = 1; /* PCI1 always uses the new scheme */
340 /* Clear any errors that the BADADDR probe may have caused */
341 t2_csr[1]->cerr1 |= t2_csr[1]->cerr1;
342 t2_csr[1]->pcierr1 |= t2_csr[1]->pcierr1;
343 device_printf(dev, "found EXT_IO!!!!!\n");
344 /* t2_num_hoses = 2; XXX not ready for this yet */
347 for (h = 0; h < t2_num_hoses; h++)
351 child = device_add_child(dev, "pcib", 0);
352 device_set_ivars(child, 0);
358 t2_attach(device_t dev)
362 set_iointr(t2_dispatch_intr);
363 platform.isa_setup_intr = t2_setup_intr;
364 platform.isa_teardown_intr = t2_teardown_intr;
366 snprintf(chipset_type, sizeof(chipset_type), "t2");
368 bus_generic_attach(dev);
375 * magical mystery table partly obtained from Linux
376 * at least some of their values for PCI masks
377 * were incorrect, and I've filled in my own extrapolations
378 * XXX this needs more testers
381 unsigned long t2_shadow_mask = -1L;
382 static const char irq_to_mask[40] = {
383 -1, 6, -1, 8, 15, 12, 7, 9, /* ISA 0-7 */
384 -1, 16, 17, 18, 3, -1, 21, 22, /* ISA 8-15 */
385 -1, -1, -1, -1, -1, -1, -1, -1, /* ?? EISA XXX */
386 -1, -1, -1, -1, -1, -1, -1, -1, /* ?? EISA XXX */
387 0, 1, 2, 3, 4, 5, 6, 7 /* PCI 0-7 XXX */
392 t2_8259_disable_mask(int mask)
394 t2_shadow_mask |= (1UL << mask);
397 outb(SLAVE0_ICU, t2_shadow_mask);
399 outb(SLAVE1_ICU, t2_shadow_mask >> 8);
401 outb(SLAVE2_ICU, t2_shadow_mask >> 16);
405 t2_8259_enable_mask(int mask)
407 t2_shadow_mask &= ~(1UL << mask);
410 outb(SLAVE0_ICU, t2_shadow_mask);
412 outb(SLAVE1_ICU, t2_shadow_mask >> 8);
414 outb(SLAVE2_ICU, t2_shadow_mask >> 16);
423 hose = (vector >= 0xC00);
424 irq = (vector - 0x800) >> 4;
426 if (pci_int_type[hose]) {
428 /* New interrupt scheme. Both PCI0 and PCI1 can use
429 * the same handler. Dispatching interrupts with the
430 * IC IC chip is easy. We simply write the vector
431 * address register (var) on the T3/T4 (offset
432 * 0x480) with the IRQ level (0 - 63) of what came in. */
433 t2_csr[hose]->var = (u_long) irq;
439 outb(SLAVE0_ICU-1, (0xe0 | (irq)));
440 outb(MASTER_ICU-1, (0xe0 | 1));
443 outb(SLAVE1_ICU-1, (0xe0 | (irq - 8)));
444 outb(MASTER_ICU-1, (0xe0 | 3));
447 outb(SLAVE2_ICU-1, (0xe0 | (irq - 16)));
448 outb(MASTER_ICU-1, (0xe0 | 4));
455 t2_enable_vec(int vector)
458 u_long IC_mask, scratch;
460 hose = (vector >= 0xC00);
461 irq = (vector - 0x800) >> 4;
463 if (pci_int_type[hose]) {
465 /* Write the air register on the T3/T4 with the
466 * address of the IC IC masks register (offset 0x40) */
467 t2_csr[hose]->air = 0x40;
469 scratch = t2_csr[hose]->air;
471 IC_mask = t2_csr[hose]->dir;
472 IC_mask &= ~(1L << ( (u_long) irq));
473 t2_csr[hose]->dir = IC_mask;
477 * EOI the interrupt we just enabled.
481 /* Old style 8259 (Gack!!!) interrupts */
482 t2_8259_enable_mask(irq);
487 t2_disable_vec(int vector)
490 u_long scratch, IC_mask;
492 hose = (vector >= 0xC00);
493 irq = (vector - 0x800) >> 4;
495 if (pci_int_type[hose]) {
497 /* Write the air register on the T3/T4 wioth the
498 * address of the IC IC masks register (offset 0x40) */
500 t2_csr[hose]->air = 0x40;
502 scratch = t2_csr[hose]->air;
505 * Read the dir register to fetch the mask data, 'or' in the
506 * new disable bit, and write the data back.
508 IC_mask = t2_csr[hose]->dir;
509 IC_mask |= (1L << ( (u_long) irq));
510 /* Set the disable bit */
511 t2_csr[hose]->dir = IC_mask;
515 /* Old style 8259 (Gack!!!) interrupts */
516 t2_8259_disable_mask(irq);
522 t2_setup_intr(device_t dev, device_t child,
523 struct resource *irq, int flags,
524 void *intr, void *arg, void **cookiep)
526 int error, vector, stdio_irq;
528 device_t bus, parent;
530 name = device_get_nameunit(dev);
531 stdio_irq = irq->r_start;
532 if (strncmp(name, "eisa", 4) == 0) {
533 if ((stdio_irq != 6 ) && (stdio_irq != 3 )) {
535 T2_EISA_IRQ_TO_STDIO_IRQ(stdio_irq);
537 } else if ((strncmp(name, "isa", 3)) == 0) {
538 stdio_irq = irq_to_mask[stdio_irq];
544 parent = device_get_parent(bus);
545 } while (parent && strncmp("t2", device_get_nameunit(parent), 2));
547 if (parent && (device_get_unit(bus) != 0))
548 vector = STDIO_PCI1_IRQ_TO_SCB_VECTOR(stdio_irq);
550 vector = STDIO_PCI0_IRQ_TO_SCB_VECTOR(stdio_irq);
552 error = rman_activate_resource(irq);
556 error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
557 vector, intr, arg, flags, cookiep,
558 &intrcnt[irq->r_start], t2_disable_vec, t2_enable_vec);
563 /* Enable interrupt */
564 t2_enable_vec(vector);
566 if (bootverbose != 0)
568 "interrupting at T2 irq %d (stdio irq %d)\n",
569 (int) irq->r_start, stdio_irq);
574 t2_teardown_intr(device_t dev, device_t child,
575 struct resource *irq, void *cookie)
579 mask = irq_to_mask[irq->r_start];
581 /* Disable interrupt */
584 * XXX this is totally broken!
585 * we don't have enough info to figure out where the interrupt
586 * came from if hose != 0 and pci_int_type[hose] != 0
587 * We should probably carry around the vector someplace --
588 * that would be enough to figure out the hose and the stdio irq
591 t2_shadow_mask |= (1UL << mask);
594 outb(SLAVE0_ICU, t2_shadow_mask);
596 outb(SLAVE1_ICU, t2_shadow_mask >> 8);
598 outb(SLAVE2_ICU, t2_shadow_mask >> 16);
600 alpha_teardown_intr(cookie);
601 return rman_deactivate_resource(irq);
607 t2_dispatch_intr(void *frame, unsigned long vector)
609 alpha_dispatch_intr(frame, vector);
614 t2_machine_check(unsigned long mces, struct trapframe *framep,
615 unsigned long vector, unsigned long param)
619 expected = mc_expected;
620 machine_check(mces, framep, vector, param);
621 /* for some reason the alpha_pal_wrmces() doesn't clear all
622 pending machine checks & we may take another */
623 mc_expected = expected;
626 DRIVER_MODULE(t2, root, t2_driver, t2_devclass, 0, 0);