2 /* $NetBSD: am7990reg.h,v 1.4 1997/03/27 21:01:49 veego Exp $ */
5 * Copyright (c) 1995 Charles M. Hannum. All rights reserved.
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This code is derived from software contributed to Berkeley by
10 * Ralph Campbell and Rick Macklem.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93
43 #define LEBLEN 1536 /* ETHERMTU + header + CRC */
44 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
47 * Receive message descriptor
51 #if BYTE_ORDER == BIG_ENDIAN
63 * Transmit message descriptor
67 #if BYTE_ORDER == BIG_ENDIAN
79 * Initialization block
82 u_int16_t init_mode; /* +0x0000 */
83 u_int16_t init_padr[3]; /* +0x0002 */
84 u_int16_t init_ladrf[4]; /* +0x0008 */
85 u_int16_t init_rdra; /* +0x0010 */
86 u_int16_t init_rlen; /* +0x0012 */
87 u_int16_t init_tdra; /* +0x0014 */
88 u_int16_t init_tlen; /* +0x0016 */
89 int16_t pad0[4]; /* Pad to 16 shorts */
92 #define LE_INITADDR(sc) (sc->sc_initaddr)
93 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
94 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
95 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr[bix])
96 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr[bix])
98 /* register addresses */
99 #define LE_CSR0 0x0000 /* Control and status register */
100 #define LE_CSR1 0x0001 /* low address of init block */
101 #define LE_CSR2 0x0002 /* high address of init block */
102 #define LE_CSR3 0x0003 /* Bus master and control */
104 /* Control and status register 0 (csr0) */
105 #define LE_C0_ERR 0x8000 /* error summary */
106 #define LE_C0_BABL 0x4000 /* transmitter timeout error */
107 #define LE_C0_CERR 0x2000 /* collision */
108 #define LE_C0_MISS 0x1000 /* missed a packet */
109 #define LE_C0_MERR 0x0800 /* memory error */
110 #define LE_C0_RINT 0x0400 /* receiver interrupt */
111 #define LE_C0_TINT 0x0200 /* transmitter interrupt */
112 #define LE_C0_IDON 0x0100 /* initalization done */
113 #define LE_C0_INTR 0x0080 /* interrupt condition */
114 #define LE_C0_INEA 0x0040 /* interrupt enable */
115 #define LE_C0_RXON 0x0020 /* receiver on */
116 #define LE_C0_TXON 0x0010 /* transmitter on */
117 #define LE_C0_TDMD 0x0008 /* transmit demand */
118 #define LE_C0_STOP 0x0004 /* disable all external activity */
119 #define LE_C0_STRT 0x0002 /* enable external activity */
120 #define LE_C0_INIT 0x0001 /* begin initalization */
123 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
124 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
126 /* Control and status register 3 (csr3) */
127 #define LE_C3_BSWP 0x0004 /* byte swap */
128 #define LE_C3_ACON 0x0002 /* ALE control, eh? */
129 #define LE_C3_BCON 0x0001 /* byte control */
131 /* Initialzation block (mode) */
132 #define LE_MODE_PROM 0x8000 /* promiscuous mode */
133 /* 0x7f80 reserved, must be zero */
134 /* 0x4000 - 0x0080 are not available on LANCE 7990 */
135 #define LE_MODE_DRCVBC 0x4000 /* disable receive brodcast */
136 #define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */
137 #define LE_MODE_DLNKTST 0x1000 /* disable link status */
138 #define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */
139 #define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */
140 #define LE_MODE_LRTTSEL 0x0200 /* lower receice threshold /
141 transmit mode selection */
142 #define LE_MODE_PSEL1 0x0100 /* port selection bit1 */
143 #define LE_MODE_PSEL0 0x0080 /* port selection bit0 */
144 #define LE_MODE_INTL 0x0040 /* internal loopback */
145 #define LE_MODE_DRTY 0x0020 /* disable retry */
146 #define LE_MODE_COLL 0x0010 /* force a collision */
147 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
148 #define LE_MODE_LOOP 0x0004 /* loopback mode */
149 #define LE_MODE_DTX 0x0002 /* disable transmitter */
150 #define LE_MODE_DRX 0x0001 /* disable receiver */
151 #define LE_MODE_NORMAL 0 /* none of the above */
153 /* Receive message descriptor 1 (rmd1_bits) */
154 #define LE_R1_OWN 0x80 /* LANCE owns the packet */
155 #define LE_R1_ERR 0x40 /* error summary */
156 #define LE_R1_FRAM 0x20 /* framing error */
157 #define LE_R1_OFLO 0x10 /* overflow error */
158 #define LE_R1_CRC 0x08 /* CRC error */
159 #define LE_R1_BUFF 0x04 /* buffer error */
160 #define LE_R1_STP 0x02 /* start of packet */
161 #define LE_R1_ENP 0x01 /* end of packet */
164 "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
166 /* Transmit message descriptor 1 (tmd1_bits) */
167 #define LE_T1_OWN 0x80 /* LANCE owns the packet */
168 #define LE_T1_ERR 0x40 /* error summary */
169 #define LE_T1_MORE 0x10 /* multiple collisions */
170 #define LE_T1_ONE 0x08 /* single collision */
171 #define LE_T1_DEF 0x04 /* defferred transmit */
172 #define LE_T1_STP 0x02 /* start of packet */
173 #define LE_T1_ENP 0x01 /* end of packet */
176 "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
178 /* Transmit message descriptor 3 (tmd3) */
179 #define LE_T3_BUFF 0x8000 /* buffer error */
180 #define LE_T3_UFLO 0x4000 /* underflow error */
181 #define LE_T3_LCOL 0x1000 /* late collision */
182 #define LE_T3_LCAR 0x0800 /* loss of carrier */
183 #define LE_T3_RTRY 0x0400 /* retry error */
184 #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
186 #define LE_XMD2_ONES 0xf000
189 "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
192 * PCnet-ISA defines which are not available on LANCE 7990
195 /* (ISA) Bus Configuration Registers */
196 #define LE_BCR_MSRDA 0x0000
197 #define LE_BCR_MSWRA 0x0001
198 #define LE_BCR_MC 0x0002
199 #define LE_BCR_LED1 0x0005
200 #define LE_BCR_LED2 0x0006
201 #define LE_BCR_LED3 0x0007
203 /* Bus configurations bits (MC) */
204 #define LE_MC_EADISEL 0x0008 /* EADI selection */
205 #define LE_MC_AWAKE 0x0004 /* auto-wake */
206 #define LE_MC_ASEL 0x0002 /* auto selection */
207 #define LE_MC_XMAUSEL 0x0001 /* external MAU selection */
209 /* LED bis (LED[123]) */
210 #define LE_LED_LEDOUT 0x8000
211 #define LE_LED_PSE 0x0080
212 #define LE_LED_XMTE 0x0010
213 #define LE_LED_PVPE 0x0008
214 #define LE_LED_PCVE 0x0004
215 #define LE_LED_JABE 0x0002
216 #define LE_LED_COLE 0x0001