2 * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/memrange.h>
36 #include <sys/sysctl.h>
39 #include <vm/vm_param.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
47 * amd64 memory range operations
49 * This code will probably be impenetrable without reference to the
50 * Intel Pentium Pro documentation or x86-64 programmers manual vol 2.
53 static char *mem_owner_bios = "BIOS";
55 #define MR686_FIXMTRR (1<<0)
57 #define mrwithin(mr, a) \
58 (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
59 #define mroverlap(mra, mrb) \
60 (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
62 #define mrvalid(base, len) \
63 ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \
64 ((len) >= (1 << 12)) && /* length is >= 4k */ \
65 powerof2((len)) && /* ... and power of two */ \
66 !((base) & ((len) - 1))) /* range is not discontiuous */
68 #define mrcopyflags(curr, new) \
69 (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
71 static int mtrrs_disabled;
72 SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN,
73 &mtrrs_disabled, 0, "Disable amd64 MTRRs.");
75 static void amd64_mrinit(struct mem_range_softc *sc);
76 static int amd64_mrset(struct mem_range_softc *sc,
77 struct mem_range_desc *mrd, int *arg);
78 static void amd64_mrAPinit(struct mem_range_softc *sc);
79 static void amd64_mrreinit(struct mem_range_softc *sc);
81 static struct mem_range_ops amd64_mrops = {
88 /* XXX for AP startup hook */
89 static u_int64_t mtrrcap, mtrrdef;
91 /* The bitmask for the PhysBase and PhysMask fields of the variable MTRRs. */
92 static u_int64_t mtrr_physmask;
94 static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc,
95 struct mem_range_desc *mrd);
96 static void amd64_mrfetch(struct mem_range_softc *sc);
97 static int amd64_mtrrtype(int flags);
98 static int amd64_mrt2mtrr(int flags, int oldval);
99 static int amd64_mtrrconflict(int flag1, int flag2);
100 static void amd64_mrstore(struct mem_range_softc *sc);
101 static void amd64_mrstoreone(void *arg);
102 static struct mem_range_desc *amd64_mtrrfixsearch(struct mem_range_softc *sc,
104 static int amd64_mrsetlow(struct mem_range_softc *sc,
105 struct mem_range_desc *mrd, int *arg);
106 static int amd64_mrsetvariable(struct mem_range_softc *sc,
107 struct mem_range_desc *mrd, int *arg);
109 /* amd64 MTRR type to memory range type conversion */
110 static int amd64_mtrrtomrt[] = {
120 #define MTRRTOMRTLEN (sizeof(amd64_mtrrtomrt) / sizeof(amd64_mtrrtomrt[0]))
123 amd64_mtrr2mrt(int val)
126 if (val < 0 || val >= MTRRTOMRTLEN)
127 return (MDF_UNKNOWN);
128 return (amd64_mtrrtomrt[val]);
132 * amd64 MTRR conflicts. Writeback and uncachable may overlap.
135 amd64_mtrrconflict(int flag1, int flag2)
138 flag1 &= MDF_ATTRMASK;
139 flag2 &= MDF_ATTRMASK;
140 if ((flag1 & MDF_UNKNOWN) || (flag2 & MDF_UNKNOWN))
142 if (flag1 == flag2 ||
143 (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
144 (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
150 * Look for an exactly-matching range.
152 static struct mem_range_desc *
153 mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd)
155 struct mem_range_desc *cand;
158 for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
159 if ((cand->mr_base == mrd->mr_base) &&
160 (cand->mr_len == mrd->mr_len))
166 * Fetch the current mtrr settings from the current CPU (assumed to
167 * all be in sync in the SMP case). Note that if we are here, we
168 * assume that MTRRs are enabled, and we may or may not have fixed
172 amd64_mrfetch(struct mem_range_softc *sc)
174 struct mem_range_desc *mrd;
180 /* Get fixed-range MTRRs. */
181 if (sc->mr_cap & MR686_FIXMTRR) {
182 msr = MSR_MTRR64kBase;
183 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
185 for (j = 0; j < 8; j++, mrd++) {
187 (mrd->mr_flags & ~MDF_ATTRMASK) |
188 amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
189 if (mrd->mr_owner[0] == 0)
190 strcpy(mrd->mr_owner, mem_owner_bios);
194 msr = MSR_MTRR16kBase;
195 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
197 for (j = 0; j < 8; j++, mrd++) {
199 (mrd->mr_flags & ~MDF_ATTRMASK) |
200 amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
201 if (mrd->mr_owner[0] == 0)
202 strcpy(mrd->mr_owner, mem_owner_bios);
206 msr = MSR_MTRR4kBase;
207 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
209 for (j = 0; j < 8; j++, mrd++) {
211 (mrd->mr_flags & ~MDF_ATTRMASK) |
212 amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
213 if (mrd->mr_owner[0] == 0)
214 strcpy(mrd->mr_owner, mem_owner_bios);
220 /* Get remainder which must be variable MTRRs. */
221 msr = MSR_MTRRVarBase;
222 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
224 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
225 amd64_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE);
226 mrd->mr_base = msrv & mtrr_physmask;
227 msrv = rdmsr(msr + 1);
228 mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ?
229 (mrd->mr_flags | MDF_ACTIVE) :
230 (mrd->mr_flags & ~MDF_ACTIVE);
232 /* Compute the range from the mask. Ick. */
233 mrd->mr_len = (~(msrv & mtrr_physmask) &
234 (mtrr_physmask | 0xfffL)) + 1;
235 if (!mrvalid(mrd->mr_base, mrd->mr_len))
236 mrd->mr_flags |= MDF_BOGUS;
238 /* If unclaimed and active, must be the BIOS. */
239 if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
240 strcpy(mrd->mr_owner, mem_owner_bios);
245 * Return the MTRR memory type matching a region's flags
248 amd64_mtrrtype(int flags)
252 flags &= MDF_ATTRMASK;
254 for (i = 0; i < MTRRTOMRTLEN; i++) {
255 if (amd64_mtrrtomrt[i] == MDF_UNKNOWN)
257 if (flags == amd64_mtrrtomrt[i])
264 amd64_mrt2mtrr(int flags, int oldval)
268 if ((val = amd64_mtrrtype(flags)) == -1)
269 return (oldval & 0xff);
274 * Update running CPU(s) MTRRs to match the ranges in the descriptor
277 * XXX Must be called with interrupts enabled.
280 amd64_mrstore(struct mem_range_softc *sc)
284 * We should use ipi_all_but_self() to call other CPUs into a
285 * locking gate, then call a target function to do this work.
286 * The "proper" solution involves a generalised locking gate
287 * implementation, not ready yet.
289 smp_rendezvous(NULL, amd64_mrstoreone, NULL, sc);
291 disable_intr(); /* disable interrupts */
292 amd64_mrstoreone(sc);
298 * Update the current CPU's MTRRs with those represented in the
299 * descriptor list. Note that we do this wholesale rather than just
300 * stuffing one entry; this is simpler (but slower, of course).
303 amd64_mrstoreone(void *arg)
305 struct mem_range_softc *sc = arg;
306 struct mem_range_desc *mrd;
307 u_int64_t omsrv, msrv;
317 load_cr4(cr4 & ~CR4_PGE);
319 /* Disable caches (CD = 1, NW = 0). */
321 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
323 /* Flushes caches and TLBs. */
327 /* Disable MTRRs (E = 0). */
328 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
330 /* Set fixed-range MTRRs. */
331 if (sc->mr_cap & MR686_FIXMTRR) {
332 msr = MSR_MTRR64kBase;
333 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
336 for (j = 7; j >= 0; j--) {
338 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
344 msr = MSR_MTRR16kBase;
345 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
348 for (j = 7; j >= 0; j--) {
350 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
356 msr = MSR_MTRR4kBase;
357 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
360 for (j = 7; j >= 0; j--) {
362 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
370 /* Set remainder which must be variable MTRRs. */
371 msr = MSR_MTRRVarBase;
372 for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
373 /* base/type register */
375 if (mrd->mr_flags & MDF_ACTIVE) {
376 msrv = mrd->mr_base & mtrr_physmask;
377 msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv);
383 /* mask/active register */
384 if (mrd->mr_flags & MDF_ACTIVE) {
385 msrv = MTRR_PHYSMASK_VALID |
386 (~(mrd->mr_len - 1) & mtrr_physmask);
390 wrmsr(msr + 1, msrv);
393 /* Flush caches and TLBs. */
398 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
400 /* Restore caches and PGE. */
408 * Hunt for the fixed MTRR referencing (addr)
410 static struct mem_range_desc *
411 amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
413 struct mem_range_desc *mrd;
416 for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K);
418 if ((addr >= mrd->mr_base) &&
419 (addr < (mrd->mr_base + mrd->mr_len)))
425 * Try to satisfy the given range request by manipulating the fixed
426 * MTRRs that cover low memory.
428 * Note that we try to be generous here; we'll bloat the range out to
429 * the next higher/lower boundary to avoid the consumer having to know
430 * too much about the mechanisms here.
432 * XXX note that this will have to be updated when we start supporting
436 amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
438 struct mem_range_desc *first_md, *last_md, *curr_md;
441 if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
442 ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
445 /* Check that we aren't doing something risky. */
446 if (!(mrd->mr_flags & MDF_FORCE))
447 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
448 if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
452 /* Set flags, clear set-by-firmware flag. */
453 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
454 curr_md->mr_flags = mrcopyflags(curr_md->mr_flags &
455 ~MDF_FIRMWARE, mrd->mr_flags);
456 bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
463 * Modify/add a variable MTRR to satisfy the request.
465 * XXX needs to be updated to properly support "busy" ranges.
468 amd64_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd,
471 struct mem_range_desc *curr_md, *free_md;
475 * Scan the currently active variable descriptors, look for
476 * one we exactly match (straight takeover) and for possible
477 * accidental overlaps.
479 * Keep track of the first empty variable descriptor in case
480 * we can't perform a takeover.
482 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
483 curr_md = sc->mr_desc + i;
485 for (; i < sc->mr_ndesc; i++, curr_md++) {
486 if (curr_md->mr_flags & MDF_ACTIVE) {
488 if ((curr_md->mr_base == mrd->mr_base) &&
489 (curr_md->mr_len == mrd->mr_len)) {
491 /* Whoops, owned by someone. */
492 if (curr_md->mr_flags & MDF_BUSY)
495 /* Check that we aren't doing something risky */
496 if (!(mrd->mr_flags & MDF_FORCE) &&
497 ((curr_md->mr_flags & MDF_ATTRMASK) ==
501 /* Ok, just hijack this entry. */
506 /* Non-exact overlap? */
507 if (mroverlap(curr_md, mrd)) {
508 /* Between conflicting region types? */
509 if (amd64_mtrrconflict(curr_md->mr_flags,
513 } else if (free_md == NULL) {
518 /* Got somewhere to put it? */
522 /* Set up new descriptor. */
523 free_md->mr_base = mrd->mr_base;
524 free_md->mr_len = mrd->mr_len;
525 free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
526 bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
531 * Handle requests to set memory range attributes by manipulating MTRRs.
534 amd64_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
536 struct mem_range_desc *targ;
540 case MEMRANGE_SET_UPDATE:
542 * Make sure that what's being asked for is even
545 if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
546 amd64_mtrrtype(mrd->mr_flags) == -1)
549 #define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
551 /* Are the "low memory" conditions applicable? */
552 if ((sc->mr_cap & MR686_FIXMTRR) &&
553 ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
554 if ((error = amd64_mrsetlow(sc, mrd, arg)) != 0)
557 /* It's time to play with variable MTRRs. */
558 if ((error = amd64_mrsetvariable(sc, mrd, arg)) != 0)
563 case MEMRANGE_SET_REMOVE:
564 if ((targ = mem_range_match(sc, mrd)) == NULL)
566 if (targ->mr_flags & MDF_FIXACTIVE)
568 if (targ->mr_flags & MDF_BUSY)
570 targ->mr_flags &= ~MDF_ACTIVE;
571 targ->mr_owner[0] = 0;
579 * Ensure that the direct map region does not contain any mappings
580 * that span MTRRs of different types. However, the fixed MTRRs can
581 * be ignored, because a large page mapping the first 1 MB of physical
582 * memory is a special case that the processor handles. The entire
583 * TLB will be invalidated by amd64_mrstore(), so pmap_demote_DMAP()
586 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
587 mrd = sc->mr_desc + i;
588 for (; i < sc->mr_ndesc; i++, mrd++) {
589 if ((mrd->mr_flags & (MDF_ACTIVE | MDF_BOGUS)) == MDF_ACTIVE)
590 pmap_demote_DMAP(mrd->mr_base, mrd->mr_len, FALSE);
593 /* Update the hardware. */
596 /* Refetch to see where we're at. */
602 * Work out how many ranges we support, initialise storage for them,
603 * and fetch the initial settings.
606 amd64_mrinit(struct mem_range_softc *sc)
608 struct mem_range_desc *mrd;
610 int i, nmdesc = 0, pabits;
612 mtrrcap = rdmsr(MSR_MTRRcap);
613 mtrrdef = rdmsr(MSR_MTRRdefType);
615 /* For now, bail out if MTRRs are not enabled. */
616 if (!(mtrrdef & MTRR_DEF_ENABLE)) {
618 printf("CPU supports MTRRs but not enabled\n");
621 nmdesc = mtrrcap & MTRR_CAP_VCNT;
624 * Determine the size of the PhysMask and PhysBase fields in
625 * the variable range MTRRs. If the extended CPUID 0x80000008
626 * is present, use that to figure out how many physical
627 * address bits the CPU supports. Otherwise, default to 36
630 if (cpu_exthigh >= 0x80000008) {
631 do_cpuid(0x80000008, regs);
632 pabits = regs[0] & 0xff;
635 mtrr_physmask = ((1UL << pabits) - 1) & ~0xfffUL;
637 /* If fixed MTRRs supported and enabled. */
638 if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) {
639 sc->mr_cap = MR686_FIXMTRR;
640 nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
643 sc->mr_desc = malloc(nmdesc * sizeof(struct mem_range_desc), M_MEMDESC,
645 sc->mr_ndesc = nmdesc;
649 /* Populate the fixed MTRR entries' base/length. */
650 if (sc->mr_cap & MR686_FIXMTRR) {
651 for (i = 0; i < MTRR_N64K; i++, mrd++) {
652 mrd->mr_base = i * 0x10000;
653 mrd->mr_len = 0x10000;
654 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
657 for (i = 0; i < MTRR_N16K; i++, mrd++) {
658 mrd->mr_base = i * 0x4000 + 0x80000;
659 mrd->mr_len = 0x4000;
660 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
663 for (i = 0; i < MTRR_N4K; i++, mrd++) {
664 mrd->mr_base = i * 0x1000 + 0xc0000;
665 mrd->mr_len = 0x1000;
666 mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
672 * Get current settings, anything set now is considered to
673 * have been set by the firmware. (XXX has something already
678 for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
679 if (mrd->mr_flags & MDF_ACTIVE)
680 mrd->mr_flags |= MDF_FIRMWARE;
684 * Ensure that the direct map region does not contain any mappings
685 * that span MTRRs of different types. However, the fixed MTRRs can
686 * be ignored, because a large page mapping the first 1 MB of physical
687 * memory is a special case that the processor handles. Invalidate
688 * any old TLB entries that might hold inconsistent memory type
691 i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
692 mrd = sc->mr_desc + i;
693 for (; i < sc->mr_ndesc; i++, mrd++) {
694 if ((mrd->mr_flags & (MDF_ACTIVE | MDF_BOGUS)) == MDF_ACTIVE)
695 pmap_demote_DMAP(mrd->mr_base, mrd->mr_len, TRUE);
700 * Initialise MTRRs on an AP after the BSP has run the init code.
703 amd64_mrAPinit(struct mem_range_softc *sc)
706 amd64_mrstoreone(sc);
707 wrmsr(MSR_MTRRdefType, mtrrdef);
711 * Re-initialise running CPU(s) MTRRs to match the ranges in the descriptor
714 * XXX Must be called with interrupts enabled.
717 amd64_mrreinit(struct mem_range_softc *sc)
721 * We should use ipi_all_but_self() to call other CPUs into a
722 * locking gate, then call a target function to do this work.
723 * The "proper" solution involves a generalised locking gate
724 * implementation, not ready yet.
726 smp_rendezvous(NULL, (void *)amd64_mrAPinit, NULL, sc);
728 disable_intr(); /* disable interrupts */
735 amd64_mem_drvinit(void *unused)
740 if (!(cpu_feature & CPUID_MTRR))
742 if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
744 switch (cpu_vendor_id) {
745 case CPU_VENDOR_INTEL:
747 case CPU_VENDOR_CENTAUR:
752 mem_range_softc.mr_op = &amd64_mrops;
754 SYSINIT(amd64memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, amd64_mem_drvinit, NULL);