2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
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11 * 2. Redistributions in binary form must reproduce the above copyright
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14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
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18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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30 * from: vector.s, 386BSD 0.1 unknown origin
35 * Interrupt entry points for external interrupts triggered by I/O APICs
36 * as well as IPI handlers.
41 #include <machine/asmacros.h>
42 #include <machine/specialreg.h>
43 #include <x86/apicreg.h>
55 /* End Of Interrupt to APIC */
63 movl $MSR_APIC_EOI,%ecx
70 * I/O Interrupt Entry Point. Rather than having one entry point for
71 * each interrupt source, we use one entry point for each 32-bit word
72 * in the ISR. The handler determines the highest bit set in the ISR,
73 * translates that into a vector, and passes the vector to the
74 * lapic_handle_intr() function.
76 #define ISR_VEC(index, vec_name) \
81 FAKE_MCOUNT(TF_RIP(%rsp)) ; \
82 cmpl $0,x2apic_mode ; \
84 movl $(MSR_APIC_ISR0 + index),%ecx ; \
88 movq lapic_map, %rdx ; /* pointer to local APIC */ \
89 movl LA_ISR + 16 * (index)(%rdx), %eax ; /* load ISR */ \
91 bsrl %eax, %eax ; /* index of highest set bit in ISR */ \
93 addl $(32 * index),%eax ; \
95 movl %eax, %edi ; /* pass the IRQ */ \
96 call lapic_handle_intr ; \
102 * Handle "spurious INTerrupts".
104 * This is different than the "spurious INTerrupt" generated by an
105 * 8259 PIC for missing INTs. See the APIC documentation for details.
106 * This routine should NOT do an 'EOI' cycle.
112 /* No EOI cycle used here */
116 ISR_VEC(1, apic_isr1)
117 ISR_VEC(2, apic_isr2)
118 ISR_VEC(3, apic_isr3)
119 ISR_VEC(4, apic_isr4)
120 ISR_VEC(5, apic_isr5)
121 ISR_VEC(6, apic_isr6)
122 ISR_VEC(7, apic_isr7)
125 * Local APIC periodic timer handler.
131 FAKE_MCOUNT(TF_RIP(%rsp))
133 call lapic_handle_timer
138 * Local APIC CMCI handler.
144 FAKE_MCOUNT(TF_RIP(%rsp))
145 call lapic_handle_cmc
150 * Local APIC error interrupt handler.
156 FAKE_MCOUNT(TF_RIP(%rsp))
157 call lapic_handle_error
163 * Xen event channel upcall interrupt handler.
164 * Only used when the hypervisor supports direct vector callbacks.
168 IDTVEC(xen_intr_upcall)
170 FAKE_MCOUNT(TF_RIP(%rsp))
172 call xen_intr_handle_upcall
179 * This is the Hyper-V vmbus channel direct callback interrupt.
180 * Only used when it is running on Hyper-V.
184 IDTVEC(hv_vmbus_callback)
186 FAKE_MCOUNT(TF_RIP(%rsp))
188 call hv_vector_handler
195 * Global address space TLB shootdown.
215 call invltlb_pcid_handler
218 IDTVEC(invltlb_invpcid)
221 call invltlb_invpcid_handler
225 * Single page TLB shootdown
237 * Page range TLB shootdown.
255 call invlcache_handler
259 * Handler for IPIs sent via the per-cpu IPI bitmap.
263 IDTVEC(ipi_intr_bitmap_handler)
268 FAKE_MCOUNT(TF_RIP(%rsp))
270 call ipi_bitmap_handler
275 * Executed by a CPU when it receives an IPI_STOP from another CPU.
288 * Executed by a CPU when it receives an IPI_SUSPEND from another CPU.
295 call cpususpend_handler
300 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
302 * - Calls the generic rendezvous action function.
309 movl PCPU(CPUID), %eax
310 movq ipi_rendezvous_counts(,%rax,8), %rax
313 call smp_rendezvous_action
318 * IPI handler whose purpose is to interrupt the CPU with minimum overhead.
319 * This is used by bhyve to force a host cpu executing in guest context to
320 * trap into the hypervisor.
322 * This handler is different from other IPI handlers in the following aspects:
324 * 1. It doesn't push a trapframe on the stack.
326 * This implies that a DDB backtrace involving 'justreturn' will skip the
327 * function that was interrupted by this handler.
329 * 2. It doesn't 'swapgs' when userspace is interrupted.
331 * The 'justreturn' handler does not access any pcpu data so it is not an
332 * issue. Moreover the 'justreturn' handler can only be interrupted by an NMI
333 * whose handler already doesn't trust GS.base when kernel code is interrupted.