2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
5 * Copyright (c) 2014-2018 The FreeBSD Foundation
8 * Portions of this software were developed by
9 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
10 * the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: vector.s, 386BSD 0.1 unknown origin
41 * Interrupt entry points for external interrupts triggered by I/O APICs
42 * as well as IPI handlers.
49 #include <machine/asmacros.h>
50 #include <machine/specialreg.h>
51 #include <x86/apicreg.h>
61 /* End Of Interrupt to APIC */
69 movl $MSR_APIC_EOI,%ecx
76 * I/O Interrupt Entry Point. Rather than having one entry point for
77 * each interrupt source, we use one entry point for each 32-bit word
78 * in the ISR. The handler determines the highest bit set in the ISR,
79 * translates that into a vector, and passes the vector to the
80 * lapic_handle_intr() function.
82 .macro ISR_VEC index, vec_name
83 INTR_HANDLER \vec_name
86 movl $(MSR_APIC_ISR0 + \index),%ecx
90 movq lapic_map, %rdx /* pointer to local APIC */
91 movl LA_ISR + 16 * (\index)(%rdx), %eax /* load ISR */
93 bsrl %eax, %eax /* index of highest set bit in ISR */
95 addl $(32 * \index),%eax
97 movl %eax, %edi /* pass the IRQ */
98 call lapic_handle_intr
104 * Handle "spurious INTerrupts".
106 * This is different than the "spurious INTerrupt" generated by an
107 * 8259 PIC for missing INTs. See the APIC documentation for details.
108 * This routine should NOT do an 'EOI' cycle.
113 /* No EOI cycle used here */
125 * Local APIC periodic timer handler.
127 INTR_HANDLER timerint
129 call lapic_handle_timer
133 * Local APIC CMCI handler.
136 call lapic_handle_cmc
140 * Local APIC error interrupt handler.
142 INTR_HANDLER errorint
143 call lapic_handle_error
148 * Xen event channel upcall interrupt handler.
149 * Only used when the hypervisor supports direct vector callbacks.
151 INTR_HANDLER xen_intr_upcall
153 call xen_intr_handle_upcall
159 * Global address space TLB shootdown.
165 * IPI handler for cache and TLB shootdown
173 * Handler for IPIs sent via the per-cpu IPI bitmap.
175 INTR_HANDLER ipi_intr_bitmap_handler
177 call ipi_bitmap_handler
181 * Executed by a CPU when it receives an IPI_STOP from another CPU.
189 * Executed by a CPU when it receives an IPI_SUSPEND from another CPU.
191 INTR_HANDLER cpususpend
192 call cpususpend_handler
197 * Executed by a CPU when it receives an IPI_SWI.
205 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
207 * - Calls the generic rendezvous action function.
209 INTR_HANDLER rendezvous
211 movl PCPU(CPUID), %eax
212 movq ipi_rendezvous_counts(,%rax,8), %rax
215 call smp_rendezvous_action
220 * IPI handler whose purpose is to interrupt the CPU with minimum overhead.
221 * This is used by bhyve to force a host cpu executing in guest context to
222 * trap into the hypervisor.
224 * This handler is different from other IPI handlers in the following aspects:
226 * 1. It doesn't push a trapframe on the stack.
228 * This implies that a DDB backtrace involving 'justreturn' will skip the
229 * function that was interrupted by this handler.
231 * 2. It doesn't 'swapgs' when userspace is interrupted.
233 * The 'justreturn' handler does not access any pcpu data so it is not an
234 * issue. Moreover the 'justreturn' handler can only be interrupted by an NMI
235 * whose handler already doesn't trust GS.base when kernel code is interrupted.
249 INTR_HANDLER justreturn1