2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_compat.h"
43 #include "opt_hwpmc_hooks.h"
47 #include <machine/asmacros.h>
48 #include <machine/psl.h>
49 #include <machine/trap.h>
50 #include <machine/specialreg.h>
54 .globl dtrace_invop_jump_addr
56 .type dtrace_invop_jump_addr,@object
57 .size dtrace_invop_jump_addr,8
58 dtrace_invop_jump_addr:
60 .globl dtrace_invop_calltrap_addr
62 .type dtrace_invop_calltrap_addr,@object
63 .size dtrace_invop_calltrap_addr,8
64 dtrace_invop_calltrap_addr:
69 ENTRY(start_exceptions)
72 /*****************************************************************************/
74 /*****************************************************************************/
76 * Trap and fault vector routines.
78 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
79 * state on the stack but also disables interrupts. This is important for
80 * us for the use of the swapgs instruction. We cannot be interrupted
81 * until the GS.base value is correct. For most traps, we automatically
82 * then enable interrupts if the interrupted context had them enabled.
83 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
85 * The cpu will push a certain amount of state onto the kernel stack for
86 * the current process. See amd64/include/frame.h.
87 * This includes the current RFLAGS (status register, which includes
88 * the interrupt disable state prior to the trap), the code segment register,
89 * and the return instruction pointer are pushed by the cpu. The cpu
90 * will also push an 'error' code for certain traps. We push a dummy
91 * error code for those traps where the cpu doesn't in order to maintain
92 * a consistent frame. We also push a contrived 'trap number'.
94 * The CPU does not push the general registers, so we must do that, and we
95 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
96 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
97 * for the kernel mode operation shortly, without changes to the selector
98 * loaded. Since superuser long mode works with any selectors loaded into
99 * segment registers other then %cs, which makes them mostly unused in long
100 * mode, and kernel does not reference %fs, leave them alone. The segment
101 * registers are reloaded on return to the usermode.
107 /* Traps that we leave interrupts disabled for. */
108 .macro TRAP_NOEN l, trapno
112 X\l: subq $TF_RIP,%rsp
113 movl $\trapno,TF_TRAPNO(%rsp)
114 movq $0,TF_ADDR(%rsp)
119 TRAP_NOEN bpt, T_BPTFLT
121 TRAP_NOEN dtrace_ret, T_DTRACE_RET
124 /* Regular traps; The cpu does not supply tf_err for these. */
125 .macro TRAP l, trapno
131 movl $\trapno,TF_TRAPNO(%rsp)
132 movq $0,TF_ADDR(%rsp)
140 TRAP ill, T_PRIVINFLT
142 TRAP fpusegm, T_FPOPFLT
143 TRAP rsvd, T_RESERVED
144 TRAP fpu, T_ARITHTRAP
147 /* This group of traps have tf_err already pushed by the cpu. */
148 .macro TRAP_ERR l, trapno
149 PTI_ENTRY \l,X\l,has_err=1
154 movl $\trapno,TF_TRAPNO(%rsp)
155 movq $0,TF_ADDR(%rsp)
159 TRAP_ERR tss, T_TSSFLT
160 TRAP_ERR align, T_ALIGNFLT
163 * alltraps entry point. Use swapgs if this is the first time in the
164 * kernel from userland. Reenable interrupts if they were enabled
165 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
169 .type alltraps,@function
171 movq %rdi,TF_RDI(%rsp)
172 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
173 jz 1f /* already running with kernel GS.base */
175 movq PCPU(CURPCB),%rdi
176 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
178 movq %rdx,TF_RDX(%rsp)
179 movq %rax,TF_RAX(%rsp)
180 movq %rcx,TF_RCX(%rsp)
181 testb $SEL_RPL_MASK,TF_CS(%rsp)
183 call handle_ibrs_entry
184 2: testl $PSL_I,TF_RFLAGS(%rsp)
185 jz alltraps_pushregs_no_rax
187 alltraps_pushregs_no_rax:
188 movq %rsi,TF_RSI(%rsp)
191 movq %rbx,TF_RBX(%rsp)
192 movq %rbp,TF_RBP(%rsp)
193 movq %r10,TF_R10(%rsp)
194 movq %r11,TF_R11(%rsp)
195 movq %r12,TF_R12(%rsp)
196 movq %r13,TF_R13(%rsp)
197 movq %r14,TF_R14(%rsp)
198 movq %r15,TF_R15(%rsp)
199 movl $TF_HASSEGS,TF_FLAGS(%rsp)
201 FAKE_MCOUNT(TF_RIP(%rsp))
204 * DTrace Function Boundary Trace (fbt) probes are triggered
205 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
206 * interrupt. For all other trap types, just handle them in
209 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
210 jnz calltrap /* ignore userland traps */
211 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
214 /* Check if there is no DTrace hook registered. */
215 cmpq $0,dtrace_invop_jump_addr
219 * Set our jump address for the jump back in the event that
220 * the breakpoint wasn't caused by DTrace at all.
222 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
224 /* Jump to the code hooked in by DTrace. */
225 jmpq *dtrace_invop_jump_addr
228 .type calltrap,@function
233 jmp doreti /* Handle any pending ASTs */
236 * alltraps_noen entry point. Unlike alltraps above, we want to
237 * leave the interrupts disabled. This corresponds to
238 * SDT_SYS386IGT on the i386 port.
242 .type alltraps_noen,@function
244 movq %rdi,TF_RDI(%rsp)
245 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
246 jz 1f /* already running with kernel GS.base */
248 movq PCPU(CURPCB),%rdi
249 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
251 movq %rdx,TF_RDX(%rsp)
252 movq %rax,TF_RAX(%rsp)
253 movq %rcx,TF_RCX(%rsp)
254 testb $SEL_RPL_MASK,TF_CS(%rsp)
255 jz alltraps_pushregs_no_rax
256 call handle_ibrs_entry
257 jmp alltraps_pushregs_no_rax
261 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
262 movq $0,TF_ADDR(%rsp)
264 movq %rdi,TF_RDI(%rsp)
265 movq %rsi,TF_RSI(%rsp)
266 movq %rdx,TF_RDX(%rsp)
267 movq %rcx,TF_RCX(%rsp)
270 movq %rax,TF_RAX(%rsp)
271 movq %rbx,TF_RBX(%rsp)
272 movq %rbp,TF_RBP(%rsp)
273 movq %r10,TF_R10(%rsp)
274 movq %r11,TF_R11(%rsp)
275 movq %r12,TF_R12(%rsp)
276 movq %r13,TF_R13(%rsp)
277 movq %r14,TF_R14(%rsp)
278 movq %r15,TF_R15(%rsp)
280 movl $TF_HASSEGS,TF_FLAGS(%rsp)
282 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
283 jz 1f /* already running with kernel GS.base */
291 call dblfault_handler
297 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp)
302 movq %rax,PCPU(SAVED_UCR3)
308 PTI_UUENTRY has_err=1
310 movq %rdi,TF_RDI(%rsp)
311 movq %rax,TF_RAX(%rsp)
312 movq %rdx,TF_RDX(%rsp)
313 movq %rcx,TF_RCX(%rsp)
317 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
318 movq %rax,TF_RAX(%rsp)
319 movq %rdx,TF_RDX(%rsp)
320 movq %rcx,TF_RCX(%rsp)
321 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
322 jz page_cr2 /* already running with kernel GS.base */
324 page_u: movq PCPU(CURPCB),%rdi
325 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
326 movq PCPU(SAVED_UCR3),%rax
327 movq %rax,PCB_SAVED_UCR3(%rdi)
328 call handle_ibrs_entry
330 movq %cr2,%rdi /* preserve %cr2 before .. */
331 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
333 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
334 testl $PSL_I,TF_RFLAGS(%rsp)
335 jz alltraps_pushregs_no_rax
337 jmp alltraps_pushregs_no_rax
340 * We have to special-case this one. If we get a trap in doreti() at
341 * the iretq stage, we'll reenter with the wrong gs state. We'll have
342 * to do a special the swapgs in this case even coming from the kernel.
343 * XXX linux has a trap handler for their equivalent of load_gs().
345 * On the stack, we have the hardware interrupt frame to return
346 * to usermode (faulted) and another frame with error code, for
347 * fault. For PTI, copy both frames to the main thread stack.
348 * Handle the potential 16-byte alignment adjustment incurred
349 * during the second fault by copying both frames independently
350 * while unwinding the stack in between.
352 .macro PROTF_ENTRY name,trapno
362 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
363 MOVE_STACKS (PTI_SIZE / 8)
365 movq PTI_RSP(%rsp),%rsp
366 MOVE_STACKS (PTI_SIZE / 8 - 3)
374 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
375 je \name\()_pti_doreti
376 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
382 movl $\trapno,TF_TRAPNO(%rsp)
386 PROTF_ENTRY missing, T_SEGNPFLT
387 PROTF_ENTRY stk, T_STKFLT
388 PROTF_ENTRY prot, T_PROTFLT
391 movq $0,TF_ADDR(%rsp)
392 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
393 movq %rax,TF_RAX(%rsp)
394 movq %rdx,TF_RDX(%rsp)
395 movq %rcx,TF_RCX(%rsp)
398 leaq doreti_iret(%rip),%rdi
399 cmpq %rdi,TF_RIP(%rsp)
400 je 5f /* kernel but with user gsbase!! */
401 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
402 jz 6f /* already running with kernel GS.base */
403 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
405 cmpw $KUF32SEL,TF_FS(%rsp)
408 1: cmpw $KUG32SEL,TF_GS(%rsp)
412 movq PCPU(CURPCB),%rdi
413 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
415 cmpw $KUF32SEL,TF_FS(%rsp)
417 movq %rax,PCB_FSBASE(%rdi)
418 3: cmpw $KUG32SEL,TF_GS(%rsp)
420 movq %rdx,PCB_GSBASE(%rdi)
421 4: call handle_ibrs_entry
422 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
425 testl $PSL_I,TF_RFLAGS(%rsp)
426 jz alltraps_pushregs_no_rax
428 jmp alltraps_pushregs_no_rax
431 6: movq PCPU(CURPCB),%rdi
435 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
436 * and the new privilige level. We are still running on the old user stack
437 * pointer. We have to juggle a few things around to find our stack etc.
438 * swapgs gives us access to our PCPU space only.
440 * We do not support invoking this from a custom segment registers,
441 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
444 IDTVEC(fast_syscall_pti)
446 movq %rax,PCPU(SCRATCH_RAX)
448 je fast_syscall_common
451 jmp fast_syscall_common
455 movq %rax,PCPU(SCRATCH_RAX)
457 movq %rsp,PCPU(SCRATCH_RSP)
459 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
461 /* defer TF_RSP till we have a spare register */
462 movq %r11,TF_RFLAGS(%rsp)
463 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
464 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
465 movq %r11,TF_RSP(%rsp) /* user stack pointer */
466 movq PCPU(SCRATCH_RAX),%rax
467 movq %rax,TF_RAX(%rsp) /* syscall number */
468 movq %rdx,TF_RDX(%rsp) /* arg 3 */
470 call handle_ibrs_entry
471 movq PCPU(CURPCB),%r11
472 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
474 movq $KUDSEL,TF_SS(%rsp)
475 movq $KUCSEL,TF_CS(%rsp)
477 movq %rdi,TF_RDI(%rsp) /* arg 1 */
478 movq %rsi,TF_RSI(%rsp) /* arg 2 */
479 movq %r10,TF_RCX(%rsp) /* arg 4 */
480 movq %r8,TF_R8(%rsp) /* arg 5 */
481 movq %r9,TF_R9(%rsp) /* arg 6 */
482 movq %rbx,TF_RBX(%rsp) /* C preserved */
483 movq %rbp,TF_RBP(%rsp) /* C preserved */
484 movq %r12,TF_R12(%rsp) /* C preserved */
485 movq %r13,TF_R13(%rsp) /* C preserved */
486 movq %r14,TF_R14(%rsp) /* C preserved */
487 movq %r15,TF_R15(%rsp) /* C preserved */
488 movl $TF_HASSEGS,TF_FLAGS(%rsp)
489 FAKE_MCOUNT(TF_RIP(%rsp))
490 movq PCPU(CURTHREAD),%rdi
491 movq %rsp,TD_FRAME(%rdi)
492 movl TF_RFLAGS(%rsp),%esi
495 1: movq PCPU(CURPCB),%rax
496 /* Disable interrupts before testing PCB_FULL_IRET. */
498 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
500 /* Check for and handle AST's on return to userland. */
501 movq PCPU(CURTHREAD),%rax
502 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
504 call handle_ibrs_exit
506 /* Restore preserved registers. */
508 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
509 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
510 movq TF_RDX(%rsp),%rdx /* return value 2 */
511 movq TF_RAX(%rsp),%rax /* return value 1 */
512 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
513 movq TF_RIP(%rsp),%rcx /* original %rip */
514 movq TF_RSP(%rsp),%rsp /* user stack pointer */
515 xorl %r8d,%r8d /* zero the rest of GPRs */
525 3: /* AST scheduled. */
531 4: /* Requested full context restore, use doreti for that. */
536 * Here for CYA insurance, in case a "syscall" instruction gets
537 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
538 * to *something* if EFER_SCE is enabled.
540 IDTVEC(fast_syscall32)
544 * DB# handler is very similar to NM#, because 'mov/pop %ss' delay
545 * generation of exception until the next instruction is executed,
546 * which might be a kernel entry. So we must execute the handler
547 * on IST stack and be ready for non-kernel GSBASE.
551 movl $(T_TRCTRAP),TF_TRAPNO(%rsp)
552 movq $0,TF_ADDR(%rsp)
554 movq %rdi,TF_RDI(%rsp)
555 movq %rsi,TF_RSI(%rsp)
556 movq %rdx,TF_RDX(%rsp)
557 movq %rcx,TF_RCX(%rsp)
560 movq %rax,TF_RAX(%rsp)
561 movq %rbx,TF_RBX(%rsp)
562 movq %rbp,TF_RBP(%rsp)
563 movq %r10,TF_R10(%rsp)
564 movq %r11,TF_R11(%rsp)
565 movq %r12,TF_R12(%rsp)
566 movq %r13,TF_R13(%rsp)
567 movq %r14,TF_R14(%rsp)
568 movq %r15,TF_R15(%rsp)
570 movl $TF_HASSEGS,TF_FLAGS(%rsp)
572 testb $SEL_RPL_MASK,TF_CS(%rsp)
573 jnz dbg_fromuserspace
575 * We've interrupted the kernel. Preserve GS.base in %r12,
576 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
578 movl $MSR_GSBASE,%ecx
583 /* Retrieve and load the canonical value for GS.base. */
584 movq TF_SIZE(%rsp),%rdx
593 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
595 movl $MSR_IA32_SPEC_CTRL,%ecx
598 call handle_ibrs_entry
599 2: FAKE_MCOUNT(TF_RIP(%rsp))
603 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
607 movl $MSR_IA32_SPEC_CTRL,%ecx
610 * Put back the preserved MSR_GSBASE value.
612 3: movl $MSR_GSBASE,%ecx
623 * Switch to kernel GSBASE and kernel page table, and copy frame
624 * from the IST stack to the normal kernel stack, since trap()
625 * re-enables interrupts, and since we might trap on DB# while
633 1: movq PCPU(RSP0),%rax
640 call handle_ibrs_entry
641 movq PCPU(CURPCB),%rdi
642 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
643 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
645 cmpw $KUF32SEL,TF_FS(%rsp)
648 movq %rax,PCB_FSBASE(%rdi)
649 2: cmpw $KUG32SEL,TF_GS(%rsp)
651 movl $MSR_KGSBASE,%ecx
655 movq %rax,PCB_GSBASE(%rdi)
659 * NMI handling is special.
661 * First, NMIs do not respect the state of the processor's RFLAGS.IF
662 * bit. The NMI handler may be entered at any time, including when
663 * the processor is in a critical section with RFLAGS.IF == 0.
664 * The processor's GS.base value could be invalid on entry to the
667 * Second, the processor treats NMIs specially, blocking further NMIs
668 * until an 'iretq' instruction is executed. We thus need to execute
669 * the NMI handler with interrupts disabled, to prevent a nested interrupt
670 * from executing an 'iretq' instruction and inadvertently taking the
671 * processor out of NMI mode.
673 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
674 * GS.base value for the processor is stored just above the bottom of its
675 * NMI stack. For NMIs taken from kernel mode, the current value in
676 * the processor's GS.base is saved at entry to C-preserved register %r12,
677 * the canonical value for GS.base is then loaded into the processor, and
678 * the saved value is restored at exit time. For NMIs taken from user mode,
679 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
684 movl $(T_NMI),TF_TRAPNO(%rsp)
685 movq $0,TF_ADDR(%rsp)
687 movq %rdi,TF_RDI(%rsp)
688 movq %rsi,TF_RSI(%rsp)
689 movq %rdx,TF_RDX(%rsp)
690 movq %rcx,TF_RCX(%rsp)
693 movq %rax,TF_RAX(%rsp)
694 movq %rbx,TF_RBX(%rsp)
695 movq %rbp,TF_RBP(%rsp)
696 movq %r10,TF_R10(%rsp)
697 movq %r11,TF_R11(%rsp)
698 movq %r12,TF_R12(%rsp)
699 movq %r13,TF_R13(%rsp)
700 movq %r14,TF_R14(%rsp)
701 movq %r15,TF_R15(%rsp)
703 movl $TF_HASSEGS,TF_FLAGS(%rsp)
706 testb $SEL_RPL_MASK,TF_CS(%rsp)
707 jnz nmi_fromuserspace
709 * We've interrupted the kernel. Preserve GS.base in %r12,
710 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
712 movl $MSR_GSBASE,%ecx
717 /* Retrieve and load the canonical value for GS.base. */
718 movq TF_SIZE(%rsp),%rdx
727 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
729 movl $MSR_IA32_SPEC_CTRL,%ecx
732 call handle_ibrs_entry
742 1: call handle_ibrs_entry
743 movq PCPU(CURPCB),%rdi
746 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
747 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
749 cmpw $KUF32SEL,TF_FS(%rsp)
752 movq %rax,PCB_FSBASE(%rdi)
753 2: cmpw $KUG32SEL,TF_GS(%rsp)
755 movl $MSR_KGSBASE,%ecx
759 movq %rax,PCB_GSBASE(%rdi)
761 /* Note: this label is also used by ddb and gdb: */
763 FAKE_MCOUNT(TF_RIP(%rsp))
769 * Capture a userspace callchain if needed.
771 * - Check if the current trap was from user mode.
772 * - Check if the current thread is valid.
773 * - Check if the thread requires a user call chain to be
776 * We are still in NMI mode at this point.
779 jz nocallchain /* not from userspace */
780 movq PCPU(CURTHREAD),%rax
781 orq %rax,%rax /* curthread present? */
784 * Move execution to the regular kernel stack, because we
785 * committed to return through doreti.
787 movq %rsp,%rsi /* source stack pointer */
791 movq %rdx,%rdi /* destination stack pointer */
792 shrq $3,%rcx /* trap frame size in long words */
795 movsq /* copy trapframe */
796 movq %rdx,%rsp /* we are on the regular kstack */
798 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
801 * A user callchain is to be captured, so:
802 * - Take the processor out of "NMI" mode by faking an "iret",
803 * to allow for nested NMI interrupts.
804 * - Enable interrupts, so that copyin() can work.
807 pushq %rax /* tf_ss */
808 pushq %rdx /* tf_rsp (on kernel stack) */
809 pushfq /* tf_rflags */
811 pushq %rax /* tf_cs */
812 pushq $outofnmi /* tf_rip */
816 * At this point the processor has exited NMI mode and is running
817 * with interrupts turned off on the normal kernel stack.
819 * If a pending NMI gets recognized at or after this point, it
820 * will cause a kernel callchain to be traced.
822 * We turn interrupts back on, and call the user callchain capture hook.
827 movq PCPU(CURTHREAD),%rdi /* thread */
828 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
829 movq %rsp,%rdx /* frame */
835 testl %ebx,%ebx /* %ebx == 0 => return to userland */
838 * Restore speculation control MSR, if preserved.
840 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
844 movl $MSR_IA32_SPEC_CTRL,%ecx
847 * Put back the preserved MSR_GSBASE value.
849 1: movl $MSR_GSBASE,%ecx
854 cmpb $0, nmi_flush_l1d_sw(%rip)
856 call flush_l1d_sw /* bhyve L1TF assist */
863 * MC# handling is similar to NMI.
865 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
866 * can occur at any time with a GS.base value that does not correspond
867 * to the privilege level in CS.
869 * Machine checks are not unblocked by iretq, but it is best to run
870 * the handler with interrupts disabled since the exception may have
871 * interrupted a critical section.
873 * The MC# handler runs on its own stack (tss_ist3). The canonical
874 * GS.base value for the processor is stored just above the bottom of
875 * its MC# stack. For exceptions taken from kernel mode, the current
876 * value in the processor's GS.base is saved at entry to C-preserved
877 * register %r12, the canonical value for GS.base is then loaded into
878 * the processor, and the saved value is restored at exit time. For
879 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
880 * are used for swapping GS.base.
885 movl $(T_MCHK),TF_TRAPNO(%rsp)
886 movq $0,TF_ADDR(%rsp)
888 movq %rdi,TF_RDI(%rsp)
889 movq %rsi,TF_RSI(%rsp)
890 movq %rdx,TF_RDX(%rsp)
891 movq %rcx,TF_RCX(%rsp)
894 movq %rax,TF_RAX(%rsp)
895 movq %rbx,TF_RBX(%rsp)
896 movq %rbp,TF_RBP(%rsp)
897 movq %r10,TF_R10(%rsp)
898 movq %r11,TF_R11(%rsp)
899 movq %r12,TF_R12(%rsp)
900 movq %r13,TF_R13(%rsp)
901 movq %r14,TF_R14(%rsp)
902 movq %r15,TF_R15(%rsp)
904 movl $TF_HASSEGS,TF_FLAGS(%rsp)
907 testb $SEL_RPL_MASK,TF_CS(%rsp)
908 jnz mchk_fromuserspace
910 * We've interrupted the kernel. Preserve GS.base in %r12,
911 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
913 movl $MSR_GSBASE,%ecx
918 /* Retrieve and load the canonical value for GS.base. */
919 movq TF_SIZE(%rsp),%rdx
928 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
930 movl $MSR_IA32_SPEC_CTRL,%ecx
933 call handle_ibrs_entry
943 1: call handle_ibrs_entry
944 /* Note: this label is also used by ddb and gdb: */
946 FAKE_MCOUNT(TF_RIP(%rsp))
950 testl %ebx,%ebx /* %ebx == 0 => return to userland */
953 * Restore speculation control MSR, if preserved.
955 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
959 movl $MSR_IA32_SPEC_CTRL,%ecx
962 * Put back the preserved MSR_GSBASE value.
964 1: movl $MSR_GSBASE,%ecx
974 ENTRY(fork_trampoline)
975 movq %r12,%rdi /* function */
976 movq %rbx,%rsi /* arg1 */
977 movq %rsp,%rdx /* trapframe pointer */
980 jmp doreti /* Handle any ASTs */
983 * To efficiently implement classification of trap and interrupt handlers
984 * for profiling, there must be only trap handlers between the labels btrap
985 * and bintr, and only interrupt handlers between the labels bintr and
986 * eintr. This is implemented (partly) by including files that contain
987 * some of the handlers. Before including the files, set up a normal asm
988 * environment so that the included files doen't need to know that they are
992 #ifdef COMPAT_FREEBSD32
998 #include <amd64/ia32/ia32_exception.S>
1007 #include <amd64/amd64/apic_vector.S>
1015 #include <amd64/amd64/atpic_vector.S>
1022 * void doreti(struct trapframe)
1024 * Handle return from interrupts, traps and syscalls.
1028 .type doreti,@function
1031 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
1033 * Check if ASTs can be handled now.
1035 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
1036 jz doreti_exit /* can't handle ASTs now if not */
1040 * Check for ASTs atomically with returning. Disabling CPU
1041 * interrupts provides sufficient locking even in the SMP case,
1042 * since we will be informed of any new ASTs by an IPI.
1045 movq PCPU(CURTHREAD),%rax
1046 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
1049 movq %rsp,%rdi /* pass a pointer to the trapframe */
1054 * doreti_exit: pop registers, iret.
1056 * The segment register pop is a special case, since it may
1057 * fault if (for example) a sigreturn specifies bad segment
1058 * registers. The fault is handled in trap.c.
1062 movq PCPU(CURPCB),%r8
1065 * Do not reload segment registers for kernel.
1066 * Since we do not reload segments registers with sane
1067 * values on kernel entry, descriptors referenced by
1068 * segments registers might be not valid. This is fatal
1069 * for user mode, but is not a problem for the kernel.
1071 testb $SEL_RPL_MASK,TF_CS(%rsp)
1073 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
1075 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
1076 testl $TF_HASSEGS,TF_FLAGS(%rsp)
1080 /* Restore %fs and fsbase */
1081 movw TF_FS(%rsp),%ax
1087 movl $MSR_FSBASE,%ecx
1088 movl PCB_FSBASE(%r8),%eax
1089 movl PCB_FSBASE+4(%r8),%edx
1094 /* Restore %gs and gsbase */
1095 movw TF_GS(%rsp),%si
1098 movl $MSR_GSBASE,%ecx
1099 /* Save current kernel %gs base into %r12d:%r13d */
1106 /* Save user %gs base into %r14d:%r15d */
1110 /* Restore kernel %gs base */
1116 * Restore user %gs base, either from PCB if used for TLS, or
1117 * from the previously saved msr read.
1119 movl $MSR_KGSBASE,%ecx
1122 movl PCB_GSBASE(%r8),%eax
1123 movl PCB_GSBASE+4(%r8),%edx
1130 wrmsr /* May trap if non-canonical, but only for TLS. */
1133 movw TF_ES(%rsp),%es
1136 movw TF_DS(%rsp),%ds
1139 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1140 jz 2f /* keep running with kernel GS.base */
1142 call handle_ibrs_exit_rs
1147 movq PCPU(PTI_RSP0),%rdx
1149 movq %rax,PTI_RAX(%rdx)
1151 movq %rax,PTI_RDX(%rdx)
1152 movq TF_RIP(%rsp),%rax
1153 movq %rax,PTI_RIP(%rdx)
1154 movq TF_CS(%rsp),%rax
1155 movq %rax,PTI_CS(%rdx)
1156 movq TF_RFLAGS(%rsp),%rax
1157 movq %rax,PTI_RFLAGS(%rdx)
1158 movq TF_RSP(%rsp),%rax
1159 movq %rax,PTI_RSP(%rdx)
1160 movq TF_SS(%rsp),%rax
1161 movq %rax,PTI_SS(%rdx)
1162 movq PCPU(UCR3),%rax
1171 2: addq $TF_RIP,%rsp
1178 movw %ax,TF_DS(%rsp)
1179 movw %ax,TF_ES(%rsp)
1180 movw $KUF32SEL,TF_FS(%rsp)
1181 movw $KUG32SEL,TF_GS(%rsp)
1185 * doreti_iret_fault. Alternative return code for
1186 * the case where we get a fault in the doreti_exit code
1187 * above. trap() (amd64/amd64/trap.c) catches this specific
1188 * case, sends the process a signal and continues in the
1189 * corresponding place in the code below.
1192 .globl doreti_iret_fault
1194 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1195 movq %rax,TF_RAX(%rsp)
1196 movq %rdx,TF_RDX(%rsp)
1197 movq %rcx,TF_RCX(%rsp)
1198 call handle_ibrs_entry
1199 testb $SEL_RPL_MASK,TF_CS(%rsp)
1204 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1205 movq %rdi,TF_RDI(%rsp)
1206 movq %rsi,TF_RSI(%rsp)
1207 movq %r8,TF_R8(%rsp)
1208 movq %r9,TF_R9(%rsp)
1209 movq %rbx,TF_RBX(%rsp)
1210 movq %rbp,TF_RBP(%rsp)
1211 movq %r10,TF_R10(%rsp)
1212 movq %r11,TF_R11(%rsp)
1213 movq %r12,TF_R12(%rsp)
1214 movq %r13,TF_R13(%rsp)
1215 movq %r14,TF_R14(%rsp)
1216 movq %r15,TF_R15(%rsp)
1217 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1218 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1219 movq $0,TF_ADDR(%rsp)
1220 FAKE_MCOUNT(TF_RIP(%rsp))
1224 .globl ds_load_fault
1226 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1227 testb $SEL_RPL_MASK,TF_CS(%rsp)
1233 movw $KUDSEL,TF_DS(%rsp)
1237 .globl es_load_fault
1239 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1240 testl $PSL_I,TF_RFLAGS(%rsp)
1246 movw $KUDSEL,TF_ES(%rsp)
1250 .globl fs_load_fault
1252 testl $PSL_I,TF_RFLAGS(%rsp)
1256 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1259 movw $KUF32SEL,TF_FS(%rsp)
1263 .globl gs_load_fault
1266 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1267 testl $PSL_I,TF_RFLAGS(%rsp)
1273 movw $KUG32SEL,TF_GS(%rsp)
1277 .globl fsbase_load_fault
1279 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1280 testl $PSL_I,TF_RFLAGS(%rsp)
1286 movq PCPU(CURTHREAD),%r8
1287 movq TD_PCB(%r8),%r8
1288 movq $0,PCB_FSBASE(%r8)
1292 .globl gsbase_load_fault
1294 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1295 testl $PSL_I,TF_RFLAGS(%rsp)
1301 movq PCPU(CURTHREAD),%r8
1302 movq TD_PCB(%r8),%r8
1303 movq $0,PCB_GSBASE(%r8)
1307 ENTRY(end_exceptions)