2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_hwpmc_hooks.h"
46 #include <machine/psl.h>
47 #include <machine/asmacros.h>
48 #include <machine/trap.h>
49 #include <machine/specialreg.h>
50 #include <machine/pmap.h>
54 .globl dtrace_invop_jump_addr
56 .type dtrace_invop_jump_addr,@object
57 .size dtrace_invop_jump_addr,8
58 dtrace_invop_jump_addr:
60 .globl dtrace_invop_calltrap_addr
62 .type dtrace_invop_calltrap_addr,@object
63 .size dtrace_invop_calltrap_addr,8
64 dtrace_invop_calltrap_addr:
69 ENTRY(start_exceptions)
72 /*****************************************************************************/
74 /*****************************************************************************/
76 * Trap and fault vector routines.
78 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
79 * state on the stack but also disables interrupts. This is important for
80 * us for the use of the swapgs instruction. We cannot be interrupted
81 * until the GS.base value is correct. For most traps, we automatically
82 * then enable interrupts if the interrupted context had them enabled.
83 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
85 * The cpu will push a certain amount of state onto the kernel stack for
86 * the current process. See amd64/include/frame.h.
87 * This includes the current RFLAGS (status register, which includes
88 * the interrupt disable state prior to the trap), the code segment register,
89 * and the return instruction pointer are pushed by the cpu. The cpu
90 * will also push an 'error' code for certain traps. We push a dummy
91 * error code for those traps where the cpu doesn't in order to maintain
92 * a consistent frame. We also push a contrived 'trap number'.
94 * The CPU does not push the general registers, so we must do that, and we
95 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
96 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
97 * for the kernel mode operation shortly, without changes to the selector
98 * loaded. Since superuser long mode works with any selectors loaded into
99 * segment registers other then %cs, which makes them mostly unused in long
100 * mode, and kernel does not reference %fs, leave them alone. The segment
101 * registers are reloaded on return to the usermode.
104 /* Traps that we leave interrupts disabled for. */
105 .macro TRAP_NOEN l, trapno
106 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u
109 movl $\trapno,TF_TRAPNO(%rsp)
110 movq $0,TF_ADDR(%rsp)
115 movl $\trapno,TF_TRAPNO(%rsp)
116 movq $0,TF_ADDR(%rsp)
124 movl $\trapno,TF_TRAPNO(%rsp)
125 movq $0,TF_ADDR(%rsp)
127 testb $SEL_RPL_MASK,TF_CS(%rsp)
134 TRAP_NOEN bpt, T_BPTFLT
136 TRAP_NOEN dtrace_ret, T_DTRACE_RET
139 /* Regular traps; The cpu does not supply tf_err for these. */
140 .macro TRAP l, trapno
141 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u
144 movl $\trapno,TF_TRAPNO(%rsp)
145 movq $0,TF_ADDR(%rsp)
150 movl $\trapno,TF_TRAPNO(%rsp)
151 movq $0,TF_ADDR(%rsp)
159 movl $\trapno,TF_TRAPNO(%rsp)
160 movq $0,TF_ADDR(%rsp)
162 testb $SEL_RPL_MASK,TF_CS(%rsp)
172 TRAP ill, T_PRIVINFLT
174 TRAP fpusegm, T_FPOPFLT
175 TRAP rsvd, T_RESERVED
176 TRAP fpu, T_ARITHTRAP
179 /* This group of traps have tf_err already pushed by the cpu. */
180 .macro TRAP_ERR l, trapno
181 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u,has_err=1
184 movl $\trapno,TF_TRAPNO(%rsp)
185 movq $0,TF_ADDR(%rsp)
189 movl $\trapno,TF_TRAPNO(%rsp)
190 movq $0,TF_ADDR(%rsp)
196 movl $\trapno,TF_TRAPNO(%rsp)
197 movq $0,TF_ADDR(%rsp)
198 testb $SEL_RPL_MASK,TF_CS(%rsp)
205 TRAP_ERR tss, T_TSSFLT
206 TRAP_ERR align, T_ALIGNFLT
209 * alltraps_u/k entry points.
210 * SWAPGS must be already performed by prologue,
211 * if this is the first time in the kernel from userland.
212 * Reenable interrupts if they were enabled before the trap.
213 * This approximates SDT_SYS386TGT on the i386 port.
217 .type alltraps_u,@function
219 movq %rdi,TF_RDI(%rsp)
220 movq %rdx,TF_RDX(%rsp)
221 movq %rax,TF_RAX(%rsp)
222 movq %rcx,TF_RCX(%rsp)
223 movq PCPU(CURPCB),%rdi
224 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
225 call handle_ibrs_entry
226 jmp alltraps_save_segs
229 .type alltraps_k,@function
232 movq %rdi,TF_RDI(%rsp)
233 movq %rdx,TF_RDX(%rsp)
234 movq %rax,TF_RAX(%rsp)
235 movq %rcx,TF_RCX(%rsp)
238 testl $PSL_I,TF_RFLAGS(%rsp)
239 jz alltraps_pushregs_no_rax
241 alltraps_pushregs_no_rax:
242 movq %rsi,TF_RSI(%rsp)
245 movq %rbx,TF_RBX(%rsp)
246 movq %rbp,TF_RBP(%rsp)
247 movq %r10,TF_R10(%rsp)
248 movq %r11,TF_R11(%rsp)
249 movq %r12,TF_R12(%rsp)
250 movq %r13,TF_R13(%rsp)
251 movq %r14,TF_R14(%rsp)
252 movq %r15,TF_R15(%rsp)
253 movl $TF_HASSEGS,TF_FLAGS(%rsp)
255 andq $~(PSL_D | PSL_AC),(%rsp)
259 * DTrace Function Boundary Trace (fbt) probes are triggered
260 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
261 * interrupt. For all other trap types, just handle them in
264 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
265 jnz calltrap /* ignore userland traps */
266 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
269 /* Check if there is no DTrace hook registered. */
270 cmpq $0,dtrace_invop_jump_addr
274 * Set our jump address for the jump back in the event that
275 * the breakpoint wasn't caused by DTrace at all.
277 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
279 /* Jump to the code hooked in by DTrace. */
280 jmpq *dtrace_invop_jump_addr
283 .type calltrap,@function
287 jmp doreti /* Handle any pending ASTs */
290 * alltraps_noen_u/k entry points.
291 * Again, SWAPGS must be already performed by prologue, if needed.
292 * Unlike alltraps above, we want to leave the interrupts disabled.
293 * This corresponds to SDT_SYS386IGT on the i386 port.
296 .globl alltraps_noen_u
297 .type alltraps_noen_u,@function
299 movq %rdi,TF_RDI(%rsp)
300 movq PCPU(CURPCB),%rdi
301 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
302 jmp alltraps_noen_save_segs
304 .globl alltraps_noen_k
305 .type alltraps_noen_k,@function
308 movq %rdi,TF_RDI(%rsp)
309 alltraps_noen_save_segs:
311 movq %rdx,TF_RDX(%rsp)
312 movq %rax,TF_RAX(%rsp)
313 movq %rcx,TF_RCX(%rsp)
314 testb $SEL_RPL_MASK,TF_CS(%rsp)
315 jz alltraps_pushregs_no_rax
316 call handle_ibrs_entry
317 jmp alltraps_pushregs_no_rax
321 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
322 movq $0,TF_ADDR(%rsp)
324 movq %rdi,TF_RDI(%rsp)
325 movq %rsi,TF_RSI(%rsp)
326 movq %rdx,TF_RDX(%rsp)
327 movq %rcx,TF_RCX(%rsp)
330 movq %rax,TF_RAX(%rsp)
331 movq %rbx,TF_RBX(%rsp)
332 movq %rbp,TF_RBP(%rsp)
333 movq %r10,TF_R10(%rsp)
334 movq %r11,TF_R11(%rsp)
335 movq %r12,TF_R12(%rsp)
336 movq %r13,TF_R13(%rsp)
337 movq %r14,TF_R14(%rsp)
338 movq %r15,TF_R15(%rsp)
340 movl $TF_HASSEGS,TF_FLAGS(%rsp)
342 andq $~(PSL_D | PSL_AC),(%rsp)
344 movq TF_SIZE(%rsp),%rdx
347 movl $MSR_GSBASE,%ecx
350 movq %rax,PCPU(SAVED_UCR3)
356 call dblfault_handler
362 testb $SEL_RPL_MASK,PTI_CS-PTI_ERR(%rsp)
368 movq %rax,PCPU(SAVED_UCR3)
374 PTI_UUENTRY has_err=1
378 testb $SEL_RPL_MASK,TF_CS-TF_ERR(%rsp) /* Did we come from kernel? */
379 jnz page_u_swapgs /* already running with kernel GS.base */
383 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
384 movq %rax,TF_RAX(%rsp)
385 movq %rdx,TF_RDX(%rsp)
386 movq %rcx,TF_RCX(%rsp)
394 movq %rdi,TF_RDI(%rsp)
395 movq %rax,TF_RAX(%rsp)
396 movq %rdx,TF_RDX(%rsp)
397 movq %rcx,TF_RCX(%rsp)
398 movq PCPU(CURPCB),%rdi
399 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
400 movq PCPU(SAVED_UCR3),%rax
401 movq %rax,PCB_SAVED_UCR3(%rdi)
402 call handle_ibrs_entry
404 movq %cr2,%rdi /* preserve %cr2 before .. */
405 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
407 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
408 testl $PSL_I,TF_RFLAGS(%rsp)
409 jz alltraps_pushregs_no_rax
411 jmp alltraps_pushregs_no_rax
414 * We have to special-case this one. If we get a trap in doreti() at
415 * the iretq stage, we'll reenter with the wrong gs state. We'll have
416 * to do a special the swapgs in this case even coming from the kernel.
417 * XXX linux has a trap handler for their equivalent of load_gs().
419 * On the stack, we have the hardware interrupt frame to return
420 * to usermode (faulted) and another frame with error code, for
421 * fault. For PTI, copy both frames to the main thread stack.
422 * Handle the potential 16-byte alignment adjustment incurred
423 * during the second fault by copying both frames independently
424 * while unwinding the stack in between.
426 .macro PROTF_ENTRY name,trapno
437 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
438 MOVE_STACKS (PTI_SIZE / 8)
440 movq PTI_RSP(%rsp),%rsp
441 MOVE_STACKS (PTI_SIZE / 8 - 3)
449 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
450 je \name\()_pti_doreti
451 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
452 jz X\name /* lfence is not needed until %gs: use */
454 swapgs /* fence provided by PTI_UENTRY */
457 movl $\trapno,TF_TRAPNO(%rsp)
461 PROTF_ENTRY missing, T_SEGNPFLT
462 PROTF_ENTRY stk, T_STKFLT
463 PROTF_ENTRY prot, T_PROTFLT
466 movq $0,TF_ADDR(%rsp)
467 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
468 movq %rax,TF_RAX(%rsp)
469 movq %rdx,TF_RDX(%rsp)
470 movq %rcx,TF_RCX(%rsp)
473 leaq doreti_iret(%rip),%rdi
474 cmpq %rdi,TF_RIP(%rsp)
475 je 5f /* kernel but with user gsbase!! */
476 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
477 jz 6f /* already running with kernel GS.base */
478 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
480 cmpw $KUF32SEL,TF_FS(%rsp)
483 1: cmpw $KUG32SEL,TF_GS(%rsp)
488 movq PCPU(CURPCB),%rdi
489 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
491 cmpw $KUF32SEL,TF_FS(%rsp)
493 movq %rax,PCB_FSBASE(%rdi)
494 3: cmpw $KUG32SEL,TF_GS(%rsp)
496 movq %rdx,PCB_GSBASE(%rdi)
497 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* full iret from user #gp */
498 4: call handle_ibrs_entry
501 testl $PSL_I,TF_RFLAGS(%rsp)
502 jz alltraps_pushregs_no_rax
504 jmp alltraps_pushregs_no_rax
508 movq PCPU(CURPCB),%rdi
512 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
513 * and the new privilige level. We are still running on the old user stack
514 * pointer. We have to juggle a few things around to find our stack etc.
515 * swapgs gives us access to our PCPU space only.
517 * We do not support invoking this from a custom segment registers,
518 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
521 IDTVEC(fast_syscall_pti)
525 je fast_syscall_common
526 movq %rax,PCPU(SCRATCH_RAX)
529 movq PCPU(SCRATCH_RAX),%rax
530 jmp fast_syscall_common
536 movq %rsp,PCPU(SCRATCH_RSP)
538 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
540 /* defer TF_RSP till we have a spare register */
541 movq %r11,TF_RFLAGS(%rsp)
542 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
543 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
544 movq %r11,TF_RSP(%rsp) /* user stack pointer */
546 * Save a few arg registers early to free them for use in
547 * handle_ibrs_entry(). %r10 is especially tricky. It is not an
548 * arg register, but it holds the arg register %rcx. Profiling
549 * preserves %rcx, but may clobber %r10. Profiling may also
550 * clobber %r11, but %r11 (original %eflags) has been saved.
552 movq %rax,TF_RAX(%rsp) /* syscall number */
553 movq %rdx,TF_RDX(%rsp) /* arg 3 */
554 movq %r10,TF_RCX(%rsp) /* arg 4 */
556 call handle_ibrs_entry
557 movq PCPU(CURPCB),%r11
558 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
560 movq $KUDSEL,TF_SS(%rsp)
561 movq $KUCSEL,TF_CS(%rsp)
563 movq %rdi,TF_RDI(%rsp) /* arg 1 */
564 movq %rsi,TF_RSI(%rsp) /* arg 2 */
565 movq %r8,TF_R8(%rsp) /* arg 5 */
566 movq %r9,TF_R9(%rsp) /* arg 6 */
567 movq %rbx,TF_RBX(%rsp) /* C preserved */
568 movq %rbp,TF_RBP(%rsp) /* C preserved */
569 movq %r12,TF_R12(%rsp) /* C preserved */
570 movq %r13,TF_R13(%rsp) /* C preserved */
571 movq %r14,TF_R14(%rsp) /* C preserved */
572 movq %r15,TF_R15(%rsp) /* C preserved */
573 movl $TF_HASSEGS,TF_FLAGS(%rsp)
574 movq PCPU(CURTHREAD),%rdi
575 movq %rsp,TD_FRAME(%rdi)
576 movl TF_RFLAGS(%rsp),%esi
579 1: movq PCPU(CURPCB),%rax
580 /* Disable interrupts before testing PCB_FULL_IRET. */
582 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
584 /* Check for and handle AST's on return to userland. */
585 movq PCPU(CURTHREAD),%rax
586 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
588 call handle_ibrs_exit
590 /* Restore preserved registers. */
591 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
592 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
593 movq TF_RDX(%rsp),%rdx /* return value 2 */
594 movq TF_RAX(%rsp),%rax /* return value 1 */
595 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
596 movq TF_RIP(%rsp),%rcx /* original %rip */
597 movq TF_RSP(%rsp),%rsp /* user stack pointer */
598 xorl %r8d,%r8d /* zero the rest of GPRs */
603 andq PCPU(UCR3_LOAD_MASK),%r9
606 movq $PMAP_UCR3_NOMASK,PCPU(UCR3_LOAD_MASK)
610 3: /* AST scheduled. */
616 4: /* Requested full context restore, use doreti for that. */
620 * Here for CYA insurance, in case a "syscall" instruction gets
621 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
622 * to *something* if EFER_SCE is enabled.
624 IDTVEC(fast_syscall32)
628 * DB# handler is very similar to NM#, because 'mov/pop %ss' delay
629 * generation of exception until the next instruction is executed,
630 * which might be a kernel entry. So we must execute the handler
631 * on IST stack and be ready for non-kernel GSBASE.
635 movl $(T_TRCTRAP),TF_TRAPNO(%rsp)
636 movq $0,TF_ADDR(%rsp)
638 movq %rdi,TF_RDI(%rsp)
639 movq %rsi,TF_RSI(%rsp)
640 movq %rdx,TF_RDX(%rsp)
641 movq %rcx,TF_RCX(%rsp)
644 movq %rax,TF_RAX(%rsp)
645 movq %rbx,TF_RBX(%rsp)
646 movq %rbp,TF_RBP(%rsp)
647 movq %r10,TF_R10(%rsp)
648 movq %r11,TF_R11(%rsp)
649 movq %r12,TF_R12(%rsp)
650 movq %r13,TF_R13(%rsp)
651 movq %r14,TF_R14(%rsp)
652 movq %r15,TF_R15(%rsp)
654 movl $TF_HASSEGS,TF_FLAGS(%rsp)
656 andq $~(PSL_D | PSL_AC),(%rsp)
658 testb $SEL_RPL_MASK,TF_CS(%rsp)
659 jnz dbg_fromuserspace
662 * We've interrupted the kernel. See comment in NMI handler about
666 movl $MSR_GSBASE,%ecx
671 /* Retrieve and load the canonical value for GS.base. */
672 movq TF_SIZE(%rsp),%rdx
681 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
683 movl $MSR_IA32_SPEC_CTRL,%ecx
686 call handle_ibrs_entry
689 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
693 movl $MSR_IA32_SPEC_CTRL,%ecx
696 * Put back the preserved MSR_GSBASE value.
698 3: movl $MSR_GSBASE,%ecx
710 * Switch to kernel GSBASE and kernel page table, and copy frame
711 * from the IST stack to the normal kernel stack, since trap()
712 * re-enables interrupts, and since we might trap on DB# while
721 1: movq PCPU(RSP0),%rax
728 call handle_ibrs_entry
729 movq PCPU(CURPCB),%rdi
730 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
731 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
733 cmpw $KUF32SEL,TF_FS(%rsp)
736 movq %rax,PCB_FSBASE(%rdi)
737 2: cmpw $KUG32SEL,TF_GS(%rsp)
739 movl $MSR_KGSBASE,%ecx
743 movq %rax,PCB_GSBASE(%rdi)
747 * NMI handling is special.
749 * First, NMIs do not respect the state of the processor's RFLAGS.IF
750 * bit. The NMI handler may be entered at any time, including when
751 * the processor is in a critical section with RFLAGS.IF == 0.
752 * The processor's GS.base value could be invalid on entry to the
755 * Second, the processor treats NMIs specially, blocking further NMIs
756 * until an 'iretq' instruction is executed. We thus need to execute
757 * the NMI handler with interrupts disabled, to prevent a nested interrupt
758 * from executing an 'iretq' instruction and inadvertently taking the
759 * processor out of NMI mode.
761 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
762 * GS.base value for the processor is stored just above the bottom of its
763 * NMI stack. For NMIs taken from kernel mode, the current value in
764 * the processor's GS.base is saved at entry to C-preserved register %r12,
765 * the canonical value for GS.base is then loaded into the processor, and
766 * the saved value is restored at exit time. For NMIs taken from user mode,
767 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
772 movl $(T_NMI),TF_TRAPNO(%rsp)
773 movq $0,TF_ADDR(%rsp)
775 movq %rdi,TF_RDI(%rsp)
776 movq %rsi,TF_RSI(%rsp)
777 movq %rdx,TF_RDX(%rsp)
778 movq %rcx,TF_RCX(%rsp)
781 movq %rax,TF_RAX(%rsp)
782 movq %rbx,TF_RBX(%rsp)
783 movq %rbp,TF_RBP(%rsp)
784 movq %r10,TF_R10(%rsp)
785 movq %r11,TF_R11(%rsp)
786 movq %r12,TF_R12(%rsp)
787 movq %r13,TF_R13(%rsp)
788 movq %r14,TF_R14(%rsp)
789 movq %r15,TF_R15(%rsp)
791 movl $TF_HASSEGS,TF_FLAGS(%rsp)
793 andq $~(PSL_D | PSL_AC),(%rsp)
796 testb $SEL_RPL_MASK,TF_CS(%rsp)
797 jnz nmi_fromuserspace
799 * We've interrupted the kernel. Preserve in callee-saved regs:
802 * possibly lower half of MSR_IA32_SPEC_CTL in %r14d,
807 movl $MSR_GSBASE,%ecx
812 /* Retrieve and load the canonical value for GS.base. */
813 movq TF_SIZE(%rsp),%rdx
822 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
824 movl $MSR_IA32_SPEC_CTRL,%ecx
827 call handle_ibrs_entry
838 1: call handle_ibrs_entry
839 movq PCPU(CURPCB),%rdi
842 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
843 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
845 cmpw $KUF32SEL,TF_FS(%rsp)
848 movq %rax,PCB_FSBASE(%rdi)
849 2: cmpw $KUG32SEL,TF_GS(%rsp)
851 movl $MSR_KGSBASE,%ecx
855 movq %rax,PCB_GSBASE(%rdi)
857 /* Note: this label is also used by ddb and gdb: */
863 * Capture a userspace callchain if needed.
865 * - Check if the current trap was from user mode.
866 * - Check if the current thread is valid.
867 * - Check if the thread requires a user call chain to be
870 * We are still in NMI mode at this point.
873 jz nocallchain /* not from userspace */
874 movq PCPU(CURTHREAD),%rax
875 orq %rax,%rax /* curthread present? */
878 * Move execution to the regular kernel stack, because we
879 * committed to return through doreti.
881 movq %rsp,%rsi /* source stack pointer */
885 movq %rdx,%rdi /* destination stack pointer */
886 shrq $3,%rcx /* trap frame size in long words */
888 andq $~(PSL_D | PSL_AC),(%rsp)
891 movsq /* copy trapframe */
892 movq %rdx,%rsp /* we are on the regular kstack */
894 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
897 * A user callchain is to be captured, so:
898 * - Take the processor out of "NMI" mode by faking an "iret",
899 * to allow for nested NMI interrupts.
900 * - Enable interrupts, so that copyin() can work.
903 pushq %rax /* tf_ss */
904 pushq %rdx /* tf_rsp (on kernel stack) */
905 pushfq /* tf_rflags */
907 pushq %rax /* tf_cs */
908 pushq $outofnmi /* tf_rip */
912 * At this point the processor has exited NMI mode and is running
913 * with interrupts turned off on the normal kernel stack.
915 * If a pending NMI gets recognized at or after this point, it
916 * will cause a kernel callchain to be traced.
918 * We turn interrupts back on, and call the user callchain capture hook.
923 movq PCPU(CURTHREAD),%rdi /* thread */
924 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
925 movq %rsp,%rdx /* frame */
931 testl %ebx,%ebx /* %ebx != 0 => return to userland */
934 * Restore speculation control MSR, if preserved.
936 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
940 movl $MSR_IA32_SPEC_CTRL,%ecx
943 * Put back the preserved MSR_GSBASE value.
945 1: movl $MSR_GSBASE,%ecx
950 cmpb $0, nmi_flush_l1d_sw(%rip)
952 call flush_l1d_sw /* bhyve L1TF assist */
960 * MC# handling is similar to NMI.
962 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
963 * can occur at any time with a GS.base value that does not correspond
964 * to the privilege level in CS.
966 * Machine checks are not unblocked by iretq, but it is best to run
967 * the handler with interrupts disabled since the exception may have
968 * interrupted a critical section.
970 * The MC# handler runs on its own stack (tss_ist3). The canonical
971 * GS.base value for the processor is stored just above the bottom of
972 * its MC# stack. For exceptions taken from kernel mode, the current
973 * value in the processor's GS.base is saved at entry to C-preserved
974 * register %r12, the canonical value for GS.base is then loaded into
975 * the processor, and the saved value is restored at exit time. For
976 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
977 * are used for swapping GS.base.
982 movl $(T_MCHK),TF_TRAPNO(%rsp)
983 movq $0,TF_ADDR(%rsp)
985 movq %rdi,TF_RDI(%rsp)
986 movq %rsi,TF_RSI(%rsp)
987 movq %rdx,TF_RDX(%rsp)
988 movq %rcx,TF_RCX(%rsp)
991 movq %rax,TF_RAX(%rsp)
992 movq %rbx,TF_RBX(%rsp)
993 movq %rbp,TF_RBP(%rsp)
994 movq %r10,TF_R10(%rsp)
995 movq %r11,TF_R11(%rsp)
996 movq %r12,TF_R12(%rsp)
997 movq %r13,TF_R13(%rsp)
998 movq %r14,TF_R14(%rsp)
999 movq %r15,TF_R15(%rsp)
1001 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1003 andq $~(PSL_D | PSL_AC),(%rsp)
1006 testb $SEL_RPL_MASK,TF_CS(%rsp)
1007 jnz mchk_fromuserspace
1009 * We've interrupted the kernel. See comment in NMI handler about
1013 movl $MSR_GSBASE,%ecx
1018 /* Retrieve and load the canonical value for GS.base. */
1019 movq TF_SIZE(%rsp),%rdx
1024 movq PCPU(KCR3),%rax
1028 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
1030 movl $MSR_IA32_SPEC_CTRL,%ecx
1033 call handle_ibrs_entry
1039 movq PCPU(KCR3),%rax
1043 1: call handle_ibrs_entry
1044 /* Note: this label is also used by ddb and gdb: */
1048 testl %ebx,%ebx /* %ebx != 0 => return to userland */
1051 * Restore speculation control MSR, if preserved.
1053 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
1057 movl $MSR_IA32_SPEC_CTRL,%ecx
1060 * Put back the preserved MSR_GSBASE value.
1062 1: movl $MSR_GSBASE,%ecx
1073 ENTRY(fork_trampoline)
1074 movq %r12,%rdi /* function */
1075 movq %rbx,%rsi /* arg1 */
1076 movq %rsp,%rdx /* trapframe pointer */
1078 jmp doreti /* Handle any ASTs */
1081 * To efficiently implement classification of trap and interrupt handlers
1082 * for profiling, there must be only trap handlers between the labels btrap
1083 * and bintr, and only interrupt handlers between the labels bintr and
1084 * eintr. This is implemented (partly) by including files that contain
1085 * some of the handlers. Before including the files, set up a normal asm
1086 * environment so that the included files doen't need to know that they are
1090 #ifdef COMPAT_FREEBSD32
1096 #include <amd64/ia32/ia32_exception.S>
1103 #include <amd64/amd64/apic_vector.S>
1111 #include <amd64/amd64/atpic_vector.S>
1115 * void doreti(struct trapframe)
1117 * Handle return from interrupts, traps and syscalls.
1121 .type doreti,@function
1125 * Check if ASTs can be handled now.
1127 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
1128 jz doreti_exit /* can't handle ASTs now if not */
1132 * Check for ASTs atomically with returning. Disabling CPU
1133 * interrupts provides sufficient locking even in the SMP case,
1134 * since we will be informed of any new ASTs by an IPI.
1137 movq PCPU(CURTHREAD),%rax
1138 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
1141 movq %rsp,%rdi /* pass a pointer to the trapframe */
1146 * doreti_exit: pop registers, iret.
1148 * The segment register pop is a special case, since it may
1149 * fault if (for example) a sigreturn specifies bad segment
1150 * registers. The fault is handled in trap.c.
1153 movq PCPU(CURPCB),%r8
1156 * Do not reload segment registers for kernel.
1157 * Since we do not reload segments registers with sane
1158 * values on kernel entry, descriptors referenced by
1159 * segments registers might be not valid. This is fatal
1160 * for user mode, but is not a problem for the kernel.
1162 testb $SEL_RPL_MASK,TF_CS(%rsp)
1164 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
1166 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
1167 testl $TF_HASSEGS,TF_FLAGS(%rsp)
1171 /* Restore %fs and fsbase */
1172 movw TF_FS(%rsp),%ax
1178 movl $MSR_FSBASE,%ecx
1179 movl PCB_FSBASE(%r8),%eax
1180 movl PCB_FSBASE+4(%r8),%edx
1185 /* Restore %gs and gsbase */
1186 movw TF_GS(%rsp),%si
1189 movl $MSR_GSBASE,%ecx
1190 /* Save current kernel %gs base into %r12d:%r13d */
1197 /* Save user %gs base into %r14d:%r15d */
1201 /* Restore kernel %gs base */
1207 * Restore user %gs base, either from PCB if used for TLS, or
1208 * from the previously saved msr read.
1210 movl $MSR_KGSBASE,%ecx
1213 movl PCB_GSBASE(%r8),%eax
1214 movl PCB_GSBASE+4(%r8),%edx
1221 wrmsr /* May trap if non-canonical, but only for TLS. */
1224 movw TF_ES(%rsp),%es
1227 movw TF_DS(%rsp),%ds
1230 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1231 jz 2f /* keep running with kernel GS.base */
1233 call handle_ibrs_exit_rs
1238 movq PCPU(PTI_RSP0),%rdx
1240 movq %rax,PTI_RAX(%rdx)
1242 movq %rax,PTI_RDX(%rdx)
1243 movq TF_RIP(%rsp),%rax
1244 movq %rax,PTI_RIP(%rdx)
1245 movq TF_CS(%rsp),%rax
1246 movq %rax,PTI_CS(%rdx)
1247 movq TF_RFLAGS(%rsp),%rax
1248 movq %rax,PTI_RFLAGS(%rdx)
1249 movq TF_RSP(%rsp),%rax
1250 movq %rax,PTI_RSP(%rdx)
1251 movq TF_SS(%rsp),%rax
1252 movq %rax,PTI_SS(%rdx)
1253 movq PCPU(UCR3),%rax
1254 andq PCPU(UCR3_LOAD_MASK),%rax
1255 movq $PMAP_UCR3_NOMASK,PCPU(UCR3_LOAD_MASK)
1264 2: addq $TF_RIP,%rsp
1271 movw %ax,TF_DS(%rsp)
1272 movw %ax,TF_ES(%rsp)
1273 movw $KUF32SEL,TF_FS(%rsp)
1274 movw $KUG32SEL,TF_GS(%rsp)
1278 * doreti_iret_fault. Alternative return code for
1279 * the case where we get a fault in the doreti_exit code
1280 * above. trap() (amd64/amd64/trap.c) catches this specific
1281 * case, sends the process a signal and continues in the
1282 * corresponding place in the code below.
1285 .globl doreti_iret_fault
1287 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1288 movq %rax,TF_RAX(%rsp)
1289 movq %rdx,TF_RDX(%rsp)
1290 movq %rcx,TF_RCX(%rsp)
1291 call handle_ibrs_entry
1292 testb $SEL_RPL_MASK,TF_CS(%rsp)
1297 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1298 movq %rdi,TF_RDI(%rsp)
1299 movq %rsi,TF_RSI(%rsp)
1300 movq %r8,TF_R8(%rsp)
1301 movq %r9,TF_R9(%rsp)
1302 movq %rbx,TF_RBX(%rsp)
1303 movq %rbp,TF_RBP(%rsp)
1304 movq %r10,TF_R10(%rsp)
1305 movq %r11,TF_R11(%rsp)
1306 movq %r12,TF_R12(%rsp)
1307 movq %r13,TF_R13(%rsp)
1308 movq %r14,TF_R14(%rsp)
1309 movq %r15,TF_R15(%rsp)
1310 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1311 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1312 movq $0,TF_ADDR(%rsp)
1316 .globl ds_load_fault
1318 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1319 testb $SEL_RPL_MASK,TF_CS(%rsp)
1325 movw $KUDSEL,TF_DS(%rsp)
1329 .globl es_load_fault
1331 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1332 testl $PSL_I,TF_RFLAGS(%rsp)
1338 movw $KUDSEL,TF_ES(%rsp)
1342 .globl fs_load_fault
1344 testl $PSL_I,TF_RFLAGS(%rsp)
1348 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1351 movw $KUF32SEL,TF_FS(%rsp)
1355 .globl gs_load_fault
1358 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1359 testl $PSL_I,TF_RFLAGS(%rsp)
1365 movw $KUG32SEL,TF_GS(%rsp)
1369 .globl fsbase_load_fault
1371 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1372 testl $PSL_I,TF_RFLAGS(%rsp)
1378 movq PCPU(CURTHREAD),%r8
1379 movq TD_PCB(%r8),%r8
1380 movq $0,PCB_FSBASE(%r8)
1384 .globl gsbase_load_fault
1386 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1387 testl $PSL_I,TF_RFLAGS(%rsp)
1393 movq PCPU(CURTHREAD),%r8
1394 movq TD_PCB(%r8),%r8
1395 movq $0,PCB_GSBASE(%r8)
1399 ENTRY(end_exceptions)