2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_hwpmc_hooks.h"
46 #include <machine/psl.h>
47 #include <machine/asmacros.h>
48 #include <machine/trap.h>
49 #include <machine/specialreg.h>
50 #include <machine/pmap.h>
54 .globl dtrace_invop_jump_addr
56 .type dtrace_invop_jump_addr,@object
57 .size dtrace_invop_jump_addr,8
58 dtrace_invop_jump_addr:
60 .globl dtrace_invop_calltrap_addr
62 .type dtrace_invop_calltrap_addr,@object
63 .size dtrace_invop_calltrap_addr,8
64 dtrace_invop_calltrap_addr:
69 ENTRY(start_exceptions)
72 /*****************************************************************************/
74 /*****************************************************************************/
76 * Trap and fault vector routines.
78 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
79 * state on the stack but also disables interrupts. This is important for
80 * us for the use of the swapgs instruction. We cannot be interrupted
81 * until the GS.base value is correct. For most traps, we automatically
82 * then enable interrupts if the interrupted context had them enabled.
83 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
85 * The cpu will push a certain amount of state onto the kernel stack for
86 * the current process. See amd64/include/frame.h.
87 * This includes the current RFLAGS (status register, which includes
88 * the interrupt disable state prior to the trap), the code segment register,
89 * and the return instruction pointer are pushed by the cpu. The cpu
90 * will also push an 'error' code for certain traps. We push a dummy
91 * error code for those traps where the cpu doesn't in order to maintain
92 * a consistent frame. We also push a contrived 'trap number'.
94 * The CPU does not push the general registers, so we must do that, and we
95 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
96 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
97 * for the kernel mode operation shortly, without changes to the selector
98 * loaded. Since superuser long mode works with any selectors loaded into
99 * segment registers other then %cs, which makes them mostly unused in long
100 * mode, and kernel does not reference %fs, leave them alone. The segment
101 * registers are reloaded on return to the usermode.
104 /* Traps that we leave interrupts disabled for. */
105 .macro TRAP_NOEN l, trapno
106 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u
109 movl $\trapno,TF_TRAPNO(%rsp)
110 movq $0,TF_ADDR(%rsp)
115 movl $\trapno,TF_TRAPNO(%rsp)
116 movq $0,TF_ADDR(%rsp)
124 movl $\trapno,TF_TRAPNO(%rsp)
125 movq $0,TF_ADDR(%rsp)
127 testb $SEL_RPL_MASK,TF_CS(%rsp)
134 TRAP_NOEN bpt, T_BPTFLT
136 TRAP_NOEN dtrace_ret, T_DTRACE_RET
139 /* Regular traps; The cpu does not supply tf_err for these. */
140 .macro TRAP l, trapno
141 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u
144 movl $\trapno,TF_TRAPNO(%rsp)
145 movq $0,TF_ADDR(%rsp)
150 movl $\trapno,TF_TRAPNO(%rsp)
151 movq $0,TF_ADDR(%rsp)
159 movl $\trapno,TF_TRAPNO(%rsp)
160 movq $0,TF_ADDR(%rsp)
162 testb $SEL_RPL_MASK,TF_CS(%rsp)
172 TRAP ill, T_PRIVINFLT
174 TRAP fpusegm, T_FPOPFLT
175 TRAP rsvd, T_RESERVED
176 TRAP fpu, T_ARITHTRAP
179 /* This group of traps have tf_err already pushed by the cpu. */
180 .macro TRAP_ERR l, trapno
181 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u,has_err=1
184 movl $\trapno,TF_TRAPNO(%rsp)
185 movq $0,TF_ADDR(%rsp)
189 movl $\trapno,TF_TRAPNO(%rsp)
190 movq $0,TF_ADDR(%rsp)
196 movl $\trapno,TF_TRAPNO(%rsp)
197 movq $0,TF_ADDR(%rsp)
198 testb $SEL_RPL_MASK,TF_CS(%rsp)
205 TRAP_ERR tss, T_TSSFLT
206 TRAP_ERR align, T_ALIGNFLT
209 * alltraps_u/k entry points.
210 * SWAPGS must be already performed by prologue,
211 * if this is the first time in the kernel from userland.
212 * Reenable interrupts if they were enabled before the trap.
213 * This approximates SDT_SYS386TGT on the i386 port.
217 .type alltraps_u,@function
219 movq %rdi,TF_RDI(%rsp)
220 movq %rdx,TF_RDX(%rsp)
221 movq %rax,TF_RAX(%rsp)
222 movq %rcx,TF_RCX(%rsp)
223 movq PCPU(CURPCB),%rdi
224 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
225 call handle_ibrs_entry
226 jmp alltraps_save_segs
229 .type alltraps_k,@function
232 movq %rdi,TF_RDI(%rsp)
233 movq %rdx,TF_RDX(%rsp)
234 movq %rax,TF_RAX(%rsp)
235 movq %rcx,TF_RCX(%rsp)
238 testl $PSL_I,TF_RFLAGS(%rsp)
239 jz alltraps_pushregs_no_rax
241 alltraps_pushregs_no_rax:
242 movq %rsi,TF_RSI(%rsp)
245 movq %rbx,TF_RBX(%rsp)
246 movq %rbp,TF_RBP(%rsp)
247 movq %r10,TF_R10(%rsp)
248 movq %r11,TF_R11(%rsp)
249 movq %r12,TF_R12(%rsp)
250 movq %r13,TF_R13(%rsp)
251 movq %r14,TF_R14(%rsp)
252 movq %r15,TF_R15(%rsp)
253 movl $TF_HASSEGS,TF_FLAGS(%rsp)
255 andq $~(PSL_D | PSL_AC),(%rsp)
259 * DTrace Function Boundary Trace (fbt) probes are triggered
260 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
261 * interrupt. For all other trap types, just handle them in
264 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
265 jnz calltrap /* ignore userland traps */
266 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
269 /* Check if there is no DTrace hook registered. */
270 cmpq $0,dtrace_invop_jump_addr
274 * Set our jump address for the jump back in the event that
275 * the breakpoint wasn't caused by DTrace at all.
277 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
279 /* Jump to the code hooked in by DTrace. */
280 jmpq *dtrace_invop_jump_addr
283 .type calltrap,@function
289 jmp doreti /* Handle any pending ASTs */
292 * alltraps_noen_u/k entry points.
293 * Again, SWAPGS must be already performed by prologue, if needed.
294 * Unlike alltraps above, we want to leave the interrupts disabled.
295 * This corresponds to SDT_SYS386IGT on the i386 port.
298 .globl alltraps_noen_u
299 .type alltraps_noen_u,@function
301 movq %rdi,TF_RDI(%rsp)
302 movq PCPU(CURPCB),%rdi
303 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
304 jmp alltraps_noen_save_segs
306 .globl alltraps_noen_k
307 .type alltraps_noen_k,@function
310 movq %rdi,TF_RDI(%rsp)
311 alltraps_noen_save_segs:
313 movq %rdx,TF_RDX(%rsp)
314 movq %rax,TF_RAX(%rsp)
315 movq %rcx,TF_RCX(%rsp)
316 testb $SEL_RPL_MASK,TF_CS(%rsp)
317 jz alltraps_pushregs_no_rax
318 call handle_ibrs_entry
319 jmp alltraps_pushregs_no_rax
323 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
324 movq $0,TF_ADDR(%rsp)
326 movq %rdi,TF_RDI(%rsp)
327 movq %rsi,TF_RSI(%rsp)
328 movq %rdx,TF_RDX(%rsp)
329 movq %rcx,TF_RCX(%rsp)
332 movq %rax,TF_RAX(%rsp)
333 movq %rbx,TF_RBX(%rsp)
334 movq %rbp,TF_RBP(%rsp)
335 movq %r10,TF_R10(%rsp)
336 movq %r11,TF_R11(%rsp)
337 movq %r12,TF_R12(%rsp)
338 movq %r13,TF_R13(%rsp)
339 movq %r14,TF_R14(%rsp)
340 movq %r15,TF_R15(%rsp)
342 movl $TF_HASSEGS,TF_FLAGS(%rsp)
344 andq $~(PSL_D | PSL_AC),(%rsp)
346 movq TF_SIZE(%rsp),%rdx
349 movl $MSR_GSBASE,%ecx
352 movq %rax,PCPU(SAVED_UCR3)
359 call dblfault_handler
366 testb $SEL_RPL_MASK,PTI_CS-PTI_ERR(%rsp)
372 movq %rax,PCPU(SAVED_UCR3)
378 PTI_UUENTRY has_err=1
382 testb $SEL_RPL_MASK,TF_CS-TF_ERR(%rsp) /* Did we come from kernel? */
383 jnz page_u_swapgs /* already running with kernel GS.base */
387 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
388 movq %rax,TF_RAX(%rsp)
389 movq %rdx,TF_RDX(%rsp)
390 movq %rcx,TF_RCX(%rsp)
398 movq %rdi,TF_RDI(%rsp)
399 movq %rax,TF_RAX(%rsp)
400 movq %rdx,TF_RDX(%rsp)
401 movq %rcx,TF_RCX(%rsp)
402 movq PCPU(CURPCB),%rdi
403 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
404 movq PCPU(SAVED_UCR3),%rax
405 movq %rax,PCB_SAVED_UCR3(%rdi)
406 call handle_ibrs_entry
408 movq %cr2,%rdi /* preserve %cr2 before .. */
409 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
411 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
412 testl $PSL_I,TF_RFLAGS(%rsp)
413 jz alltraps_pushregs_no_rax
415 jmp alltraps_pushregs_no_rax
418 * We have to special-case this one. If we get a trap in doreti() at
419 * the iretq stage, we'll reenter with the wrong gs state. We'll have
420 * to do a special the swapgs in this case even coming from the kernel.
421 * XXX linux has a trap handler for their equivalent of load_gs().
423 * On the stack, we have the hardware interrupt frame to return
424 * to usermode (faulted) and another frame with error code, for
425 * fault. For PTI, copy both frames to the main thread stack.
426 * Handle the potential 16-byte alignment adjustment incurred
427 * during the second fault by copying both frames independently
428 * while unwinding the stack in between.
430 .macro PROTF_ENTRY name,trapno
441 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
442 MOVE_STACKS (PTI_SIZE / 8)
444 movq PTI_RSP(%rsp),%rsp
445 MOVE_STACKS (PTI_SIZE / 8 - 3)
453 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
454 je \name\()_pti_doreti
455 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
456 jz X\name /* lfence is not needed until %gs: use */
458 swapgs /* fence provided by PTI_UENTRY */
461 movl $\trapno,TF_TRAPNO(%rsp)
465 PROTF_ENTRY missing, T_SEGNPFLT
466 PROTF_ENTRY stk, T_STKFLT
467 PROTF_ENTRY prot, T_PROTFLT
470 movq $0,TF_ADDR(%rsp)
471 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
472 movq %rax,TF_RAX(%rsp)
473 movq %rdx,TF_RDX(%rsp)
474 movq %rcx,TF_RCX(%rsp)
477 leaq doreti_iret(%rip),%rdi
478 cmpq %rdi,TF_RIP(%rsp)
479 je 5f /* kernel but with user gsbase!! */
480 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
481 jz 6f /* already running with kernel GS.base */
482 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
484 cmpw $KUF32SEL,TF_FS(%rsp)
487 1: cmpw $KUG32SEL,TF_GS(%rsp)
492 movq PCPU(CURPCB),%rdi
493 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
495 cmpw $KUF32SEL,TF_FS(%rsp)
497 movq %rax,PCB_FSBASE(%rdi)
498 3: cmpw $KUG32SEL,TF_GS(%rsp)
500 movq %rdx,PCB_GSBASE(%rdi)
501 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* full iret from user #gp */
502 4: call handle_ibrs_entry
505 testl $PSL_I,TF_RFLAGS(%rsp)
506 jz alltraps_pushregs_no_rax
508 jmp alltraps_pushregs_no_rax
512 movq PCPU(CURPCB),%rdi
516 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
517 * and the new privilige level. We are still running on the old user stack
518 * pointer. We have to juggle a few things around to find our stack etc.
519 * swapgs gives us access to our PCPU space only.
521 * We do not support invoking this from a custom segment registers,
522 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
525 IDTVEC(fast_syscall_pti)
528 je fast_syscall_common
529 movq %rax,PCPU(SCRATCH_RAX)
532 movq PCPU(SCRATCH_RAX),%rax
533 jmp fast_syscall_common
538 movq %rsp,PCPU(SCRATCH_RSP)
540 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
542 /* defer TF_RSP till we have a spare register */
543 movq %r11,TF_RFLAGS(%rsp)
544 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
545 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
546 movq %r11,TF_RSP(%rsp) /* user stack pointer */
548 * Save a few arg registers early to free them for use in
549 * handle_ibrs_entry(). %r10 is especially tricky. It is not an
550 * arg register, but it holds the arg register %rcx. Profiling
551 * preserves %rcx, but may clobber %r10. Profiling may also
552 * clobber %r11, but %r11 (original %eflags) has been saved.
554 movq %rax,TF_RAX(%rsp) /* syscall number */
555 movq %rdx,TF_RDX(%rsp) /* arg 3 */
556 movq %r10,TF_RCX(%rsp) /* arg 4 */
558 call handle_ibrs_entry
559 movq PCPU(CURPCB),%r11
560 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
562 movq $KUDSEL,TF_SS(%rsp)
563 movq $KUCSEL,TF_CS(%rsp)
565 movq %rdi,TF_RDI(%rsp) /* arg 1 */
566 movq %rsi,TF_RSI(%rsp) /* arg 2 */
567 movq %r8,TF_R8(%rsp) /* arg 5 */
568 movq %r9,TF_R9(%rsp) /* arg 6 */
569 movq %rbx,TF_RBX(%rsp) /* C preserved */
570 movq %rbp,TF_RBP(%rsp) /* C preserved */
571 movq %r12,TF_R12(%rsp) /* C preserved */
572 movq %r13,TF_R13(%rsp) /* C preserved */
573 movq %r14,TF_R14(%rsp) /* C preserved */
574 movq %r15,TF_R15(%rsp) /* C preserved */
575 movl $TF_HASSEGS,TF_FLAGS(%rsp)
576 movq PCPU(CURTHREAD),%rdi
577 movq %rsp,TD_FRAME(%rdi)
578 movl TF_RFLAGS(%rsp),%esi
581 1: movq PCPU(CURPCB),%rax
582 /* Disable interrupts before testing PCB_FULL_IRET. */
584 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
586 /* Check for and handle AST's on return to userland. */
587 movq PCPU(CURTHREAD),%rax
588 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
590 call handle_ibrs_exit
592 /* Restore preserved registers. */
593 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
594 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
595 movq TF_RDX(%rsp),%rdx /* return value 2 */
596 movq TF_RAX(%rsp),%rax /* return value 1 */
597 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
598 movq TF_RIP(%rsp),%rcx /* original %rip */
599 movq TF_RSP(%rsp),%rsp /* user stack pointer */
600 xorl %r8d,%r8d /* zero the rest of GPRs */
605 andq PCPU(UCR3_LOAD_MASK),%r9
608 movq $PMAP_UCR3_NOMASK,PCPU(UCR3_LOAD_MASK)
612 3: /* AST scheduled. */
618 4: /* Requested full context restore, use doreti for that. */
622 * Here for CYA insurance, in case a "syscall" instruction gets
623 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
624 * to *something* if EFER_SCE is enabled.
626 IDTVEC(fast_syscall32)
630 * DB# handler is very similar to NM#, because 'mov/pop %ss' delay
631 * generation of exception until the next instruction is executed,
632 * which might be a kernel entry. So we must execute the handler
633 * on IST stack and be ready for non-kernel GSBASE.
637 movl $(T_TRCTRAP),TF_TRAPNO(%rsp)
638 movq $0,TF_ADDR(%rsp)
640 movq %rdi,TF_RDI(%rsp)
641 movq %rsi,TF_RSI(%rsp)
642 movq %rdx,TF_RDX(%rsp)
643 movq %rcx,TF_RCX(%rsp)
646 movq %rax,TF_RAX(%rsp)
647 movq %rbx,TF_RBX(%rsp)
648 movq %rbp,TF_RBP(%rsp)
649 movq %r10,TF_R10(%rsp)
650 movq %r11,TF_R11(%rsp)
651 movq %r12,TF_R12(%rsp)
652 movq %r13,TF_R13(%rsp)
653 movq %r14,TF_R14(%rsp)
654 movq %r15,TF_R15(%rsp)
656 movl $TF_HASSEGS,TF_FLAGS(%rsp)
658 andq $~(PSL_D | PSL_AC),(%rsp)
660 testb $SEL_RPL_MASK,TF_CS(%rsp)
661 jnz dbg_fromuserspace
664 * We've interrupted the kernel. See comment in NMI handler about
668 movl $MSR_GSBASE,%ecx
673 /* Retrieve and load the canonical value for GS.base. */
674 movq TF_SIZE(%rsp),%rdx
683 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
685 movl $MSR_IA32_SPEC_CTRL,%ecx
688 call handle_ibrs_entry
691 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
695 movl $MSR_IA32_SPEC_CTRL,%ecx
698 * Put back the preserved MSR_GSBASE value.
700 3: movl $MSR_GSBASE,%ecx
712 * Switch to kernel GSBASE and kernel page table, and copy frame
713 * from the IST stack to the normal kernel stack, since trap()
714 * re-enables interrupts, and since we might trap on DB# while
723 1: movq PCPU(RSP0),%rax
730 call handle_ibrs_entry
731 movq PCPU(CURPCB),%rdi
732 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
733 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
735 cmpw $KUF32SEL,TF_FS(%rsp)
738 movq %rax,PCB_FSBASE(%rdi)
739 2: cmpw $KUG32SEL,TF_GS(%rsp)
741 movl $MSR_KGSBASE,%ecx
745 movq %rax,PCB_GSBASE(%rdi)
749 * NMI handling is special.
751 * First, NMIs do not respect the state of the processor's RFLAGS.IF
752 * bit. The NMI handler may be entered at any time, including when
753 * the processor is in a critical section with RFLAGS.IF == 0.
754 * The processor's GS.base value could be invalid on entry to the
757 * Second, the processor treats NMIs specially, blocking further NMIs
758 * until an 'iretq' instruction is executed. We thus need to execute
759 * the NMI handler with interrupts disabled, to prevent a nested interrupt
760 * from executing an 'iretq' instruction and inadvertently taking the
761 * processor out of NMI mode.
763 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
764 * GS.base value for the processor is stored just above the bottom of its
765 * NMI stack. For NMIs taken from kernel mode, the current value in
766 * the processor's GS.base is saved at entry to C-preserved register %r12,
767 * the canonical value for GS.base is then loaded into the processor, and
768 * the saved value is restored at exit time. For NMIs taken from user mode,
769 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
774 movl $(T_NMI),TF_TRAPNO(%rsp)
775 movq $0,TF_ADDR(%rsp)
777 movq %rdi,TF_RDI(%rsp)
778 movq %rsi,TF_RSI(%rsp)
779 movq %rdx,TF_RDX(%rsp)
780 movq %rcx,TF_RCX(%rsp)
783 movq %rax,TF_RAX(%rsp)
784 movq %rbx,TF_RBX(%rsp)
785 movq %rbp,TF_RBP(%rsp)
786 movq %r10,TF_R10(%rsp)
787 movq %r11,TF_R11(%rsp)
788 movq %r12,TF_R12(%rsp)
789 movq %r13,TF_R13(%rsp)
790 movq %r14,TF_R14(%rsp)
791 movq %r15,TF_R15(%rsp)
793 movl $TF_HASSEGS,TF_FLAGS(%rsp)
795 andq $~(PSL_D | PSL_AC),(%rsp)
798 testb $SEL_RPL_MASK,TF_CS(%rsp)
799 jnz nmi_fromuserspace
801 * We've interrupted the kernel. Preserve in callee-saved regs:
804 * possibly lower half of MSR_IA32_SPEC_CTL in %r14d,
809 movl $MSR_GSBASE,%ecx
814 /* Retrieve and load the canonical value for GS.base. */
815 movq TF_SIZE(%rsp),%rdx
824 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
826 movl $MSR_IA32_SPEC_CTRL,%ecx
829 call handle_ibrs_entry
840 1: call handle_ibrs_entry
841 movq PCPU(CURPCB),%rdi
844 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
845 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
847 cmpw $KUF32SEL,TF_FS(%rsp)
850 movq %rax,PCB_FSBASE(%rdi)
851 2: cmpw $KUG32SEL,TF_GS(%rsp)
853 movl $MSR_KGSBASE,%ecx
857 movq %rax,PCB_GSBASE(%rdi)
859 /* Note: this label is also used by ddb and gdb: */
867 * Capture a userspace callchain if needed.
869 * - Check if the current trap was from user mode.
870 * - Check if the current thread is valid.
871 * - Check if the thread requires a user call chain to be
874 * We are still in NMI mode at this point.
877 jz nocallchain /* not from userspace */
878 movq PCPU(CURTHREAD),%rax
879 orq %rax,%rax /* curthread present? */
882 * Move execution to the regular kernel stack, because we
883 * committed to return through doreti.
885 movq %rsp,%rsi /* source stack pointer */
889 movq %rdx,%rdi /* destination stack pointer */
890 shrq $3,%rcx /* trap frame size in long words */
892 andq $~(PSL_D | PSL_AC),(%rsp)
895 movsq /* copy trapframe */
896 movq %rdx,%rsp /* we are on the regular kstack */
898 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
901 * A user callchain is to be captured, so:
902 * - Take the processor out of "NMI" mode by faking an "iret",
903 * to allow for nested NMI interrupts.
904 * - Enable interrupts, so that copyin() can work.
907 pushq %rax /* tf_ss */
908 pushq %rdx /* tf_rsp (on kernel stack) */
909 pushfq /* tf_rflags */
911 pushq %rax /* tf_cs */
912 pushq $outofnmi /* tf_rip */
916 * At this point the processor has exited NMI mode and is running
917 * with interrupts turned off on the normal kernel stack.
919 * If a pending NMI gets recognized at or after this point, it
920 * will cause a kernel callchain to be traced.
922 * We turn interrupts back on, and call the user callchain capture hook.
927 movq PCPU(CURTHREAD),%rdi /* thread */
928 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
929 movq %rsp,%rdx /* frame */
935 testl %ebx,%ebx /* %ebx != 0 => return to userland */
938 * Restore speculation control MSR, if preserved.
940 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
944 movl $MSR_IA32_SPEC_CTRL,%ecx
947 * Put back the preserved MSR_GSBASE value.
949 1: movl $MSR_GSBASE,%ecx
954 cmpb $0, nmi_flush_l1d_sw(%rip)
956 call flush_l1d_sw /* bhyve L1TF assist */
964 * MC# handling is similar to NMI.
966 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
967 * can occur at any time with a GS.base value that does not correspond
968 * to the privilege level in CS.
970 * Machine checks are not unblocked by iretq, but it is best to run
971 * the handler with interrupts disabled since the exception may have
972 * interrupted a critical section.
974 * The MC# handler runs on its own stack (tss_ist3). The canonical
975 * GS.base value for the processor is stored just above the bottom of
976 * its MC# stack. For exceptions taken from kernel mode, the current
977 * value in the processor's GS.base is saved at entry to C-preserved
978 * register %r12, the canonical value for GS.base is then loaded into
979 * the processor, and the saved value is restored at exit time. For
980 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
981 * are used for swapping GS.base.
986 movl $(T_MCHK),TF_TRAPNO(%rsp)
987 movq $0,TF_ADDR(%rsp)
989 movq %rdi,TF_RDI(%rsp)
990 movq %rsi,TF_RSI(%rsp)
991 movq %rdx,TF_RDX(%rsp)
992 movq %rcx,TF_RCX(%rsp)
995 movq %rax,TF_RAX(%rsp)
996 movq %rbx,TF_RBX(%rsp)
997 movq %rbp,TF_RBP(%rsp)
998 movq %r10,TF_R10(%rsp)
999 movq %r11,TF_R11(%rsp)
1000 movq %r12,TF_R12(%rsp)
1001 movq %r13,TF_R13(%rsp)
1002 movq %r14,TF_R14(%rsp)
1003 movq %r15,TF_R15(%rsp)
1005 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1007 andq $~(PSL_D | PSL_AC),(%rsp)
1010 testb $SEL_RPL_MASK,TF_CS(%rsp)
1011 jnz mchk_fromuserspace
1013 * We've interrupted the kernel. See comment in NMI handler about
1017 movl $MSR_GSBASE,%ecx
1022 /* Retrieve and load the canonical value for GS.base. */
1023 movq TF_SIZE(%rsp),%rdx
1028 movq PCPU(KCR3),%rax
1032 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
1034 movl $MSR_IA32_SPEC_CTRL,%ecx
1037 call handle_ibrs_entry
1043 movq PCPU(KCR3),%rax
1047 1: call handle_ibrs_entry
1048 /* Note: this label is also used by ddb and gdb: */
1054 testl %ebx,%ebx /* %ebx != 0 => return to userland */
1057 * Restore speculation control MSR, if preserved.
1059 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
1063 movl $MSR_IA32_SPEC_CTRL,%ecx
1066 * Put back the preserved MSR_GSBASE value.
1068 1: movl $MSR_GSBASE,%ecx
1079 ENTRY(fork_trampoline)
1080 movq %r12,%rdi /* function */
1081 movq %rbx,%rsi /* arg1 */
1082 movq %rsp,%rdx /* trapframe pointer */
1084 jmp doreti /* Handle any ASTs */
1087 * To efficiently implement classification of trap and interrupt handlers
1088 * for profiling, there must be only trap handlers between the labels btrap
1089 * and bintr, and only interrupt handlers between the labels bintr and
1090 * eintr. This is implemented (partly) by including files that contain
1091 * some of the handlers. Before including the files, set up a normal asm
1092 * environment so that the included files doen't need to know that they are
1096 #ifdef COMPAT_FREEBSD32
1102 #include <amd64/ia32/ia32_exception.S>
1109 #include <amd64/amd64/apic_vector.S>
1117 #include <amd64/amd64/atpic_vector.S>
1121 * void doreti(struct trapframe)
1123 * Handle return from interrupts, traps and syscalls.
1127 .type doreti,@function
1131 * Check if ASTs can be handled now.
1133 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
1134 jz doreti_exit /* can't handle ASTs now if not */
1138 * Check for ASTs atomically with returning. Disabling CPU
1139 * interrupts provides sufficient locking even in the SMP case,
1140 * since we will be informed of any new ASTs by an IPI.
1143 movq PCPU(CURTHREAD),%rax
1144 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
1147 movq %rsp,%rdi /* pass a pointer to the trapframe */
1152 * doreti_exit: pop registers, iret.
1154 * The segment register pop is a special case, since it may
1155 * fault if (for example) a sigreturn specifies bad segment
1156 * registers. The fault is handled in trap.c.
1159 movq PCPU(CURPCB),%r8
1162 * Do not reload segment registers for kernel.
1163 * Since we do not reload segments registers with sane
1164 * values on kernel entry, descriptors referenced by
1165 * segments registers might be not valid. This is fatal
1166 * for user mode, but is not a problem for the kernel.
1168 testb $SEL_RPL_MASK,TF_CS(%rsp)
1170 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
1172 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
1173 testl $TF_HASSEGS,TF_FLAGS(%rsp)
1177 /* Restore %fs and fsbase */
1178 movw TF_FS(%rsp),%ax
1184 movl $MSR_FSBASE,%ecx
1185 movl PCB_FSBASE(%r8),%eax
1186 movl PCB_FSBASE+4(%r8),%edx
1191 /* Restore %gs and gsbase */
1192 movw TF_GS(%rsp),%si
1195 movl $MSR_GSBASE,%ecx
1196 /* Save current kernel %gs base into %r12d:%r13d */
1203 /* Save user %gs base into %r14d:%r15d */
1207 /* Restore kernel %gs base */
1213 * Restore user %gs base, either from PCB if used for TLS, or
1214 * from the previously saved msr read.
1216 movl $MSR_KGSBASE,%ecx
1219 movl PCB_GSBASE(%r8),%eax
1220 movl PCB_GSBASE+4(%r8),%edx
1227 wrmsr /* May trap if non-canonical, but only for TLS. */
1230 movw TF_ES(%rsp),%es
1233 movw TF_DS(%rsp),%ds
1236 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1237 jz 2f /* keep running with kernel GS.base */
1239 call handle_ibrs_exit_rs
1244 movq PCPU(PTI_RSP0),%rdx
1246 movq %rax,PTI_RAX(%rdx)
1248 movq %rax,PTI_RDX(%rdx)
1249 movq TF_RIP(%rsp),%rax
1250 movq %rax,PTI_RIP(%rdx)
1251 movq TF_CS(%rsp),%rax
1252 movq %rax,PTI_CS(%rdx)
1253 movq TF_RFLAGS(%rsp),%rax
1254 movq %rax,PTI_RFLAGS(%rdx)
1255 movq TF_RSP(%rsp),%rax
1256 movq %rax,PTI_RSP(%rdx)
1257 movq TF_SS(%rsp),%rax
1258 movq %rax,PTI_SS(%rdx)
1259 movq PCPU(UCR3),%rax
1260 andq PCPU(UCR3_LOAD_MASK),%rax
1261 movq $PMAP_UCR3_NOMASK,PCPU(UCR3_LOAD_MASK)
1270 2: addq $TF_RIP,%rsp
1277 movw %ax,TF_DS(%rsp)
1278 movw %ax,TF_ES(%rsp)
1279 movw $KUF32SEL,TF_FS(%rsp)
1280 movw $KUG32SEL,TF_GS(%rsp)
1284 * doreti_iret_fault. Alternative return code for
1285 * the case where we get a fault in the doreti_exit code
1286 * above. trap() (amd64/amd64/trap.c) catches this specific
1287 * case, sends the process a signal and continues in the
1288 * corresponding place in the code below.
1291 .globl doreti_iret_fault
1293 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1294 movq %rax,TF_RAX(%rsp)
1295 movq %rdx,TF_RDX(%rsp)
1296 movq %rcx,TF_RCX(%rsp)
1297 call handle_ibrs_entry
1298 testb $SEL_RPL_MASK,TF_CS(%rsp)
1303 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1304 movq %rdi,TF_RDI(%rsp)
1305 movq %rsi,TF_RSI(%rsp)
1306 movq %r8,TF_R8(%rsp)
1307 movq %r9,TF_R9(%rsp)
1308 movq %rbx,TF_RBX(%rsp)
1309 movq %rbp,TF_RBP(%rsp)
1310 movq %r10,TF_R10(%rsp)
1311 movq %r11,TF_R11(%rsp)
1312 movq %r12,TF_R12(%rsp)
1313 movq %r13,TF_R13(%rsp)
1314 movq %r14,TF_R14(%rsp)
1315 movq %r15,TF_R15(%rsp)
1316 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1317 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1318 movq $0,TF_ADDR(%rsp)
1322 .globl ds_load_fault
1324 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1325 testb $SEL_RPL_MASK,TF_CS(%rsp)
1331 movw $KUDSEL,TF_DS(%rsp)
1335 .globl es_load_fault
1337 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1338 testl $PSL_I,TF_RFLAGS(%rsp)
1344 movw $KUDSEL,TF_ES(%rsp)
1348 .globl fs_load_fault
1350 testl $PSL_I,TF_RFLAGS(%rsp)
1354 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1357 movw $KUF32SEL,TF_FS(%rsp)
1361 .globl gs_load_fault
1364 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1365 testl $PSL_I,TF_RFLAGS(%rsp)
1371 movw $KUG32SEL,TF_GS(%rsp)
1375 .globl fsbase_load_fault
1377 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1378 testl $PSL_I,TF_RFLAGS(%rsp)
1384 movq PCPU(CURTHREAD),%r8
1385 movq TD_PCB(%r8),%r8
1386 movq $0,PCB_FSBASE(%r8)
1390 .globl gsbase_load_fault
1392 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1393 testl $PSL_I,TF_RFLAGS(%rsp)
1399 movq PCPU(CURTHREAD),%r8
1400 movq TD_PCB(%r8),%r8
1401 movq $0,PCB_GSBASE(%r8)
1405 ENTRY(end_exceptions)