2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_hwpmc_hooks.h"
46 #include <machine/psl.h>
47 #include <machine/asmacros.h>
48 #include <machine/trap.h>
49 #include <machine/specialreg.h>
53 .globl dtrace_invop_jump_addr
55 .type dtrace_invop_jump_addr,@object
56 .size dtrace_invop_jump_addr,8
57 dtrace_invop_jump_addr:
59 .globl dtrace_invop_calltrap_addr
61 .type dtrace_invop_calltrap_addr,@object
62 .size dtrace_invop_calltrap_addr,8
63 dtrace_invop_calltrap_addr:
68 ENTRY(start_exceptions)
71 /*****************************************************************************/
73 /*****************************************************************************/
75 * Trap and fault vector routines.
77 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
78 * state on the stack but also disables interrupts. This is important for
79 * us for the use of the swapgs instruction. We cannot be interrupted
80 * until the GS.base value is correct. For most traps, we automatically
81 * then enable interrupts if the interrupted context had them enabled.
82 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
84 * The cpu will push a certain amount of state onto the kernel stack for
85 * the current process. See amd64/include/frame.h.
86 * This includes the current RFLAGS (status register, which includes
87 * the interrupt disable state prior to the trap), the code segment register,
88 * and the return instruction pointer are pushed by the cpu. The cpu
89 * will also push an 'error' code for certain traps. We push a dummy
90 * error code for those traps where the cpu doesn't in order to maintain
91 * a consistent frame. We also push a contrived 'trap number'.
93 * The CPU does not push the general registers, so we must do that, and we
94 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
95 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
96 * for the kernel mode operation shortly, without changes to the selector
97 * loaded. Since superuser long mode works with any selectors loaded into
98 * segment registers other then %cs, which makes them mostly unused in long
99 * mode, and kernel does not reference %fs, leave them alone. The segment
100 * registers are reloaded on return to the usermode.
106 /* Traps that we leave interrupts disabled for. */
107 .macro TRAP_NOEN l, trapno
108 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u
111 movl $\trapno,TF_TRAPNO(%rsp)
112 movq $0,TF_ADDR(%rsp)
117 movl $\trapno,TF_TRAPNO(%rsp)
118 movq $0,TF_ADDR(%rsp)
126 movl $\trapno,TF_TRAPNO(%rsp)
127 movq $0,TF_ADDR(%rsp)
129 testb $SEL_RPL_MASK,TF_CS(%rsp)
136 TRAP_NOEN bpt, T_BPTFLT
138 TRAP_NOEN dtrace_ret, T_DTRACE_RET
141 /* Regular traps; The cpu does not supply tf_err for these. */
142 .macro TRAP l, trapno
143 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u
146 movl $\trapno,TF_TRAPNO(%rsp)
147 movq $0,TF_ADDR(%rsp)
152 movl $\trapno,TF_TRAPNO(%rsp)
153 movq $0,TF_ADDR(%rsp)
161 movl $\trapno,TF_TRAPNO(%rsp)
162 movq $0,TF_ADDR(%rsp)
164 testb $SEL_RPL_MASK,TF_CS(%rsp)
174 TRAP ill, T_PRIVINFLT
176 TRAP fpusegm, T_FPOPFLT
177 TRAP rsvd, T_RESERVED
178 TRAP fpu, T_ARITHTRAP
181 /* This group of traps have tf_err already pushed by the cpu. */
182 .macro TRAP_ERR l, trapno
183 PTI_ENTRY \l,\l\()_pti_k,\l\()_pti_u,has_err=1
186 movl $\trapno,TF_TRAPNO(%rsp)
187 movq $0,TF_ADDR(%rsp)
191 movl $\trapno,TF_TRAPNO(%rsp)
192 movq $0,TF_ADDR(%rsp)
198 movl $\trapno,TF_TRAPNO(%rsp)
199 movq $0,TF_ADDR(%rsp)
200 testb $SEL_RPL_MASK,TF_CS(%rsp)
207 TRAP_ERR tss, T_TSSFLT
208 TRAP_ERR align, T_ALIGNFLT
211 * alltraps_u/k entry points.
212 * SWAPGS must be already performed by prologue,
213 * if this is the first time in the kernel from userland.
214 * Reenable interrupts if they were enabled before the trap.
215 * This approximates SDT_SYS386TGT on the i386 port.
219 .type alltraps_u,@function
221 movq %rdi,TF_RDI(%rsp)
222 movq %rdx,TF_RDX(%rsp)
223 movq %rax,TF_RAX(%rsp)
224 movq %rcx,TF_RCX(%rsp)
225 movq PCPU(CURPCB),%rdi
226 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
227 call handle_ibrs_entry
228 jmp alltraps_save_segs
231 .type alltraps_k,@function
234 movq %rdi,TF_RDI(%rsp)
235 movq %rdx,TF_RDX(%rsp)
236 movq %rax,TF_RAX(%rsp)
237 movq %rcx,TF_RCX(%rsp)
240 testl $PSL_I,TF_RFLAGS(%rsp)
241 jz alltraps_pushregs_no_rax
243 alltraps_pushregs_no_rax:
244 movq %rsi,TF_RSI(%rsp)
247 movq %rbx,TF_RBX(%rsp)
248 movq %rbp,TF_RBP(%rsp)
249 movq %r10,TF_R10(%rsp)
250 movq %r11,TF_R11(%rsp)
251 movq %r12,TF_R12(%rsp)
252 movq %r13,TF_R13(%rsp)
253 movq %r14,TF_R14(%rsp)
254 movq %r15,TF_R15(%rsp)
255 movl $TF_HASSEGS,TF_FLAGS(%rsp)
257 andq $~(PSL_D | PSL_AC),(%rsp)
259 FAKE_MCOUNT(TF_RIP(%rsp))
262 * DTrace Function Boundary Trace (fbt) probes are triggered
263 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
264 * interrupt. For all other trap types, just handle them in
267 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
268 jnz calltrap /* ignore userland traps */
269 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
272 /* Check if there is no DTrace hook registered. */
273 cmpq $0,dtrace_invop_jump_addr
277 * Set our jump address for the jump back in the event that
278 * the breakpoint wasn't caused by DTrace at all.
280 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
282 /* Jump to the code hooked in by DTrace. */
283 jmpq *dtrace_invop_jump_addr
286 .type calltrap,@function
291 jmp doreti /* Handle any pending ASTs */
294 * alltraps_noen_u/k entry points.
295 * Again, SWAPGS must be already performed by prologue, if needed.
296 * Unlike alltraps above, we want to leave the interrupts disabled.
297 * This corresponds to SDT_SYS386IGT on the i386 port.
300 .globl alltraps_noen_u
301 .type alltraps_noen_u,@function
303 movq %rdi,TF_RDI(%rsp)
304 movq PCPU(CURPCB),%rdi
305 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
306 jmp alltraps_noen_save_segs
308 .globl alltraps_noen_k
309 .type alltraps_noen_k,@function
312 movq %rdi,TF_RDI(%rsp)
313 alltraps_noen_save_segs:
315 movq %rdx,TF_RDX(%rsp)
316 movq %rax,TF_RAX(%rsp)
317 movq %rcx,TF_RCX(%rsp)
318 testb $SEL_RPL_MASK,TF_CS(%rsp)
319 jz alltraps_pushregs_no_rax
320 call handle_ibrs_entry
321 jmp alltraps_pushregs_no_rax
325 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
326 movq $0,TF_ADDR(%rsp)
328 movq %rdi,TF_RDI(%rsp)
329 movq %rsi,TF_RSI(%rsp)
330 movq %rdx,TF_RDX(%rsp)
331 movq %rcx,TF_RCX(%rsp)
334 movq %rax,TF_RAX(%rsp)
335 movq %rbx,TF_RBX(%rsp)
336 movq %rbp,TF_RBP(%rsp)
337 movq %r10,TF_R10(%rsp)
338 movq %r11,TF_R11(%rsp)
339 movq %r12,TF_R12(%rsp)
340 movq %r13,TF_R13(%rsp)
341 movq %r14,TF_R14(%rsp)
342 movq %r15,TF_R15(%rsp)
344 movl $TF_HASSEGS,TF_FLAGS(%rsp)
346 andq $~(PSL_D | PSL_AC),(%rsp)
348 movq TF_SIZE(%rsp),%rdx
351 movl $MSR_GSBASE,%ecx
354 movq %rax,PCPU(SAVED_UCR3)
360 call dblfault_handler
366 testb $SEL_RPL_MASK,PTI_CS-PTI_ERR(%rsp)
372 movq %rax,PCPU(SAVED_UCR3)
378 PTI_UUENTRY has_err=1
382 testb $SEL_RPL_MASK,TF_CS-TF_ERR(%rsp) /* Did we come from kernel? */
383 jnz page_u_swapgs /* already running with kernel GS.base */
387 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
388 movq %rax,TF_RAX(%rsp)
389 movq %rdx,TF_RDX(%rsp)
390 movq %rcx,TF_RCX(%rsp)
398 movq %rdi,TF_RDI(%rsp)
399 movq %rax,TF_RAX(%rsp)
400 movq %rdx,TF_RDX(%rsp)
401 movq %rcx,TF_RCX(%rsp)
402 movq PCPU(CURPCB),%rdi
403 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
404 movq PCPU(SAVED_UCR3),%rax
405 movq %rax,PCB_SAVED_UCR3(%rdi)
406 call handle_ibrs_entry
408 movq %cr2,%rdi /* preserve %cr2 before .. */
409 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
411 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
412 testl $PSL_I,TF_RFLAGS(%rsp)
413 jz alltraps_pushregs_no_rax
415 jmp alltraps_pushregs_no_rax
418 * We have to special-case this one. If we get a trap in doreti() at
419 * the iretq stage, we'll reenter with the wrong gs state. We'll have
420 * to do a special the swapgs in this case even coming from the kernel.
421 * XXX linux has a trap handler for their equivalent of load_gs().
423 * On the stack, we have the hardware interrupt frame to return
424 * to usermode (faulted) and another frame with error code, for
425 * fault. For PTI, copy both frames to the main thread stack.
426 * Handle the potential 16-byte alignment adjustment incurred
427 * during the second fault by copying both frames independently
428 * while unwinding the stack in between.
430 .macro PROTF_ENTRY name,trapno
441 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
442 MOVE_STACKS (PTI_SIZE / 8)
444 movq PTI_RSP(%rsp),%rsp
445 MOVE_STACKS (PTI_SIZE / 8 - 3)
453 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
454 je \name\()_pti_doreti
455 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
456 jz X\name /* lfence is not needed until %gs: use */
458 swapgs /* fence provided by PTI_UENTRY */
461 movl $\trapno,TF_TRAPNO(%rsp)
465 PROTF_ENTRY missing, T_SEGNPFLT
466 PROTF_ENTRY stk, T_STKFLT
467 PROTF_ENTRY prot, T_PROTFLT
470 movq $0,TF_ADDR(%rsp)
471 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
472 movq %rax,TF_RAX(%rsp)
473 movq %rdx,TF_RDX(%rsp)
474 movq %rcx,TF_RCX(%rsp)
477 leaq doreti_iret(%rip),%rdi
478 cmpq %rdi,TF_RIP(%rsp)
479 je 5f /* kernel but with user gsbase!! */
480 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
481 jz 6f /* already running with kernel GS.base */
482 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
484 cmpw $KUF32SEL,TF_FS(%rsp)
487 1: cmpw $KUG32SEL,TF_GS(%rsp)
492 movq PCPU(CURPCB),%rdi
493 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
495 cmpw $KUF32SEL,TF_FS(%rsp)
497 movq %rax,PCB_FSBASE(%rdi)
498 3: cmpw $KUG32SEL,TF_GS(%rsp)
500 movq %rdx,PCB_GSBASE(%rdi)
501 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* full iret from user #gp */
502 4: call handle_ibrs_entry
505 testl $PSL_I,TF_RFLAGS(%rsp)
506 jz alltraps_pushregs_no_rax
508 jmp alltraps_pushregs_no_rax
512 movq PCPU(CURPCB),%rdi
516 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
517 * and the new privilige level. We are still running on the old user stack
518 * pointer. We have to juggle a few things around to find our stack etc.
519 * swapgs gives us access to our PCPU space only.
521 * We do not support invoking this from a custom segment registers,
522 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
525 IDTVEC(fast_syscall_pti)
528 movq %rax,PCPU(SCRATCH_RAX)
530 je fast_syscall_common
533 jmp fast_syscall_common
538 movq %rax,PCPU(SCRATCH_RAX)
540 movq %rsp,PCPU(SCRATCH_RSP)
542 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
544 /* defer TF_RSP till we have a spare register */
545 movq %r11,TF_RFLAGS(%rsp)
546 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
547 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
548 movq %r11,TF_RSP(%rsp) /* user stack pointer */
549 movq PCPU(SCRATCH_RAX),%rax
551 * Save a few arg registers early to free them for use in
552 * handle_ibrs_entry(). %r10 is especially tricky. It is not an
553 * arg register, but it holds the arg register %rcx. Profiling
554 * preserves %rcx, but may clobber %r10. Profiling may also
555 * clobber %r11, but %r11 (original %eflags) has been saved.
557 movq %rax,TF_RAX(%rsp) /* syscall number */
558 movq %rdx,TF_RDX(%rsp) /* arg 3 */
559 movq %r10,TF_RCX(%rsp) /* arg 4 */
561 call handle_ibrs_entry
562 movq PCPU(CURPCB),%r11
563 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
565 movq $KUDSEL,TF_SS(%rsp)
566 movq $KUCSEL,TF_CS(%rsp)
568 movq %rdi,TF_RDI(%rsp) /* arg 1 */
569 movq %rsi,TF_RSI(%rsp) /* arg 2 */
570 movq %r8,TF_R8(%rsp) /* arg 5 */
571 movq %r9,TF_R9(%rsp) /* arg 6 */
572 movq %rbx,TF_RBX(%rsp) /* C preserved */
573 movq %rbp,TF_RBP(%rsp) /* C preserved */
574 movq %r12,TF_R12(%rsp) /* C preserved */
575 movq %r13,TF_R13(%rsp) /* C preserved */
576 movq %r14,TF_R14(%rsp) /* C preserved */
577 movq %r15,TF_R15(%rsp) /* C preserved */
578 movl $TF_HASSEGS,TF_FLAGS(%rsp)
579 FAKE_MCOUNT(TF_RIP(%rsp))
580 movq PCPU(CURTHREAD),%rdi
581 movq %rsp,TD_FRAME(%rdi)
582 movl TF_RFLAGS(%rsp),%esi
585 1: movq PCPU(CURPCB),%rax
586 /* Disable interrupts before testing PCB_FULL_IRET. */
588 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
590 /* Check for and handle AST's on return to userland. */
591 movq PCPU(CURTHREAD),%rax
592 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
594 call handle_ibrs_exit
596 /* Restore preserved registers. */
598 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
599 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
600 movq TF_RDX(%rsp),%rdx /* return value 2 */
601 movq TF_RAX(%rsp),%rax /* return value 1 */
602 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
603 movq TF_RIP(%rsp),%rcx /* original %rip */
604 movq TF_RSP(%rsp),%rsp /* user stack pointer */
605 xorl %r8d,%r8d /* zero the rest of GPRs */
615 3: /* AST scheduled. */
621 4: /* Requested full context restore, use doreti for that. */
626 * Here for CYA insurance, in case a "syscall" instruction gets
627 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
628 * to *something* if EFER_SCE is enabled.
630 IDTVEC(fast_syscall32)
634 * DB# handler is very similar to NM#, because 'mov/pop %ss' delay
635 * generation of exception until the next instruction is executed,
636 * which might be a kernel entry. So we must execute the handler
637 * on IST stack and be ready for non-kernel GSBASE.
641 movl $(T_TRCTRAP),TF_TRAPNO(%rsp)
642 movq $0,TF_ADDR(%rsp)
644 movq %rdi,TF_RDI(%rsp)
645 movq %rsi,TF_RSI(%rsp)
646 movq %rdx,TF_RDX(%rsp)
647 movq %rcx,TF_RCX(%rsp)
650 movq %rax,TF_RAX(%rsp)
651 movq %rbx,TF_RBX(%rsp)
652 movq %rbp,TF_RBP(%rsp)
653 movq %r10,TF_R10(%rsp)
654 movq %r11,TF_R11(%rsp)
655 movq %r12,TF_R12(%rsp)
656 movq %r13,TF_R13(%rsp)
657 movq %r14,TF_R14(%rsp)
658 movq %r15,TF_R15(%rsp)
660 movl $TF_HASSEGS,TF_FLAGS(%rsp)
662 andq $~(PSL_D | PSL_AC),(%rsp)
664 testb $SEL_RPL_MASK,TF_CS(%rsp)
665 jnz dbg_fromuserspace
668 * We've interrupted the kernel. Preserve GS.base in %r12,
669 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
671 movl $MSR_GSBASE,%ecx
676 /* Retrieve and load the canonical value for GS.base. */
677 movq TF_SIZE(%rsp),%rdx
686 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
688 movl $MSR_IA32_SPEC_CTRL,%ecx
691 call handle_ibrs_entry
692 2: FAKE_MCOUNT(TF_RIP(%rsp))
696 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
700 movl $MSR_IA32_SPEC_CTRL,%ecx
703 * Put back the preserved MSR_GSBASE value.
705 3: movl $MSR_GSBASE,%ecx
716 * Switch to kernel GSBASE and kernel page table, and copy frame
717 * from the IST stack to the normal kernel stack, since trap()
718 * re-enables interrupts, and since we might trap on DB# while
727 1: movq PCPU(RSP0),%rax
734 call handle_ibrs_entry
735 movq PCPU(CURPCB),%rdi
736 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
737 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
739 cmpw $KUF32SEL,TF_FS(%rsp)
742 movq %rax,PCB_FSBASE(%rdi)
743 2: cmpw $KUG32SEL,TF_GS(%rsp)
745 movl $MSR_KGSBASE,%ecx
749 movq %rax,PCB_GSBASE(%rdi)
753 * NMI handling is special.
755 * First, NMIs do not respect the state of the processor's RFLAGS.IF
756 * bit. The NMI handler may be entered at any time, including when
757 * the processor is in a critical section with RFLAGS.IF == 0.
758 * The processor's GS.base value could be invalid on entry to the
761 * Second, the processor treats NMIs specially, blocking further NMIs
762 * until an 'iretq' instruction is executed. We thus need to execute
763 * the NMI handler with interrupts disabled, to prevent a nested interrupt
764 * from executing an 'iretq' instruction and inadvertently taking the
765 * processor out of NMI mode.
767 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
768 * GS.base value for the processor is stored just above the bottom of its
769 * NMI stack. For NMIs taken from kernel mode, the current value in
770 * the processor's GS.base is saved at entry to C-preserved register %r12,
771 * the canonical value for GS.base is then loaded into the processor, and
772 * the saved value is restored at exit time. For NMIs taken from user mode,
773 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
778 movl $(T_NMI),TF_TRAPNO(%rsp)
779 movq $0,TF_ADDR(%rsp)
781 movq %rdi,TF_RDI(%rsp)
782 movq %rsi,TF_RSI(%rsp)
783 movq %rdx,TF_RDX(%rsp)
784 movq %rcx,TF_RCX(%rsp)
787 movq %rax,TF_RAX(%rsp)
788 movq %rbx,TF_RBX(%rsp)
789 movq %rbp,TF_RBP(%rsp)
790 movq %r10,TF_R10(%rsp)
791 movq %r11,TF_R11(%rsp)
792 movq %r12,TF_R12(%rsp)
793 movq %r13,TF_R13(%rsp)
794 movq %r14,TF_R14(%rsp)
795 movq %r15,TF_R15(%rsp)
797 movl $TF_HASSEGS,TF_FLAGS(%rsp)
799 andq $~(PSL_D | PSL_AC),(%rsp)
802 testb $SEL_RPL_MASK,TF_CS(%rsp)
803 jnz nmi_fromuserspace
805 * We've interrupted the kernel. Preserve GS.base in %r12,
806 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
809 movl $MSR_GSBASE,%ecx
814 /* Retrieve and load the canonical value for GS.base. */
815 movq TF_SIZE(%rsp),%rdx
824 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
826 movl $MSR_IA32_SPEC_CTRL,%ecx
829 call handle_ibrs_entry
840 1: call handle_ibrs_entry
841 movq PCPU(CURPCB),%rdi
844 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
845 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
847 cmpw $KUF32SEL,TF_FS(%rsp)
850 movq %rax,PCB_FSBASE(%rdi)
851 2: cmpw $KUG32SEL,TF_GS(%rsp)
853 movl $MSR_KGSBASE,%ecx
857 movq %rax,PCB_GSBASE(%rdi)
859 /* Note: this label is also used by ddb and gdb: */
861 FAKE_MCOUNT(TF_RIP(%rsp))
867 * Capture a userspace callchain if needed.
869 * - Check if the current trap was from user mode.
870 * - Check if the current thread is valid.
871 * - Check if the thread requires a user call chain to be
874 * We are still in NMI mode at this point.
877 jz nocallchain /* not from userspace */
878 movq PCPU(CURTHREAD),%rax
879 orq %rax,%rax /* curthread present? */
882 * Move execution to the regular kernel stack, because we
883 * committed to return through doreti.
885 movq %rsp,%rsi /* source stack pointer */
889 movq %rdx,%rdi /* destination stack pointer */
890 shrq $3,%rcx /* trap frame size in long words */
892 andq $~(PSL_D | PSL_AC),(%rsp)
895 movsq /* copy trapframe */
896 movq %rdx,%rsp /* we are on the regular kstack */
898 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
901 * A user callchain is to be captured, so:
902 * - Take the processor out of "NMI" mode by faking an "iret",
903 * to allow for nested NMI interrupts.
904 * - Enable interrupts, so that copyin() can work.
907 pushq %rax /* tf_ss */
908 pushq %rdx /* tf_rsp (on kernel stack) */
909 pushfq /* tf_rflags */
911 pushq %rax /* tf_cs */
912 pushq $outofnmi /* tf_rip */
916 * At this point the processor has exited NMI mode and is running
917 * with interrupts turned off on the normal kernel stack.
919 * If a pending NMI gets recognized at or after this point, it
920 * will cause a kernel callchain to be traced.
922 * We turn interrupts back on, and call the user callchain capture hook.
927 movq PCPU(CURTHREAD),%rdi /* thread */
928 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
929 movq %rsp,%rdx /* frame */
935 testl %ebx,%ebx /* %ebx == 0 => return to userland */
938 * Restore speculation control MSR, if preserved.
940 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
944 movl $MSR_IA32_SPEC_CTRL,%ecx
947 * Put back the preserved MSR_GSBASE value.
949 1: movl $MSR_GSBASE,%ecx
954 cmpb $0, nmi_flush_l1d_sw(%rip)
956 call flush_l1d_sw /* bhyve L1TF assist */
963 * MC# handling is similar to NMI.
965 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
966 * can occur at any time with a GS.base value that does not correspond
967 * to the privilege level in CS.
969 * Machine checks are not unblocked by iretq, but it is best to run
970 * the handler with interrupts disabled since the exception may have
971 * interrupted a critical section.
973 * The MC# handler runs on its own stack (tss_ist3). The canonical
974 * GS.base value for the processor is stored just above the bottom of
975 * its MC# stack. For exceptions taken from kernel mode, the current
976 * value in the processor's GS.base is saved at entry to C-preserved
977 * register %r12, the canonical value for GS.base is then loaded into
978 * the processor, and the saved value is restored at exit time. For
979 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
980 * are used for swapping GS.base.
985 movl $(T_MCHK),TF_TRAPNO(%rsp)
986 movq $0,TF_ADDR(%rsp)
988 movq %rdi,TF_RDI(%rsp)
989 movq %rsi,TF_RSI(%rsp)
990 movq %rdx,TF_RDX(%rsp)
991 movq %rcx,TF_RCX(%rsp)
994 movq %rax,TF_RAX(%rsp)
995 movq %rbx,TF_RBX(%rsp)
996 movq %rbp,TF_RBP(%rsp)
997 movq %r10,TF_R10(%rsp)
998 movq %r11,TF_R11(%rsp)
999 movq %r12,TF_R12(%rsp)
1000 movq %r13,TF_R13(%rsp)
1001 movq %r14,TF_R14(%rsp)
1002 movq %r15,TF_R15(%rsp)
1004 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1006 andq $~(PSL_D | PSL_AC),(%rsp)
1009 testb $SEL_RPL_MASK,TF_CS(%rsp)
1010 jnz mchk_fromuserspace
1012 * We've interrupted the kernel. Preserve GS.base in %r12,
1013 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
1015 movl $MSR_GSBASE,%ecx
1020 /* Retrieve and load the canonical value for GS.base. */
1021 movq TF_SIZE(%rsp),%rdx
1026 movq PCPU(KCR3),%rax
1030 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
1032 movl $MSR_IA32_SPEC_CTRL,%ecx
1035 call handle_ibrs_entry
1041 movq PCPU(KCR3),%rax
1045 1: call handle_ibrs_entry
1046 /* Note: this label is also used by ddb and gdb: */
1048 FAKE_MCOUNT(TF_RIP(%rsp))
1052 testl %ebx,%ebx /* %ebx == 0 => return to userland */
1055 * Restore speculation control MSR, if preserved.
1057 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
1061 movl $MSR_IA32_SPEC_CTRL,%ecx
1064 * Put back the preserved MSR_GSBASE value.
1066 1: movl $MSR_GSBASE,%ecx
1076 ENTRY(fork_trampoline)
1077 movq %r12,%rdi /* function */
1078 movq %rbx,%rsi /* arg1 */
1079 movq %rsp,%rdx /* trapframe pointer */
1082 jmp doreti /* Handle any ASTs */
1085 * To efficiently implement classification of trap and interrupt handlers
1086 * for profiling, there must be only trap handlers between the labels btrap
1087 * and bintr, and only interrupt handlers between the labels bintr and
1088 * eintr. This is implemented (partly) by including files that contain
1089 * some of the handlers. Before including the files, set up a normal asm
1090 * environment so that the included files doen't need to know that they are
1094 #ifdef COMPAT_FREEBSD32
1100 #include <amd64/ia32/ia32_exception.S>
1109 #include <amd64/amd64/apic_vector.S>
1117 #include <amd64/amd64/atpic_vector.S>
1124 * void doreti(struct trapframe)
1126 * Handle return from interrupts, traps and syscalls.
1130 .type doreti,@function
1133 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
1135 * Check if ASTs can be handled now.
1137 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
1138 jz doreti_exit /* can't handle ASTs now if not */
1142 * Check for ASTs atomically with returning. Disabling CPU
1143 * interrupts provides sufficient locking even in the SMP case,
1144 * since we will be informed of any new ASTs by an IPI.
1147 movq PCPU(CURTHREAD),%rax
1148 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
1151 movq %rsp,%rdi /* pass a pointer to the trapframe */
1156 * doreti_exit: pop registers, iret.
1158 * The segment register pop is a special case, since it may
1159 * fault if (for example) a sigreturn specifies bad segment
1160 * registers. The fault is handled in trap.c.
1164 movq PCPU(CURPCB),%r8
1167 * Do not reload segment registers for kernel.
1168 * Since we do not reload segments registers with sane
1169 * values on kernel entry, descriptors referenced by
1170 * segments registers might be not valid. This is fatal
1171 * for user mode, but is not a problem for the kernel.
1173 testb $SEL_RPL_MASK,TF_CS(%rsp)
1175 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
1177 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
1178 testl $TF_HASSEGS,TF_FLAGS(%rsp)
1182 /* Restore %fs and fsbase */
1183 movw TF_FS(%rsp),%ax
1189 movl $MSR_FSBASE,%ecx
1190 movl PCB_FSBASE(%r8),%eax
1191 movl PCB_FSBASE+4(%r8),%edx
1196 /* Restore %gs and gsbase */
1197 movw TF_GS(%rsp),%si
1200 movl $MSR_GSBASE,%ecx
1201 /* Save current kernel %gs base into %r12d:%r13d */
1208 /* Save user %gs base into %r14d:%r15d */
1212 /* Restore kernel %gs base */
1218 * Restore user %gs base, either from PCB if used for TLS, or
1219 * from the previously saved msr read.
1221 movl $MSR_KGSBASE,%ecx
1224 movl PCB_GSBASE(%r8),%eax
1225 movl PCB_GSBASE+4(%r8),%edx
1232 wrmsr /* May trap if non-canonical, but only for TLS. */
1235 movw TF_ES(%rsp),%es
1238 movw TF_DS(%rsp),%ds
1241 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1242 jz 2f /* keep running with kernel GS.base */
1244 call handle_ibrs_exit_rs
1249 movq PCPU(PTI_RSP0),%rdx
1251 movq %rax,PTI_RAX(%rdx)
1253 movq %rax,PTI_RDX(%rdx)
1254 movq TF_RIP(%rsp),%rax
1255 movq %rax,PTI_RIP(%rdx)
1256 movq TF_CS(%rsp),%rax
1257 movq %rax,PTI_CS(%rdx)
1258 movq TF_RFLAGS(%rsp),%rax
1259 movq %rax,PTI_RFLAGS(%rdx)
1260 movq TF_RSP(%rsp),%rax
1261 movq %rax,PTI_RSP(%rdx)
1262 movq TF_SS(%rsp),%rax
1263 movq %rax,PTI_SS(%rdx)
1264 movq PCPU(UCR3),%rax
1273 2: addq $TF_RIP,%rsp
1280 movw %ax,TF_DS(%rsp)
1281 movw %ax,TF_ES(%rsp)
1282 movw $KUF32SEL,TF_FS(%rsp)
1283 movw $KUG32SEL,TF_GS(%rsp)
1287 * doreti_iret_fault. Alternative return code for
1288 * the case where we get a fault in the doreti_exit code
1289 * above. trap() (amd64/amd64/trap.c) catches this specific
1290 * case, sends the process a signal and continues in the
1291 * corresponding place in the code below.
1294 .globl doreti_iret_fault
1296 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1297 movq %rax,TF_RAX(%rsp)
1298 movq %rdx,TF_RDX(%rsp)
1299 movq %rcx,TF_RCX(%rsp)
1300 call handle_ibrs_entry
1301 testb $SEL_RPL_MASK,TF_CS(%rsp)
1306 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1307 movq %rdi,TF_RDI(%rsp)
1308 movq %rsi,TF_RSI(%rsp)
1309 movq %r8,TF_R8(%rsp)
1310 movq %r9,TF_R9(%rsp)
1311 movq %rbx,TF_RBX(%rsp)
1312 movq %rbp,TF_RBP(%rsp)
1313 movq %r10,TF_R10(%rsp)
1314 movq %r11,TF_R11(%rsp)
1315 movq %r12,TF_R12(%rsp)
1316 movq %r13,TF_R13(%rsp)
1317 movq %r14,TF_R14(%rsp)
1318 movq %r15,TF_R15(%rsp)
1319 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1320 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1321 movq $0,TF_ADDR(%rsp)
1322 FAKE_MCOUNT(TF_RIP(%rsp))
1326 .globl ds_load_fault
1328 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1329 testb $SEL_RPL_MASK,TF_CS(%rsp)
1335 movw $KUDSEL,TF_DS(%rsp)
1339 .globl es_load_fault
1341 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1342 testl $PSL_I,TF_RFLAGS(%rsp)
1348 movw $KUDSEL,TF_ES(%rsp)
1352 .globl fs_load_fault
1354 testl $PSL_I,TF_RFLAGS(%rsp)
1358 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1361 movw $KUF32SEL,TF_FS(%rsp)
1365 .globl gs_load_fault
1368 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1369 testl $PSL_I,TF_RFLAGS(%rsp)
1375 movw $KUG32SEL,TF_GS(%rsp)
1379 .globl fsbase_load_fault
1381 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1382 testl $PSL_I,TF_RFLAGS(%rsp)
1388 movq PCPU(CURTHREAD),%r8
1389 movq TD_PCB(%r8),%r8
1390 movq $0,PCB_FSBASE(%r8)
1394 .globl gsbase_load_fault
1396 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1397 testl $PSL_I,TF_RFLAGS(%rsp)
1403 movq PCPU(CURTHREAD),%r8
1404 movq TD_PCB(%r8),%r8
1405 movq $0,PCB_GSBASE(%r8)
1409 ENTRY(end_exceptions)