2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_compat.h"
43 #include "opt_hwpmc_hooks.h"
47 #include <machine/asmacros.h>
48 #include <machine/psl.h>
49 #include <machine/trap.h>
50 #include <machine/specialreg.h>
54 .globl dtrace_invop_jump_addr
56 .type dtrace_invop_jump_addr,@object
57 .size dtrace_invop_jump_addr,8
58 dtrace_invop_jump_addr:
60 .globl dtrace_invop_calltrap_addr
62 .type dtrace_invop_calltrap_addr,@object
63 .size dtrace_invop_calltrap_addr,8
64 dtrace_invop_calltrap_addr:
69 ENTRY(start_exceptions)
72 /*****************************************************************************/
74 /*****************************************************************************/
76 * Trap and fault vector routines.
78 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
79 * state on the stack but also disables interrupts. This is important for
80 * us for the use of the swapgs instruction. We cannot be interrupted
81 * until the GS.base value is correct. For most traps, we automatically
82 * then enable interrupts if the interrupted context had them enabled.
83 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
85 * The cpu will push a certain amount of state onto the kernel stack for
86 * the current process. See amd64/include/frame.h.
87 * This includes the current RFLAGS (status register, which includes
88 * the interrupt disable state prior to the trap), the code segment register,
89 * and the return instruction pointer are pushed by the cpu. The cpu
90 * will also push an 'error' code for certain traps. We push a dummy
91 * error code for those traps where the cpu doesn't in order to maintain
92 * a consistent frame. We also push a contrived 'trap number'.
94 * The CPU does not push the general registers, so we must do that, and we
95 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
96 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
97 * for the kernel mode operation shortly, without changes to the selector
98 * loaded. Since superuser long mode works with any selectors loaded into
99 * segment registers other then %cs, which makes them mostly unused in long
100 * mode, and kernel does not reference %fs, leave them alone. The segment
101 * registers are reloaded on return to the usermode.
107 /* Traps that we leave interrupts disabled for. */
108 .macro TRAP_NOEN l, trapno
112 X\l: subq $TF_RIP,%rsp
113 movl $\trapno,TF_TRAPNO(%rsp)
114 movq $0,TF_ADDR(%rsp)
119 TRAP_NOEN dbg, T_TRCTRAP
120 TRAP_NOEN bpt, T_BPTFLT
122 TRAP_NOEN dtrace_ret, T_DTRACE_RET
125 /* Regular traps; The cpu does not supply tf_err for these. */
126 .macro TRAP l, trapno
132 movl $\trapno,TF_TRAPNO(%rsp)
133 movq $0,TF_ADDR(%rsp)
141 TRAP ill, T_PRIVINFLT
143 TRAP fpusegm, T_FPOPFLT
144 TRAP rsvd, T_RESERVED
145 TRAP fpu, T_ARITHTRAP
148 /* This group of traps have tf_err already pushed by the cpu. */
149 .macro TRAP_ERR l, trapno
150 PTI_ENTRY \l,X\l,has_err=1
155 movl $\trapno,TF_TRAPNO(%rsp)
156 movq $0,TF_ADDR(%rsp)
160 TRAP_ERR tss, T_TSSFLT
161 TRAP_ERR align, T_ALIGNFLT
164 * alltraps entry point. Use swapgs if this is the first time in the
165 * kernel from userland. Reenable interrupts if they were enabled
166 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
170 .type alltraps,@function
172 movq %rdi,TF_RDI(%rsp)
173 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
174 jz 1f /* already running with kernel GS.base */
176 movq PCPU(CURPCB),%rdi
177 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
179 movq %rdx,TF_RDX(%rsp)
180 movq %rax,TF_RAX(%rsp)
181 movq %rcx,TF_RCX(%rsp)
182 testb $SEL_RPL_MASK,TF_CS(%rsp)
184 call handle_ibrs_entry
185 2: testl $PSL_I,TF_RFLAGS(%rsp)
186 jz alltraps_pushregs_no_rax
188 alltraps_pushregs_no_rax:
189 movq %rsi,TF_RSI(%rsp)
192 movq %rbx,TF_RBX(%rsp)
193 movq %rbp,TF_RBP(%rsp)
194 movq %r10,TF_R10(%rsp)
195 movq %r11,TF_R11(%rsp)
196 movq %r12,TF_R12(%rsp)
197 movq %r13,TF_R13(%rsp)
198 movq %r14,TF_R14(%rsp)
199 movq %r15,TF_R15(%rsp)
200 movl $TF_HASSEGS,TF_FLAGS(%rsp)
202 FAKE_MCOUNT(TF_RIP(%rsp))
205 * DTrace Function Boundary Trace (fbt) probes are triggered
206 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
207 * interrupt. For all other trap types, just handle them in
210 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
211 jnz calltrap /* ignore userland traps */
212 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
215 /* Check if there is no DTrace hook registered. */
216 cmpq $0,dtrace_invop_jump_addr
220 * Set our jump address for the jump back in the event that
221 * the breakpoint wasn't caused by DTrace at all.
223 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
225 /* Jump to the code hooked in by DTrace. */
226 jmpq *dtrace_invop_jump_addr
229 .type calltrap,@function
234 jmp doreti /* Handle any pending ASTs */
237 * alltraps_noen entry point. Unlike alltraps above, we want to
238 * leave the interrupts disabled. This corresponds to
239 * SDT_SYS386IGT on the i386 port.
243 .type alltraps_noen,@function
245 movq %rdi,TF_RDI(%rsp)
246 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
247 jz 1f /* already running with kernel GS.base */
249 movq PCPU(CURPCB),%rdi
250 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
252 movq %rdx,TF_RDX(%rsp)
253 movq %rax,TF_RAX(%rsp)
254 movq %rcx,TF_RCX(%rsp)
255 testb $SEL_RPL_MASK,TF_CS(%rsp)
256 jz alltraps_pushregs_no_rax
257 call handle_ibrs_entry
258 jmp alltraps_pushregs_no_rax
262 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
263 movq $0,TF_ADDR(%rsp)
265 movq %rdi,TF_RDI(%rsp)
266 movq %rsi,TF_RSI(%rsp)
267 movq %rdx,TF_RDX(%rsp)
268 movq %rcx,TF_RCX(%rsp)
271 movq %rax,TF_RAX(%rsp)
272 movq %rbx,TF_RBX(%rsp)
273 movq %rbp,TF_RBP(%rsp)
274 movq %r10,TF_R10(%rsp)
275 movq %r11,TF_R11(%rsp)
276 movq %r12,TF_R12(%rsp)
277 movq %r13,TF_R13(%rsp)
278 movq %r14,TF_R14(%rsp)
279 movq %r15,TF_R15(%rsp)
281 movl $TF_HASSEGS,TF_FLAGS(%rsp)
283 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
284 jz 1f /* already running with kernel GS.base */
292 call dblfault_handler
298 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp)
304 movq %rax,PCPU(SAVED_UCR3)
305 PTI_UUENTRY has_err=1
307 movq %rdi,TF_RDI(%rsp)
308 movq %rax,TF_RAX(%rsp)
309 movq %rdx,TF_RDX(%rsp)
310 movq %rcx,TF_RCX(%rsp)
314 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
315 movq %rax,TF_RAX(%rsp)
316 movq %rdx,TF_RDX(%rsp)
317 movq %rcx,TF_RCX(%rsp)
318 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
319 jz page_cr2 /* already running with kernel GS.base */
321 page_u: movq PCPU(CURPCB),%rdi
322 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
323 movq PCPU(SAVED_UCR3),%rax
324 movq %rax,PCB_SAVED_UCR3(%rdi)
325 call handle_ibrs_entry
327 movq %cr2,%rdi /* preserve %cr2 before .. */
328 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
330 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
331 testl $PSL_I,TF_RFLAGS(%rsp)
332 jz alltraps_pushregs_no_rax
334 jmp alltraps_pushregs_no_rax
337 * We have to special-case this one. If we get a trap in doreti() at
338 * the iretq stage, we'll reenter with the wrong gs state. We'll have
339 * to do a special the swapgs in this case even coming from the kernel.
340 * XXX linux has a trap handler for their equivalent of load_gs().
342 * On the stack, we have the hardware interrupt frame to return
343 * to usermode (faulted) and another frame with error code, for
344 * fault. For PTI, copy both frames to the main thread stack.
346 .macro PROTF_ENTRY name,trapno
354 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
355 MOVE_STACKS (PTI_SIZE / 4 - 3)
362 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
363 je \name\()_pti_doreti
364 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
370 movl $\trapno,TF_TRAPNO(%rsp)
374 PROTF_ENTRY missing, T_SEGNPFLT
375 PROTF_ENTRY stk, T_STKFLT
376 PROTF_ENTRY prot, T_PROTFLT
379 movq $0,TF_ADDR(%rsp)
380 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
381 movq %rax,TF_RAX(%rsp)
382 movq %rdx,TF_RDX(%rsp)
383 movq %rcx,TF_RCX(%rsp)
386 leaq doreti_iret(%rip),%rdi
387 cmpq %rdi,TF_RIP(%rsp)
388 je 5f /* kernel but with user gsbase!! */
389 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
390 jz 6f /* already running with kernel GS.base */
391 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
393 cmpw $KUF32SEL,TF_FS(%rsp)
396 1: cmpw $KUG32SEL,TF_GS(%rsp)
400 movq PCPU(CURPCB),%rdi
401 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
403 cmpw $KUF32SEL,TF_FS(%rsp)
405 movq %rax,PCB_FSBASE(%rdi)
406 3: cmpw $KUG32SEL,TF_GS(%rsp)
408 movq %rdx,PCB_GSBASE(%rdi)
409 4: call handle_ibrs_entry
410 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
413 testl $PSL_I,TF_RFLAGS(%rsp)
414 jz alltraps_pushregs_no_rax
416 jmp alltraps_pushregs_no_rax
419 6: movq PCPU(CURPCB),%rdi
423 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
424 * and the new privilige level. We are still running on the old user stack
425 * pointer. We have to juggle a few things around to find our stack etc.
426 * swapgs gives us access to our PCPU space only.
428 * We do not support invoking this from a custom segment registers,
429 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
432 IDTVEC(fast_syscall_pti)
434 movq %rax,PCPU(SCRATCH_RAX)
437 jmp fast_syscall_common
441 movq %rax,PCPU(SCRATCH_RAX)
443 movq %rsp,PCPU(SCRATCH_RSP)
445 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
447 /* defer TF_RSP till we have a spare register */
448 movq %r11,TF_RFLAGS(%rsp)
449 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
450 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
451 movq %r11,TF_RSP(%rsp) /* user stack pointer */
452 movq PCPU(SCRATCH_RAX),%rax
453 movq %rax,TF_RAX(%rsp) /* syscall number */
454 movq %rdx,TF_RDX(%rsp) /* arg 3 */
456 call handle_ibrs_entry
457 movq PCPU(CURPCB),%r11
458 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
460 movq $KUDSEL,TF_SS(%rsp)
461 movq $KUCSEL,TF_CS(%rsp)
463 movq %rdi,TF_RDI(%rsp) /* arg 1 */
464 movq %rsi,TF_RSI(%rsp) /* arg 2 */
465 movq %r10,TF_RCX(%rsp) /* arg 4 */
466 movq %r8,TF_R8(%rsp) /* arg 5 */
467 movq %r9,TF_R9(%rsp) /* arg 6 */
468 movq %rbx,TF_RBX(%rsp) /* C preserved */
469 movq %rbp,TF_RBP(%rsp) /* C preserved */
470 movq %r12,TF_R12(%rsp) /* C preserved */
471 movq %r13,TF_R13(%rsp) /* C preserved */
472 movq %r14,TF_R14(%rsp) /* C preserved */
473 movq %r15,TF_R15(%rsp) /* C preserved */
474 movl $TF_HASSEGS,TF_FLAGS(%rsp)
475 FAKE_MCOUNT(TF_RIP(%rsp))
476 movq PCPU(CURTHREAD),%rdi
477 movq %rsp,TD_FRAME(%rdi)
478 movl TF_RFLAGS(%rsp),%esi
481 1: movq PCPU(CURPCB),%rax
482 /* Disable interrupts before testing PCB_FULL_IRET. */
484 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
486 /* Check for and handle AST's on return to userland. */
487 movq PCPU(CURTHREAD),%rax
488 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
490 call handle_ibrs_exit
491 /* Restore preserved registers. */
493 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
494 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
495 movq TF_RDX(%rsp),%rdx /* return value 2 */
496 movq TF_RAX(%rsp),%rax /* return value 1 */
497 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
498 movq TF_RIP(%rsp),%rcx /* original %rip */
499 movq TF_RSP(%rsp),%rsp /* user stack pointer */
508 3: /* AST scheduled. */
514 4: /* Requested full context restore, use doreti for that. */
519 * Here for CYA insurance, in case a "syscall" instruction gets
520 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
521 * to *something* if EFER_SCE is enabled.
523 IDTVEC(fast_syscall32)
527 * NMI handling is special.
529 * First, NMIs do not respect the state of the processor's RFLAGS.IF
530 * bit. The NMI handler may be entered at any time, including when
531 * the processor is in a critical section with RFLAGS.IF == 0.
532 * The processor's GS.base value could be invalid on entry to the
535 * Second, the processor treats NMIs specially, blocking further NMIs
536 * until an 'iretq' instruction is executed. We thus need to execute
537 * the NMI handler with interrupts disabled, to prevent a nested interrupt
538 * from executing an 'iretq' instruction and inadvertently taking the
539 * processor out of NMI mode.
541 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
542 * GS.base value for the processor is stored just above the bottom of its
543 * NMI stack. For NMIs taken from kernel mode, the current value in
544 * the processor's GS.base is saved at entry to C-preserved register %r12,
545 * the canonical value for GS.base is then loaded into the processor, and
546 * the saved value is restored at exit time. For NMIs taken from user mode,
547 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
552 movl $(T_NMI),TF_TRAPNO(%rsp)
553 movq $0,TF_ADDR(%rsp)
555 movq %rdi,TF_RDI(%rsp)
556 movq %rsi,TF_RSI(%rsp)
557 movq %rdx,TF_RDX(%rsp)
558 movq %rcx,TF_RCX(%rsp)
561 movq %rax,TF_RAX(%rsp)
562 movq %rbx,TF_RBX(%rsp)
563 movq %rbp,TF_RBP(%rsp)
564 movq %r10,TF_R10(%rsp)
565 movq %r11,TF_R11(%rsp)
566 movq %r12,TF_R12(%rsp)
567 movq %r13,TF_R13(%rsp)
568 movq %r14,TF_R14(%rsp)
569 movq %r15,TF_R15(%rsp)
571 movl $TF_HASSEGS,TF_FLAGS(%rsp)
574 testb $SEL_RPL_MASK,TF_CS(%rsp)
575 jnz nmi_fromuserspace
577 * We've interrupted the kernel. Preserve GS.base in %r12,
578 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
580 movl $MSR_GSBASE,%ecx
585 /* Retrieve and load the canonical value for GS.base. */
586 movq TF_SIZE(%rsp),%rdx
595 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
597 movl $MSR_IA32_SPEC_CTRL,%ecx
600 call handle_ibrs_entry
610 1: call handle_ibrs_entry
611 movq PCPU(CURPCB),%rdi
614 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
615 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
617 cmpw $KUF32SEL,TF_FS(%rsp)
620 movq %rax,PCB_FSBASE(%rdi)
621 2: cmpw $KUG32SEL,TF_GS(%rsp)
623 movl $MSR_KGSBASE,%ecx
627 movq %rax,PCB_GSBASE(%rdi)
629 /* Note: this label is also used by ddb and gdb: */
631 FAKE_MCOUNT(TF_RIP(%rsp))
637 * Capture a userspace callchain if needed.
639 * - Check if the current trap was from user mode.
640 * - Check if the current thread is valid.
641 * - Check if the thread requires a user call chain to be
644 * We are still in NMI mode at this point.
647 jz nocallchain /* not from userspace */
648 movq PCPU(CURTHREAD),%rax
649 orq %rax,%rax /* curthread present? */
652 * Move execution to the regular kernel stack, because we
653 * committed to return through doreti.
655 movq %rsp,%rsi /* source stack pointer */
659 movq %rdx,%rdi /* destination stack pointer */
660 shrq $3,%rcx /* trap frame size in long words */
663 movsq /* copy trapframe */
664 movq %rdx,%rsp /* we are on the regular kstack */
666 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
669 * A user callchain is to be captured, so:
670 * - Take the processor out of "NMI" mode by faking an "iret",
671 * to allow for nested NMI interrupts.
672 * - Enable interrupts, so that copyin() can work.
675 pushq %rax /* tf_ss */
676 pushq %rdx /* tf_rsp (on kernel stack) */
677 pushfq /* tf_rflags */
679 pushq %rax /* tf_cs */
680 pushq $outofnmi /* tf_rip */
684 * At this point the processor has exited NMI mode and is running
685 * with interrupts turned off on the normal kernel stack.
687 * If a pending NMI gets recognized at or after this point, it
688 * will cause a kernel callchain to be traced.
690 * We turn interrupts back on, and call the user callchain capture hook.
695 movq PCPU(CURTHREAD),%rdi /* thread */
696 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
697 movq %rsp,%rdx /* frame */
703 testl %ebx,%ebx /* %ebx == 0 => return to userland */
706 * Restore speculation control MSR, if preserved.
708 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
712 movl $MSR_IA32_SPEC_CTRL,%ecx
715 * Put back the preserved MSR_GSBASE value.
717 1: movl $MSR_GSBASE,%ecx
728 * MC# handling is similar to NMI.
730 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
731 * can occur at any time with a GS.base value that does not correspond
732 * to the privilege level in CS.
734 * Machine checks are not unblocked by iretq, but it is best to run
735 * the handler with interrupts disabled since the exception may have
736 * interrupted a critical section.
738 * The MC# handler runs on its own stack (tss_ist3). The canonical
739 * GS.base value for the processor is stored just above the bottom of
740 * its MC# stack. For exceptions taken from kernel mode, the current
741 * value in the processor's GS.base is saved at entry to C-preserved
742 * register %r12, the canonical value for GS.base is then loaded into
743 * the processor, and the saved value is restored at exit time. For
744 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
745 * are used for swapping GS.base.
750 movl $(T_MCHK),TF_TRAPNO(%rsp)
751 movq $0,TF_ADDR(%rsp)
753 movq %rdi,TF_RDI(%rsp)
754 movq %rsi,TF_RSI(%rsp)
755 movq %rdx,TF_RDX(%rsp)
756 movq %rcx,TF_RCX(%rsp)
759 movq %rax,TF_RAX(%rsp)
760 movq %rbx,TF_RBX(%rsp)
761 movq %rbp,TF_RBP(%rsp)
762 movq %r10,TF_R10(%rsp)
763 movq %r11,TF_R11(%rsp)
764 movq %r12,TF_R12(%rsp)
765 movq %r13,TF_R13(%rsp)
766 movq %r14,TF_R14(%rsp)
767 movq %r15,TF_R15(%rsp)
769 movl $TF_HASSEGS,TF_FLAGS(%rsp)
772 testb $SEL_RPL_MASK,TF_CS(%rsp)
773 jnz mchk_fromuserspace
775 * We've interrupted the kernel. Preserve GS.base in %r12,
776 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
778 movl $MSR_GSBASE,%ecx
783 /* Retrieve and load the canonical value for GS.base. */
784 movq TF_SIZE(%rsp),%rdx
793 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
795 movl $MSR_IA32_SPEC_CTRL,%ecx
798 call handle_ibrs_entry
808 1: call handle_ibrs_entry
809 /* Note: this label is also used by ddb and gdb: */
811 FAKE_MCOUNT(TF_RIP(%rsp))
815 testl %ebx,%ebx /* %ebx == 0 => return to userland */
818 * Restore speculation control MSR, if preserved.
820 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
824 movl $MSR_IA32_SPEC_CTRL,%ecx
827 * Put back the preserved MSR_GSBASE value.
829 1: movl $MSR_GSBASE,%ecx
839 ENTRY(fork_trampoline)
840 movq %r12,%rdi /* function */
841 movq %rbx,%rsi /* arg1 */
842 movq %rsp,%rdx /* trapframe pointer */
845 jmp doreti /* Handle any ASTs */
848 * To efficiently implement classification of trap and interrupt handlers
849 * for profiling, there must be only trap handlers between the labels btrap
850 * and bintr, and only interrupt handlers between the labels bintr and
851 * eintr. This is implemented (partly) by including files that contain
852 * some of the handlers. Before including the files, set up a normal asm
853 * environment so that the included files doen't need to know that they are
857 #ifdef COMPAT_FREEBSD32
863 #include <amd64/ia32/ia32_exception.S>
872 #include <amd64/amd64/apic_vector.S>
880 #include <amd64/amd64/atpic_vector.S>
887 * void doreti(struct trapframe)
889 * Handle return from interrupts, traps and syscalls.
893 .type doreti,@function
896 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
898 * Check if ASTs can be handled now.
900 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
901 jz doreti_exit /* can't handle ASTs now if not */
905 * Check for ASTs atomically with returning. Disabling CPU
906 * interrupts provides sufficient locking even in the SMP case,
907 * since we will be informed of any new ASTs by an IPI.
910 movq PCPU(CURTHREAD),%rax
911 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
914 movq %rsp,%rdi /* pass a pointer to the trapframe */
919 * doreti_exit: pop registers, iret.
921 * The segment register pop is a special case, since it may
922 * fault if (for example) a sigreturn specifies bad segment
923 * registers. The fault is handled in trap.c.
927 movq PCPU(CURPCB),%r8
930 * Do not reload segment registers for kernel.
931 * Since we do not reload segments registers with sane
932 * values on kernel entry, descriptors referenced by
933 * segments registers might be not valid. This is fatal
934 * for user mode, but is not a problem for the kernel.
936 testb $SEL_RPL_MASK,TF_CS(%rsp)
938 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
940 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
941 testl $TF_HASSEGS,TF_FLAGS(%rsp)
945 /* Restore %fs and fsbase */
952 movl $MSR_FSBASE,%ecx
953 movl PCB_FSBASE(%r8),%eax
954 movl PCB_FSBASE+4(%r8),%edx
959 /* Restore %gs and gsbase */
963 movl $MSR_GSBASE,%ecx
964 /* Save current kernel %gs base into %r12d:%r13d */
971 /* Save user %gs base into %r14d:%r15d */
975 /* Restore kernel %gs base */
981 * Restore user %gs base, either from PCB if used for TLS, or
982 * from the previously saved msr read.
984 movl $MSR_KGSBASE,%ecx
987 movl PCB_GSBASE(%r8),%eax
988 movl PCB_GSBASE+4(%r8),%edx
995 wrmsr /* May trap if non-canonical, but only for TLS. */
1001 movw TF_DS(%rsp),%ds
1004 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1005 jz 2f /* keep running with kernel GS.base */
1007 call handle_ibrs_exit_rs
1011 movq PCPU(PRVSPACE),%rdx
1012 addq $PC_PTI_STACK+PC_PTI_STACK_SZ*8-PTI_SIZE,%rdx
1013 movq %rax,PTI_RAX(%rdx)
1015 movq %rax,PTI_RDX(%rdx)
1016 movq TF_RIP(%rsp),%rax
1017 movq %rax,PTI_RIP(%rdx)
1018 movq TF_CS(%rsp),%rax
1019 movq %rax,PTI_CS(%rdx)
1020 movq TF_RFLAGS(%rsp),%rax
1021 movq %rax,PTI_RFLAGS(%rdx)
1022 movq TF_RSP(%rsp),%rax
1023 movq %rax,PTI_RSP(%rdx)
1024 movq TF_SS(%rsp),%rax
1025 movq %rax,PTI_SS(%rdx)
1026 movq PCPU(UCR3),%rax
1035 2: addq $TF_RIP,%rsp
1042 movw %ax,TF_DS(%rsp)
1043 movw %ax,TF_ES(%rsp)
1044 movw $KUF32SEL,TF_FS(%rsp)
1045 movw $KUG32SEL,TF_GS(%rsp)
1049 * doreti_iret_fault. Alternative return code for
1050 * the case where we get a fault in the doreti_exit code
1051 * above. trap() (amd64/amd64/trap.c) catches this specific
1052 * case, sends the process a signal and continues in the
1053 * corresponding place in the code below.
1056 .globl doreti_iret_fault
1058 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1059 movq %rax,TF_RAX(%rsp)
1060 movq %rdx,TF_RDX(%rsp)
1061 movq %rcx,TF_RCX(%rsp)
1062 call handle_ibrs_entry
1063 testb $SEL_RPL_MASK,TF_CS(%rsp)
1068 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1069 movq %rdi,TF_RDI(%rsp)
1070 movq %rsi,TF_RSI(%rsp)
1071 movq %r8,TF_R8(%rsp)
1072 movq %r9,TF_R9(%rsp)
1073 movq %rbx,TF_RBX(%rsp)
1074 movq %rbp,TF_RBP(%rsp)
1075 movq %r10,TF_R10(%rsp)
1076 movq %r11,TF_R11(%rsp)
1077 movq %r12,TF_R12(%rsp)
1078 movq %r13,TF_R13(%rsp)
1079 movq %r14,TF_R14(%rsp)
1080 movq %r15,TF_R15(%rsp)
1081 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1082 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1083 movq $0,TF_ADDR(%rsp)
1084 FAKE_MCOUNT(TF_RIP(%rsp))
1088 .globl ds_load_fault
1090 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1091 testb $SEL_RPL_MASK,TF_CS(%rsp)
1097 movw $KUDSEL,TF_DS(%rsp)
1101 .globl es_load_fault
1103 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1104 testl $PSL_I,TF_RFLAGS(%rsp)
1110 movw $KUDSEL,TF_ES(%rsp)
1114 .globl fs_load_fault
1116 testl $PSL_I,TF_RFLAGS(%rsp)
1120 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1123 movw $KUF32SEL,TF_FS(%rsp)
1127 .globl gs_load_fault
1130 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1131 testl $PSL_I,TF_RFLAGS(%rsp)
1137 movw $KUG32SEL,TF_GS(%rsp)
1141 .globl fsbase_load_fault
1143 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1144 testl $PSL_I,TF_RFLAGS(%rsp)
1150 movq PCPU(CURTHREAD),%r8
1151 movq TD_PCB(%r8),%r8
1152 movq $0,PCB_FSBASE(%r8)
1156 .globl gsbase_load_fault
1158 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1159 testl $PSL_I,TF_RFLAGS(%rsp)
1165 movq PCPU(CURTHREAD),%r8
1166 movq TD_PCB(%r8),%r8
1167 movq $0,PCB_GSBASE(%r8)
1171 ENTRY(end_exceptions)