2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_hwpmc_hooks.h"
46 #include <machine/asmacros.h>
47 #include <machine/psl.h>
48 #include <machine/trap.h>
49 #include <machine/specialreg.h>
53 .globl dtrace_invop_jump_addr
55 .type dtrace_invop_jump_addr,@object
56 .size dtrace_invop_jump_addr,8
57 dtrace_invop_jump_addr:
59 .globl dtrace_invop_calltrap_addr
61 .type dtrace_invop_calltrap_addr,@object
62 .size dtrace_invop_calltrap_addr,8
63 dtrace_invop_calltrap_addr:
68 ENTRY(start_exceptions)
71 /*****************************************************************************/
73 /*****************************************************************************/
75 * Trap and fault vector routines.
77 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
78 * state on the stack but also disables interrupts. This is important for
79 * us for the use of the swapgs instruction. We cannot be interrupted
80 * until the GS.base value is correct. For most traps, we automatically
81 * then enable interrupts if the interrupted context had them enabled.
82 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
84 * The cpu will push a certain amount of state onto the kernel stack for
85 * the current process. See amd64/include/frame.h.
86 * This includes the current RFLAGS (status register, which includes
87 * the interrupt disable state prior to the trap), the code segment register,
88 * and the return instruction pointer are pushed by the cpu. The cpu
89 * will also push an 'error' code for certain traps. We push a dummy
90 * error code for those traps where the cpu doesn't in order to maintain
91 * a consistent frame. We also push a contrived 'trap number'.
93 * The CPU does not push the general registers, so we must do that, and we
94 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
95 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
96 * for the kernel mode operation shortly, without changes to the selector
97 * loaded. Since superuser long mode works with any selectors loaded into
98 * segment registers other then %cs, which makes them mostly unused in long
99 * mode, and kernel does not reference %fs, leave them alone. The segment
100 * registers are reloaded on return to the usermode.
106 /* Traps that we leave interrupts disabled for. */
107 .macro TRAP_NOEN l, trapno
111 X\l: subq $TF_RIP,%rsp
112 movl $\trapno,TF_TRAPNO(%rsp)
113 movq $0,TF_ADDR(%rsp)
118 TRAP_NOEN dbg, T_TRCTRAP
119 TRAP_NOEN bpt, T_BPTFLT
121 TRAP_NOEN dtrace_ret, T_DTRACE_RET
124 /* Regular traps; The cpu does not supply tf_err for these. */
125 .macro TRAP l, trapno
131 movl $\trapno,TF_TRAPNO(%rsp)
132 movq $0,TF_ADDR(%rsp)
140 TRAP ill, T_PRIVINFLT
142 TRAP fpusegm, T_FPOPFLT
143 TRAP rsvd, T_RESERVED
144 TRAP fpu, T_ARITHTRAP
147 /* This group of traps have tf_err already pushed by the cpu. */
148 .macro TRAP_ERR l, trapno
149 PTI_ENTRY \l,X\l,has_err=1
154 movl $\trapno,TF_TRAPNO(%rsp)
155 movq $0,TF_ADDR(%rsp)
159 TRAP_ERR tss, T_TSSFLT
160 TRAP_ERR align, T_ALIGNFLT
163 * alltraps entry point. Use swapgs if this is the first time in the
164 * kernel from userland. Reenable interrupts if they were enabled
165 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
169 .type alltraps,@function
171 movq %rdi,TF_RDI(%rsp)
172 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
173 jz 1f /* already running with kernel GS.base */
175 movq PCPU(CURPCB),%rdi
176 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
178 movq %rdx,TF_RDX(%rsp)
179 movq %rax,TF_RAX(%rsp)
180 movq %rcx,TF_RCX(%rsp)
181 testb $SEL_RPL_MASK,TF_CS(%rsp)
183 call handle_ibrs_entry
184 2: testl $PSL_I,TF_RFLAGS(%rsp)
185 jz alltraps_pushregs_no_rax
187 alltraps_pushregs_no_rax:
188 movq %rsi,TF_RSI(%rsp)
191 movq %rbx,TF_RBX(%rsp)
192 movq %rbp,TF_RBP(%rsp)
193 movq %r10,TF_R10(%rsp)
194 movq %r11,TF_R11(%rsp)
195 movq %r12,TF_R12(%rsp)
196 movq %r13,TF_R13(%rsp)
197 movq %r14,TF_R14(%rsp)
198 movq %r15,TF_R15(%rsp)
199 movl $TF_HASSEGS,TF_FLAGS(%rsp)
201 FAKE_MCOUNT(TF_RIP(%rsp))
204 * DTrace Function Boundary Trace (fbt) probes are triggered
205 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
206 * interrupt. For all other trap types, just handle them in
209 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
210 jnz calltrap /* ignore userland traps */
211 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
214 /* Check if there is no DTrace hook registered. */
215 cmpq $0,dtrace_invop_jump_addr
219 * Set our jump address for the jump back in the event that
220 * the breakpoint wasn't caused by DTrace at all.
222 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
224 /* Jump to the code hooked in by DTrace. */
225 jmpq *dtrace_invop_jump_addr
228 .type calltrap,@function
233 jmp doreti /* Handle any pending ASTs */
236 * alltraps_noen entry point. Unlike alltraps above, we want to
237 * leave the interrupts disabled. This corresponds to
238 * SDT_SYS386IGT on the i386 port.
242 .type alltraps_noen,@function
244 movq %rdi,TF_RDI(%rsp)
245 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
246 jz 1f /* already running with kernel GS.base */
248 movq PCPU(CURPCB),%rdi
249 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
251 movq %rdx,TF_RDX(%rsp)
252 movq %rax,TF_RAX(%rsp)
253 movq %rcx,TF_RCX(%rsp)
254 testb $SEL_RPL_MASK,TF_CS(%rsp)
255 jz alltraps_pushregs_no_rax
256 call handle_ibrs_entry
257 jmp alltraps_pushregs_no_rax
261 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
262 movq $0,TF_ADDR(%rsp)
264 movq %rdi,TF_RDI(%rsp)
265 movq %rsi,TF_RSI(%rsp)
266 movq %rdx,TF_RDX(%rsp)
267 movq %rcx,TF_RCX(%rsp)
270 movq %rax,TF_RAX(%rsp)
271 movq %rbx,TF_RBX(%rsp)
272 movq %rbp,TF_RBP(%rsp)
273 movq %r10,TF_R10(%rsp)
274 movq %r11,TF_R11(%rsp)
275 movq %r12,TF_R12(%rsp)
276 movq %r13,TF_R13(%rsp)
277 movq %r14,TF_R14(%rsp)
278 movq %r15,TF_R15(%rsp)
280 movl $TF_HASSEGS,TF_FLAGS(%rsp)
282 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
283 jz 1f /* already running with kernel GS.base */
291 call dblfault_handler
297 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp)
303 movq %rax,PCPU(SAVED_UCR3)
304 PTI_UUENTRY has_err=1
306 movq %rdi,TF_RDI(%rsp)
307 movq %rax,TF_RAX(%rsp)
308 movq %rdx,TF_RDX(%rsp)
309 movq %rcx,TF_RCX(%rsp)
313 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
314 movq %rax,TF_RAX(%rsp)
315 movq %rdx,TF_RDX(%rsp)
316 movq %rcx,TF_RCX(%rsp)
317 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
318 jz page_cr2 /* already running with kernel GS.base */
320 page_u: movq PCPU(CURPCB),%rdi
321 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
322 movq PCPU(SAVED_UCR3),%rax
323 movq %rax,PCB_SAVED_UCR3(%rdi)
324 call handle_ibrs_entry
326 movq %cr2,%rdi /* preserve %cr2 before .. */
327 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
329 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
330 testl $PSL_I,TF_RFLAGS(%rsp)
331 jz alltraps_pushregs_no_rax
333 jmp alltraps_pushregs_no_rax
336 * We have to special-case this one. If we get a trap in doreti() at
337 * the iretq stage, we'll reenter with the wrong gs state. We'll have
338 * to do a special the swapgs in this case even coming from the kernel.
339 * XXX linux has a trap handler for their equivalent of load_gs().
341 * On the stack, we have the hardware interrupt frame to return
342 * to usermode (faulted) and another frame with error code, for
343 * fault. For PTI, copy both frames to the main thread stack.
344 * Handle the potential 16-byte alignment adjustment incurred
345 * during the second fault by copying both frames independently
346 * while unwinding the stack in between.
348 .macro PROTF_ENTRY name,trapno
356 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
357 MOVE_STACKS (PTI_SIZE / 8)
359 movq PTI_RSP(%rsp),%rsp
360 MOVE_STACKS (PTI_SIZE / 8 - 3)
368 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
369 je \name\()_pti_doreti
370 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
376 movl $\trapno,TF_TRAPNO(%rsp)
380 PROTF_ENTRY missing, T_SEGNPFLT
381 PROTF_ENTRY stk, T_STKFLT
382 PROTF_ENTRY prot, T_PROTFLT
385 movq $0,TF_ADDR(%rsp)
386 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
387 movq %rax,TF_RAX(%rsp)
388 movq %rdx,TF_RDX(%rsp)
389 movq %rcx,TF_RCX(%rsp)
392 leaq doreti_iret(%rip),%rdi
393 cmpq %rdi,TF_RIP(%rsp)
394 je 5f /* kernel but with user gsbase!! */
395 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
396 jz 6f /* already running with kernel GS.base */
397 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
399 cmpw $KUF32SEL,TF_FS(%rsp)
402 1: cmpw $KUG32SEL,TF_GS(%rsp)
406 movq PCPU(CURPCB),%rdi
407 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
409 cmpw $KUF32SEL,TF_FS(%rsp)
411 movq %rax,PCB_FSBASE(%rdi)
412 3: cmpw $KUG32SEL,TF_GS(%rsp)
414 movq %rdx,PCB_GSBASE(%rdi)
415 4: call handle_ibrs_entry
416 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
419 testl $PSL_I,TF_RFLAGS(%rsp)
420 jz alltraps_pushregs_no_rax
422 jmp alltraps_pushregs_no_rax
425 6: movq PCPU(CURPCB),%rdi
429 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
430 * and the new privilige level. We are still running on the old user stack
431 * pointer. We have to juggle a few things around to find our stack etc.
432 * swapgs gives us access to our PCPU space only.
434 * We do not support invoking this from a custom segment registers,
435 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
438 IDTVEC(fast_syscall_pti)
440 movq %rax,PCPU(SCRATCH_RAX)
443 jmp fast_syscall_common
447 movq %rax,PCPU(SCRATCH_RAX)
449 movq %rsp,PCPU(SCRATCH_RSP)
451 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
453 /* defer TF_RSP till we have a spare register */
454 movq %r11,TF_RFLAGS(%rsp)
455 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
456 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
457 movq %r11,TF_RSP(%rsp) /* user stack pointer */
458 movq PCPU(SCRATCH_RAX),%rax
459 movq %rax,TF_RAX(%rsp) /* syscall number */
460 movq %rdx,TF_RDX(%rsp) /* arg 3 */
462 call handle_ibrs_entry
463 movq PCPU(CURPCB),%r11
464 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
466 movq $KUDSEL,TF_SS(%rsp)
467 movq $KUCSEL,TF_CS(%rsp)
469 movq %rdi,TF_RDI(%rsp) /* arg 1 */
470 movq %rsi,TF_RSI(%rsp) /* arg 2 */
471 movq %r10,TF_RCX(%rsp) /* arg 4 */
472 movq %r8,TF_R8(%rsp) /* arg 5 */
473 movq %r9,TF_R9(%rsp) /* arg 6 */
474 movq %rbx,TF_RBX(%rsp) /* C preserved */
475 movq %rbp,TF_RBP(%rsp) /* C preserved */
476 movq %r12,TF_R12(%rsp) /* C preserved */
477 movq %r13,TF_R13(%rsp) /* C preserved */
478 movq %r14,TF_R14(%rsp) /* C preserved */
479 movq %r15,TF_R15(%rsp) /* C preserved */
480 movl $TF_HASSEGS,TF_FLAGS(%rsp)
481 FAKE_MCOUNT(TF_RIP(%rsp))
482 movq PCPU(CURTHREAD),%rdi
483 movq %rsp,TD_FRAME(%rdi)
484 movl TF_RFLAGS(%rsp),%esi
487 1: movq PCPU(CURPCB),%rax
488 /* Disable interrupts before testing PCB_FULL_IRET. */
490 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
492 /* Check for and handle AST's on return to userland. */
493 movq PCPU(CURTHREAD),%rax
494 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
496 call handle_ibrs_exit
497 /* Restore preserved registers. */
499 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
500 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
501 movq TF_RDX(%rsp),%rdx /* return value 2 */
502 movq TF_RAX(%rsp),%rax /* return value 1 */
503 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
504 movq TF_RIP(%rsp),%rcx /* original %rip */
505 movq TF_RSP(%rsp),%rsp /* user stack pointer */
514 3: /* AST scheduled. */
520 4: /* Requested full context restore, use doreti for that. */
525 * Here for CYA insurance, in case a "syscall" instruction gets
526 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
527 * to *something* if EFER_SCE is enabled.
529 IDTVEC(fast_syscall32)
533 * NMI handling is special.
535 * First, NMIs do not respect the state of the processor's RFLAGS.IF
536 * bit. The NMI handler may be entered at any time, including when
537 * the processor is in a critical section with RFLAGS.IF == 0.
538 * The processor's GS.base value could be invalid on entry to the
541 * Second, the processor treats NMIs specially, blocking further NMIs
542 * until an 'iretq' instruction is executed. We thus need to execute
543 * the NMI handler with interrupts disabled, to prevent a nested interrupt
544 * from executing an 'iretq' instruction and inadvertently taking the
545 * processor out of NMI mode.
547 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
548 * GS.base value for the processor is stored just above the bottom of its
549 * NMI stack. For NMIs taken from kernel mode, the current value in
550 * the processor's GS.base is saved at entry to C-preserved register %r12,
551 * the canonical value for GS.base is then loaded into the processor, and
552 * the saved value is restored at exit time. For NMIs taken from user mode,
553 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
558 movl $(T_NMI),TF_TRAPNO(%rsp)
559 movq $0,TF_ADDR(%rsp)
561 movq %rdi,TF_RDI(%rsp)
562 movq %rsi,TF_RSI(%rsp)
563 movq %rdx,TF_RDX(%rsp)
564 movq %rcx,TF_RCX(%rsp)
567 movq %rax,TF_RAX(%rsp)
568 movq %rbx,TF_RBX(%rsp)
569 movq %rbp,TF_RBP(%rsp)
570 movq %r10,TF_R10(%rsp)
571 movq %r11,TF_R11(%rsp)
572 movq %r12,TF_R12(%rsp)
573 movq %r13,TF_R13(%rsp)
574 movq %r14,TF_R14(%rsp)
575 movq %r15,TF_R15(%rsp)
577 movl $TF_HASSEGS,TF_FLAGS(%rsp)
580 testb $SEL_RPL_MASK,TF_CS(%rsp)
581 jnz nmi_fromuserspace
583 * We've interrupted the kernel. Preserve GS.base in %r12,
584 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
586 movl $MSR_GSBASE,%ecx
591 /* Retrieve and load the canonical value for GS.base. */
592 movq TF_SIZE(%rsp),%rdx
601 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
603 movl $MSR_IA32_SPEC_CTRL,%ecx
606 call handle_ibrs_entry
616 1: call handle_ibrs_entry
617 movq PCPU(CURPCB),%rdi
620 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
621 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
623 cmpw $KUF32SEL,TF_FS(%rsp)
626 movq %rax,PCB_FSBASE(%rdi)
627 2: cmpw $KUG32SEL,TF_GS(%rsp)
629 movl $MSR_KGSBASE,%ecx
633 movq %rax,PCB_GSBASE(%rdi)
635 /* Note: this label is also used by ddb and gdb: */
637 FAKE_MCOUNT(TF_RIP(%rsp))
643 * Capture a userspace callchain if needed.
645 * - Check if the current trap was from user mode.
646 * - Check if the current thread is valid.
647 * - Check if the thread requires a user call chain to be
650 * We are still in NMI mode at this point.
653 jz nocallchain /* not from userspace */
654 movq PCPU(CURTHREAD),%rax
655 orq %rax,%rax /* curthread present? */
658 * Move execution to the regular kernel stack, because we
659 * committed to return through doreti.
661 movq %rsp,%rsi /* source stack pointer */
665 movq %rdx,%rdi /* destination stack pointer */
666 shrq $3,%rcx /* trap frame size in long words */
669 movsq /* copy trapframe */
670 movq %rdx,%rsp /* we are on the regular kstack */
672 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
675 * A user callchain is to be captured, so:
676 * - Take the processor out of "NMI" mode by faking an "iret",
677 * to allow for nested NMI interrupts.
678 * - Enable interrupts, so that copyin() can work.
681 pushq %rax /* tf_ss */
682 pushq %rdx /* tf_rsp (on kernel stack) */
683 pushfq /* tf_rflags */
685 pushq %rax /* tf_cs */
686 pushq $outofnmi /* tf_rip */
690 * At this point the processor has exited NMI mode and is running
691 * with interrupts turned off on the normal kernel stack.
693 * If a pending NMI gets recognized at or after this point, it
694 * will cause a kernel callchain to be traced.
696 * We turn interrupts back on, and call the user callchain capture hook.
701 movq PCPU(CURTHREAD),%rdi /* thread */
702 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
703 movq %rsp,%rdx /* frame */
709 testl %ebx,%ebx /* %ebx == 0 => return to userland */
712 * Restore speculation control MSR, if preserved.
714 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
718 movl $MSR_IA32_SPEC_CTRL,%ecx
721 * Put back the preserved MSR_GSBASE value.
723 1: movl $MSR_GSBASE,%ecx
734 * MC# handling is similar to NMI.
736 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
737 * can occur at any time with a GS.base value that does not correspond
738 * to the privilege level in CS.
740 * Machine checks are not unblocked by iretq, but it is best to run
741 * the handler with interrupts disabled since the exception may have
742 * interrupted a critical section.
744 * The MC# handler runs on its own stack (tss_ist3). The canonical
745 * GS.base value for the processor is stored just above the bottom of
746 * its MC# stack. For exceptions taken from kernel mode, the current
747 * value in the processor's GS.base is saved at entry to C-preserved
748 * register %r12, the canonical value for GS.base is then loaded into
749 * the processor, and the saved value is restored at exit time. For
750 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
751 * are used for swapping GS.base.
756 movl $(T_MCHK),TF_TRAPNO(%rsp)
757 movq $0,TF_ADDR(%rsp)
759 movq %rdi,TF_RDI(%rsp)
760 movq %rsi,TF_RSI(%rsp)
761 movq %rdx,TF_RDX(%rsp)
762 movq %rcx,TF_RCX(%rsp)
765 movq %rax,TF_RAX(%rsp)
766 movq %rbx,TF_RBX(%rsp)
767 movq %rbp,TF_RBP(%rsp)
768 movq %r10,TF_R10(%rsp)
769 movq %r11,TF_R11(%rsp)
770 movq %r12,TF_R12(%rsp)
771 movq %r13,TF_R13(%rsp)
772 movq %r14,TF_R14(%rsp)
773 movq %r15,TF_R15(%rsp)
775 movl $TF_HASSEGS,TF_FLAGS(%rsp)
778 testb $SEL_RPL_MASK,TF_CS(%rsp)
779 jnz mchk_fromuserspace
781 * We've interrupted the kernel. Preserve GS.base in %r12,
782 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
784 movl $MSR_GSBASE,%ecx
789 /* Retrieve and load the canonical value for GS.base. */
790 movq TF_SIZE(%rsp),%rdx
799 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
801 movl $MSR_IA32_SPEC_CTRL,%ecx
804 call handle_ibrs_entry
814 1: call handle_ibrs_entry
815 /* Note: this label is also used by ddb and gdb: */
817 FAKE_MCOUNT(TF_RIP(%rsp))
821 testl %ebx,%ebx /* %ebx == 0 => return to userland */
824 * Restore speculation control MSR, if preserved.
826 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
830 movl $MSR_IA32_SPEC_CTRL,%ecx
833 * Put back the preserved MSR_GSBASE value.
835 1: movl $MSR_GSBASE,%ecx
845 ENTRY(fork_trampoline)
846 movq %r12,%rdi /* function */
847 movq %rbx,%rsi /* arg1 */
848 movq %rsp,%rdx /* trapframe pointer */
851 jmp doreti /* Handle any ASTs */
854 * To efficiently implement classification of trap and interrupt handlers
855 * for profiling, there must be only trap handlers between the labels btrap
856 * and bintr, and only interrupt handlers between the labels bintr and
857 * eintr. This is implemented (partly) by including files that contain
858 * some of the handlers. Before including the files, set up a normal asm
859 * environment so that the included files doen't need to know that they are
863 #ifdef COMPAT_FREEBSD32
869 #include <amd64/ia32/ia32_exception.S>
878 #include <amd64/amd64/apic_vector.S>
886 #include <amd64/amd64/atpic_vector.S>
893 * void doreti(struct trapframe)
895 * Handle return from interrupts, traps and syscalls.
899 .type doreti,@function
902 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
904 * Check if ASTs can be handled now.
906 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
907 jz doreti_exit /* can't handle ASTs now if not */
911 * Check for ASTs atomically with returning. Disabling CPU
912 * interrupts provides sufficient locking even in the SMP case,
913 * since we will be informed of any new ASTs by an IPI.
916 movq PCPU(CURTHREAD),%rax
917 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
920 movq %rsp,%rdi /* pass a pointer to the trapframe */
925 * doreti_exit: pop registers, iret.
927 * The segment register pop is a special case, since it may
928 * fault if (for example) a sigreturn specifies bad segment
929 * registers. The fault is handled in trap.c.
933 movq PCPU(CURPCB),%r8
936 * Do not reload segment registers for kernel.
937 * Since we do not reload segments registers with sane
938 * values on kernel entry, descriptors referenced by
939 * segments registers might be not valid. This is fatal
940 * for user mode, but is not a problem for the kernel.
942 testb $SEL_RPL_MASK,TF_CS(%rsp)
944 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
946 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
947 testl $TF_HASSEGS,TF_FLAGS(%rsp)
951 /* Restore %fs and fsbase */
958 movl $MSR_FSBASE,%ecx
959 movl PCB_FSBASE(%r8),%eax
960 movl PCB_FSBASE+4(%r8),%edx
965 /* Restore %gs and gsbase */
969 movl $MSR_GSBASE,%ecx
970 /* Save current kernel %gs base into %r12d:%r13d */
977 /* Save user %gs base into %r14d:%r15d */
981 /* Restore kernel %gs base */
987 * Restore user %gs base, either from PCB if used for TLS, or
988 * from the previously saved msr read.
990 movl $MSR_KGSBASE,%ecx
993 movl PCB_GSBASE(%r8),%eax
994 movl PCB_GSBASE+4(%r8),%edx
1001 wrmsr /* May trap if non-canonical, but only for TLS. */
1004 movw TF_ES(%rsp),%es
1007 movw TF_DS(%rsp),%ds
1010 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1011 jz 2f /* keep running with kernel GS.base */
1013 call handle_ibrs_exit_rs
1017 movq PCPU(PRVSPACE),%rdx
1018 addq $PC_PTI_STACK+PC_PTI_STACK_SZ*8-PTI_SIZE,%rdx
1019 movq %rax,PTI_RAX(%rdx)
1021 movq %rax,PTI_RDX(%rdx)
1022 movq TF_RIP(%rsp),%rax
1023 movq %rax,PTI_RIP(%rdx)
1024 movq TF_CS(%rsp),%rax
1025 movq %rax,PTI_CS(%rdx)
1026 movq TF_RFLAGS(%rsp),%rax
1027 movq %rax,PTI_RFLAGS(%rdx)
1028 movq TF_RSP(%rsp),%rax
1029 movq %rax,PTI_RSP(%rdx)
1030 movq TF_SS(%rsp),%rax
1031 movq %rax,PTI_SS(%rdx)
1032 movq PCPU(UCR3),%rax
1041 2: addq $TF_RIP,%rsp
1048 movw %ax,TF_DS(%rsp)
1049 movw %ax,TF_ES(%rsp)
1050 movw $KUF32SEL,TF_FS(%rsp)
1051 movw $KUG32SEL,TF_GS(%rsp)
1055 * doreti_iret_fault. Alternative return code for
1056 * the case where we get a fault in the doreti_exit code
1057 * above. trap() (amd64/amd64/trap.c) catches this specific
1058 * case, sends the process a signal and continues in the
1059 * corresponding place in the code below.
1062 .globl doreti_iret_fault
1064 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1065 movq %rax,TF_RAX(%rsp)
1066 movq %rdx,TF_RDX(%rsp)
1067 movq %rcx,TF_RCX(%rsp)
1068 call handle_ibrs_entry
1069 testb $SEL_RPL_MASK,TF_CS(%rsp)
1074 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1075 movq %rdi,TF_RDI(%rsp)
1076 movq %rsi,TF_RSI(%rsp)
1077 movq %r8,TF_R8(%rsp)
1078 movq %r9,TF_R9(%rsp)
1079 movq %rbx,TF_RBX(%rsp)
1080 movq %rbp,TF_RBP(%rsp)
1081 movq %r10,TF_R10(%rsp)
1082 movq %r11,TF_R11(%rsp)
1083 movq %r12,TF_R12(%rsp)
1084 movq %r13,TF_R13(%rsp)
1085 movq %r14,TF_R14(%rsp)
1086 movq %r15,TF_R15(%rsp)
1087 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1088 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1089 movq $0,TF_ADDR(%rsp)
1090 FAKE_MCOUNT(TF_RIP(%rsp))
1094 .globl ds_load_fault
1096 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1097 testb $SEL_RPL_MASK,TF_CS(%rsp)
1103 movw $KUDSEL,TF_DS(%rsp)
1107 .globl es_load_fault
1109 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1110 testl $PSL_I,TF_RFLAGS(%rsp)
1116 movw $KUDSEL,TF_ES(%rsp)
1120 .globl fs_load_fault
1122 testl $PSL_I,TF_RFLAGS(%rsp)
1126 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1129 movw $KUF32SEL,TF_FS(%rsp)
1133 .globl gs_load_fault
1136 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1137 testl $PSL_I,TF_RFLAGS(%rsp)
1143 movw $KUG32SEL,TF_GS(%rsp)
1147 .globl fsbase_load_fault
1149 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1150 testl $PSL_I,TF_RFLAGS(%rsp)
1156 movq PCPU(CURTHREAD),%r8
1157 movq TD_PCB(%r8),%r8
1158 movq $0,PCB_FSBASE(%r8)
1162 .globl gsbase_load_fault
1164 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1165 testl $PSL_I,TF_RFLAGS(%rsp)
1171 movq PCPU(CURTHREAD),%r8
1172 movq TD_PCB(%r8),%r8
1173 movq $0,PCB_GSBASE(%r8)
1177 ENTRY(end_exceptions)