2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007-2018 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Portions of this software were developed by
11 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
12 * the FreeBSD Foundation.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 #include "opt_atpic.h"
42 #include "opt_hwpmc_hooks.h"
46 #include <machine/asmacros.h>
47 #include <machine/psl.h>
48 #include <machine/trap.h>
49 #include <machine/specialreg.h>
53 .globl dtrace_invop_jump_addr
55 .type dtrace_invop_jump_addr,@object
56 .size dtrace_invop_jump_addr,8
57 dtrace_invop_jump_addr:
59 .globl dtrace_invop_calltrap_addr
61 .type dtrace_invop_calltrap_addr,@object
62 .size dtrace_invop_calltrap_addr,8
63 dtrace_invop_calltrap_addr:
68 ENTRY(start_exceptions)
71 /*****************************************************************************/
73 /*****************************************************************************/
75 * Trap and fault vector routines.
77 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
78 * state on the stack but also disables interrupts. This is important for
79 * us for the use of the swapgs instruction. We cannot be interrupted
80 * until the GS.base value is correct. For most traps, we automatically
81 * then enable interrupts if the interrupted context had them enabled.
82 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
84 * The cpu will push a certain amount of state onto the kernel stack for
85 * the current process. See amd64/include/frame.h.
86 * This includes the current RFLAGS (status register, which includes
87 * the interrupt disable state prior to the trap), the code segment register,
88 * and the return instruction pointer are pushed by the cpu. The cpu
89 * will also push an 'error' code for certain traps. We push a dummy
90 * error code for those traps where the cpu doesn't in order to maintain
91 * a consistent frame. We also push a contrived 'trap number'.
93 * The CPU does not push the general registers, so we must do that, and we
94 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
95 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
96 * for the kernel mode operation shortly, without changes to the selector
97 * loaded. Since superuser long mode works with any selectors loaded into
98 * segment registers other then %cs, which makes them mostly unused in long
99 * mode, and kernel does not reference %fs, leave them alone. The segment
100 * registers are reloaded on return to the usermode.
106 /* Traps that we leave interrupts disabled for. */
107 .macro TRAP_NOEN l, trapno
111 X\l: subq $TF_RIP,%rsp
112 movl $\trapno,TF_TRAPNO(%rsp)
113 movq $0,TF_ADDR(%rsp)
118 TRAP_NOEN bpt, T_BPTFLT
120 TRAP_NOEN dtrace_ret, T_DTRACE_RET
123 /* Regular traps; The cpu does not supply tf_err for these. */
124 .macro TRAP l, trapno
130 movl $\trapno,TF_TRAPNO(%rsp)
131 movq $0,TF_ADDR(%rsp)
139 TRAP ill, T_PRIVINFLT
141 TRAP fpusegm, T_FPOPFLT
142 TRAP rsvd, T_RESERVED
143 TRAP fpu, T_ARITHTRAP
146 /* This group of traps have tf_err already pushed by the cpu. */
147 .macro TRAP_ERR l, trapno
148 PTI_ENTRY \l,X\l,has_err=1
153 movl $\trapno,TF_TRAPNO(%rsp)
154 movq $0,TF_ADDR(%rsp)
158 TRAP_ERR tss, T_TSSFLT
159 TRAP_ERR align, T_ALIGNFLT
162 * alltraps entry point. Use swapgs if this is the first time in the
163 * kernel from userland. Reenable interrupts if they were enabled
164 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
168 .type alltraps,@function
170 movq %rdi,TF_RDI(%rsp)
171 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
172 jz 1f /* already running with kernel GS.base */
174 movq PCPU(CURPCB),%rdi
175 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
177 movq %rdx,TF_RDX(%rsp)
178 movq %rax,TF_RAX(%rsp)
179 movq %rcx,TF_RCX(%rsp)
180 testb $SEL_RPL_MASK,TF_CS(%rsp)
182 call handle_ibrs_entry
183 2: testl $PSL_I,TF_RFLAGS(%rsp)
184 jz alltraps_pushregs_no_rax
186 alltraps_pushregs_no_rax:
187 movq %rsi,TF_RSI(%rsp)
190 movq %rbx,TF_RBX(%rsp)
191 movq %rbp,TF_RBP(%rsp)
192 movq %r10,TF_R10(%rsp)
193 movq %r11,TF_R11(%rsp)
194 movq %r12,TF_R12(%rsp)
195 movq %r13,TF_R13(%rsp)
196 movq %r14,TF_R14(%rsp)
197 movq %r15,TF_R15(%rsp)
198 movl $TF_HASSEGS,TF_FLAGS(%rsp)
200 FAKE_MCOUNT(TF_RIP(%rsp))
203 * DTrace Function Boundary Trace (fbt) probes are triggered
204 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
205 * interrupt. For all other trap types, just handle them in
208 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
209 jnz calltrap /* ignore userland traps */
210 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
213 /* Check if there is no DTrace hook registered. */
214 cmpq $0,dtrace_invop_jump_addr
218 * Set our jump address for the jump back in the event that
219 * the breakpoint wasn't caused by DTrace at all.
221 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
223 /* Jump to the code hooked in by DTrace. */
224 jmpq *dtrace_invop_jump_addr
227 .type calltrap,@function
232 jmp doreti /* Handle any pending ASTs */
235 * alltraps_noen entry point. Unlike alltraps above, we want to
236 * leave the interrupts disabled. This corresponds to
237 * SDT_SYS386IGT on the i386 port.
241 .type alltraps_noen,@function
243 movq %rdi,TF_RDI(%rsp)
244 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
245 jz 1f /* already running with kernel GS.base */
247 movq PCPU(CURPCB),%rdi
248 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
250 movq %rdx,TF_RDX(%rsp)
251 movq %rax,TF_RAX(%rsp)
252 movq %rcx,TF_RCX(%rsp)
253 testb $SEL_RPL_MASK,TF_CS(%rsp)
254 jz alltraps_pushregs_no_rax
255 call handle_ibrs_entry
256 jmp alltraps_pushregs_no_rax
260 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
261 movq $0,TF_ADDR(%rsp)
263 movq %rdi,TF_RDI(%rsp)
264 movq %rsi,TF_RSI(%rsp)
265 movq %rdx,TF_RDX(%rsp)
266 movq %rcx,TF_RCX(%rsp)
269 movq %rax,TF_RAX(%rsp)
270 movq %rbx,TF_RBX(%rsp)
271 movq %rbp,TF_RBP(%rsp)
272 movq %r10,TF_R10(%rsp)
273 movq %r11,TF_R11(%rsp)
274 movq %r12,TF_R12(%rsp)
275 movq %r13,TF_R13(%rsp)
276 movq %r14,TF_R14(%rsp)
277 movq %r15,TF_R15(%rsp)
279 movl $TF_HASSEGS,TF_FLAGS(%rsp)
281 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
282 jz 1f /* already running with kernel GS.base */
290 call dblfault_handler
296 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp)
301 movq %rax,PCPU(SAVED_UCR3)
307 PTI_UUENTRY has_err=1
309 movq %rdi,TF_RDI(%rsp)
310 movq %rax,TF_RAX(%rsp)
311 movq %rdx,TF_RDX(%rsp)
312 movq %rcx,TF_RCX(%rsp)
316 movq %rdi,TF_RDI(%rsp) /* free up GP registers */
317 movq %rax,TF_RAX(%rsp)
318 movq %rdx,TF_RDX(%rsp)
319 movq %rcx,TF_RCX(%rsp)
320 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
321 jz page_cr2 /* already running with kernel GS.base */
323 page_u: movq PCPU(CURPCB),%rdi
324 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
325 movq PCPU(SAVED_UCR3),%rax
326 movq %rax,PCB_SAVED_UCR3(%rdi)
327 call handle_ibrs_entry
329 movq %cr2,%rdi /* preserve %cr2 before .. */
330 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
332 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
333 testl $PSL_I,TF_RFLAGS(%rsp)
334 jz alltraps_pushregs_no_rax
336 jmp alltraps_pushregs_no_rax
339 * We have to special-case this one. If we get a trap in doreti() at
340 * the iretq stage, we'll reenter with the wrong gs state. We'll have
341 * to do a special the swapgs in this case even coming from the kernel.
342 * XXX linux has a trap handler for their equivalent of load_gs().
344 * On the stack, we have the hardware interrupt frame to return
345 * to usermode (faulted) and another frame with error code, for
346 * fault. For PTI, copy both frames to the main thread stack.
347 * Handle the potential 16-byte alignment adjustment incurred
348 * during the second fault by copying both frames independently
349 * while unwinding the stack in between.
351 .macro PROTF_ENTRY name,trapno
361 subq $2*PTI_SIZE-3*8,%rax /* no err, %rax, %rdx in faulted frame */
362 MOVE_STACKS (PTI_SIZE / 8)
364 movq PTI_RSP(%rsp),%rsp
365 MOVE_STACKS (PTI_SIZE / 8 - 3)
373 cmpq $doreti_iret,PTI_RIP-2*8(%rsp)
374 je \name\()_pti_doreti
375 testb $SEL_RPL_MASK,PTI_CS-2*8(%rsp) /* %rax, %rdx not yet pushed */
381 movl $\trapno,TF_TRAPNO(%rsp)
385 PROTF_ENTRY missing, T_SEGNPFLT
386 PROTF_ENTRY stk, T_STKFLT
387 PROTF_ENTRY prot, T_PROTFLT
390 movq $0,TF_ADDR(%rsp)
391 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
392 movq %rax,TF_RAX(%rsp)
393 movq %rdx,TF_RDX(%rsp)
394 movq %rcx,TF_RCX(%rsp)
397 leaq doreti_iret(%rip),%rdi
398 cmpq %rdi,TF_RIP(%rsp)
399 je 5f /* kernel but with user gsbase!! */
400 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
401 jz 6f /* already running with kernel GS.base */
402 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
404 cmpw $KUF32SEL,TF_FS(%rsp)
407 1: cmpw $KUG32SEL,TF_GS(%rsp)
411 movq PCPU(CURPCB),%rdi
412 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
414 cmpw $KUF32SEL,TF_FS(%rsp)
416 movq %rax,PCB_FSBASE(%rdi)
417 3: cmpw $KUG32SEL,TF_GS(%rsp)
419 movq %rdx,PCB_GSBASE(%rdi)
420 4: call handle_ibrs_entry
421 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
424 testl $PSL_I,TF_RFLAGS(%rsp)
425 jz alltraps_pushregs_no_rax
427 jmp alltraps_pushregs_no_rax
430 6: movq PCPU(CURPCB),%rdi
434 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
435 * and the new privilige level. We are still running on the old user stack
436 * pointer. We have to juggle a few things around to find our stack etc.
437 * swapgs gives us access to our PCPU space only.
439 * We do not support invoking this from a custom segment registers,
440 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
443 IDTVEC(fast_syscall_pti)
445 movq %rax,PCPU(SCRATCH_RAX)
447 je fast_syscall_common
450 jmp fast_syscall_common
454 movq %rax,PCPU(SCRATCH_RAX)
456 movq %rsp,PCPU(SCRATCH_RSP)
458 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
460 /* defer TF_RSP till we have a spare register */
461 movq %r11,TF_RFLAGS(%rsp)
462 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
463 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
464 movq %r11,TF_RSP(%rsp) /* user stack pointer */
465 movq PCPU(SCRATCH_RAX),%rax
467 * Save a few arg registers early to free them for use in
468 * handle_ibrs_entry(). %r10 is especially tricky. It is not an
469 * arg register, but it holds the arg register %rcx. Profiling
470 * preserves %rcx, but may clobber %r10. Profiling may also
471 * clobber %r11, but %r11 (original %eflags) has been saved.
473 movq %rax,TF_RAX(%rsp) /* syscall number */
474 movq %rdx,TF_RDX(%rsp) /* arg 3 */
475 movq %r10,TF_RCX(%rsp) /* arg 4 */
477 call handle_ibrs_entry
478 movq PCPU(CURPCB),%r11
479 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
481 movq $KUDSEL,TF_SS(%rsp)
482 movq $KUCSEL,TF_CS(%rsp)
484 movq %rdi,TF_RDI(%rsp) /* arg 1 */
485 movq %rsi,TF_RSI(%rsp) /* arg 2 */
486 movq %r8,TF_R8(%rsp) /* arg 5 */
487 movq %r9,TF_R9(%rsp) /* arg 6 */
488 movq %rbx,TF_RBX(%rsp) /* C preserved */
489 movq %rbp,TF_RBP(%rsp) /* C preserved */
490 movq %r12,TF_R12(%rsp) /* C preserved */
491 movq %r13,TF_R13(%rsp) /* C preserved */
492 movq %r14,TF_R14(%rsp) /* C preserved */
493 movq %r15,TF_R15(%rsp) /* C preserved */
494 movl $TF_HASSEGS,TF_FLAGS(%rsp)
495 FAKE_MCOUNT(TF_RIP(%rsp))
496 movq PCPU(CURTHREAD),%rdi
497 movq %rsp,TD_FRAME(%rdi)
498 movl TF_RFLAGS(%rsp),%esi
501 1: movq PCPU(CURPCB),%rax
502 /* Disable interrupts before testing PCB_FULL_IRET. */
504 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
506 /* Check for and handle AST's on return to userland. */
507 movq PCPU(CURTHREAD),%rax
508 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
510 call handle_ibrs_exit
511 /* Restore preserved registers. */
513 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
514 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
515 movq TF_RDX(%rsp),%rdx /* return value 2 */
516 movq TF_RAX(%rsp),%rax /* return value 1 */
517 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
518 movq TF_RIP(%rsp),%rcx /* original %rip */
519 movq TF_RSP(%rsp),%rsp /* user stack pointer */
528 3: /* AST scheduled. */
534 4: /* Requested full context restore, use doreti for that. */
539 * Here for CYA insurance, in case a "syscall" instruction gets
540 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
541 * to *something* if EFER_SCE is enabled.
543 IDTVEC(fast_syscall32)
547 * DB# handler is very similar to NM#, because 'mov/pop %ss' delay
548 * generation of exception until the next instruction is executed,
549 * which might be a kernel entry. So we must execute the handler
550 * on IST stack and be ready for non-kernel GSBASE.
554 movl $(T_TRCTRAP),TF_TRAPNO(%rsp)
555 movq $0,TF_ADDR(%rsp)
557 movq %rdi,TF_RDI(%rsp)
558 movq %rsi,TF_RSI(%rsp)
559 movq %rdx,TF_RDX(%rsp)
560 movq %rcx,TF_RCX(%rsp)
563 movq %rax,TF_RAX(%rsp)
564 movq %rbx,TF_RBX(%rsp)
565 movq %rbp,TF_RBP(%rsp)
566 movq %r10,TF_R10(%rsp)
567 movq %r11,TF_R11(%rsp)
568 movq %r12,TF_R12(%rsp)
569 movq %r13,TF_R13(%rsp)
570 movq %r14,TF_R14(%rsp)
571 movq %r15,TF_R15(%rsp)
573 movl $TF_HASSEGS,TF_FLAGS(%rsp)
575 testb $SEL_RPL_MASK,TF_CS(%rsp)
576 jnz dbg_fromuserspace
578 * We've interrupted the kernel. Preserve GS.base in %r12,
579 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
581 movl $MSR_GSBASE,%ecx
586 /* Retrieve and load the canonical value for GS.base. */
587 movq TF_SIZE(%rsp),%rdx
596 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
598 movl $MSR_IA32_SPEC_CTRL,%ecx
601 call handle_ibrs_entry
602 2: FAKE_MCOUNT(TF_RIP(%rsp))
606 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
610 movl $MSR_IA32_SPEC_CTRL,%ecx
613 * Put back the preserved MSR_GSBASE value.
615 3: movl $MSR_GSBASE,%ecx
626 * Switch to kernel GSBASE and kernel page table, and copy frame
627 * from the IST stack to the normal kernel stack, since trap()
628 * re-enables interrupts, and since we might trap on DB# while
636 1: movq PCPU(RSP0),%rax
643 call handle_ibrs_entry
644 movq PCPU(CURPCB),%rdi
645 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
646 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
648 cmpw $KUF32SEL,TF_FS(%rsp)
651 movq %rax,PCB_FSBASE(%rdi)
652 2: cmpw $KUG32SEL,TF_GS(%rsp)
654 movl $MSR_KGSBASE,%ecx
658 movq %rax,PCB_GSBASE(%rdi)
662 * NMI handling is special.
664 * First, NMIs do not respect the state of the processor's RFLAGS.IF
665 * bit. The NMI handler may be entered at any time, including when
666 * the processor is in a critical section with RFLAGS.IF == 0.
667 * The processor's GS.base value could be invalid on entry to the
670 * Second, the processor treats NMIs specially, blocking further NMIs
671 * until an 'iretq' instruction is executed. We thus need to execute
672 * the NMI handler with interrupts disabled, to prevent a nested interrupt
673 * from executing an 'iretq' instruction and inadvertently taking the
674 * processor out of NMI mode.
676 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
677 * GS.base value for the processor is stored just above the bottom of its
678 * NMI stack. For NMIs taken from kernel mode, the current value in
679 * the processor's GS.base is saved at entry to C-preserved register %r12,
680 * the canonical value for GS.base is then loaded into the processor, and
681 * the saved value is restored at exit time. For NMIs taken from user mode,
682 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
687 movl $(T_NMI),TF_TRAPNO(%rsp)
688 movq $0,TF_ADDR(%rsp)
690 movq %rdi,TF_RDI(%rsp)
691 movq %rsi,TF_RSI(%rsp)
692 movq %rdx,TF_RDX(%rsp)
693 movq %rcx,TF_RCX(%rsp)
696 movq %rax,TF_RAX(%rsp)
697 movq %rbx,TF_RBX(%rsp)
698 movq %rbp,TF_RBP(%rsp)
699 movq %r10,TF_R10(%rsp)
700 movq %r11,TF_R11(%rsp)
701 movq %r12,TF_R12(%rsp)
702 movq %r13,TF_R13(%rsp)
703 movq %r14,TF_R14(%rsp)
704 movq %r15,TF_R15(%rsp)
706 movl $TF_HASSEGS,TF_FLAGS(%rsp)
709 testb $SEL_RPL_MASK,TF_CS(%rsp)
710 jnz nmi_fromuserspace
712 * We've interrupted the kernel. Preserve GS.base in %r12,
713 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
715 movl $MSR_GSBASE,%ecx
720 /* Retrieve and load the canonical value for GS.base. */
721 movq TF_SIZE(%rsp),%rdx
730 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
732 movl $MSR_IA32_SPEC_CTRL,%ecx
735 call handle_ibrs_entry
745 1: call handle_ibrs_entry
746 movq PCPU(CURPCB),%rdi
749 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
750 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
752 cmpw $KUF32SEL,TF_FS(%rsp)
755 movq %rax,PCB_FSBASE(%rdi)
756 2: cmpw $KUG32SEL,TF_GS(%rsp)
758 movl $MSR_KGSBASE,%ecx
762 movq %rax,PCB_GSBASE(%rdi)
764 /* Note: this label is also used by ddb and gdb: */
766 FAKE_MCOUNT(TF_RIP(%rsp))
772 * Capture a userspace callchain if needed.
774 * - Check if the current trap was from user mode.
775 * - Check if the current thread is valid.
776 * - Check if the thread requires a user call chain to be
779 * We are still in NMI mode at this point.
782 jz nocallchain /* not from userspace */
783 movq PCPU(CURTHREAD),%rax
784 orq %rax,%rax /* curthread present? */
787 * Move execution to the regular kernel stack, because we
788 * committed to return through doreti.
790 movq %rsp,%rsi /* source stack pointer */
794 movq %rdx,%rdi /* destination stack pointer */
795 shrq $3,%rcx /* trap frame size in long words */
798 movsq /* copy trapframe */
799 movq %rdx,%rsp /* we are on the regular kstack */
801 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
804 * A user callchain is to be captured, so:
805 * - Take the processor out of "NMI" mode by faking an "iret",
806 * to allow for nested NMI interrupts.
807 * - Enable interrupts, so that copyin() can work.
810 pushq %rax /* tf_ss */
811 pushq %rdx /* tf_rsp (on kernel stack) */
812 pushfq /* tf_rflags */
814 pushq %rax /* tf_cs */
815 pushq $outofnmi /* tf_rip */
819 * At this point the processor has exited NMI mode and is running
820 * with interrupts turned off on the normal kernel stack.
822 * If a pending NMI gets recognized at or after this point, it
823 * will cause a kernel callchain to be traced.
825 * We turn interrupts back on, and call the user callchain capture hook.
830 movq PCPU(CURTHREAD),%rdi /* thread */
831 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
832 movq %rsp,%rdx /* frame */
838 testl %ebx,%ebx /* %ebx == 0 => return to userland */
841 * Restore speculation control MSR, if preserved.
843 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
847 movl $MSR_IA32_SPEC_CTRL,%ecx
850 * Put back the preserved MSR_GSBASE value.
852 1: movl $MSR_GSBASE,%ecx
863 * MC# handling is similar to NMI.
865 * As with NMIs, machine check exceptions do not respect RFLAGS.IF and
866 * can occur at any time with a GS.base value that does not correspond
867 * to the privilege level in CS.
869 * Machine checks are not unblocked by iretq, but it is best to run
870 * the handler with interrupts disabled since the exception may have
871 * interrupted a critical section.
873 * The MC# handler runs on its own stack (tss_ist3). The canonical
874 * GS.base value for the processor is stored just above the bottom of
875 * its MC# stack. For exceptions taken from kernel mode, the current
876 * value in the processor's GS.base is saved at entry to C-preserved
877 * register %r12, the canonical value for GS.base is then loaded into
878 * the processor, and the saved value is restored at exit time. For
879 * exceptions taken from user mode, the cheaper 'SWAPGS' instructions
880 * are used for swapping GS.base.
885 movl $(T_MCHK),TF_TRAPNO(%rsp)
886 movq $0,TF_ADDR(%rsp)
888 movq %rdi,TF_RDI(%rsp)
889 movq %rsi,TF_RSI(%rsp)
890 movq %rdx,TF_RDX(%rsp)
891 movq %rcx,TF_RCX(%rsp)
894 movq %rax,TF_RAX(%rsp)
895 movq %rbx,TF_RBX(%rsp)
896 movq %rbp,TF_RBP(%rsp)
897 movq %r10,TF_R10(%rsp)
898 movq %r11,TF_R11(%rsp)
899 movq %r12,TF_R12(%rsp)
900 movq %r13,TF_R13(%rsp)
901 movq %r14,TF_R14(%rsp)
902 movq %r15,TF_R15(%rsp)
904 movl $TF_HASSEGS,TF_FLAGS(%rsp)
907 testb $SEL_RPL_MASK,TF_CS(%rsp)
908 jnz mchk_fromuserspace
910 * We've interrupted the kernel. Preserve GS.base in %r12,
911 * %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
913 movl $MSR_GSBASE,%ecx
918 /* Retrieve and load the canonical value for GS.base. */
919 movq TF_SIZE(%rsp),%rdx
928 1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
930 movl $MSR_IA32_SPEC_CTRL,%ecx
933 call handle_ibrs_entry
943 1: call handle_ibrs_entry
944 /* Note: this label is also used by ddb and gdb: */
946 FAKE_MCOUNT(TF_RIP(%rsp))
950 testl %ebx,%ebx /* %ebx == 0 => return to userland */
953 * Restore speculation control MSR, if preserved.
955 testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
959 movl $MSR_IA32_SPEC_CTRL,%ecx
962 * Put back the preserved MSR_GSBASE value.
964 1: movl $MSR_GSBASE,%ecx
974 ENTRY(fork_trampoline)
975 movq %r12,%rdi /* function */
976 movq %rbx,%rsi /* arg1 */
977 movq %rsp,%rdx /* trapframe pointer */
980 jmp doreti /* Handle any ASTs */
983 * To efficiently implement classification of trap and interrupt handlers
984 * for profiling, there must be only trap handlers between the labels btrap
985 * and bintr, and only interrupt handlers between the labels bintr and
986 * eintr. This is implemented (partly) by including files that contain
987 * some of the handlers. Before including the files, set up a normal asm
988 * environment so that the included files doen't need to know that they are
992 #ifdef COMPAT_FREEBSD32
998 #include <amd64/ia32/ia32_exception.S>
1007 #include <amd64/amd64/apic_vector.S>
1015 #include <amd64/amd64/atpic_vector.S>
1022 * void doreti(struct trapframe)
1024 * Handle return from interrupts, traps and syscalls.
1028 .type doreti,@function
1031 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
1033 * Check if ASTs can be handled now.
1035 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
1036 jz doreti_exit /* can't handle ASTs now if not */
1040 * Check for ASTs atomically with returning. Disabling CPU
1041 * interrupts provides sufficient locking even in the SMP case,
1042 * since we will be informed of any new ASTs by an IPI.
1045 movq PCPU(CURTHREAD),%rax
1046 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
1049 movq %rsp,%rdi /* pass a pointer to the trapframe */
1054 * doreti_exit: pop registers, iret.
1056 * The segment register pop is a special case, since it may
1057 * fault if (for example) a sigreturn specifies bad segment
1058 * registers. The fault is handled in trap.c.
1062 movq PCPU(CURPCB),%r8
1065 * Do not reload segment registers for kernel.
1066 * Since we do not reload segments registers with sane
1067 * values on kernel entry, descriptors referenced by
1068 * segments registers might be not valid. This is fatal
1069 * for user mode, but is not a problem for the kernel.
1071 testb $SEL_RPL_MASK,TF_CS(%rsp)
1073 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
1075 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
1076 testl $TF_HASSEGS,TF_FLAGS(%rsp)
1080 /* Restore %fs and fsbase */
1081 movw TF_FS(%rsp),%ax
1087 movl $MSR_FSBASE,%ecx
1088 movl PCB_FSBASE(%r8),%eax
1089 movl PCB_FSBASE+4(%r8),%edx
1094 /* Restore %gs and gsbase */
1095 movw TF_GS(%rsp),%si
1098 movl $MSR_GSBASE,%ecx
1099 /* Save current kernel %gs base into %r12d:%r13d */
1106 /* Save user %gs base into %r14d:%r15d */
1110 /* Restore kernel %gs base */
1116 * Restore user %gs base, either from PCB if used for TLS, or
1117 * from the previously saved msr read.
1119 movl $MSR_KGSBASE,%ecx
1122 movl PCB_GSBASE(%r8),%eax
1123 movl PCB_GSBASE+4(%r8),%edx
1130 wrmsr /* May trap if non-canonical, but only for TLS. */
1133 movw TF_ES(%rsp),%es
1136 movw TF_DS(%rsp),%ds
1139 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
1140 jz 2f /* keep running with kernel GS.base */
1142 call handle_ibrs_exit_rs
1146 movq PCPU(PTI_RSP0),%rdx
1148 movq %rax,PTI_RAX(%rdx)
1150 movq %rax,PTI_RDX(%rdx)
1151 movq TF_RIP(%rsp),%rax
1152 movq %rax,PTI_RIP(%rdx)
1153 movq TF_CS(%rsp),%rax
1154 movq %rax,PTI_CS(%rdx)
1155 movq TF_RFLAGS(%rsp),%rax
1156 movq %rax,PTI_RFLAGS(%rdx)
1157 movq TF_RSP(%rsp),%rax
1158 movq %rax,PTI_RSP(%rdx)
1159 movq TF_SS(%rsp),%rax
1160 movq %rax,PTI_SS(%rdx)
1161 movq PCPU(UCR3),%rax
1170 2: addq $TF_RIP,%rsp
1177 movw %ax,TF_DS(%rsp)
1178 movw %ax,TF_ES(%rsp)
1179 movw $KUF32SEL,TF_FS(%rsp)
1180 movw $KUG32SEL,TF_GS(%rsp)
1184 * doreti_iret_fault. Alternative return code for
1185 * the case where we get a fault in the doreti_exit code
1186 * above. trap() (amd64/amd64/trap.c) catches this specific
1187 * case, sends the process a signal and continues in the
1188 * corresponding place in the code below.
1191 .globl doreti_iret_fault
1193 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
1194 movq %rax,TF_RAX(%rsp)
1195 movq %rdx,TF_RDX(%rsp)
1196 movq %rcx,TF_RCX(%rsp)
1197 call handle_ibrs_entry
1198 testb $SEL_RPL_MASK,TF_CS(%rsp)
1203 movl $TF_HASSEGS,TF_FLAGS(%rsp)
1204 movq %rdi,TF_RDI(%rsp)
1205 movq %rsi,TF_RSI(%rsp)
1206 movq %r8,TF_R8(%rsp)
1207 movq %r9,TF_R9(%rsp)
1208 movq %rbx,TF_RBX(%rsp)
1209 movq %rbp,TF_RBP(%rsp)
1210 movq %r10,TF_R10(%rsp)
1211 movq %r11,TF_R11(%rsp)
1212 movq %r12,TF_R12(%rsp)
1213 movq %r13,TF_R13(%rsp)
1214 movq %r14,TF_R14(%rsp)
1215 movq %r15,TF_R15(%rsp)
1216 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1217 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
1218 movq $0,TF_ADDR(%rsp)
1219 FAKE_MCOUNT(TF_RIP(%rsp))
1223 .globl ds_load_fault
1225 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1226 testb $SEL_RPL_MASK,TF_CS(%rsp)
1232 movw $KUDSEL,TF_DS(%rsp)
1236 .globl es_load_fault
1238 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1239 testl $PSL_I,TF_RFLAGS(%rsp)
1245 movw $KUDSEL,TF_ES(%rsp)
1249 .globl fs_load_fault
1251 testl $PSL_I,TF_RFLAGS(%rsp)
1255 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1258 movw $KUF32SEL,TF_FS(%rsp)
1262 .globl gs_load_fault
1265 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1266 testl $PSL_I,TF_RFLAGS(%rsp)
1272 movw $KUG32SEL,TF_GS(%rsp)
1276 .globl fsbase_load_fault
1278 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1279 testl $PSL_I,TF_RFLAGS(%rsp)
1285 movq PCPU(CURTHREAD),%r8
1286 movq TD_PCB(%r8),%r8
1287 movq $0,PCB_FSBASE(%r8)
1291 .globl gsbase_load_fault
1293 movl $T_PROTFLT,TF_TRAPNO(%rsp)
1294 testl $PSL_I,TF_RFLAGS(%rsp)
1300 movq PCPU(CURTHREAD),%r8
1301 movq TD_PCB(%r8),%r8
1302 movq $0,PCB_GSBASE(%r8)
1306 ENTRY(end_exceptions)