2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
41 #include <machine/asmacros.h>
42 #include <machine/psl.h>
43 #include <machine/trap.h>
44 #include <machine/specialreg.h>
50 .globl dtrace_invop_jump_addr
52 .type dtrace_invop_jump_addr,@object
53 .size dtrace_invop_jump_addr,8
54 dtrace_invop_jump_addr:
56 .globl dtrace_invop_calltrap_addr
58 .type dtrace_invop_calltrap_addr,@object
59 .size dtrace_invop_calltrap_addr,8
60 dtrace_invop_calltrap_addr:
65 ENTRY(start_exceptions)
68 /*****************************************************************************/
70 /*****************************************************************************/
72 * Trap and fault vector routines.
74 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
75 * state on the stack but also disables interrupts. This is important for
76 * us for the use of the swapgs instruction. We cannot be interrupted
77 * until the GS.base value is correct. For most traps, we automatically
78 * then enable interrupts if the interrupted context had them enabled.
79 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
81 * The cpu will push a certain amount of state onto the kernel stack for
82 * the current process. See amd64/include/frame.h.
83 * This includes the current RFLAGS (status register, which includes
84 * the interrupt disable state prior to the trap), the code segment register,
85 * and the return instruction pointer are pushed by the cpu. The cpu
86 * will also push an 'error' code for certain traps. We push a dummy
87 * error code for those traps where the cpu doesn't in order to maintain
88 * a consistent frame. We also push a contrived 'trap number'.
90 * The CPU does not push the general registers, so we must do that, and we
91 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
92 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
93 * for the kernel mode operation shortly, without changes to the selector
94 * loaded. Since superuser long mode works with any selectors loaded into
95 * segment registers other then %cs, which makes them mostly unused in long
96 * mode, and kernel does not reference %fs, leave them alone. The segment
97 * registers are reloaded on return to the usermode.
103 /* Traps that we leave interrupts disabled for.. */
104 #define TRAP_NOEN(a) \
106 movl $(a),TF_TRAPNO(%rsp) ; \
107 movq $0,TF_ADDR(%rsp) ; \
108 movq $0,TF_ERR(%rsp) ; \
116 TRAP_NOEN(T_DTRACE_RET)
119 /* Regular traps; The cpu does not supply tf_err for these. */
122 movl $(a),TF_TRAPNO(%rsp) ; \
123 movq $0,TF_ADDR(%rsp) ; \
124 movq $0,TF_ERR(%rsp) ; \
147 /* This group of traps have tf_err already pushed by the cpu */
148 #define TRAP_ERR(a) \
150 movl $(a),TF_TRAPNO(%rsp) ; \
151 movq $0,TF_ADDR(%rsp) ; \
157 movl $T_SEGNPFLT,TF_TRAPNO(%rsp)
161 movl $T_STKFLT,TF_TRAPNO(%rsp)
167 * alltraps entry point. Use swapgs if this is the first time in the
168 * kernel from userland. Reenable interrupts if they were enabled
169 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
173 .type alltraps,@function
175 movq %rdi,TF_RDI(%rsp)
176 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
177 jz alltraps_testi /* already running with kernel GS.base */
179 movq PCPU(CURPCB),%rdi
180 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
186 testl $PSL_I,TF_RFLAGS(%rsp)
187 jz alltraps_pushregs_no_rdi
189 alltraps_pushregs_no_rdi:
190 movq %rsi,TF_RSI(%rsp)
191 movq %rdx,TF_RDX(%rsp)
192 movq %rcx,TF_RCX(%rsp)
195 movq %rax,TF_RAX(%rsp)
196 movq %rbx,TF_RBX(%rsp)
197 movq %rbp,TF_RBP(%rsp)
198 movq %r10,TF_R10(%rsp)
199 movq %r11,TF_R11(%rsp)
200 movq %r12,TF_R12(%rsp)
201 movq %r13,TF_R13(%rsp)
202 movq %r14,TF_R14(%rsp)
203 movq %r15,TF_R15(%rsp)
204 movl $TF_HASSEGS,TF_FLAGS(%rsp)
206 FAKE_MCOUNT(TF_RIP(%rsp))
209 * DTrace Function Boundary Trace (fbt) probes are triggered
210 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
211 * interrupt. For all other trap types, just handle them in
214 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
217 /* Check if there is no DTrace hook registered. */
218 cmpq $0,dtrace_invop_jump_addr
222 * Set our jump address for the jump back in the event that
223 * the breakpoint wasn't caused by DTrace at all.
225 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
227 /* Jump to the code hooked in by DTrace. */
228 jmpq *dtrace_invop_jump_addr
231 .type calltrap,@function
236 jmp doreti /* Handle any pending ASTs */
239 * alltraps_noen entry point. Unlike alltraps above, we want to
240 * leave the interrupts disabled. This corresponds to
241 * SDT_SYS386IGT on the i386 port.
245 .type alltraps_noen,@function
247 movq %rdi,TF_RDI(%rsp)
248 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
249 jz 1f /* already running with kernel GS.base */
251 movq PCPU(CURPCB),%rdi
252 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
253 1: movw %fs,TF_FS(%rsp)
257 jmp alltraps_pushregs_no_rdi
261 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
262 movq $0,TF_ADDR(%rsp)
264 movq %rdi,TF_RDI(%rsp)
265 movq %rsi,TF_RSI(%rsp)
266 movq %rdx,TF_RDX(%rsp)
267 movq %rcx,TF_RCX(%rsp)
270 movq %rax,TF_RAX(%rsp)
271 movq %rbx,TF_RBX(%rsp)
272 movq %rbp,TF_RBP(%rsp)
273 movq %r10,TF_R10(%rsp)
274 movq %r11,TF_R11(%rsp)
275 movq %r12,TF_R12(%rsp)
276 movq %r13,TF_R13(%rsp)
277 movq %r14,TF_R14(%rsp)
278 movq %r15,TF_R15(%rsp)
283 movl $TF_HASSEGS,TF_FLAGS(%rsp)
285 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
286 jz 1f /* already running with kernel GS.base */
290 call dblfault_handler
297 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
298 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
299 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
300 jz 1f /* already running with kernel GS.base */
302 movq PCPU(CURPCB),%rdi
303 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
304 1: movq %cr2,%rdi /* preserve %cr2 before .. */
305 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
310 testl $PSL_I,TF_RFLAGS(%rsp)
311 jz alltraps_pushregs_no_rdi
313 jmp alltraps_pushregs_no_rdi
316 * We have to special-case this one. If we get a trap in doreti() at
317 * the iretq stage, we'll reenter with the wrong gs state. We'll have
318 * to do a special the swapgs in this case even coming from the kernel.
319 * XXX linux has a trap handler for their equivalent of load_gs().
323 movl $T_PROTFLT,TF_TRAPNO(%rsp)
325 movq $0,TF_ADDR(%rsp)
326 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
327 leaq doreti_iret(%rip),%rdi
328 cmpq %rdi,TF_RIP(%rsp)
329 je 1f /* kernel but with user gsbase!! */
330 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
331 jz 2f /* already running with kernel GS.base */
333 2: movq PCPU(CURPCB),%rdi
334 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
339 testl $PSL_I,TF_RFLAGS(%rsp)
340 jz alltraps_pushregs_no_rdi
342 jmp alltraps_pushregs_no_rdi
345 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
346 * and the new privilige level. We are still running on the old user stack
347 * pointer. We have to juggle a few things around to find our stack etc.
348 * swapgs gives us access to our PCPU space only.
350 * We do not support invoking this from a custom %cs or %ss (e.g. using
351 * entries from an LDT).
355 movq %rsp,PCPU(SCRATCH_RSP)
357 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
359 /* defer TF_RSP till we have a spare register */
360 movq %r11,TF_RFLAGS(%rsp)
361 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
362 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
363 movq %r11,TF_RSP(%rsp) /* user stack pointer */
368 movq PCPU(CURPCB),%r11
369 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
371 movq $KUDSEL,TF_SS(%rsp)
372 movq $KUCSEL,TF_CS(%rsp)
374 movq %rdi,TF_RDI(%rsp) /* arg 1 */
375 movq %rsi,TF_RSI(%rsp) /* arg 2 */
376 movq %rdx,TF_RDX(%rsp) /* arg 3 */
377 movq %r10,TF_RCX(%rsp) /* arg 4 */
378 movq %r8,TF_R8(%rsp) /* arg 5 */
379 movq %r9,TF_R9(%rsp) /* arg 6 */
380 movq %rax,TF_RAX(%rsp) /* syscall number */
381 movq %rbx,TF_RBX(%rsp) /* C preserved */
382 movq %rbp,TF_RBP(%rsp) /* C preserved */
383 movq %r12,TF_R12(%rsp) /* C preserved */
384 movq %r13,TF_R13(%rsp) /* C preserved */
385 movq %r14,TF_R14(%rsp) /* C preserved */
386 movq %r15,TF_R15(%rsp) /* C preserved */
387 movl $TF_HASSEGS,TF_FLAGS(%rsp)
389 FAKE_MCOUNT(TF_RIP(%rsp))
390 movq PCPU(CURTHREAD),%rdi
391 movq %rsp,TD_FRAME(%rdi)
392 movl TF_RFLAGS(%rsp),%esi
395 1: movq PCPU(CURPCB),%rax
396 /* Disable interrupts before testing PCB_FULL_IRET. */
398 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
400 /* Check for and handle AST's on return to userland. */
401 movq PCPU(CURTHREAD),%rax
402 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
404 /* Restore preserved registers. */
406 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
407 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
408 movq TF_RDX(%rsp),%rdx /* return value 2 */
409 movq TF_RAX(%rsp),%rax /* return value 1 */
410 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
411 movq TF_RIP(%rsp),%rcx /* original %rip */
412 movq TF_RSP(%rsp),%rsp /* user stack pointer */
416 2: /* AST scheduled. */
422 3: /* Requested full context restore, use doreti for that. */
427 * Here for CYA insurance, in case a "syscall" instruction gets
428 * issued from 32 bit compatability mode. MSR_CSTAR has to point
429 * to *something* if EFER_SCE is enabled.
431 IDTVEC(fast_syscall32)
435 * NMI handling is special.
437 * First, NMIs do not respect the state of the processor's RFLAGS.IF
438 * bit. The NMI handler may be entered at any time, including when
439 * the processor is in a critical section with RFLAGS.IF == 0.
440 * The processor's GS.base value could be invalid on entry to the
443 * Second, the processor treats NMIs specially, blocking further NMIs
444 * until an 'iretq' instruction is executed. We thus need to execute
445 * the NMI handler with interrupts disabled, to prevent a nested interrupt
446 * from executing an 'iretq' instruction and inadvertently taking the
447 * processor out of NMI mode.
449 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
450 * GS.base value for the processor is stored just above the bottom of its
451 * NMI stack. For NMIs taken from kernel mode, the current value in
452 * the processor's GS.base is saved at entry to C-preserved register %r12,
453 * the canonical value for GS.base is then loaded into the processor, and
454 * the saved value is restored at exit time. For NMIs taken from user mode,
455 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
460 movl $(T_NMI),TF_TRAPNO(%rsp)
461 movq $0,TF_ADDR(%rsp)
463 movq %rdi,TF_RDI(%rsp)
464 movq %rsi,TF_RSI(%rsp)
465 movq %rdx,TF_RDX(%rsp)
466 movq %rcx,TF_RCX(%rsp)
469 movq %rax,TF_RAX(%rsp)
470 movq %rbx,TF_RBX(%rsp)
471 movq %rbp,TF_RBP(%rsp)
472 movq %r10,TF_R10(%rsp)
473 movq %r11,TF_R11(%rsp)
474 movq %r12,TF_R12(%rsp)
475 movq %r13,TF_R13(%rsp)
476 movq %r14,TF_R14(%rsp)
477 movq %r15,TF_R15(%rsp)
482 movl $TF_HASSEGS,TF_FLAGS(%rsp)
485 testb $SEL_RPL_MASK,TF_CS(%rsp)
486 jnz nmi_fromuserspace
488 * We've interrupted the kernel. Preserve GS.base in %r12.
490 movl $MSR_GSBASE,%ecx
495 /* Retrieve and load the canonical value for GS.base. */
496 movq TF_SIZE(%rsp),%rdx
504 /* Note: this label is also used by ddb and gdb: */
506 FAKE_MCOUNT(TF_RIP(%rsp))
512 * Capture a userspace callchain if needed.
514 * - Check if the current trap was from user mode.
515 * - Check if the current thread is valid.
516 * - Check if the thread requires a user call chain to be
519 * We are still in NMI mode at this point.
522 jz nocallchain /* not from userspace */
523 movq PCPU(CURTHREAD),%rax
524 orq %rax,%rax /* curthread present? */
526 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
529 * A user callchain is to be captured, so:
530 * - Move execution to the regular kernel stack, to allow for
531 * nested NMI interrupts.
532 * - Take the processor out of "NMI" mode by faking an "iret".
533 * - Enable interrupts, so that copyin() can work.
535 movq %rsp,%rsi /* source stack pointer */
539 movq %rdx,%rdi /* destination stack pointer */
541 shrq $3,%rcx /* trap frame size in long words */
544 movsq /* copy trapframe */
547 pushq %rax /* tf_ss */
548 pushq %rdx /* tf_rsp (on kernel stack) */
549 pushfq /* tf_rflags */
551 pushq %rax /* tf_cs */
552 pushq $outofnmi /* tf_rip */
556 * At this point the processor has exited NMI mode and is running
557 * with interrupts turned off on the normal kernel stack.
559 * If a pending NMI gets recognized at or after this point, it
560 * will cause a kernel callchain to be traced.
562 * We turn interrupts back on, and call the user callchain capture hook.
567 movq PCPU(CURTHREAD),%rdi /* thread */
568 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
569 movq %rsp,%rdx /* frame */
579 * Put back the preserved MSR_GSBASE value.
581 movl $MSR_GSBASE,%ecx
587 movq TF_RDI(%rsp),%rdi
588 movq TF_RSI(%rsp),%rsi
589 movq TF_RDX(%rsp),%rdx
590 movq TF_RCX(%rsp),%rcx
593 movq TF_RAX(%rsp),%rax
594 movq TF_RBX(%rsp),%rbx
595 movq TF_RBP(%rsp),%rbp
596 movq TF_R10(%rsp),%r10
597 movq TF_R11(%rsp),%r11
598 movq TF_R12(%rsp),%r12
599 movq TF_R13(%rsp),%r13
600 movq TF_R14(%rsp),%r14
601 movq TF_R15(%rsp),%r15
605 ENTRY(fork_trampoline)
606 movq %r12,%rdi /* function */
607 movq %rbx,%rsi /* arg1 */
608 movq %rsp,%rdx /* trapframe pointer */
611 jmp doreti /* Handle any ASTs */
614 * To efficiently implement classification of trap and interrupt handlers
615 * for profiling, there must be only trap handlers between the labels btrap
616 * and bintr, and only interrupt handlers between the labels bintr and
617 * eintr. This is implemented (partly) by including files that contain
618 * some of the handlers. Before including the files, set up a normal asm
619 * environment so that the included files doen't need to know that they are
623 #ifdef COMPAT_FREEBSD32
629 #include <amd64/ia32/ia32_exception.S>
638 #include <amd64/amd64/apic_vector.S>
646 #include <amd64/amd64/atpic_vector.S>
653 * void doreti(struct trapframe)
655 * Handle return from interrupts, traps and syscalls.
659 .type doreti,@function
661 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
663 * Check if ASTs can be handled now.
665 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
666 jz doreti_exit /* can't handle ASTs now if not */
670 * Check for ASTs atomically with returning. Disabling CPU
671 * interrupts provides sufficient locking even in the SMP case,
672 * since we will be informed of any new ASTs by an IPI.
675 movq PCPU(CURTHREAD),%rax
676 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
679 movq %rsp,%rdi /* pass a pointer to the trapframe */
684 * doreti_exit: pop registers, iret.
686 * The segment register pop is a special case, since it may
687 * fault if (for example) a sigreturn specifies bad segment
688 * registers. The fault is handled in trap.c.
692 movq PCPU(CURPCB),%r8
695 * Do not reload segment registers for kernel.
696 * Since we do not reload segments registers with sane
697 * values on kernel entry, descriptors referenced by
698 * segments registers might be not valid. This is fatal
699 * for user mode, but is not a problem for the kernel.
701 testb $SEL_RPL_MASK,TF_CS(%rsp)
703 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
705 testl $TF_HASSEGS,TF_FLAGS(%rsp)
709 /* Restore %fs and fsbase */
716 movl $MSR_FSBASE,%ecx
717 movl PCB_FSBASE(%r8),%eax
718 movl PCB_FSBASE+4(%r8),%edx
723 /* Restore %gs and gsbase */
727 movl $MSR_GSBASE,%ecx
728 /* Save current kernel %gs base into %r12d:%r13d */
735 /* Save user %gs base into %r14d:%r15d */
739 /* Restore kernel %gs base */
745 * Restore user %gs base, either from PCB if used for TLS, or
746 * from the previously saved msr read.
748 movl $MSR_KGSBASE,%ecx
751 movl PCB_GSBASE(%r8),%eax
752 movl PCB_GSBASE+4(%r8),%edx
759 wrmsr /* May trap if non-canonical, but only for TLS. */
767 movq TF_RDI(%rsp),%rdi
768 movq TF_RSI(%rsp),%rsi
769 movq TF_RDX(%rsp),%rdx
770 movq TF_RCX(%rsp),%rcx
773 movq TF_RAX(%rsp),%rax
774 movq TF_RBX(%rsp),%rbx
775 movq TF_RBP(%rsp),%rbp
776 movq TF_R10(%rsp),%r10
777 movq TF_R11(%rsp),%r11
778 movq TF_R12(%rsp),%r12
779 movq TF_R13(%rsp),%r13
780 movq TF_R14(%rsp),%r14
781 movq TF_R15(%rsp),%r15
782 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
783 jz 1f /* keep running with kernel GS.base */
787 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
796 movw $KUF32SEL,TF_FS(%rsp)
797 movw $KUG32SEL,TF_GS(%rsp)
801 * doreti_iret_fault. Alternative return code for
802 * the case where we get a fault in the doreti_exit code
803 * above. trap() (amd64/amd64/trap.c) catches this specific
804 * case, sends the process a signal and continues in the
805 * corresponding place in the code below.
808 .globl doreti_iret_fault
810 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
811 testl $PSL_I,TF_RFLAGS(%rsp)
819 movl $TF_HASSEGS,TF_FLAGS(%rsp)
820 movq %rdi,TF_RDI(%rsp)
821 movq %rsi,TF_RSI(%rsp)
822 movq %rdx,TF_RDX(%rsp)
823 movq %rcx,TF_RCX(%rsp)
826 movq %rax,TF_RAX(%rsp)
827 movq %rbx,TF_RBX(%rsp)
828 movq %rbp,TF_RBP(%rsp)
829 movq %r10,TF_R10(%rsp)
830 movq %r11,TF_R11(%rsp)
831 movq %r12,TF_R12(%rsp)
832 movq %r13,TF_R13(%rsp)
833 movq %r14,TF_R14(%rsp)
834 movq %r15,TF_R15(%rsp)
835 movl $T_PROTFLT,TF_TRAPNO(%rsp)
836 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
837 movq $0,TF_ADDR(%rsp)
838 FAKE_MCOUNT(TF_RIP(%rsp))
844 movl $T_PROTFLT,TF_TRAPNO(%rsp)
845 testl $PSL_I,TF_RFLAGS(%rsp)
851 movw $KUDSEL,TF_DS(%rsp)
857 movl $T_PROTFLT,TF_TRAPNO(%rsp)
858 testl $PSL_I,TF_RFLAGS(%rsp)
864 movw $KUDSEL,TF_ES(%rsp)
870 testl $PSL_I,TF_RFLAGS(%rsp)
874 movl $T_PROTFLT,TF_TRAPNO(%rsp)
877 movw $KUF32SEL,TF_FS(%rsp)
884 movl $T_PROTFLT,TF_TRAPNO(%rsp)
885 testl $PSL_I,TF_RFLAGS(%rsp)
891 movw $KUG32SEL,TF_GS(%rsp)
895 .globl fsbase_load_fault
897 movl $T_PROTFLT,TF_TRAPNO(%rsp)
898 testl $PSL_I,TF_RFLAGS(%rsp)
904 movq PCPU(CURTHREAD),%r8
906 movq $0,PCB_FSBASE(%r8)
910 .globl gsbase_load_fault
912 movl $T_PROTFLT,TF_TRAPNO(%rsp)
913 testl $PSL_I,TF_RFLAGS(%rsp)
919 movq PCPU(CURTHREAD),%r8
921 movq $0,PCB_GSBASE(%r8)
925 ENTRY(end_exceptions)