2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
41 #include <machine/asmacros.h>
42 #include <machine/psl.h>
43 #include <machine/trap.h>
44 #include <machine/specialreg.h>
50 .globl dtrace_invop_jump_addr
52 .type dtrace_invop_jump_addr,@object
53 .size dtrace_invop_jump_addr,8
54 dtrace_invop_jump_addr:
56 .globl dtrace_invop_calltrap_addr
58 .type dtrace_invop_calltrap_addr,@object
59 .size dtrace_invop_calltrap_addr,8
60 dtrace_invop_calltrap_addr:
65 ENTRY(start_exceptions)
68 /*****************************************************************************/
70 /*****************************************************************************/
72 * Trap and fault vector routines.
74 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
75 * state on the stack but also disables interrupts. This is important for
76 * us for the use of the swapgs instruction. We cannot be interrupted
77 * until the GS.base value is correct. For most traps, we automatically
78 * then enable interrupts if the interrupted context had them enabled.
79 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
81 * The cpu will push a certain amount of state onto the kernel stack for
82 * the current process. See amd64/include/frame.h.
83 * This includes the current RFLAGS (status register, which includes
84 * the interrupt disable state prior to the trap), the code segment register,
85 * and the return instruction pointer are pushed by the cpu. The cpu
86 * will also push an 'error' code for certain traps. We push a dummy
87 * error code for those traps where the cpu doesn't in order to maintain
88 * a consistent frame. We also push a contrived 'trap number'.
90 * The CPU does not push the general registers, so we must do that, and we
91 * must restore them prior to calling 'iret'. The CPU adjusts %cs and %ss
92 * but does not mess with %ds, %es, %gs or %fs. We swap the %gs base for
93 * for the kernel mode operation shortly, without changes to the selector
94 * loaded. Since superuser long mode works with any selectors loaded into
95 * segment registers other then %cs, which makes them mostly unused in long
96 * mode, and kernel does not reference %fs, leave them alone. The segment
97 * registers are reloaded on return to the usermode.
103 /* Traps that we leave interrupts disabled for.. */
104 #define TRAP_NOEN(a) \
106 movl $(a),TF_TRAPNO(%rsp) ; \
107 movq $0,TF_ADDR(%rsp) ; \
108 movq $0,TF_ERR(%rsp) ; \
116 TRAP_NOEN(T_DTRACE_RET)
119 /* Regular traps; The cpu does not supply tf_err for these. */
122 movl $(a),TF_TRAPNO(%rsp) ; \
123 movq $0,TF_ADDR(%rsp) ; \
124 movq $0,TF_ERR(%rsp) ; \
147 /* This group of traps have tf_err already pushed by the cpu */
148 #define TRAP_ERR(a) \
150 movl $(a),TF_TRAPNO(%rsp) ; \
151 movq $0,TF_ADDR(%rsp) ; \
157 movl $T_SEGNPFLT,TF_TRAPNO(%rsp)
161 movl $T_STKFLT,TF_TRAPNO(%rsp)
167 * alltraps entry point. Use swapgs if this is the first time in the
168 * kernel from userland. Reenable interrupts if they were enabled
169 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
173 .type alltraps,@function
175 movq %rdi,TF_RDI(%rsp)
176 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
177 jz alltraps_testi /* already running with kernel GS.base */
179 movq PCPU(CURPCB),%rdi
180 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
186 testl $PSL_I,TF_RFLAGS(%rsp)
187 jz alltraps_pushregs_no_rdi
189 alltraps_pushregs_no_rdi:
190 movq %rdx,TF_RDX(%rsp)
191 movq %rax,TF_RAX(%rsp)
192 alltraps_pushregs_no_rax:
193 movq %rsi,TF_RSI(%rsp)
194 movq %rcx,TF_RCX(%rsp)
197 movq %rbx,TF_RBX(%rsp)
198 movq %rbp,TF_RBP(%rsp)
199 movq %r10,TF_R10(%rsp)
200 movq %r11,TF_R11(%rsp)
201 movq %r12,TF_R12(%rsp)
202 movq %r13,TF_R13(%rsp)
203 movq %r14,TF_R14(%rsp)
204 movq %r15,TF_R15(%rsp)
205 movl $TF_HASSEGS,TF_FLAGS(%rsp)
207 FAKE_MCOUNT(TF_RIP(%rsp))
210 * DTrace Function Boundary Trace (fbt) probes are triggered
211 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
212 * interrupt. For all other trap types, just handle them in
215 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
216 jnz calltrap /* ignore userland traps */
217 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
220 /* Check if there is no DTrace hook registered. */
221 cmpq $0,dtrace_invop_jump_addr
225 * Set our jump address for the jump back in the event that
226 * the breakpoint wasn't caused by DTrace at all.
228 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
230 /* Jump to the code hooked in by DTrace. */
231 jmpq *dtrace_invop_jump_addr
234 .type calltrap,@function
239 jmp doreti /* Handle any pending ASTs */
242 * alltraps_noen entry point. Unlike alltraps above, we want to
243 * leave the interrupts disabled. This corresponds to
244 * SDT_SYS386IGT on the i386 port.
248 .type alltraps_noen,@function
250 movq %rdi,TF_RDI(%rsp)
251 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
252 jz 1f /* already running with kernel GS.base */
254 movq PCPU(CURPCB),%rdi
255 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
256 1: movw %fs,TF_FS(%rsp)
260 jmp alltraps_pushregs_no_rdi
264 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
265 movq $0,TF_ADDR(%rsp)
267 movq %rdi,TF_RDI(%rsp)
268 movq %rsi,TF_RSI(%rsp)
269 movq %rdx,TF_RDX(%rsp)
270 movq %rcx,TF_RCX(%rsp)
273 movq %rax,TF_RAX(%rsp)
274 movq %rbx,TF_RBX(%rsp)
275 movq %rbp,TF_RBP(%rsp)
276 movq %r10,TF_R10(%rsp)
277 movq %r11,TF_R11(%rsp)
278 movq %r12,TF_R12(%rsp)
279 movq %r13,TF_R13(%rsp)
280 movq %r14,TF_R14(%rsp)
281 movq %r15,TF_R15(%rsp)
286 movl $TF_HASSEGS,TF_FLAGS(%rsp)
288 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
289 jz 1f /* already running with kernel GS.base */
293 call dblfault_handler
300 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
301 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
302 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
303 jz 1f /* already running with kernel GS.base */
305 movq PCPU(CURPCB),%rdi
306 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
307 1: movq %cr2,%rdi /* preserve %cr2 before .. */
308 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
313 testl $PSL_I,TF_RFLAGS(%rsp)
314 jz alltraps_pushregs_no_rdi
316 jmp alltraps_pushregs_no_rdi
319 * We have to special-case this one. If we get a trap in doreti() at
320 * the iretq stage, we'll reenter with the wrong gs state. We'll have
321 * to do a special the swapgs in this case even coming from the kernel.
322 * XXX linux has a trap handler for their equivalent of load_gs().
326 movl $T_PROTFLT,TF_TRAPNO(%rsp)
328 movq $0,TF_ADDR(%rsp)
329 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
330 movq %rax,TF_RAX(%rsp)
331 movq %rdx,TF_RDX(%rsp)
334 leaq doreti_iret(%rip),%rdi
335 cmpq %rdi,TF_RIP(%rsp)
336 je 5f /* kernel but with user gsbase!! */
337 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
338 jz 6f /* already running with kernel GS.base */
339 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
341 cmpw $KUF32SEL,TF_FS(%rsp)
344 1: cmpw $KUG32SEL,TF_GS(%rsp)
348 movq PCPU(CURPCB),%rdi
349 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
351 cmpw $KUF32SEL,TF_FS(%rsp)
353 movq %rax,PCB_FSBASE(%rdi)
354 3: cmpw $KUG32SEL,TF_GS(%rsp)
356 movq %rdx,PCB_GSBASE(%rdi)
357 4: orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
360 testl $PSL_I,TF_RFLAGS(%rsp)
361 jz alltraps_pushregs_no_rax
363 jmp alltraps_pushregs_no_rax
366 6: movq PCPU(CURPCB),%rdi
370 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
371 * and the new privilige level. We are still running on the old user stack
372 * pointer. We have to juggle a few things around to find our stack etc.
373 * swapgs gives us access to our PCPU space only.
375 * We do not support invoking this from a custom segment registers,
376 * esp. %cs, %ss, %fs, %gs, e.g. using entries from an LDT.
380 movq %rsp,PCPU(SCRATCH_RSP)
382 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
384 /* defer TF_RSP till we have a spare register */
385 movq %r11,TF_RFLAGS(%rsp)
386 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
387 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
388 movq %r11,TF_RSP(%rsp) /* user stack pointer */
393 movq PCPU(CURPCB),%r11
394 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
396 movq $KUDSEL,TF_SS(%rsp)
397 movq $KUCSEL,TF_CS(%rsp)
399 movq %rdi,TF_RDI(%rsp) /* arg 1 */
400 movq %rsi,TF_RSI(%rsp) /* arg 2 */
401 movq %rdx,TF_RDX(%rsp) /* arg 3 */
402 movq %r10,TF_RCX(%rsp) /* arg 4 */
403 movq %r8,TF_R8(%rsp) /* arg 5 */
404 movq %r9,TF_R9(%rsp) /* arg 6 */
405 movq %rax,TF_RAX(%rsp) /* syscall number */
406 movq %rbx,TF_RBX(%rsp) /* C preserved */
407 movq %rbp,TF_RBP(%rsp) /* C preserved */
408 movq %r12,TF_R12(%rsp) /* C preserved */
409 movq %r13,TF_R13(%rsp) /* C preserved */
410 movq %r14,TF_R14(%rsp) /* C preserved */
411 movq %r15,TF_R15(%rsp) /* C preserved */
412 movl $TF_HASSEGS,TF_FLAGS(%rsp)
414 FAKE_MCOUNT(TF_RIP(%rsp))
415 movq PCPU(CURTHREAD),%rdi
416 movq %rsp,TD_FRAME(%rdi)
417 movl TF_RFLAGS(%rsp),%esi
420 1: movq PCPU(CURPCB),%rax
421 /* Disable interrupts before testing PCB_FULL_IRET. */
423 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
425 /* Check for and handle AST's on return to userland. */
426 movq PCPU(CURTHREAD),%rax
427 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
429 /* Restore preserved registers. */
431 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
432 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
433 movq TF_RDX(%rsp),%rdx /* return value 2 */
434 movq TF_RAX(%rsp),%rax /* return value 1 */
435 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
436 movq TF_RIP(%rsp),%rcx /* original %rip */
437 movq TF_RSP(%rsp),%rsp /* user stack pointer */
441 2: /* AST scheduled. */
447 3: /* Requested full context restore, use doreti for that. */
452 * Here for CYA insurance, in case a "syscall" instruction gets
453 * issued from 32 bit compatibility mode. MSR_CSTAR has to point
454 * to *something* if EFER_SCE is enabled.
456 IDTVEC(fast_syscall32)
460 * NMI handling is special.
462 * First, NMIs do not respect the state of the processor's RFLAGS.IF
463 * bit. The NMI handler may be entered at any time, including when
464 * the processor is in a critical section with RFLAGS.IF == 0.
465 * The processor's GS.base value could be invalid on entry to the
468 * Second, the processor treats NMIs specially, blocking further NMIs
469 * until an 'iretq' instruction is executed. We thus need to execute
470 * the NMI handler with interrupts disabled, to prevent a nested interrupt
471 * from executing an 'iretq' instruction and inadvertently taking the
472 * processor out of NMI mode.
474 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
475 * GS.base value for the processor is stored just above the bottom of its
476 * NMI stack. For NMIs taken from kernel mode, the current value in
477 * the processor's GS.base is saved at entry to C-preserved register %r12,
478 * the canonical value for GS.base is then loaded into the processor, and
479 * the saved value is restored at exit time. For NMIs taken from user mode,
480 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
485 movl $(T_NMI),TF_TRAPNO(%rsp)
486 movq $0,TF_ADDR(%rsp)
488 movq %rdi,TF_RDI(%rsp)
489 movq %rsi,TF_RSI(%rsp)
490 movq %rdx,TF_RDX(%rsp)
491 movq %rcx,TF_RCX(%rsp)
494 movq %rax,TF_RAX(%rsp)
495 movq %rbx,TF_RBX(%rsp)
496 movq %rbp,TF_RBP(%rsp)
497 movq %r10,TF_R10(%rsp)
498 movq %r11,TF_R11(%rsp)
499 movq %r12,TF_R12(%rsp)
500 movq %r13,TF_R13(%rsp)
501 movq %r14,TF_R14(%rsp)
502 movq %r15,TF_R15(%rsp)
507 movl $TF_HASSEGS,TF_FLAGS(%rsp)
510 testb $SEL_RPL_MASK,TF_CS(%rsp)
511 jnz nmi_fromuserspace
513 * We've interrupted the kernel. Preserve GS.base in %r12.
515 movl $MSR_GSBASE,%ecx
520 /* Retrieve and load the canonical value for GS.base. */
521 movq TF_SIZE(%rsp),%rdx
529 testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
531 movq PCPU(CURPCB),%rdi
534 cmpw $KUF32SEL,TF_FS(%rsp)
537 movq %rax,PCB_FSBASE(%rdi)
538 1: cmpw $KUG32SEL,TF_GS(%rsp)
540 movl $MSR_KGSBASE,%ecx
544 movq %rax,PCB_GSBASE(%rdi)
546 /* Note: this label is also used by ddb and gdb: */
548 FAKE_MCOUNT(TF_RIP(%rsp))
554 * Capture a userspace callchain if needed.
556 * - Check if the current trap was from user mode.
557 * - Check if the current thread is valid.
558 * - Check if the thread requires a user call chain to be
561 * We are still in NMI mode at this point.
564 jz nocallchain /* not from userspace */
565 movq PCPU(CURTHREAD),%rax
566 orq %rax,%rax /* curthread present? */
568 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
571 * A user callchain is to be captured, so:
572 * - Move execution to the regular kernel stack, to allow for
573 * nested NMI interrupts.
574 * - Take the processor out of "NMI" mode by faking an "iret".
575 * - Enable interrupts, so that copyin() can work.
577 movq %rsp,%rsi /* source stack pointer */
581 movq %rdx,%rdi /* destination stack pointer */
583 shrq $3,%rcx /* trap frame size in long words */
586 movsq /* copy trapframe */
589 pushq %rax /* tf_ss */
590 pushq %rdx /* tf_rsp (on kernel stack) */
591 pushfq /* tf_rflags */
593 pushq %rax /* tf_cs */
594 pushq $outofnmi /* tf_rip */
598 * At this point the processor has exited NMI mode and is running
599 * with interrupts turned off on the normal kernel stack.
601 * If a pending NMI gets recognized at or after this point, it
602 * will cause a kernel callchain to be traced.
604 * We turn interrupts back on, and call the user callchain capture hook.
609 movq PCPU(CURTHREAD),%rdi /* thread */
610 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
611 movq %rsp,%rdx /* frame */
621 * Put back the preserved MSR_GSBASE value.
623 movl $MSR_GSBASE,%ecx
629 movq TF_RDI(%rsp),%rdi
630 movq TF_RSI(%rsp),%rsi
631 movq TF_RDX(%rsp),%rdx
632 movq TF_RCX(%rsp),%rcx
635 movq TF_RAX(%rsp),%rax
636 movq TF_RBX(%rsp),%rbx
637 movq TF_RBP(%rsp),%rbp
638 movq TF_R10(%rsp),%r10
639 movq TF_R11(%rsp),%r11
640 movq TF_R12(%rsp),%r12
641 movq TF_R13(%rsp),%r13
642 movq TF_R14(%rsp),%r14
643 movq TF_R15(%rsp),%r15
647 ENTRY(fork_trampoline)
648 movq %r12,%rdi /* function */
649 movq %rbx,%rsi /* arg1 */
650 movq %rsp,%rdx /* trapframe pointer */
653 jmp doreti /* Handle any ASTs */
656 * To efficiently implement classification of trap and interrupt handlers
657 * for profiling, there must be only trap handlers between the labels btrap
658 * and bintr, and only interrupt handlers between the labels bintr and
659 * eintr. This is implemented (partly) by including files that contain
660 * some of the handlers. Before including the files, set up a normal asm
661 * environment so that the included files doen't need to know that they are
665 #ifdef COMPAT_FREEBSD32
671 #include <amd64/ia32/ia32_exception.S>
680 #include <amd64/amd64/apic_vector.S>
688 #include <amd64/amd64/atpic_vector.S>
695 * void doreti(struct trapframe)
697 * Handle return from interrupts, traps and syscalls.
701 .type doreti,@function
704 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
706 * Check if ASTs can be handled now.
708 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
709 jz doreti_exit /* can't handle ASTs now if not */
713 * Check for ASTs atomically with returning. Disabling CPU
714 * interrupts provides sufficient locking even in the SMP case,
715 * since we will be informed of any new ASTs by an IPI.
718 movq PCPU(CURTHREAD),%rax
719 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
722 movq %rsp,%rdi /* pass a pointer to the trapframe */
727 * doreti_exit: pop registers, iret.
729 * The segment register pop is a special case, since it may
730 * fault if (for example) a sigreturn specifies bad segment
731 * registers. The fault is handled in trap.c.
735 movq PCPU(CURPCB),%r8
738 * Do not reload segment registers for kernel.
739 * Since we do not reload segments registers with sane
740 * values on kernel entry, descriptors referenced by
741 * segments registers might be not valid. This is fatal
742 * for user mode, but is not a problem for the kernel.
744 testb $SEL_RPL_MASK,TF_CS(%rsp)
746 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
748 andl $~PCB_FULL_IRET,PCB_FLAGS(%r8)
749 testl $TF_HASSEGS,TF_FLAGS(%rsp)
753 /* Restore %fs and fsbase */
760 movl $MSR_FSBASE,%ecx
761 movl PCB_FSBASE(%r8),%eax
762 movl PCB_FSBASE+4(%r8),%edx
767 /* Restore %gs and gsbase */
771 movl $MSR_GSBASE,%ecx
772 /* Save current kernel %gs base into %r12d:%r13d */
779 /* Save user %gs base into %r14d:%r15d */
783 /* Restore kernel %gs base */
789 * Restore user %gs base, either from PCB if used for TLS, or
790 * from the previously saved msr read.
792 movl $MSR_KGSBASE,%ecx
795 movl PCB_GSBASE(%r8),%eax
796 movl PCB_GSBASE+4(%r8),%edx
803 wrmsr /* May trap if non-canonical, but only for TLS. */
811 movq TF_RDI(%rsp),%rdi
812 movq TF_RSI(%rsp),%rsi
813 movq TF_RDX(%rsp),%rdx
814 movq TF_RCX(%rsp),%rcx
817 movq TF_RAX(%rsp),%rax
818 movq TF_RBX(%rsp),%rbx
819 movq TF_RBP(%rsp),%rbp
820 movq TF_R10(%rsp),%r10
821 movq TF_R11(%rsp),%r11
822 movq TF_R12(%rsp),%r12
823 movq TF_R13(%rsp),%r13
824 movq TF_R14(%rsp),%r14
825 movq TF_R15(%rsp),%r15
826 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
827 jz 1f /* keep running with kernel GS.base */
831 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
840 movw $KUF32SEL,TF_FS(%rsp)
841 movw $KUG32SEL,TF_GS(%rsp)
845 * doreti_iret_fault. Alternative return code for
846 * the case where we get a fault in the doreti_exit code
847 * above. trap() (amd64/amd64/trap.c) catches this specific
848 * case, sends the process a signal and continues in the
849 * corresponding place in the code below.
852 .globl doreti_iret_fault
854 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
855 testl $PSL_I,TF_RFLAGS(%rsp)
863 movl $TF_HASSEGS,TF_FLAGS(%rsp)
864 movq %rdi,TF_RDI(%rsp)
865 movq %rsi,TF_RSI(%rsp)
866 movq %rdx,TF_RDX(%rsp)
867 movq %rcx,TF_RCX(%rsp)
870 movq %rax,TF_RAX(%rsp)
871 movq %rbx,TF_RBX(%rsp)
872 movq %rbp,TF_RBP(%rsp)
873 movq %r10,TF_R10(%rsp)
874 movq %r11,TF_R11(%rsp)
875 movq %r12,TF_R12(%rsp)
876 movq %r13,TF_R13(%rsp)
877 movq %r14,TF_R14(%rsp)
878 movq %r15,TF_R15(%rsp)
879 movl $T_PROTFLT,TF_TRAPNO(%rsp)
880 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
881 movq $0,TF_ADDR(%rsp)
882 FAKE_MCOUNT(TF_RIP(%rsp))
888 movl $T_PROTFLT,TF_TRAPNO(%rsp)
889 testl $PSL_I,TF_RFLAGS(%rsp)
895 movw $KUDSEL,TF_DS(%rsp)
901 movl $T_PROTFLT,TF_TRAPNO(%rsp)
902 testl $PSL_I,TF_RFLAGS(%rsp)
908 movw $KUDSEL,TF_ES(%rsp)
914 testl $PSL_I,TF_RFLAGS(%rsp)
918 movl $T_PROTFLT,TF_TRAPNO(%rsp)
921 movw $KUF32SEL,TF_FS(%rsp)
928 movl $T_PROTFLT,TF_TRAPNO(%rsp)
929 testl $PSL_I,TF_RFLAGS(%rsp)
935 movw $KUG32SEL,TF_GS(%rsp)
939 .globl fsbase_load_fault
941 movl $T_PROTFLT,TF_TRAPNO(%rsp)
942 testl $PSL_I,TF_RFLAGS(%rsp)
948 movq PCPU(CURTHREAD),%r8
950 movq $0,PCB_FSBASE(%r8)
954 .globl gsbase_load_fault
956 movl $T_PROTFLT,TF_TRAPNO(%rsp)
957 testl $PSL_I,TF_RFLAGS(%rsp)
963 movq PCPU(CURTHREAD),%r8
965 movq $0,PCB_GSBASE(%r8)
969 ENTRY(end_exceptions)