2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
41 #include "opt_debug_npx.h"
42 #include "opt_math_emulate.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
50 #include <sys/sysctl.h>
52 #include <machine/bus.h>
55 #include <sys/syslog.h>
57 #include <sys/signalvar.h>
60 #include <machine/asmacros.h>
62 #include <machine/cputypes.h>
63 #include <machine/frame.h>
64 #include <machine/ipl.h>
65 #include <machine/md_var.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
69 #include <machine/clock.h>
71 #include <machine/resource.h>
72 #include <machine/specialreg.h>
73 #include <machine/segments.h>
76 #include <i386/isa/icu.h>
77 #include <i386/isa/intr_machdep.h>
78 #include <i386/isa/isa.h>
82 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
85 /* Configuration flags. */
86 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
87 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
88 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
89 #define NPX_PREFER_EMULATOR (1 << 3)
93 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
94 #define fnclex() __asm("fnclex")
95 #define fninit() __asm("fninit")
96 #define fnop() __asm("fnop")
97 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
98 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
99 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
100 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
101 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
102 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
103 : : "n" (CR0_TS) : "ax")
104 #define stop_emulating() __asm("clts")
106 #else /* not __GNUC__ */
108 void fldcw __P((caddr_t addr));
109 void fnclex __P((void));
110 void fninit __P((void));
111 void fnop __P((void));
112 void fnsave __P((caddr_t addr));
113 void fnstcw __P((caddr_t addr));
114 void fnstsw __P((caddr_t addr));
115 void fp_divide_by_0 __P((void));
116 void frstor __P((caddr_t addr));
117 void start_emulating __P((void));
118 void stop_emulating __P((void));
120 #endif /* __GNUC__ */
122 typedef u_char bool_t;
124 static int npx_attach __P((device_t dev));
125 void npx_intr __P((void *));
126 static void npx_identify __P((driver_t *driver, device_t parent));
127 static int npx_probe __P((device_t dev));
128 static int npx_probe1 __P((device_t dev));
130 static long timezero __P((const char *funcname,
131 void (*func)(void *buf, size_t len)));
132 #endif /* I586_CPU */
134 int hw_float; /* XXX currently just alias for npx_exists */
136 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
137 CTLFLAG_RD, &hw_float, 0,
138 "Floatingpoint instructions executed in hardware");
141 static u_int npx0_imask = SWI_CLOCK_MASK;
142 static struct gate_descriptor npx_idt_probeintr;
143 static int npx_intrno;
144 static volatile u_int npx_intrs_while_probing;
145 static volatile u_int npx_traps_while_probing;
148 static bool_t npx_ex16;
149 static bool_t npx_exists;
150 static bool_t npx_irq13;
151 static int npx_irq; /* irq number */
155 * Special interrupt handlers. Someday intr0-intr15 will be used to count
156 * interrupts. We'll still need a special exception 16 handler. The busy
157 * latch stuff in probeintr() can be moved to npxprobe().
163 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
164 " __XSTRING(CNAME(probeintr)) ": \n\
166 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
168 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
169 outb %al,$0xa0 # IO_ICU2 \n\
170 outb %al,$0x20 # IO_ICU1 \n\
172 outb %al,$0xf0 # clear BUSY# latch \n\
181 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
182 " __XSTRING(CNAME(probetrap)) ": \n\
184 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
191 * Identify routine. Create a connection point on our parent for probing.
194 npx_identify(driver, parent)
200 child = BUS_ADD_CHILD(parent, 0, "npx", 0);
202 panic("npx_identify");
206 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
207 * whether the device exists or not (XXX should be elsewhere). Set flags
208 * to tell npxattach() what to do. Modify device struct if npx doesn't
209 * need to use interrupts. Return 1 if device exists.
217 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
219 return npx_probe1(dev);
225 u_char save_icu1_mask;
226 u_char save_icu2_mask;
227 struct gate_descriptor save_idt_npxintr;
228 struct gate_descriptor save_idt_npxtrap;
230 * This routine is now just a wrapper for npxprobe1(), to install
231 * special npx interrupt and trap handlers, to enable npx interrupts
232 * and to disable other interrupts. Someday isa_configure() will
233 * install suitable handlers and run with interrupts enabled so we
234 * won't need to do so much here.
236 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
238 npx_intrno = NRSVIDT + npx_irq;
239 save_eflags = read_eflags();
241 save_icu1_mask = inb(IO_ICU1 + 1);
242 save_icu2_mask = inb(IO_ICU2 + 1);
243 save_idt_npxintr = idt[npx_intrno];
244 save_idt_npxtrap = idt[16];
245 outb(IO_ICU1 + 1, ~IRQ_SLAVE);
246 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
247 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
248 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
249 npx_idt_probeintr = idt[npx_intrno];
251 result = npx_probe1(dev);
253 outb(IO_ICU1 + 1, save_icu1_mask);
254 outb(IO_ICU2 + 1, save_icu2_mask);
255 idt[npx_intrno] = save_idt_npxintr;
256 idt[16] = save_idt_npxtrap;
257 write_eflags(save_eflags);
273 * Partially reset the coprocessor, if any. Some BIOS's don't reset
274 * it after a warm boot.
276 outb(0xf1, 0); /* full reset on some systems, NOP on others */
277 outb(0xf0, 0); /* clear BUSY# latch */
279 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
280 * instructions. We must set the CR0_MP bit and use the CR0_TS
281 * bit to control the trap, because setting the CR0_EM bit does
282 * not cause WAIT instructions to trap. It's important to trap
283 * WAIT instructions - otherwise the "wait" variants of no-wait
284 * control instructions would degenerate to the "no-wait" variants
285 * after FP context switches but work correctly otherwise. It's
286 * particularly important to trap WAITs when there is no NPX -
287 * otherwise the "wait" variants would always degenerate.
289 * Try setting CR0_NE to get correct error reporting on 486DX's.
290 * Setting it should fail or do nothing on lesser processors.
292 load_cr0(rcr0() | CR0_MP | CR0_NE);
294 * But don't trap while we're probing.
298 * Finish resetting the coprocessor, if any. If there is an error
299 * pending, then we may get a bogus IRQ13, but probeintr() will handle
300 * it OK. Bogus halts have never been observed, but we enabled
301 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
307 * Exception 16 MUST work for SMP.
310 npx_ex16 = hw_float = npx_exists = 1;
311 device_set_desc(dev, "math processor");
315 device_set_desc(dev, "math processor");
318 * Don't use fwait here because it might hang.
319 * Don't use fnop here because it usually hangs if there is no FPU.
321 DELAY(1000); /* wait for any IRQ13 */
323 if (npx_intrs_while_probing != 0)
324 printf("fninit caused %u bogus npx interrupt(s)\n",
325 npx_intrs_while_probing);
326 if (npx_traps_while_probing != 0)
327 printf("fninit caused %u bogus npx trap(s)\n",
328 npx_traps_while_probing);
331 * Check for a status of mostly zero.
335 if ((status & 0xb8ff) == 0) {
337 * Good, now check for a proper control word.
341 if ((control & 0x1f3f) == 0x033f) {
342 hw_float = npx_exists = 1;
344 * We have an npx, now divide by 0 to see if exception
347 control &= ~(1 << 2); /* enable divide by 0 trap */
349 npx_traps_while_probing = npx_intrs_while_probing = 0;
351 if (npx_traps_while_probing != 0) {
353 * Good, exception 16 works.
358 if (npx_intrs_while_probing != 0) {
363 * Bad, we are stuck with IRQ13.
367 * npxattach would be too late to set npx0_imask
369 npx0_imask |= (1 << npx_irq);
372 * We allocate these resources permanently,
373 * so there is no need to keep track of them.
376 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
377 &rid, IO_NPX, IO_NPX,
378 IO_NPXSIZE, RF_ACTIVE);
380 panic("npx: can't get ports");
382 r = bus_alloc_resource(dev, SYS_RES_IRQ,
383 &rid, npx_irq, npx_irq,
386 panic("npx: can't get IRQ");
387 BUS_SETUP_INTR(device_get_parent(dev),
388 dev, r, INTR_TYPE_MISC,
391 panic("npx: can't create intr");
396 * Worse, even IRQ13 is broken. Use emulator.
401 * Probe failed, but we want to get to npxattach to initialize the
402 * emulator and say that it has been installed. XXX handle devices
403 * that aren't really devices better.
410 * Attach routine - announce which it is, and wire into system
418 if (resource_int_value("npx", 0, "flags", &flags) != 0)
421 device_print_prettyname(dev);
423 printf("flags 0x%x ", flags);
425 printf("using IRQ 13 interface\n");
427 #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE)
429 if (!(flags & NPX_PREFER_EMULATOR))
430 printf("INT 16 interface\n");
432 printf("FPU exists, but flags request "
434 hw_float = npx_exists = 0;
436 } else if (npx_exists) {
437 printf("error reporting broken; using 387 emulator\n");
438 hw_float = npx_exists = 0;
440 printf("387 emulator\n");
443 printf("INT 16 interface\n");
444 if (flags & NPX_PREFER_EMULATOR) {
445 printf("emulator requested, but none compiled "
446 "into kernel, using FPU\n");
449 printf("no 387 emulator in kernel and no FPU!\n");
452 npxinit(__INITIAL_NPXCW__);
455 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
456 timezero("i586_bzero()", i586_bzero) <
457 timezero("bzero()", bzero) * 4 / 5) {
458 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
459 bcopy_vector = i586_bcopy;
460 ovbcopy_vector = i586_bcopy;
462 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
464 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
465 copyin_vector = i586_copyin;
466 copyout_vector = i586_copyout;
471 return (0); /* XXX unused */
475 * Initialize floating point unit.
486 * fninit has the same h/w bugs as fnsave. Use the detoxified
487 * fnsave to throw away any junk in the fpu. npxsave() initializes
488 * the fpu and sets npxproc = NULL as important side effects.
494 fnsave(&curpcb->pcb_savefpu);
499 * Free coprocessor (if we have it).
507 npxsave(&curpcb->pcb_savefpu);
510 u_int masked_exceptions;
512 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw
513 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f;
515 * Log exceptions that would have trapped with the old
516 * control word (overflow, divide by 0, and invalid operand).
518 if (masked_exceptions & 0x0d)
520 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
521 p->p_pid, p->p_comm, masked_exceptions);
527 * The following mechanism is used to ensure that the FPE_... value
528 * that is passed as a trapcode to the signal handler of the user
529 * process does not have more than one bit set.
531 * Multiple bits may be set if the user process modifies the control
532 * word while a status word bit is already set. While this is a sign
533 * of bad coding, we have no choise than to narrow them down to one
534 * bit, since we must not send a trapcode that is not exactly one of
537 * The mechanism has a static table with 127 entries. Each combination
538 * of the 7 FPU status word exception bits directly translates to a
539 * position in this table, where a single FPE_... value is stored.
540 * This FPE_... value stored there is considered the "most important"
541 * of the exception bits and will be sent as the signal code. The
542 * precedence of the bits is based upon Intel Document "Numerical
543 * Applications", Chapter "Special Computational Situations".
545 * The macro to choose one of these values does these steps: 1) Throw
546 * away status word bits that cannot be masked. 2) Throw away the bits
547 * currently masked in the control word, assuming the user isn't
548 * interested in them anymore. 3) Reinsert status word bit 7 (stack
549 * fault) if it is set, which cannot be masked but must be presered.
550 * 4) Use the remaining bits to point into the trapcode table.
552 * The 6 maskable bits in order of their preference, as stated in the
553 * above referenced Intel manual:
554 * 1 Invalid operation (FP_X_INV)
557 * 1c Operand of unsupported format
559 * 2 QNaN operand (not an exception, irrelavant here)
560 * 3 Any other invalid-operation not mentioned above or zero divide
561 * (FP_X_INV, FP_X_DZ)
562 * 4 Denormal operand (FP_X_DNML)
563 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
564 * 6 Inexact result (FP_X_IMP)
566 static char fpetable[128] = {
568 FPE_FLTINV, /* 1 - INV */
569 FPE_FLTUND, /* 2 - DNML */
570 FPE_FLTINV, /* 3 - INV | DNML */
571 FPE_FLTDIV, /* 4 - DZ */
572 FPE_FLTINV, /* 5 - INV | DZ */
573 FPE_FLTDIV, /* 6 - DNML | DZ */
574 FPE_FLTINV, /* 7 - INV | DNML | DZ */
575 FPE_FLTOVF, /* 8 - OFL */
576 FPE_FLTINV, /* 9 - INV | OFL */
577 FPE_FLTUND, /* A - DNML | OFL */
578 FPE_FLTINV, /* B - INV | DNML | OFL */
579 FPE_FLTDIV, /* C - DZ | OFL */
580 FPE_FLTINV, /* D - INV | DZ | OFL */
581 FPE_FLTDIV, /* E - DNML | DZ | OFL */
582 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
583 FPE_FLTUND, /* 10 - UFL */
584 FPE_FLTINV, /* 11 - INV | UFL */
585 FPE_FLTUND, /* 12 - DNML | UFL */
586 FPE_FLTINV, /* 13 - INV | DNML | UFL */
587 FPE_FLTDIV, /* 14 - DZ | UFL */
588 FPE_FLTINV, /* 15 - INV | DZ | UFL */
589 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
590 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
591 FPE_FLTOVF, /* 18 - OFL | UFL */
592 FPE_FLTINV, /* 19 - INV | OFL | UFL */
593 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
594 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
595 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
596 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
597 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
598 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
599 FPE_FLTRES, /* 20 - IMP */
600 FPE_FLTINV, /* 21 - INV | IMP */
601 FPE_FLTUND, /* 22 - DNML | IMP */
602 FPE_FLTINV, /* 23 - INV | DNML | IMP */
603 FPE_FLTDIV, /* 24 - DZ | IMP */
604 FPE_FLTINV, /* 25 - INV | DZ | IMP */
605 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
606 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
607 FPE_FLTOVF, /* 28 - OFL | IMP */
608 FPE_FLTINV, /* 29 - INV | OFL | IMP */
609 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
610 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
611 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
612 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
613 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
614 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
615 FPE_FLTUND, /* 30 - UFL | IMP */
616 FPE_FLTINV, /* 31 - INV | UFL | IMP */
617 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
618 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
619 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
620 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
621 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
622 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
623 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
624 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
625 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
626 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
627 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
628 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
629 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
630 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
631 FPE_FLTSUB, /* 40 - STK */
632 FPE_FLTSUB, /* 41 - INV | STK */
633 FPE_FLTUND, /* 42 - DNML | STK */
634 FPE_FLTSUB, /* 43 - INV | DNML | STK */
635 FPE_FLTDIV, /* 44 - DZ | STK */
636 FPE_FLTSUB, /* 45 - INV | DZ | STK */
637 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
638 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
639 FPE_FLTOVF, /* 48 - OFL | STK */
640 FPE_FLTSUB, /* 49 - INV | OFL | STK */
641 FPE_FLTUND, /* 4A - DNML | OFL | STK */
642 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
643 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
644 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
645 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
646 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
647 FPE_FLTUND, /* 50 - UFL | STK */
648 FPE_FLTSUB, /* 51 - INV | UFL | STK */
649 FPE_FLTUND, /* 52 - DNML | UFL | STK */
650 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
651 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
652 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
653 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
654 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
655 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
656 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
657 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
658 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
659 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
660 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
661 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
662 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
663 FPE_FLTRES, /* 60 - IMP | STK */
664 FPE_FLTSUB, /* 61 - INV | IMP | STK */
665 FPE_FLTUND, /* 62 - DNML | IMP | STK */
666 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
667 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
668 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
669 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
670 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
671 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
672 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
673 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
674 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
675 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
676 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
677 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
678 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
679 FPE_FLTUND, /* 70 - UFL | IMP | STK */
680 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
681 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
682 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
683 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
684 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
685 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
686 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
687 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
688 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
689 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
690 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
691 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
692 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
693 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
694 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
698 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
700 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
701 * depend on longjmp() restoring a usable state. Restoring the state
702 * or examining it might fail if we didn't clear exceptions.
704 * The error code chosen will be one of the FPE_... macros. It will be
705 * sent as the second argument to old BSD-style signal handlers and as
706 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
708 * XXX the FP state is not preserved across signal handlers. So signal
709 * handlers cannot afford to do FP unless they preserve the state or
710 * longjmp() out. Both preserving the state and longjmp()ing may be
711 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
712 * solution for signals other than SIGFPE.
720 struct intrframe *frame;
722 if (npxproc == NULL || !npx_exists) {
723 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n",
724 npxproc, curproc, npx_exists);
725 panic("npxintr from nowhere");
727 if (npxproc != curproc) {
728 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n",
729 npxproc, curproc, npx_exists);
730 panic("npxintr from non-current process");
734 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw);
739 * Pass exception to process.
741 frame = (struct intrframe *)&dummy; /* XXX */
742 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
744 * Interrupt is essentially a trap, so we can afford to call
745 * the SIGFPE handler (if any) as soon as the interrupt
748 * XXX little or nothing is gained from this, and plenty is
749 * lost - the interrupt frame has to contain the trap frame
750 * (this is otherwise only necessary for the rescheduling trap
751 * in doreti, and the frame for that could easily be set up
752 * just before it is used).
754 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
756 * Encode the appropriate code for detailed information on
760 fpetable[(curpcb->pcb_savefpu.sv_ex_sw & ~control & 0x3f) |
761 (curpcb->pcb_savefpu.sv_ex_sw & 0x40)];
762 trapsignal(curproc, SIGFPE, code);
765 * Nested interrupt. These losers occur when:
766 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
767 * o immediately after an fnsave or frstor of an
769 * o a couple of 386 instructions after
770 * "fstpl _memvar" causes a stack overflow.
771 * These are especially nasty when combined with a
773 * o an IRQ13 occurs at the same time as another higher-
774 * priority interrupt.
776 * Treat them like a true async interrupt.
778 psignal(curproc, SIGFPE);
783 * Implement device not available (DNA) exception
785 * It would be better to switch FP context here (if curproc != npxproc)
786 * and not necessarily for every context switch, but it is too hard to
787 * access foreign pcb's.
794 if (npxproc != NULL) {
795 printf("npxdna: npxproc = %p, curproc = %p\n",
801 * Record new context early in case frstor causes an IRQ13.
804 curpcb->pcb_savefpu.sv_ex_sw = 0;
806 * The following frstor may cause an IRQ13 when the state being
807 * restored has a pending error. The error will appear to have been
808 * triggered by the current (npx) user instruction even when that
809 * instruction is a no-wait instruction that should not trigger an
810 * error (e.g., fnclex). On at least one 486 system all of the
811 * no-wait instructions are broken the same as frstor, so our
812 * treatment does not amplify the breakage. On at least one
813 * 386/Cyrix 387 system, fnclex works correctly while frstor and
814 * fnsave are broken, so our treatment breaks fnclex if it is the
815 * first FPU instruction after a context switch.
817 frstor(&curpcb->pcb_savefpu);
823 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error
824 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
825 * any IRQ13 to be handled immediately, and then ignore it. This routine is
826 * often called at splhigh so it must not use many system services. In
827 * particular, it's much easier to install a special handler than to
828 * guarantee that it's safe to use npxintr() and its supporting code.
846 u_char old_icu1_mask;
847 u_char old_icu2_mask;
848 struct gate_descriptor save_idt_npxintr;
851 old_icu1_mask = inb(IO_ICU1 + 1);
852 old_icu2_mask = inb(IO_ICU2 + 1);
853 save_idt_npxintr = idt[npx_intrno];
854 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
855 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
856 idt[npx_intrno] = npx_idt_probeintr;
864 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
865 icu2_mask = inb(IO_ICU2 + 1);
867 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
869 (icu2_mask & ~(npx0_imask >> 8))
870 | (old_icu2_mask & (npx0_imask >> 8)));
871 idt[npx_intrno] = save_idt_npxintr;
872 enable_intr(); /* back to usual state */
879 timezero(funcname, func)
880 const char *funcname;
881 void (*func) __P((void *buf, size_t len));
885 #define BUFSIZE 1000000
887 struct timeval finish, start;
889 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
893 (*func)(buf, BUFSIZE);
895 usec = 1000000 * (finish.tv_sec - start.tv_sec) +
896 finish.tv_usec - start.tv_usec;
900 printf("%s bandwidth = %ld bytes/sec\n",
901 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec));
905 #endif /* I586_CPU */
907 static device_method_t npx_methods[] = {
908 /* Device interface */
909 DEVMETHOD(device_identify, npx_identify),
910 DEVMETHOD(device_probe, npx_probe),
911 DEVMETHOD(device_attach, npx_attach),
912 DEVMETHOD(device_detach, bus_generic_detach),
913 DEVMETHOD(device_shutdown, bus_generic_shutdown),
914 DEVMETHOD(device_suspend, bus_generic_suspend),
915 DEVMETHOD(device_resume, bus_generic_resume),
920 static driver_t npx_driver = {
926 static devclass_t npx_devclass;
929 * We prefer to attach to the root nexus so that the usual case (exception 16)
930 * doesn't describe the processor as being `on isa'.
932 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
934 #endif /* NNPX > 0 */