2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1990 William Jolitz.
5 * Copyright (c) 1991 The Regents of the University of California.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/mutex.h>
48 #include <sys/sysctl.h>
49 #include <machine/bus.h>
51 #include <sys/signalvar.h>
54 #include <machine/cputypes.h>
55 #include <machine/frame.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/md_var.h>
58 #include <machine/pcb.h>
59 #include <machine/psl.h>
60 #include <machine/resource.h>
61 #include <machine/specialreg.h>
62 #include <machine/segments.h>
63 #include <machine/ucontext.h>
66 * Floating point support.
69 #if defined(__GNUCLIKE_ASM) && !defined(lint)
71 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
72 #define fnclex() __asm __volatile("fnclex")
73 #define fninit() __asm __volatile("fninit")
74 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
75 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
76 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
77 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
78 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
79 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
82 xrstor(char *addr, uint64_t mask)
88 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
92 xsave(char *addr, uint64_t mask)
98 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
102 #else /* !(__GNUCLIKE_ASM && !lint) */
104 void fldcw(u_short cw);
107 void fnstcw(caddr_t addr);
108 void fnstsw(caddr_t addr);
109 void fxsave(caddr_t addr);
110 void fxrstor(caddr_t addr);
111 void ldmxcsr(u_int csr);
112 void stmxcsr(u_int *csr);
113 void xrstor(char *addr, uint64_t mask);
114 void xsave(char *addr, uint64_t mask);
116 #endif /* __GNUCLIKE_ASM && !lint */
118 #define start_emulating() load_cr0(rcr0() | CR0_TS)
119 #define stop_emulating() clts()
121 CTASSERT(sizeof(struct savefpu) == 512);
122 CTASSERT(sizeof(struct xstate_hdr) == 64);
123 CTASSERT(sizeof(struct savefpu_ymm) == 832);
126 * This requirement is to make it easier for asm code to calculate
127 * offset of the fpu save area from the pcb address. FPU save area
128 * must be 64-byte aligned.
130 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
133 * Ensure the copy of XCR0 saved in a core is contained in the padding
136 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) &&
137 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu));
139 static void fpu_clean_state(void);
141 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
142 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware");
144 int use_xsave; /* non-static for cpu_switch.S */
145 uint64_t xsave_mask; /* the same */
146 static uma_zone_t fpu_save_area_zone;
147 static struct savefpu *fpu_initialstate;
149 struct xsave_area_elm_descr {
159 xsave((char *)addr, xsave_mask);
161 fxsave((char *)addr);
165 fpurestore(void *addr)
169 xrstor((char *)addr, xsave_mask);
171 fxrstor((char *)addr);
175 fpususpend(void *addr)
186 fpuresume(void *addr)
194 load_xcr(XCR0, xsave_mask);
200 * Enable XSAVE if supported and allowed by user.
201 * Calculate the xsave_mask.
207 uint64_t xsave_mask_user;
210 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
212 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
217 cpuid_count(0xd, 0x0, cp);
218 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
219 if ((cp[0] & xsave_mask) != xsave_mask)
220 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
221 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
222 xsave_mask_user = xsave_mask;
223 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
224 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
225 xsave_mask &= xsave_mask_user;
226 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
227 xsave_mask &= ~XFEATURE_AVX512;
228 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
229 xsave_mask &= ~XFEATURE_MPX;
231 cpuid_count(0xd, 0x1, cp);
232 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
234 * Patch the XSAVE instruction in the cpu_switch code
235 * to XSAVEOPT. We assume that XSAVE encoding used
236 * REX byte, and set the bit 4 of the r/m byte.
238 * It seems that some BIOSes give control to the OS
239 * with CR0.WP already set, making the kernel text
240 * read-only before cpu_startup().
242 old_wp = disable_wp();
243 ctx_switch_xsave[3] |= 0x10;
249 * Calculate the fpu save area size.
257 cpuid_count(0xd, 0x0, cp);
258 cpu_max_ext_state_size = cp[1];
261 * Reload the cpu_feature2, since we enabled OSXSAVE.
264 cpu_feature2 = cp[2];
266 cpu_max_ext_state_size = sizeof(struct savefpu);
270 * Initialize the floating point unit.
283 load_cr4(rcr4() | CR4_XSAVE);
284 load_xcr(XCR0, xsave_mask);
288 * XCR0 shall be set up before CPU can report the save area size.
294 * It is too early for critical_enter() to work on AP.
296 saveintr = intr_disable();
299 control = __INITIAL_FPUCW__;
301 mxcsr = __INITIAL_MXCSR__;
304 intr_restore(saveintr);
308 * On the boot CPU we generate a clean state that is used to
309 * initialize the floating point unit when it is first used by a
313 fpuinitstate(void *arg __unused)
316 int cp[4], i, max_ext_n;
318 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
320 saveintr = intr_disable();
323 fpusave(fpu_initialstate);
324 if (fpu_initialstate->sv_env.en_mxcsr_mask)
325 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
327 cpu_mxcsr_mask = 0xFFBF;
330 * The fninit instruction does not modify XMM registers or x87
331 * registers (MM/ST). The fpusave call dumped the garbage
332 * contained in the registers after reset to the initial state
333 * saved. Clear XMM and x87 registers file image to make the
334 * startup program state and signal handler XMM/x87 register
335 * content predictable.
337 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp));
338 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm));
341 * Create a table describing the layout of the CPU Extended
345 max_ext_n = flsl(xsave_mask);
346 xsave_area_desc = malloc(max_ext_n * sizeof(struct
347 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
349 xsave_area_desc[0].offset = 0;
350 xsave_area_desc[0].size = 160;
352 xsave_area_desc[1].offset = 160;
353 xsave_area_desc[1].size = 288 - 160;
355 for (i = 2; i < max_ext_n; i++) {
356 cpuid_count(0xd, i, cp);
357 xsave_area_desc[i].offset = cp[1];
358 xsave_area_desc[i].size = cp[0];
362 fpu_save_area_zone = uma_zcreate("FPU_save_area",
363 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
364 XSAVE_AREA_ALIGN - 1, 0);
367 intr_restore(saveintr);
369 /* EFIRT needs this to be initialized before we can enter our EFI environment */
370 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL);
373 * Free coprocessor (if we have it).
376 fpuexit(struct thread *td)
380 if (curthread == PCPU_GET(fpcurthread)) {
382 fpusave(curpcb->pcb_save);
384 PCPU_SET(fpcurthread, NULL);
393 return (_MC_FPFMT_XMM);
397 * The following mechanism is used to ensure that the FPE_... value
398 * that is passed as a trapcode to the signal handler of the user
399 * process does not have more than one bit set.
401 * Multiple bits may be set if the user process modifies the control
402 * word while a status word bit is already set. While this is a sign
403 * of bad coding, we have no choise than to narrow them down to one
404 * bit, since we must not send a trapcode that is not exactly one of
407 * The mechanism has a static table with 127 entries. Each combination
408 * of the 7 FPU status word exception bits directly translates to a
409 * position in this table, where a single FPE_... value is stored.
410 * This FPE_... value stored there is considered the "most important"
411 * of the exception bits and will be sent as the signal code. The
412 * precedence of the bits is based upon Intel Document "Numerical
413 * Applications", Chapter "Special Computational Situations".
415 * The macro to choose one of these values does these steps: 1) Throw
416 * away status word bits that cannot be masked. 2) Throw away the bits
417 * currently masked in the control word, assuming the user isn't
418 * interested in them anymore. 3) Reinsert status word bit 7 (stack
419 * fault) if it is set, which cannot be masked but must be presered.
420 * 4) Use the remaining bits to point into the trapcode table.
422 * The 6 maskable bits in order of their preference, as stated in the
423 * above referenced Intel manual:
424 * 1 Invalid operation (FP_X_INV)
427 * 1c Operand of unsupported format
429 * 2 QNaN operand (not an exception, irrelavant here)
430 * 3 Any other invalid-operation not mentioned above or zero divide
431 * (FP_X_INV, FP_X_DZ)
432 * 4 Denormal operand (FP_X_DNML)
433 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
434 * 6 Inexact result (FP_X_IMP)
436 static char fpetable[128] = {
438 FPE_FLTINV, /* 1 - INV */
439 FPE_FLTUND, /* 2 - DNML */
440 FPE_FLTINV, /* 3 - INV | DNML */
441 FPE_FLTDIV, /* 4 - DZ */
442 FPE_FLTINV, /* 5 - INV | DZ */
443 FPE_FLTDIV, /* 6 - DNML | DZ */
444 FPE_FLTINV, /* 7 - INV | DNML | DZ */
445 FPE_FLTOVF, /* 8 - OFL */
446 FPE_FLTINV, /* 9 - INV | OFL */
447 FPE_FLTUND, /* A - DNML | OFL */
448 FPE_FLTINV, /* B - INV | DNML | OFL */
449 FPE_FLTDIV, /* C - DZ | OFL */
450 FPE_FLTINV, /* D - INV | DZ | OFL */
451 FPE_FLTDIV, /* E - DNML | DZ | OFL */
452 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
453 FPE_FLTUND, /* 10 - UFL */
454 FPE_FLTINV, /* 11 - INV | UFL */
455 FPE_FLTUND, /* 12 - DNML | UFL */
456 FPE_FLTINV, /* 13 - INV | DNML | UFL */
457 FPE_FLTDIV, /* 14 - DZ | UFL */
458 FPE_FLTINV, /* 15 - INV | DZ | UFL */
459 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
460 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
461 FPE_FLTOVF, /* 18 - OFL | UFL */
462 FPE_FLTINV, /* 19 - INV | OFL | UFL */
463 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
464 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
465 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
466 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
467 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
468 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
469 FPE_FLTRES, /* 20 - IMP */
470 FPE_FLTINV, /* 21 - INV | IMP */
471 FPE_FLTUND, /* 22 - DNML | IMP */
472 FPE_FLTINV, /* 23 - INV | DNML | IMP */
473 FPE_FLTDIV, /* 24 - DZ | IMP */
474 FPE_FLTINV, /* 25 - INV | DZ | IMP */
475 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
476 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
477 FPE_FLTOVF, /* 28 - OFL | IMP */
478 FPE_FLTINV, /* 29 - INV | OFL | IMP */
479 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
480 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
481 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
482 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
483 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
484 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
485 FPE_FLTUND, /* 30 - UFL | IMP */
486 FPE_FLTINV, /* 31 - INV | UFL | IMP */
487 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
488 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
489 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
490 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
491 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
492 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
493 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
494 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
495 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
496 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
497 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
498 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
499 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
500 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
501 FPE_FLTSUB, /* 40 - STK */
502 FPE_FLTSUB, /* 41 - INV | STK */
503 FPE_FLTUND, /* 42 - DNML | STK */
504 FPE_FLTSUB, /* 43 - INV | DNML | STK */
505 FPE_FLTDIV, /* 44 - DZ | STK */
506 FPE_FLTSUB, /* 45 - INV | DZ | STK */
507 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
508 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
509 FPE_FLTOVF, /* 48 - OFL | STK */
510 FPE_FLTSUB, /* 49 - INV | OFL | STK */
511 FPE_FLTUND, /* 4A - DNML | OFL | STK */
512 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
513 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
514 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
515 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
516 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
517 FPE_FLTUND, /* 50 - UFL | STK */
518 FPE_FLTSUB, /* 51 - INV | UFL | STK */
519 FPE_FLTUND, /* 52 - DNML | UFL | STK */
520 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
521 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
522 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
523 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
524 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
525 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
526 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
527 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
528 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
529 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
530 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
531 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
532 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
533 FPE_FLTRES, /* 60 - IMP | STK */
534 FPE_FLTSUB, /* 61 - INV | IMP | STK */
535 FPE_FLTUND, /* 62 - DNML | IMP | STK */
536 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
537 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
538 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
539 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
540 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
541 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
542 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
543 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
544 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
545 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
546 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
547 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
548 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
549 FPE_FLTUND, /* 70 - UFL | IMP | STK */
550 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
551 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
552 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
553 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
554 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
555 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
556 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
557 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
558 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
559 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
560 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
561 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
562 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
563 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
564 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
568 * Read the FP status and control words, then generate si_code value
569 * for SIGFPE. The error code chosen will be one of the
570 * FPE_... macros. It will be sent as the second argument to old
571 * BSD-style signal handlers and as "siginfo_t->si_code" (second
572 * argument) to SA_SIGINFO signal handlers.
574 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
575 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
576 * usermode code which understands the FPU hardware enough to enable
577 * the exceptions, can also handle clearing the exception state in the
578 * handler. The only consequence of not clearing the exception is the
579 * rethrow of the SIGFPE on return from the signal handler and
580 * reexecution of the corresponding instruction.
582 * For XMM traps, the exceptions were never cleared.
587 struct savefpu *pcb_save;
588 u_short control, status;
593 * Interrupt handling (for another interrupt) may have pushed the
594 * state to memory. Fetch the relevant parts of the state from
597 if (PCPU_GET(fpcurthread) != curthread) {
598 pcb_save = curpcb->pcb_save;
599 control = pcb_save->sv_env.en_cw;
600 status = pcb_save->sv_env.en_sw;
607 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
616 if (PCPU_GET(fpcurthread) != curthread)
617 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
621 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
625 * Device Not Available (DNA, #NM) exception handler.
627 * It would be better to switch FP context here (if curthread !=
628 * fpcurthread) and not necessarily for every context switch, but it
629 * is too hard to access foreign pcb's.
636 * This handler is entered with interrupts enabled, so context
637 * switches may occur before critical_enter() is executed. If
638 * a context switch occurs, then when we regain control, our
639 * state will have been completely restored. The CPU may
640 * change underneath us, but the only part of our context that
641 * lives in the CPU is CR0.TS and that will be "restored" by
642 * setting it on the new CPU.
646 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0,
647 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)"));
648 if (PCPU_GET(fpcurthread) == curthread) {
649 printf("fpudna: fpcurthread == curthread\n");
654 if (PCPU_GET(fpcurthread) != NULL) {
655 panic("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
656 PCPU_GET(fpcurthread), PCPU_GET(fpcurthread)->td_tid,
657 curthread, curthread->td_tid);
661 * Record new context early in case frstor causes a trap.
663 PCPU_SET(fpcurthread, curthread);
667 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) {
669 * This is the first time this thread has used the FPU or
670 * the PCB doesn't contain a clean FPU state. Explicitly
671 * load an initial state.
673 * We prefer to restore the state from the actual save
674 * area in PCB instead of directly loading from
675 * fpu_initialstate, to ignite the XSAVEOPT
678 bcopy(fpu_initialstate, curpcb->pcb_save,
679 cpu_max_ext_state_size);
680 fpurestore(curpcb->pcb_save);
681 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
682 fldcw(curpcb->pcb_initial_fpucw);
683 if (PCB_USER_FPU(curpcb))
684 set_pcb_flags(curpcb,
685 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
687 set_pcb_flags(curpcb, PCB_FPUINITDONE);
689 fpurestore(curpcb->pcb_save);
698 td = PCPU_GET(fpcurthread);
699 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
701 PCPU_SET(fpcurthread, NULL);
702 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
707 * Get the user state of the FPU into pcb->pcb_user_save without
708 * dropping ownership (if possible). It returns the FPU ownership
712 fpugetregs(struct thread *td)
715 uint64_t *xstate_bv, bit;
717 int max_ext_n, i, owned;
720 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
721 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
722 cpu_max_ext_state_size);
723 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
724 pcb->pcb_initial_fpucw;
726 return (_MC_FPOWNED_PCB);
729 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
730 fpusave(get_pcb_user_save_pcb(pcb));
731 owned = _MC_FPOWNED_FPU;
733 owned = _MC_FPOWNED_PCB;
738 * Handle partially saved state.
740 sa = (char *)get_pcb_user_save_pcb(pcb);
741 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
742 offsetof(struct xstate_hdr, xstate_bv));
743 max_ext_n = flsl(xsave_mask);
744 for (i = 0; i < max_ext_n; i++) {
746 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
748 bcopy((char *)fpu_initialstate +
749 xsave_area_desc[i].offset,
750 sa + xsave_area_desc[i].offset,
751 xsave_area_desc[i].size);
759 fpuuserinited(struct thread *td)
764 if (PCB_USER_FPU(pcb))
766 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
768 set_pcb_flags(pcb, PCB_FPUINITDONE);
772 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
774 struct xstate_hdr *hdr, *ehdr;
778 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
779 if (xfpustate == NULL)
784 len = xfpustate_size;
785 if (len < sizeof(struct xstate_hdr))
787 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
791 ehdr = (struct xstate_hdr *)xfpustate;
792 bv = ehdr->xstate_bv;
797 if (bv & ~xsave_mask)
800 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
803 bcopy(xfpustate + sizeof(struct xstate_hdr),
804 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
810 * Set the state of the FPU.
813 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
814 size_t xfpustate_size)
819 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask;
822 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
823 error = fpusetxstate(td, xfpustate, xfpustate_size);
828 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
829 fpurestore(get_pcb_user_save_td(td));
831 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE);
834 error = fpusetxstate(td, xfpustate, xfpustate_size);
837 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
844 * On AuthenticAMD processors, the fxrstor instruction does not restore
845 * the x87's stored last instruction pointer, last data pointer, and last
846 * opcode values, except in the rare case in which the exception summary
847 * (ES) bit in the x87 status word is set to 1.
849 * In order to avoid leaking this information across processes, we clean
850 * these values by performing a dummy load before executing fxrstor().
853 fpu_clean_state(void)
855 static float dummy_variable = 0.0;
859 * Clear the ES bit in the x87 status word if it is currently
860 * set, in order to avoid causing a fault in the upcoming load.
867 * Load the dummy variable into the x87 stack. This mangles
868 * the x87 stack, but we don't care since we're about to call
871 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
875 * This really sucks. We want the acpi version only, but it requires
876 * the isa_if.h file in order to get the definitions.
880 #include <isa/isavar.h>
882 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
884 static struct isa_pnp_id fpupnp_ids[] = {
885 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
890 fpupnp_probe(device_t dev)
894 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
901 fpupnp_attach(device_t dev)
907 static device_method_t fpupnp_methods[] = {
908 /* Device interface */
909 DEVMETHOD(device_probe, fpupnp_probe),
910 DEVMETHOD(device_attach, fpupnp_attach),
911 DEVMETHOD(device_detach, bus_generic_detach),
912 DEVMETHOD(device_shutdown, bus_generic_shutdown),
913 DEVMETHOD(device_suspend, bus_generic_suspend),
914 DEVMETHOD(device_resume, bus_generic_resume),
919 static driver_t fpupnp_driver = {
925 static devclass_t fpupnp_devclass;
927 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
928 ISA_PNP_INFO(fpupnp_ids);
931 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
932 "Kernel contexts for FPU state");
934 #define FPU_KERN_CTX_FPUINITDONE 0x01
935 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */
936 #define FPU_KERN_CTX_INUSE 0x04
938 struct fpu_kern_ctx {
939 struct savefpu *prev;
944 struct fpu_kern_ctx *
945 fpu_kern_alloc_ctx(u_int flags)
947 struct fpu_kern_ctx *res;
950 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
951 cpu_max_ext_state_size;
952 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
953 M_NOWAIT : M_WAITOK) | M_ZERO);
958 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
961 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
962 /* XXXKIB clear the memory ? */
963 free(ctx, M_FPUKERN_CTX);
966 static struct savefpu *
967 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
971 p = (vm_offset_t)&ctx->hwstate1;
972 p = roundup2(p, XSAVE_AREA_ALIGN);
973 return ((struct savefpu *)p);
977 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
982 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL,
983 ("ctx is required when !FPU_KERN_NOCTX"));
984 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0,
985 ("using inuse ctx"));
986 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0,
987 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state"));
989 if ((flags & FPU_KERN_NOCTX) != 0) {
992 if (curthread == PCPU_GET(fpcurthread)) {
993 fpusave(curpcb->pcb_save);
994 PCPU_SET(fpcurthread, NULL);
996 KASSERT(PCPU_GET(fpcurthread) == NULL,
997 ("invalid fpcurthread"));
1001 * This breaks XSAVEOPT tracker, but
1002 * PCB_FPUNOSAVE state is supposed to never need to
1003 * save FPU context at all.
1005 fpurestore(fpu_initialstate);
1006 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE |
1010 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1011 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
1014 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1015 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1016 ctx->flags = FPU_KERN_CTX_INUSE;
1017 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
1018 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
1020 ctx->prev = pcb->pcb_save;
1021 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1022 set_pcb_flags(pcb, PCB_KERNFPU);
1023 clear_pcb_flags(pcb, PCB_FPUINITDONE);
1028 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1034 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) {
1035 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX"));
1036 KASSERT(PCPU_GET(fpcurthread) == NULL,
1037 ("non-NULL fpcurthread for PCB_FPUNOSAVE"));
1038 CRITICAL_ASSERT(td);
1040 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE);
1044 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
1045 ("leaving not inuse ctx"));
1046 ctx->flags &= ~FPU_KERN_CTX_INUSE;
1048 if (is_fpu_kern_thread(0) &&
1049 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1051 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0,
1054 if (curthread == PCPU_GET(fpcurthread))
1057 pcb->pcb_save = ctx->prev;
1060 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1061 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
1062 set_pcb_flags(pcb, PCB_FPUINITDONE);
1063 clear_pcb_flags(pcb, PCB_KERNFPU);
1065 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
1067 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
1068 set_pcb_flags(pcb, PCB_FPUINITDONE);
1070 clear_pcb_flags(pcb, PCB_FPUINITDONE);
1071 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1077 fpu_kern_thread(u_int flags)
1080 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1081 ("Only kthread may use fpu_kern_thread"));
1082 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1083 ("mangled pcb_save"));
1084 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1086 set_pcb_flags(curpcb, PCB_KERNFPU);
1091 is_fpu_kern_thread(u_int flags)
1094 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1096 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0);
1100 * FPU save area alloc/free/init utility routines
1103 fpu_save_area_alloc(void)
1106 return (uma_zalloc(fpu_save_area_zone, 0));
1110 fpu_save_area_free(struct savefpu *fsa)
1113 uma_zfree(fpu_save_area_zone, fsa);
1117 fpu_save_area_reset(struct savefpu *fsa)
1120 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);