2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
49 #include <sys/signalvar.h>
52 #include <machine/cputypes.h>
53 #include <machine/frame.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/md_var.h>
56 #include <machine/pcb.h>
57 #include <machine/psl.h>
58 #include <machine/resource.h>
59 #include <machine/specialreg.h>
60 #include <machine/segments.h>
61 #include <machine/ucontext.h>
64 * Floating point support.
67 #if defined(__GNUCLIKE_ASM) && !defined(lint)
69 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
70 #define fnclex() __asm __volatile("fnclex")
71 #define fninit() __asm __volatile("fninit")
72 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
73 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
74 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
75 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
76 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
77 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
80 xrstor(char *addr, uint64_t mask)
86 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
90 xsave(char *addr, uint64_t mask)
96 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
100 #else /* !(__GNUCLIKE_ASM && !lint) */
102 void fldcw(u_short cw);
105 void fnstcw(caddr_t addr);
106 void fnstsw(caddr_t addr);
107 void fxsave(caddr_t addr);
108 void fxrstor(caddr_t addr);
109 void ldmxcsr(u_int csr);
110 void stmxcsr(u_int *csr);
111 void xrstor(char *addr, uint64_t mask);
112 void xsave(char *addr, uint64_t mask);
114 #endif /* __GNUCLIKE_ASM && !lint */
116 #define start_emulating() load_cr0(rcr0() | CR0_TS)
117 #define stop_emulating() clts()
119 CTASSERT(sizeof(struct savefpu) == 512);
120 CTASSERT(sizeof(struct xstate_hdr) == 64);
121 CTASSERT(sizeof(struct savefpu_ymm) == 832);
124 * This requirement is to make it easier for asm code to calculate
125 * offset of the fpu save area from the pcb address. FPU save area
126 * must be 64-byte aligned.
128 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
130 static void fpu_clean_state(void);
132 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
133 NULL, 1, "Floating point instructions executed in hardware");
135 int use_xsave; /* non-static for cpu_switch.S */
136 uint64_t xsave_mask; /* the same */
137 static uma_zone_t fpu_save_area_zone;
138 static struct savefpu *fpu_initialstate;
140 struct xsave_area_elm_descr {
150 xsave((char *)addr, xsave_mask);
152 fxsave((char *)addr);
156 fpurestore(void *addr)
160 xrstor((char *)addr, xsave_mask);
162 fxrstor((char *)addr);
166 fpususpend(void *addr)
177 * Enable XSAVE if supported and allowed by user.
178 * Calculate the xsave_mask.
184 uint64_t xsave_mask_user;
186 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
188 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
193 cpuid_count(0xd, 0x0, cp);
194 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
195 if ((cp[0] & xsave_mask) != xsave_mask)
196 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
197 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
198 xsave_mask_user = xsave_mask;
199 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
200 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
201 xsave_mask &= xsave_mask_user;
202 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
203 xsave_mask &= ~XFEATURE_AVX512;
204 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
205 xsave_mask &= ~XFEATURE_MPX;
207 cpuid_count(0xd, 0x1, cp);
208 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
210 * Patch the XSAVE instruction in the cpu_switch code
211 * to XSAVEOPT. We assume that XSAVE encoding used
212 * REX byte, and set the bit 4 of the r/m byte.
214 ctx_switch_xsave[3] |= 0x10;
219 * Calculate the fpu save area size.
227 cpuid_count(0xd, 0x0, cp);
228 cpu_max_ext_state_size = cp[1];
231 * Reload the cpu_feature2, since we enabled OSXSAVE.
234 cpu_feature2 = cp[2];
236 cpu_max_ext_state_size = sizeof(struct savefpu);
240 * Initialize the floating point unit.
253 load_cr4(rcr4() | CR4_XSAVE);
254 load_xcr(XCR0, xsave_mask);
258 * XCR0 shall be set up before CPU can report the save area size.
264 * It is too early for critical_enter() to work on AP.
266 saveintr = intr_disable();
269 control = __INITIAL_FPUCW__;
271 mxcsr = __INITIAL_MXCSR__;
274 intr_restore(saveintr);
278 * On the boot CPU we generate a clean state that is used to
279 * initialize the floating point unit when it is first used by a
283 fpuinitstate(void *arg __unused)
286 int cp[4], i, max_ext_n;
288 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
290 saveintr = intr_disable();
293 fpusave(fpu_initialstate);
294 if (fpu_initialstate->sv_env.en_mxcsr_mask)
295 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
297 cpu_mxcsr_mask = 0xFFBF;
300 * The fninit instruction does not modify XMM registers. The
301 * fpusave call dumped the garbage contained in the registers
302 * after reset to the initial state saved. Clear XMM
303 * registers file image to make the startup program state and
304 * signal handler XMM register content predictable.
306 bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc));
309 * Create a table describing the layout of the CPU Extended
313 max_ext_n = flsl(xsave_mask);
314 xsave_area_desc = malloc(max_ext_n * sizeof(struct
315 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
317 xsave_area_desc[0].offset = 0;
318 xsave_area_desc[0].size = 160;
320 xsave_area_desc[1].offset = 160;
321 xsave_area_desc[1].size = 288 - 160;
323 for (i = 2; i < max_ext_n; i++) {
324 cpuid_count(0xd, i, cp);
325 xsave_area_desc[i].offset = cp[1];
326 xsave_area_desc[i].size = cp[0];
330 fpu_save_area_zone = uma_zcreate("FPU_save_area",
331 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
332 XSAVE_AREA_ALIGN - 1, 0);
335 intr_restore(saveintr);
337 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL);
340 * Free coprocessor (if we have it).
343 fpuexit(struct thread *td)
347 if (curthread == PCPU_GET(fpcurthread)) {
349 fpusave(curpcb->pcb_save);
351 PCPU_SET(fpcurthread, 0);
360 return (_MC_FPFMT_XMM);
364 * The following mechanism is used to ensure that the FPE_... value
365 * that is passed as a trapcode to the signal handler of the user
366 * process does not have more than one bit set.
368 * Multiple bits may be set if the user process modifies the control
369 * word while a status word bit is already set. While this is a sign
370 * of bad coding, we have no choise than to narrow them down to one
371 * bit, since we must not send a trapcode that is not exactly one of
374 * The mechanism has a static table with 127 entries. Each combination
375 * of the 7 FPU status word exception bits directly translates to a
376 * position in this table, where a single FPE_... value is stored.
377 * This FPE_... value stored there is considered the "most important"
378 * of the exception bits and will be sent as the signal code. The
379 * precedence of the bits is based upon Intel Document "Numerical
380 * Applications", Chapter "Special Computational Situations".
382 * The macro to choose one of these values does these steps: 1) Throw
383 * away status word bits that cannot be masked. 2) Throw away the bits
384 * currently masked in the control word, assuming the user isn't
385 * interested in them anymore. 3) Reinsert status word bit 7 (stack
386 * fault) if it is set, which cannot be masked but must be presered.
387 * 4) Use the remaining bits to point into the trapcode table.
389 * The 6 maskable bits in order of their preference, as stated in the
390 * above referenced Intel manual:
391 * 1 Invalid operation (FP_X_INV)
394 * 1c Operand of unsupported format
396 * 2 QNaN operand (not an exception, irrelavant here)
397 * 3 Any other invalid-operation not mentioned above or zero divide
398 * (FP_X_INV, FP_X_DZ)
399 * 4 Denormal operand (FP_X_DNML)
400 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
401 * 6 Inexact result (FP_X_IMP)
403 static char fpetable[128] = {
405 FPE_FLTINV, /* 1 - INV */
406 FPE_FLTUND, /* 2 - DNML */
407 FPE_FLTINV, /* 3 - INV | DNML */
408 FPE_FLTDIV, /* 4 - DZ */
409 FPE_FLTINV, /* 5 - INV | DZ */
410 FPE_FLTDIV, /* 6 - DNML | DZ */
411 FPE_FLTINV, /* 7 - INV | DNML | DZ */
412 FPE_FLTOVF, /* 8 - OFL */
413 FPE_FLTINV, /* 9 - INV | OFL */
414 FPE_FLTUND, /* A - DNML | OFL */
415 FPE_FLTINV, /* B - INV | DNML | OFL */
416 FPE_FLTDIV, /* C - DZ | OFL */
417 FPE_FLTINV, /* D - INV | DZ | OFL */
418 FPE_FLTDIV, /* E - DNML | DZ | OFL */
419 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
420 FPE_FLTUND, /* 10 - UFL */
421 FPE_FLTINV, /* 11 - INV | UFL */
422 FPE_FLTUND, /* 12 - DNML | UFL */
423 FPE_FLTINV, /* 13 - INV | DNML | UFL */
424 FPE_FLTDIV, /* 14 - DZ | UFL */
425 FPE_FLTINV, /* 15 - INV | DZ | UFL */
426 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
427 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
428 FPE_FLTOVF, /* 18 - OFL | UFL */
429 FPE_FLTINV, /* 19 - INV | OFL | UFL */
430 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
431 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
432 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
433 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
434 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
435 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
436 FPE_FLTRES, /* 20 - IMP */
437 FPE_FLTINV, /* 21 - INV | IMP */
438 FPE_FLTUND, /* 22 - DNML | IMP */
439 FPE_FLTINV, /* 23 - INV | DNML | IMP */
440 FPE_FLTDIV, /* 24 - DZ | IMP */
441 FPE_FLTINV, /* 25 - INV | DZ | IMP */
442 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
443 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
444 FPE_FLTOVF, /* 28 - OFL | IMP */
445 FPE_FLTINV, /* 29 - INV | OFL | IMP */
446 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
447 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
448 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
449 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
450 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
451 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
452 FPE_FLTUND, /* 30 - UFL | IMP */
453 FPE_FLTINV, /* 31 - INV | UFL | IMP */
454 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
455 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
456 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
457 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
458 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
459 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
460 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
461 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
462 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
463 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
464 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
465 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
466 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
467 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
468 FPE_FLTSUB, /* 40 - STK */
469 FPE_FLTSUB, /* 41 - INV | STK */
470 FPE_FLTUND, /* 42 - DNML | STK */
471 FPE_FLTSUB, /* 43 - INV | DNML | STK */
472 FPE_FLTDIV, /* 44 - DZ | STK */
473 FPE_FLTSUB, /* 45 - INV | DZ | STK */
474 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
475 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
476 FPE_FLTOVF, /* 48 - OFL | STK */
477 FPE_FLTSUB, /* 49 - INV | OFL | STK */
478 FPE_FLTUND, /* 4A - DNML | OFL | STK */
479 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
480 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
481 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
482 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
483 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
484 FPE_FLTUND, /* 50 - UFL | STK */
485 FPE_FLTSUB, /* 51 - INV | UFL | STK */
486 FPE_FLTUND, /* 52 - DNML | UFL | STK */
487 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
488 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
489 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
490 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
491 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
492 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
493 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
494 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
495 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
496 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
497 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
498 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
499 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
500 FPE_FLTRES, /* 60 - IMP | STK */
501 FPE_FLTSUB, /* 61 - INV | IMP | STK */
502 FPE_FLTUND, /* 62 - DNML | IMP | STK */
503 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
504 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
505 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
506 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
507 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
508 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
509 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
510 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
511 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
512 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
513 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
514 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
515 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
516 FPE_FLTUND, /* 70 - UFL | IMP | STK */
517 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
518 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
519 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
520 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
521 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
522 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
523 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
524 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
525 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
526 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
527 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
528 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
529 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
530 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
531 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
535 * Read the FP status and control words, then generate si_code value
536 * for SIGFPE. The error code chosen will be one of the
537 * FPE_... macros. It will be sent as the second argument to old
538 * BSD-style signal handlers and as "siginfo_t->si_code" (second
539 * argument) to SA_SIGINFO signal handlers.
541 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
542 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
543 * usermode code which understands the FPU hardware enough to enable
544 * the exceptions, can also handle clearing the exception state in the
545 * handler. The only consequence of not clearing the exception is the
546 * rethrow of the SIGFPE on return from the signal handler and
547 * reexecution of the corresponding instruction.
549 * For XMM traps, the exceptions were never cleared.
554 struct savefpu *pcb_save;
555 u_short control, status;
560 * Interrupt handling (for another interrupt) may have pushed the
561 * state to memory. Fetch the relevant parts of the state from
564 if (PCPU_GET(fpcurthread) != curthread) {
565 pcb_save = curpcb->pcb_save;
566 control = pcb_save->sv_env.en_cw;
567 status = pcb_save->sv_env.en_sw;
574 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
583 if (PCPU_GET(fpcurthread) != curthread)
584 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
588 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
592 * Implement device not available (DNA) exception
594 * It would be better to switch FP context here (if curthread != fpcurthread)
595 * and not necessarily for every context switch, but it is too hard to
596 * access foreign pcb's.
599 static int err_count = 0;
606 if (PCPU_GET(fpcurthread) == curthread) {
607 printf("fpudna: fpcurthread == curthread %d times\n",
613 if (PCPU_GET(fpcurthread) != NULL) {
614 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
615 PCPU_GET(fpcurthread),
616 PCPU_GET(fpcurthread)->td_proc->p_pid,
617 curthread, curthread->td_proc->p_pid);
622 * Record new context early in case frstor causes a trap.
624 PCPU_SET(fpcurthread, curthread);
628 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) {
630 * This is the first time this thread has used the FPU or
631 * the PCB doesn't contain a clean FPU state. Explicitly
632 * load an initial state.
634 * We prefer to restore the state from the actual save
635 * area in PCB instead of directly loading from
636 * fpu_initialstate, to ignite the XSAVEOPT
639 bcopy(fpu_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
640 fpurestore(curpcb->pcb_save);
641 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
642 fldcw(curpcb->pcb_initial_fpucw);
643 if (PCB_USER_FPU(curpcb))
644 set_pcb_flags(curpcb,
645 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
647 set_pcb_flags(curpcb, PCB_FPUINITDONE);
649 fpurestore(curpcb->pcb_save);
658 td = PCPU_GET(fpcurthread);
659 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
661 PCPU_SET(fpcurthread, NULL);
662 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
667 * Get the user state of the FPU into pcb->pcb_user_save without
668 * dropping ownership (if possible). It returns the FPU ownership
672 fpugetregs(struct thread *td)
675 uint64_t *xstate_bv, bit;
677 int max_ext_n, i, owned;
680 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
681 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
682 cpu_max_ext_state_size);
683 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
684 pcb->pcb_initial_fpucw;
686 return (_MC_FPOWNED_PCB);
689 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
690 fpusave(get_pcb_user_save_pcb(pcb));
691 owned = _MC_FPOWNED_FPU;
693 owned = _MC_FPOWNED_PCB;
698 * Handle partially saved state.
700 sa = (char *)get_pcb_user_save_pcb(pcb);
701 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
702 offsetof(struct xstate_hdr, xstate_bv));
703 max_ext_n = flsl(xsave_mask);
704 for (i = 0; i < max_ext_n; i++) {
706 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
708 bcopy((char *)fpu_initialstate +
709 xsave_area_desc[i].offset,
710 sa + xsave_area_desc[i].offset,
711 xsave_area_desc[i].size);
719 fpuuserinited(struct thread *td)
724 if (PCB_USER_FPU(pcb))
726 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
728 set_pcb_flags(pcb, PCB_FPUINITDONE);
732 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
734 struct xstate_hdr *hdr, *ehdr;
738 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
739 if (xfpustate == NULL)
744 len = xfpustate_size;
745 if (len < sizeof(struct xstate_hdr))
747 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
751 ehdr = (struct xstate_hdr *)xfpustate;
752 bv = ehdr->xstate_bv;
757 if (bv & ~xsave_mask)
760 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
763 bcopy(xfpustate + sizeof(struct xstate_hdr),
764 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
770 * Set the state of the FPU.
773 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
774 size_t xfpustate_size)
781 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
782 error = fpusetxstate(td, xfpustate, xfpustate_size);
787 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
788 fpurestore(get_pcb_user_save_td(td));
790 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE);
793 error = fpusetxstate(td, xfpustate, xfpustate_size);
796 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
803 * On AuthenticAMD processors, the fxrstor instruction does not restore
804 * the x87's stored last instruction pointer, last data pointer, and last
805 * opcode values, except in the rare case in which the exception summary
806 * (ES) bit in the x87 status word is set to 1.
808 * In order to avoid leaking this information across processes, we clean
809 * these values by performing a dummy load before executing fxrstor().
812 fpu_clean_state(void)
814 static float dummy_variable = 0.0;
818 * Clear the ES bit in the x87 status word if it is currently
819 * set, in order to avoid causing a fault in the upcoming load.
826 * Load the dummy variable into the x87 stack. This mangles
827 * the x87 stack, but we don't care since we're about to call
830 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
834 * This really sucks. We want the acpi version only, but it requires
835 * the isa_if.h file in order to get the definitions.
839 #include <isa/isavar.h>
841 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
843 static struct isa_pnp_id fpupnp_ids[] = {
844 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
849 fpupnp_probe(device_t dev)
853 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
860 fpupnp_attach(device_t dev)
866 static device_method_t fpupnp_methods[] = {
867 /* Device interface */
868 DEVMETHOD(device_probe, fpupnp_probe),
869 DEVMETHOD(device_attach, fpupnp_attach),
870 DEVMETHOD(device_detach, bus_generic_detach),
871 DEVMETHOD(device_shutdown, bus_generic_shutdown),
872 DEVMETHOD(device_suspend, bus_generic_suspend),
873 DEVMETHOD(device_resume, bus_generic_resume),
878 static driver_t fpupnp_driver = {
884 static devclass_t fpupnp_devclass;
886 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
889 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
890 "Kernel contexts for FPU state");
892 #define FPU_KERN_CTX_FPUINITDONE 0x01
893 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */
895 struct fpu_kern_ctx {
896 struct savefpu *prev;
901 struct fpu_kern_ctx *
902 fpu_kern_alloc_ctx(u_int flags)
904 struct fpu_kern_ctx *res;
907 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
908 cpu_max_ext_state_size;
909 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
910 M_NOWAIT : M_WAITOK) | M_ZERO);
915 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
918 /* XXXKIB clear the memory ? */
919 free(ctx, M_FPUKERN_CTX);
922 static struct savefpu *
923 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
927 p = (vm_offset_t)&ctx->hwstate1;
928 p = roundup2(p, XSAVE_AREA_ALIGN);
929 return ((struct savefpu *)p);
933 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
937 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
938 ctx->flags = FPU_KERN_CTX_DUMMY;
942 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
943 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
945 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
946 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
948 ctx->prev = pcb->pcb_save;
949 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
950 set_pcb_flags(pcb, PCB_KERNFPU);
951 clear_pcb_flags(pcb, PCB_FPUINITDONE);
956 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
960 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
962 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, ("dummy ctx"));
965 if (curthread == PCPU_GET(fpcurthread))
968 pcb->pcb_save = ctx->prev;
969 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
970 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
971 set_pcb_flags(pcb, PCB_FPUINITDONE);
972 clear_pcb_flags(pcb, PCB_KERNFPU);
974 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
976 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
977 set_pcb_flags(pcb, PCB_FPUINITDONE);
979 clear_pcb_flags(pcb, PCB_FPUINITDONE);
980 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
986 fpu_kern_thread(u_int flags)
989 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
990 ("Only kthread may use fpu_kern_thread"));
991 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
992 ("mangled pcb_save"));
993 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
995 set_pcb_flags(curpcb, PCB_KERNFPU);
1000 is_fpu_kern_thread(u_int flags)
1003 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1005 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0);
1009 * FPU save area alloc/free/init utility routines
1012 fpu_save_area_alloc(void)
1015 return (uma_zalloc(fpu_save_area_zone, 0));
1019 fpu_save_area_free(struct savefpu *fsa)
1022 uma_zfree(fpu_save_area_zone, fsa);
1026 fpu_save_area_reset(struct savefpu *fsa)
1029 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);