2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51 #include <sys/power.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/frame.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/segments.h>
59 #include <machine/specialreg.h>
60 #include <machine/md_var.h>
62 #include <amd64/isa/icu.h>
64 /* XXX - should be in header file: */
65 void printcpuinfo(void);
66 void identify_cpu(void);
67 void earlysetcpuclass(void);
68 void panicifcpuunsupported(void);
70 static void print_AMD_info(void);
71 static void print_AMD_assoc(int i);
72 void setPQL2(int *const size, int *const ways);
73 static void setPQL2_AMD(int *const size, int *const ways);
76 char machine[] = "amd64";
77 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
78 machine, 0, "Machine class");
80 static char cpu_model[128];
81 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
82 cpu_model, 0, "Machine model");
84 static int hw_clockrate;
85 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
86 &hw_clockrate, 0, "CPU instruction clock rate");
88 static char cpu_brand[48];
94 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
95 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
99 extern int pq_l2nways;
107 cpu_class = amd64_cpus[cpu].cpu_class;
109 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
111 /* Check for extended CPUID information and a processor name. */
112 if (cpu_exthigh >= 0x80000004) {
114 for (i = 0x80000002; i < 0x80000005; i++) {
116 memcpy(brand, regs, sizeof(regs));
117 brand += sizeof(regs);
121 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
122 /* Please make up your mind folks! */
123 strcat(cpu_model, "EM64T");
124 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
126 * Values taken from AMD Processor Recognition
127 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
128 * (also describes ``Features'' encodings.
130 strcpy(cpu_model, "AMD ");
131 switch (cpu_id & 0xF00) {
133 strcat(cpu_model, "AMD64 Processor");
136 strcat(cpu_model, "Unknown");
142 * Replace cpu_model with cpu_brand minus leading spaces if
146 while (*brand == ' ')
149 strcpy(cpu_model, brand);
151 printf("%s (", cpu_model);
154 hw_clockrate = (tsc_freq + 5000) / 1000000;
155 printf("%jd.%02d-MHz ",
156 (intmax_t)(tsc_freq + 4999) / 1000000,
157 (u_int)((tsc_freq + 4999) / 10000) % 100);
161 printf("Unknown"); /* will panic below... */
163 printf("-class CPU)\n");
165 printf(" Origin = \"%s\"",cpu_vendor);
167 printf(" Id = 0x%x", cpu_id);
169 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
170 strcmp(cpu_vendor, "AuthenticAMD") == 0) {
171 printf(" Stepping = %u", cpu_id & 0xf);
173 u_int cmp = 1, htt = 1;
176 * Here we should probably set up flags indicating
177 * whether or not various features are available.
178 * The interesting ones are probably VME, PSE, PAE,
179 * and PGE. The code already assumes without bothering
180 * to check that all CPUs >= Pentium have a TSC and
183 printf("\n Features=0x%b", cpu_feature,
185 "\001FPU" /* Integral FPU */
186 "\002VME" /* Extended VM86 mode support */
187 "\003DE" /* Debugging Extensions (CR4.DE) */
188 "\004PSE" /* 4MByte page tables */
189 "\005TSC" /* Timestamp counter */
190 "\006MSR" /* Machine specific registers */
191 "\007PAE" /* Physical address extension */
192 "\010MCE" /* Machine Check support */
193 "\011CX8" /* CMPEXCH8 instruction */
194 "\012APIC" /* SMP local APIC */
195 "\013oldMTRR" /* Previous implementation of MTRR */
196 "\014SEP" /* Fast System Call */
197 "\015MTRR" /* Memory Type Range Registers */
198 "\016PGE" /* PG_G (global bit) support */
199 "\017MCA" /* Machine Check Architecture */
200 "\020CMOV" /* CMOV instruction */
201 "\021PAT" /* Page attributes table */
202 "\022PSE36" /* 36 bit address space support */
203 "\023PN" /* Processor Serial number */
204 "\024CLFLUSH" /* Has the CLFLUSH instruction */
206 "\026DTS" /* Debug Trace Store */
207 "\027ACPI" /* ACPI support */
208 "\030MMX" /* MMX instructions */
209 "\031FXSR" /* FXSAVE/FXRSTOR */
210 "\032SSE" /* Streaming SIMD Extensions */
211 "\033SSE2" /* Streaming SIMD Extensions #2 */
212 "\034SS" /* Self snoop */
213 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
214 "\036TM" /* Thermal Monitor clock slowdown */
215 "\037IA64" /* CPU can execute IA64 instructions */
216 "\040PBE" /* Pending Break Enable */
219 if (cpu_feature2 != 0) {
220 printf("\n Features2=0x%b", cpu_feature2,
222 "\001SSE3" /* SSE3 */
224 "\003RSVD2" /* "Reserved" bit 2 */
225 "\004MON" /* MONITOR/MWAIT Instructions */
226 "\005DS_CPL" /* CPL Qualified Debug Store */
227 "\006VMX" /* Virtual Machine Extensions */
229 "\010EST" /* Enhanced SpeedStep */
230 "\011TM2" /* Thermal Monitor 2 */
232 "\013CNTX-ID" /* L1 context ID available */
235 "\016CX16" /* CMPXCHG16B Instruction */
236 "\017XTPR" /* Send Task Priority Messages*/
258 * AMD64 Architecture Programmer's Manual Volume 3:
259 * General-Purpose and System Instructions
260 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
262 * IA-32 Intel Architecture Software Developer's Manual,
263 * Volume 2A: Instruction Set Reference, A-M
264 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
266 if (amd_feature != 0) {
267 printf("\n AMD Features=0x%b", amd_feature,
269 "\001<s0>" /* Same */
270 "\002<s1>" /* Same */
271 "\003<s2>" /* Same */
272 "\004<s3>" /* Same */
273 "\005<s4>" /* Same */
274 "\006<s5>" /* Same */
275 "\007<s6>" /* Same */
276 "\010<s7>" /* Same */
277 "\011<s8>" /* Same */
278 "\012<s9>" /* Same */
279 "\013<b10>" /* Undefined */
280 "\014SYSCALL" /* Have SYSCALL/SYSRET */
281 "\015<s12>" /* Same */
282 "\016<s13>" /* Same */
283 "\017<s14>" /* Same */
284 "\020<s15>" /* Same */
285 "\021<s16>" /* Same */
286 "\022<s17>" /* Same */
287 "\023<b18>" /* Reserved, unknown */
288 "\024MP" /* Multiprocessor Capable */
289 "\025NX" /* Has EFER.NXE, NX */
290 "\026<b21>" /* Undefined */
291 "\027MMX+" /* AMD MMX Extensions */
292 "\030<s23>" /* Same */
293 "\031<s24>" /* Same */
294 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
295 "\033<b26>" /* Undefined */
296 "\034RDTSCP" /* RDTSCP */
297 "\035<b28>" /* Undefined */
298 "\036LM" /* 64 bit long mode */
299 "\0373DNow+" /* AMD 3DNow! Extensions */
300 "\0403DNow" /* AMD 3DNow! */
304 if (amd_feature2 != 0) {
305 printf("\n AMD Features2=0x%b", amd_feature2,
307 "\001LAHF" /* LAHF/SAHF in long mode */
308 "\002CMP" /* CMP legacy */
311 "\005CR8" /* CR8 in legacy mode */
342 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
343 "AuthenticAMD") == 0) {
344 cpu_feature &= ~CPUID_HTT;
346 printf("\nHTT bit cleared - FreeBSD"
347 " does not have licensing issues"
352 * If this CPU supports HTT or CMP then mention the
353 * number of physical/logical cores it contains.
355 if (cpu_feature & CPUID_HTT)
356 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
357 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
358 (amd_feature2 & AMDID2_CMP))
359 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
360 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
362 cpuid_count(4, 0, regs);
363 if ((regs[0] & 0x1f) != 0)
364 cmp = ((regs[0] >> 26) & 0x3f) + 1;
367 printf("\n Cores per package: %d", cmp);
369 printf("\n Logical CPUs per core: %d",
373 /* Avoid ugly blank lines: only print newline when we have to. */
374 if (*cpu_vendor || cpu_id)
380 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
385 panicifcpuunsupported(void)
389 #error "You need to specify a cpu type"
392 * Now that we have told the user what they have,
393 * let them know if that machine type isn't configured.
400 panic("CPU class not configured");
408 * Final stage of CPU identification. -- Should I check TI?
417 ((u_int *)&cpu_vendor)[0] = regs[1];
418 ((u_int *)&cpu_vendor)[1] = regs[3];
419 ((u_int *)&cpu_vendor)[2] = regs[2];
420 cpu_vendor[12] = '\0';
424 cpu_procinfo = regs[1];
425 cpu_feature = regs[3];
426 cpu_feature2 = regs[2];
428 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
429 strcmp(cpu_vendor, "AuthenticAMD") == 0) {
430 do_cpuid(0x80000000, regs);
431 cpu_exthigh = regs[0];
433 if (cpu_exthigh >= 0x80000001) {
434 do_cpuid(0x80000001, regs);
435 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
436 amd_feature2 = regs[2];
438 if (cpu_exthigh >= 0x80000008) {
439 do_cpuid(0x80000008, regs);
440 cpu_procinfo2 = regs[2];
444 cpu = CPU_CLAWHAMMER;
448 print_AMD_assoc(int i)
451 printf(", fully associative\n");
453 printf(", %d-way associative\n", i);
457 print_AMD_l2_assoc(int i)
460 case 0: printf(", disabled/not present\n"); break;
461 case 1: printf(", direct mapped\n"); break;
462 case 2: printf(", 2-way associative\n"); break;
463 case 4: printf(", 4-way associative\n"); break;
464 case 6: printf(", 8-way associative\n"); break;
465 case 8: printf(", 16-way associative\n"); break;
466 case 15: printf(", fully associative\n"); break;
467 default: printf(", reserved configuration\n"); break;
476 if (cpu_exthigh < 0x80000005)
479 do_cpuid(0x80000005, regs);
480 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
481 print_AMD_assoc(regs[0] >> 24);
483 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
484 print_AMD_assoc((regs[0] >> 8) & 0xff);
486 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
487 print_AMD_assoc(regs[1] >> 24);
489 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
490 print_AMD_assoc((regs[1] >> 8) & 0xff);
492 printf("L1 data cache: %d kbytes", regs[2] >> 24);
493 printf(", %d bytes/line", regs[2] & 0xff);
494 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
495 print_AMD_assoc((regs[2] >> 16) & 0xff);
497 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
498 printf(", %d bytes/line", regs[3] & 0xff);
499 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
500 print_AMD_assoc((regs[3] >> 16) & 0xff);
502 if (cpu_exthigh >= 0x80000006) {
503 do_cpuid(0x80000006, regs);
504 if ((regs[0] >> 16) != 0) {
505 printf("L2 2MB data TLB: %d entries",
506 (regs[0] >> 16) & 0xfff);
507 print_AMD_l2_assoc(regs[0] >> 28);
508 printf("L2 2MB instruction TLB: %d entries",
510 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
512 printf("L2 2MB unified TLB: %d entries",
514 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
516 if ((regs[1] >> 16) != 0) {
517 printf("L2 4KB data TLB: %d entries",
518 (regs[1] >> 16) & 0xfff);
519 print_AMD_l2_assoc(regs[1] >> 28);
521 printf("L2 4KB instruction TLB: %d entries",
522 (regs[1] >> 16) & 0xfff);
523 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
525 printf("L2 4KB unified TLB: %d entries",
526 (regs[1] >> 16) & 0xfff);
527 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
529 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
530 printf(", %d bytes/line", regs[2] & 0xff);
531 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
532 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
537 setPQL2_AMD(int *const size, int *const ways)
539 if (cpu_exthigh >= 0x80000006) {
542 do_cpuid(0x80000006, regs);
543 *size = regs[2] >> 16;
544 *ways = (regs[2] >> 12) & 0x0f;
546 case 0: /* disabled/not present */
547 case 15: /* fully associative */
548 default: *ways = 1; break; /* reserved configuration */
549 case 4: *ways = 4; break;
550 case 6: *ways = 8; break;
551 case 8: *ways = 16; break;
557 setPQL2(int *const size, int *const ways)
559 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
560 setPQL2_AMD(size, ways);