2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
38 #include <sys/systm.h>
39 #include <sys/sysctl.h>
41 #include <machine/cputypes.h>
42 #include <machine/md_var.h>
43 #include <machine/specialreg.h>
48 static int hw_instruction_sse;
49 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
50 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
52 * -1: automatic (default)
53 * 0: keep enable CLFLUSH
54 * 1: force disable CLFLUSH
56 static int hw_clflush_disable = -1;
63 * Work around Erratum 721 for Family 10h and 12h processors.
64 * These processors may incorrectly update the stack pointer
65 * after a long series of push and/or near-call instructions,
66 * or a long series of pop and/or near-return instructions.
68 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
69 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
71 * Hypervisors do not provide access to the errata MSR,
72 * causing #GP exception on attempt to apply the errata. The
73 * MSR write shall be done on host and persist globally
74 * anyway, so do not try to do it when under virtualization.
76 switch (CPUID_TO_FAMILY(cpu_id)) {
79 if ((cpu_feature2 & CPUID2_HV) == 0)
80 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
86 * Initialize special VIA features
94 * Check extended CPUID for PadLock features.
96 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
98 do_cpuid(0xc0000000, regs);
99 if (regs[0] >= 0xc0000001) {
100 do_cpuid(0xc0000001, regs);
105 /* Enable RNG if present. */
106 if ((val & VIA_CPUID_HAS_RNG) != 0) {
107 via_feature_rng = VIA_HAS_RNG;
108 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
111 /* Enable PadLock if present. */
112 if ((val & VIA_CPUID_HAS_ACE) != 0)
113 via_feature_xcrypt |= VIA_HAS_AES;
114 if ((val & VIA_CPUID_HAS_ACE2) != 0)
115 via_feature_xcrypt |= VIA_HAS_AESCTR;
116 if ((val & VIA_CPUID_HAS_PHE) != 0)
117 via_feature_xcrypt |= VIA_HAS_SHA;
118 if ((val & VIA_CPUID_HAS_PMM) != 0)
119 via_feature_xcrypt |= VIA_HAS_MM;
120 if (via_feature_xcrypt != 0)
121 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
125 * Initialize CPU control registers
134 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
135 cr4 |= CR4_FXSR | CR4_XMM;
136 cpu_fxsr = hw_instruction_sse = 1;
138 if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
142 * Postpone enabling the SMEP on the boot CPU until the page
143 * tables are switched from the boot loader identity mapping
144 * to the kernel tables. The boot loader enables the U bit in
147 if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
150 if ((amd_feature & AMDID_NX) != 0) {
151 msr = rdmsr(MSR_EFER) | EFER_NXE;
152 wrmsr(MSR_EFER, msr);
155 switch (cpu_vendor_id) {
159 case CPU_VENDOR_CENTAUR:
166 initializecpucache(void)
170 * CPUID with %eax = 1, %ebx returns
171 * Bits 15-8: CLFLUSH line size
172 * (Value * 8 = cache line size in bytes)
174 if ((cpu_feature & CPUID_CLFSH) != 0)
175 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
177 * XXXKIB: (temporary) hack to work around traps generated
178 * when CLFLUSHing APIC register window under virtualization
179 * environments. These environments tend to disable the
180 * CPUID_SS feature even though the native CPU supports it.
182 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
183 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
184 cpu_feature &= ~CPUID_CLFSH;
185 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
189 * The kernel's use of CLFLUSH{,OPT} can be disabled manually
190 * by setting the hw.clflush_disable tunable.
192 if (hw_clflush_disable == 1) {
193 cpu_feature &= ~CPUID_CLFSH;
194 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;