2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include "opt_atpic.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
42 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
48 #include <machine/apicreg.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/apicvar.h>
52 #include <machine/segments.h>
54 #define IOAPIC_ISA_INTS 16
55 #define IOAPIC_MEM_REGION 32
56 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
57 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
59 #define IRQ_EXTINT (NUM_IO_INTS + 1)
60 #define IRQ_NMI (NUM_IO_INTS + 2)
61 #define IRQ_SMI (NUM_IO_INTS + 3)
62 #define IRQ_DISABLED (NUM_IO_INTS + 4)
64 #define TODO printf("%s: not implemented!\n", __func__)
66 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
69 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
70 * as laid out in the ACPI System Interrupt number model where each I/O
71 * APIC has a contiguous chunk of the System Interrupt address space.
72 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
73 * IRQs behave as PCI IRQs by default. We also assume that the pin for
74 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
75 * configuration of individual pins as indicated by their tables.
77 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
78 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
79 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
82 struct ioapic_intsrc {
83 struct intsrc io_intsrc;
89 u_int io_edgetrigger:1;
97 u_int io_id:8; /* logical ID */
99 u_int io_intbase:8; /* System Interrupt base */
101 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
102 STAILQ_ENTRY(ioapic) io_next;
103 struct ioapic_intsrc io_pins[0];
106 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
107 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
108 static const char *ioapic_bus_string(int bus_type);
109 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
110 static void ioapic_enable_source(struct intsrc *isrc);
111 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
112 static void ioapic_eoi_source(struct intsrc *isrc);
113 static void ioapic_enable_intr(struct intsrc *isrc);
114 static int ioapic_vector(struct intsrc *isrc);
115 static int ioapic_source_pending(struct intsrc *isrc);
116 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
117 enum intr_polarity pol);
118 static void ioapic_suspend(struct intsrc *isrc);
119 static void ioapic_resume(struct intsrc *isrc);
120 static void ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
121 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
123 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
124 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
125 ioapic_eoi_source, ioapic_enable_intr,
126 ioapic_vector, ioapic_source_pending,
127 ioapic_suspend, ioapic_resume,
128 ioapic_config_intr, ioapic_assign_cpu };
130 static int next_ioapic_base;
131 static u_int next_id;
133 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
134 static int enable_extint;
135 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
136 "Enable the ExtINT pin in the first I/O APIC");
137 TUNABLE_INT("hw.apic.enable_extint", &enable_extint);
140 _ioapic_eoi_source(struct intsrc *isrc)
146 ioapic_read(volatile ioapic_t *apic, int reg)
149 mtx_assert(&icu_lock, MA_OWNED);
150 apic->ioregsel = reg;
151 return (apic->iowin);
155 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
158 mtx_assert(&icu_lock, MA_OWNED);
159 apic->ioregsel = reg;
164 ioapic_bus_string(int bus_type)
180 ioapic_print_irq(struct ioapic_intsrc *intpin)
183 switch (intpin->io_irq) {
197 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
203 ioapic_enable_source(struct intsrc *isrc)
205 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
206 struct ioapic *io = (struct ioapic *)isrc->is_pic;
209 mtx_lock_spin(&icu_lock);
210 if (intpin->io_masked) {
211 flags = intpin->io_lowreg & ~IOART_INTMASK;
212 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
214 intpin->io_masked = 0;
216 mtx_unlock_spin(&icu_lock);
220 ioapic_disable_source(struct intsrc *isrc, int eoi)
222 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
223 struct ioapic *io = (struct ioapic *)isrc->is_pic;
226 mtx_lock_spin(&icu_lock);
227 if (!intpin->io_masked && !intpin->io_edgetrigger) {
228 flags = intpin->io_lowreg | IOART_INTMSET;
229 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
231 intpin->io_masked = 1;
235 _ioapic_eoi_source(isrc);
237 mtx_unlock_spin(&icu_lock);
241 ioapic_eoi_source(struct intsrc *isrc)
244 _ioapic_eoi_source(isrc);
248 * Completely program an intpin based on the data in its interrupt source
252 ioapic_program_intpin(struct ioapic_intsrc *intpin)
254 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
255 uint32_t low, high, value;
258 * If a pin is completely invalid or if it is valid but hasn't
259 * been enabled yet, just ensure that the pin is masked.
261 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
262 intpin->io_vector == 0)) {
263 mtx_lock_spin(&icu_lock);
264 low = ioapic_read(io->io_addr,
265 IOAPIC_REDTBL_LO(intpin->io_intpin));
266 if ((low & IOART_INTMASK) == IOART_INTMCLR)
267 ioapic_write(io->io_addr,
268 IOAPIC_REDTBL_LO(intpin->io_intpin),
269 low | IOART_INTMSET);
270 mtx_unlock_spin(&icu_lock);
274 /* Set the destination. */
276 high = intpin->io_cpu << APIC_ID_SHIFT;
278 /* Program the rest of the low word. */
279 if (intpin->io_edgetrigger)
280 low |= IOART_TRGREDG;
282 low |= IOART_TRGRLVL;
283 if (intpin->io_activehi)
287 if (intpin->io_masked)
288 low |= IOART_INTMSET;
289 switch (intpin->io_irq) {
291 KASSERT(intpin->io_edgetrigger,
292 ("ExtINT not edge triggered"));
293 low |= IOART_DELEXINT;
296 KASSERT(intpin->io_edgetrigger,
297 ("NMI not edge triggered"));
301 KASSERT(intpin->io_edgetrigger,
302 ("SMI not edge triggered"));
306 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
308 low |= IOART_DELFIXED | intpin->io_vector;
311 /* Write the values to the APIC. */
312 mtx_lock_spin(&icu_lock);
313 intpin->io_lowreg = low;
314 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
315 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
316 value &= ~IOART_DEST;
318 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
319 mtx_unlock_spin(&icu_lock);
323 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
325 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
326 struct ioapic *io = (struct ioapic *)isrc->is_pic;
328 intpin->io_cpu = apic_id;
330 printf("ioapic%u: Assigning ", io->io_id);
331 ioapic_print_irq(intpin);
332 printf(" to local APIC %u\n", intpin->io_cpu);
334 ioapic_program_intpin(intpin);
338 ioapic_enable_intr(struct intsrc *isrc)
340 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
341 struct ioapic *io = (struct ioapic *)isrc->is_pic;
343 if (intpin->io_vector == 0) {
345 * Allocate an APIC vector for this interrupt pin. Once
346 * we have a vector we program the interrupt pin.
348 intpin->io_vector = apic_alloc_vector(intpin->io_irq);
350 printf("ioapic%u: routing intpin %u (", io->io_id,
352 ioapic_print_irq(intpin);
353 printf(") to vector %u\n", intpin->io_vector);
355 ioapic_program_intpin(intpin);
356 apic_enable_vector(intpin->io_vector);
361 ioapic_vector(struct intsrc *isrc)
363 struct ioapic_intsrc *pin;
365 pin = (struct ioapic_intsrc *)isrc;
366 return (pin->io_irq);
370 ioapic_source_pending(struct intsrc *isrc)
372 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
374 if (intpin->io_vector == 0)
376 return (lapic_intr_pending(intpin->io_vector));
380 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
381 enum intr_polarity pol)
383 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
384 struct ioapic *io = (struct ioapic *)isrc->is_pic;
387 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
388 ("%s: Conforming trigger or polarity\n", __func__));
391 * EISA interrupts always use active high polarity, so don't allow
392 * them to be set to active low.
394 * XXX: Should we write to the ELCR if the trigger mode changes for
395 * an EISA IRQ or an ISA IRQ with the ELCR present?
397 if (intpin->io_bus == APIC_BUS_EISA)
398 pol = INTR_POLARITY_HIGH;
400 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
402 printf("ioapic%u: Changing trigger for pin %u to %s\n",
403 io->io_id, intpin->io_intpin,
404 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
405 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
408 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
410 printf("ioapic%u: Changing polarity for pin %u to %s\n",
411 io->io_id, intpin->io_intpin,
412 pol == INTR_POLARITY_HIGH ? "high" : "low");
413 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
417 ioapic_program_intpin(intpin);
422 ioapic_suspend(struct intsrc *isrc)
429 ioapic_resume(struct intsrc *isrc)
432 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
436 * Create a plain I/O APIC object.
439 ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
442 struct ioapic_intsrc *intpin;
443 volatile ioapic_t *apic;
447 /* Map the register window so we can access the device. */
448 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
449 mtx_lock_spin(&icu_lock);
450 value = ioapic_read(apic, IOAPIC_VER);
451 mtx_unlock_spin(&icu_lock);
453 /* If it's version register doesn't seem to work, punt. */
454 if (value == 0xffffffff) {
455 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
459 /* Determine the number of vectors and set the APIC ID. */
460 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
461 io = malloc(sizeof(struct ioapic) +
462 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
463 io->io_pic = ioapic_template;
464 mtx_lock_spin(&icu_lock);
465 io->io_id = next_id++;
466 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
467 if (apic_id != -1 && io->io_apic_id != apic_id) {
468 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
469 mtx_unlock_spin(&icu_lock);
470 io->io_apic_id = apic_id;
471 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
474 mtx_unlock_spin(&icu_lock);
476 intbase = next_ioapic_base;
477 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
479 } else if (intbase != next_ioapic_base)
480 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
481 io->io_id, intbase, next_ioapic_base);
482 io->io_intbase = intbase;
483 next_ioapic_base = intbase + numintr;
484 io->io_numintr = numintr;
488 * Initialize pins. Start off with interrupts disabled. Default
489 * to active-hi and edge-triggered for ISA interrupts and active-lo
490 * and level-triggered for all others.
492 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
493 mtx_lock_spin(&icu_lock);
494 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
495 intpin->io_intsrc.is_pic = (struct pic *)io;
496 intpin->io_intpin = i;
497 intpin->io_irq = intbase + i;
500 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
501 * Assume that pins 1-15 are ISA interrupts and that all
502 * other pins are PCI interrupts.
504 if (intpin->io_irq == 0)
505 ioapic_set_extint(io, i);
506 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
507 intpin->io_bus = APIC_BUS_ISA;
508 intpin->io_activehi = 1;
509 intpin->io_edgetrigger = 1;
510 intpin->io_masked = 1;
512 intpin->io_bus = APIC_BUS_PCI;
513 intpin->io_activehi = 0;
514 intpin->io_edgetrigger = 0;
515 intpin->io_masked = 1;
519 * Route interrupts to the BSP by default. Interrupts may
520 * be routed to other CPUs later after they are enabled.
522 intpin->io_cpu = PCPU_GET(apic_id);
523 if (bootverbose && intpin->io_irq != IRQ_DISABLED) {
524 printf("ioapic%u: intpin %d -> ", io->io_id, i);
525 ioapic_print_irq(intpin);
526 printf(" (%s, %s)\n", intpin->io_edgetrigger ?
527 "edge" : "level", intpin->io_activehi ? "high" :
530 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
531 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
533 mtx_unlock_spin(&icu_lock);
539 ioapic_get_vector(void *cookie, u_int pin)
543 io = (struct ioapic *)cookie;
544 if (pin >= io->io_numintr)
546 return (io->io_pins[pin].io_irq);
550 ioapic_disable_pin(void *cookie, u_int pin)
554 io = (struct ioapic *)cookie;
555 if (pin >= io->io_numintr)
557 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
559 io->io_pins[pin].io_irq = IRQ_DISABLED;
561 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
566 ioapic_remap_vector(void *cookie, u_int pin, int vector)
570 io = (struct ioapic *)cookie;
571 if (pin >= io->io_numintr || vector < 0)
573 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
575 io->io_pins[pin].io_irq = vector;
577 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
583 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
587 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
589 io = (struct ioapic *)cookie;
590 if (pin >= io->io_numintr)
592 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
594 io->io_pins[pin].io_bus = bus_type;
596 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
597 ioapic_bus_string(bus_type));
602 ioapic_set_nmi(void *cookie, u_int pin)
606 io = (struct ioapic *)cookie;
607 if (pin >= io->io_numintr)
609 if (io->io_pins[pin].io_irq == IRQ_NMI)
611 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
613 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
614 io->io_pins[pin].io_irq = IRQ_NMI;
615 io->io_pins[pin].io_masked = 0;
616 io->io_pins[pin].io_edgetrigger = 1;
617 io->io_pins[pin].io_activehi = 1;
619 printf("ioapic%u: Routing NMI -> intpin %d\n",
625 ioapic_set_smi(void *cookie, u_int pin)
629 io = (struct ioapic *)cookie;
630 if (pin >= io->io_numintr)
632 if (io->io_pins[pin].io_irq == IRQ_SMI)
634 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
636 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
637 io->io_pins[pin].io_irq = IRQ_SMI;
638 io->io_pins[pin].io_masked = 0;
639 io->io_pins[pin].io_edgetrigger = 1;
640 io->io_pins[pin].io_activehi = 1;
642 printf("ioapic%u: Routing SMI -> intpin %d\n",
648 ioapic_set_extint(void *cookie, u_int pin)
652 io = (struct ioapic *)cookie;
653 if (pin >= io->io_numintr)
655 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
657 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
659 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
660 io->io_pins[pin].io_irq = IRQ_EXTINT;
662 io->io_pins[pin].io_masked = 0;
664 io->io_pins[pin].io_masked = 1;
665 io->io_pins[pin].io_edgetrigger = 1;
666 io->io_pins[pin].io_activehi = 1;
668 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
674 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
678 io = (struct ioapic *)cookie;
679 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
681 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
683 io->io_pins[pin].io_activehi = (pol == INTR_POLARITY_HIGH);
685 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
686 pol == INTR_POLARITY_HIGH ? "high" : "low");
691 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
695 io = (struct ioapic *)cookie;
696 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
698 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
700 io->io_pins[pin].io_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
702 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
703 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
708 * Register a complete I/O APIC object with the interrupt subsystem.
711 ioapic_register(void *cookie)
713 struct ioapic_intsrc *pin;
715 volatile ioapic_t *apic;
719 io = (struct ioapic *)cookie;
721 mtx_lock_spin(&icu_lock);
722 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
723 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
724 mtx_unlock_spin(&icu_lock);
725 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
726 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
727 io->io_intbase + io->io_numintr - 1);
729 /* Register valid pins as interrupt sources. */
730 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
731 if (pin->io_irq < NUM_IO_INTS)
732 intr_register_source(&pin->io_intsrc);