2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/mutex.h>
54 #include <machine/apicreg.h>
55 #include <machine/cpu.h>
56 #include <machine/cputypes.h>
57 #include <machine/frame.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/apicvar.h>
60 #include <machine/md_var.h>
61 #include <machine/smp.h>
62 #include <machine/specialreg.h>
65 #include <sys/interrupt.h>
70 #include <sys/dtrace_bsd.h>
71 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU];
74 /* Sanity checks on IDT vectors. */
75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
77 CTASSERT(APIC_LOCAL_INTS == 240);
78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
80 /* Magic IRQ values for the timer and syscalls. */
81 #define IRQ_TIMER (NUM_IO_INTS + 1)
82 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
85 * Support for local APICs. Local APICs manage interrupts on each
86 * individual processor as opposed to I/O APICs which receive interrupts
87 * from I/O devices and then forward them on to the local APICs.
89 * Local APICs can also send interrupts to each other thus providing the
94 u_int lvt_edgetrigger:1;
103 struct lvt la_lvts[LVT_MAX + 1];
106 u_int la_cluster_id:2;
108 u_long *la_timer_count;
109 u_long la_hard_ticks;
110 u_long la_stat_ticks;
111 u_long la_prof_ticks;
112 } static lapics[MAX_APIC_ID + 1];
114 /* XXX: should thermal be an NMI? */
116 /* Global defaults for local APIC LVT entries. */
117 static struct lvt lvts[LVT_MAX + 1] = {
118 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
119 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
120 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
122 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
126 static inthand_t *ioint_handlers[] = {
128 IDTVEC(apic_isr1), /* 32 - 63 */
129 IDTVEC(apic_isr2), /* 64 - 95 */
130 IDTVEC(apic_isr3), /* 96 - 127 */
131 IDTVEC(apic_isr4), /* 128 - 159 */
132 IDTVEC(apic_isr5), /* 160 - 191 */
133 IDTVEC(apic_isr6), /* 192 - 223 */
134 IDTVEC(apic_isr7), /* 224 - 255 */
137 /* Include IDT_SYSCALL to make indexing easier. */
138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
140 static u_int32_t lapic_timer_divisors[] = {
141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
145 extern inthand_t IDTVEC(rsvd);
147 volatile lapic_t *lapic;
148 vm_paddr_t lapic_paddr;
149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
151 static void lapic_enable(void);
152 static void lapic_resume(struct pic *pic);
153 static void lapic_timer_enable_intr(void);
154 static void lapic_timer_oneshot(u_int count);
155 static void lapic_timer_periodic(u_int count);
156 static void lapic_timer_set_divisor(u_int divisor);
157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
159 struct pic lapic_pic = { .pic_resume = lapic_resume };
162 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
167 if (la->la_lvts[pin].lvt_active)
168 lvt = &la->la_lvts[pin];
172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
174 if (lvt->lvt_edgetrigger == 0)
175 value |= APIC_LVT_TM;
176 if (lvt->lvt_activehi == 0)
177 value |= APIC_LVT_IIPP_INTALO;
180 value |= lvt->lvt_mode;
181 switch (lvt->lvt_mode) {
182 case APIC_LVT_DM_NMI:
183 case APIC_LVT_DM_SMI:
184 case APIC_LVT_DM_INIT:
185 case APIC_LVT_DM_EXTINT:
186 if (!lvt->lvt_edgetrigger) {
187 printf("lapic%u: Forcing LINT%u to edge trigger\n",
189 value |= APIC_LVT_TM;
191 /* Use a vector of 0. */
193 case APIC_LVT_DM_FIXED:
194 value |= lvt->lvt_vector;
197 panic("bad APIC LVT delivery mode: %#x\n", value);
203 * Map the local APIC and setup necessary interrupt vectors.
206 lapic_init(vm_paddr_t addr)
209 /* Map the local APIC and setup the spurious interrupt handler. */
210 KASSERT(trunc_page(addr) == addr,
211 ("local APIC not aligned on a page boundary"));
212 lapic = pmap_mapdev(addr, sizeof(lapic_t));
214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
216 /* Perform basic initialization of the BSP's local APIC. */
218 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
220 /* Set BSP's per-CPU local APIC ID. */
221 PCPU_SET(apic_id, lapic_id());
223 /* Local APIC timer interrupt. */
224 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
225 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
227 /* XXX: error/thermal interrupts */
231 * Create a local APIC instance.
234 lapic_create(u_int apic_id, int boot_cpu)
238 if (apic_id > MAX_APIC_ID) {
239 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
241 panic("Can't ignore BSP");
244 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
248 * Assume no local LVT overrides and a cluster of 0 and
249 * intra-cluster ID of 0.
251 lapics[apic_id].la_present = 1;
252 lapics[apic_id].la_id = apic_id;
253 for (i = 0; i < LVT_MAX; i++) {
254 lapics[apic_id].la_lvts[i] = lvts[i];
255 lapics[apic_id].la_lvts[i].lvt_active = 0;
259 cpu_add(apic_id, boot_cpu);
264 * Dump contents of local APIC registers
267 lapic_dump(const char* str)
270 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
271 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
272 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
273 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
274 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
275 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
276 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
281 lapic_setup(int boot)
286 char buf[MAXCOMLEN + 1];
288 la = &lapics[lapic_id()];
289 KASSERT(la->la_present, ("missing APIC structure"));
290 eflags = intr_disable();
291 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
293 /* Initialize the TPR to allow all interrupts. */
296 /* Setup spurious vector and enable the local APIC. */
299 /* Program LINT[01] LVT entries. */
300 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
301 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
303 /* Program the PMC LVT entry if present. */
304 if (maxlvt >= LVT_PMC)
305 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
308 /* Program timer LVT and setup handler. */
309 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
311 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
312 intrcnt_add(buf, &la->la_timer_count);
315 /* We don't setup the timer during boot on the BSP until later. */
316 if (!(boot && PCPU_GET(cpuid) == 0)) {
317 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
319 lapic_timer_set_divisor(lapic_timer_divisor);
320 lapic_timer_periodic(lapic_timer_period);
321 lapic_timer_enable_intr();
324 /* XXX: Error and thermal LVTs */
326 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
328 * Detect the presence of C1E capability mostly on latest
329 * dual-cores (or future) k8 family. This feature renders
330 * the local APIC timer dead, so we disable it by reading
331 * the Interrupt Pending Message register and clearing both
332 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
335 * "BIOS and Kernel Developer's Guide for AMD NPT
336 * Family 0Fh Processors"
337 * #32559 revision 3.00
339 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
340 (cpu_id & 0x0fff0000) >= 0x00040000) {
343 msr = rdmsr(0xc0010055);
344 if (msr & 0x18000000)
345 wrmsr(0xc0010055, msr & ~0x18000000ULL);
349 intr_restore(eflags);
353 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
354 * that it can drive hardclock, statclock, and profclock. This function
355 * returns true if it is able to use the local APIC timer to drive the
356 * clocks and false if it is not able.
359 lapic_setup_clock(void)
363 /* Can't drive the timer without a local APIC. */
367 /* Start off with a divisor of 2 (power on reset default). */
368 lapic_timer_divisor = 2;
370 /* Try to calibrate the local APIC timer. */
372 lapic_timer_set_divisor(lapic_timer_divisor);
373 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
375 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
376 if (value != APIC_TIMER_MAX_COUNT)
378 lapic_timer_divisor <<= 1;
379 } while (lapic_timer_divisor <= 128);
380 if (lapic_timer_divisor > 128)
381 panic("lapic: Divisor too big");
384 printf("lapic: Divisor %lu, Frequency %lu hz\n",
385 lapic_timer_divisor, value);
388 * We want to run stathz in the neighborhood of 128hz. We would
389 * like profhz to run as often as possible, so we let it run on
390 * each clock tick. We try to honor the requested 'hz' value as
393 * If 'hz' is above 1500, then we just let the lapic timer
394 * (and profhz) run at hz. If 'hz' is below 1500 but above
395 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
396 * is below 750 then we let the lapic timer run at 4 * 'hz'.
401 lapic_timer_hz = hz * 2;
403 lapic_timer_hz = hz * 4;
404 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
405 profhz = lapic_timer_hz;
406 lapic_timer_period = value / lapic_timer_hz;
409 * Start up the timer on the BSP. The APs will kick off their
410 * timer during lapic_setup().
412 lapic_timer_periodic(lapic_timer_period);
413 lapic_timer_enable_intr();
422 /* Software disable the local APIC. */
424 value &= ~APIC_SVR_SWEN;
433 /* Program the spurious vector to enable the local APIC. */
435 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
436 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
440 /* Reset the local APIC on the BSP during resume. */
442 lapic_resume(struct pic *pic)
452 KASSERT(lapic != NULL, ("local APIC is not mapped"));
453 return (lapic->id >> APIC_ID_SHIFT);
457 lapic_intr_pending(u_int vector)
459 volatile u_int32_t *irr;
462 * The IRR registers are an array of 128-bit registers each of
463 * which only describes 32 interrupts in the low 32 bits.. Thus,
464 * we divide the vector by 32 to get the 128-bit index. We then
465 * multiply that index by 4 to get the equivalent index from
466 * treating the IRR as an array of 32-bit registers. Finally, we
467 * modulus the vector by 32 to determine the individual bit to
471 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
475 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
479 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
481 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
483 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
484 ("%s: intra cluster id %u too big", __func__, cluster_id));
485 la = &lapics[apic_id];
486 la->la_cluster = cluster;
487 la->la_cluster_id = cluster_id;
491 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
496 if (apic_id == APIC_ID_ALL) {
497 lvts[pin].lvt_masked = masked;
501 KASSERT(lapics[apic_id].la_present,
502 ("%s: missing APIC %u", __func__, apic_id));
503 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
504 lapics[apic_id].la_lvts[pin].lvt_active = 1;
506 printf("lapic%u:", apic_id);
509 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
514 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
520 if (apic_id == APIC_ID_ALL) {
525 KASSERT(lapics[apic_id].la_present,
526 ("%s: missing APIC %u", __func__, apic_id));
527 lvt = &lapics[apic_id].la_lvts[pin];
530 printf("lapic%u:", apic_id);
532 lvt->lvt_mode = mode;
534 case APIC_LVT_DM_NMI:
535 case APIC_LVT_DM_SMI:
536 case APIC_LVT_DM_INIT:
537 case APIC_LVT_DM_EXTINT:
538 lvt->lvt_edgetrigger = 1;
539 lvt->lvt_activehi = 1;
540 if (mode == APIC_LVT_DM_EXTINT)
546 panic("Unsupported delivery mode: 0x%x\n", mode);
551 case APIC_LVT_DM_NMI:
554 case APIC_LVT_DM_SMI:
557 case APIC_LVT_DM_INIT:
560 case APIC_LVT_DM_EXTINT:
564 printf(" -> LINT%u\n", pin);
570 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
573 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
575 if (apic_id == APIC_ID_ALL) {
576 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
580 KASSERT(lapics[apic_id].la_present,
581 ("%s: missing APIC %u", __func__, apic_id));
582 lapics[apic_id].la_lvts[pin].lvt_active = 1;
583 lapics[apic_id].la_lvts[pin].lvt_activehi =
584 (pol == INTR_POLARITY_HIGH);
586 printf("lapic%u:", apic_id);
589 printf(" LINT%u polarity: %s\n", pin,
590 pol == INTR_POLARITY_HIGH ? "high" : "low");
595 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
598 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
600 if (apic_id == APIC_ID_ALL) {
601 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
605 KASSERT(lapics[apic_id].la_present,
606 ("%s: missing APIC %u", __func__, apic_id));
607 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
608 (trigger == INTR_TRIGGER_EDGE);
609 lapics[apic_id].la_lvts[pin].lvt_active = 1;
611 printf("lapic%u:", apic_id);
614 printf(" LINT%u trigger: %s\n", pin,
615 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
620 * Adjust the TPR of the current CPU so that it blocks all interrupts below
621 * the passed in vector.
624 lapic_set_tpr(u_int vector)
631 tpr = lapic->tpr & ~APIC_TPR_PRIO;
645 lapic_handle_intr(int vector, struct trapframe *frame)
650 panic("Couldn't get vector from ISR!");
651 isrc = intr_lookup_source(apic_idt_to_irq(vector));
652 intr_execute_handlers(isrc, frame);
656 lapic_handle_timer(struct trapframe *frame)
660 /* Send EOI first thing. */
663 #if defined(SMP) && !defined(SCHED_ULE)
665 * Don't do any accounting for the disabled HTT cores, since it
666 * will provide misleading numbers for the userland.
668 * No locking is necessary here, since even if we loose the race
669 * when hlt_cpus_mask changes it is not a big deal, really.
671 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
672 * and unlike other schedulers it actually schedules threads to
675 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
679 /* Look up our local APIC structure for the tick counters. */
680 la = &lapics[PCPU_GET(apic_id)];
681 (*la->la_timer_count)++;
686 * If the DTrace hooks are configured and a callback function
687 * has been registered, then call it to process the high speed
690 int cpu = PCPU_GET(cpuid);
691 if (lapic_cyclic_clock_func[cpu] != NULL)
692 (*lapic_cyclic_clock_func[cpu])(frame);
695 /* Fire hardclock at hz. */
696 la->la_hard_ticks += hz;
697 if (la->la_hard_ticks >= lapic_timer_hz) {
698 la->la_hard_ticks -= lapic_timer_hz;
699 if (PCPU_GET(cpuid) == 0)
700 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
702 hardclock_cpu(TRAPF_USERMODE(frame));
705 /* Fire statclock at stathz. */
706 la->la_stat_ticks += stathz;
707 if (la->la_stat_ticks >= lapic_timer_hz) {
708 la->la_stat_ticks -= lapic_timer_hz;
709 statclock(TRAPF_USERMODE(frame));
712 /* Fire profclock at profhz, but only when needed. */
713 la->la_prof_ticks += profhz;
714 if (la->la_prof_ticks >= lapic_timer_hz) {
715 la->la_prof_ticks -= lapic_timer_hz;
717 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
723 lapic_timer_set_divisor(u_int divisor)
726 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
727 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
728 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
729 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
733 lapic_timer_oneshot(u_int count)
737 value = lapic->lvt_timer;
738 value &= ~APIC_LVTT_TM;
739 value |= APIC_LVTT_TM_ONE_SHOT;
740 lapic->lvt_timer = value;
741 lapic->icr_timer = count;
745 lapic_timer_periodic(u_int count)
749 value = lapic->lvt_timer;
750 value &= ~APIC_LVTT_TM;
751 value |= APIC_LVTT_TM_PERIODIC;
752 lapic->lvt_timer = value;
753 lapic->icr_timer = count;
757 lapic_timer_enable_intr(void)
761 value = lapic->lvt_timer;
762 value &= ~APIC_LVT_M;
763 lapic->lvt_timer = value;
766 /* Request a free IDT vector to be used by the specified IRQ. */
768 apic_alloc_vector(u_int irq)
772 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
775 * Search for a free vector. Currently we just use a very simple
776 * algorithm to find the first free vector.
778 mtx_lock_spin(&icu_lock);
779 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
780 if (ioint_irqs[vector] != 0)
782 ioint_irqs[vector] = irq;
783 mtx_unlock_spin(&icu_lock);
784 return (vector + APIC_IO_INTS);
786 mtx_unlock_spin(&icu_lock);
787 panic("Couldn't find an APIC vector for IRQ %u", irq);
791 * Request 'count' free contiguous IDT vectors to be used by 'count'
792 * IRQs. 'count' must be a power of two and the vectors will be
793 * aligned on a boundary of 'align'. If the request cannot be
794 * satisfied, 0 is returned.
797 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
799 u_int first, run, vector;
801 KASSERT(powerof2(count), ("bad count"));
802 KASSERT(powerof2(align), ("bad align"));
803 KASSERT(align >= count, ("align < count"));
805 for (run = 0; run < count; run++)
806 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
811 * Search for 'count' free vectors. As with apic_alloc_vector(),
812 * this just uses a simple first fit algorithm.
816 mtx_lock_spin(&icu_lock);
817 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
819 /* Vector is in use, end run. */
820 if (ioint_irqs[vector] != 0) {
826 /* Start a new run if run == 0 and vector is aligned. */
828 if ((vector & (align - 1)) != 0)
834 /* Keep looping if the run isn't long enough yet. */
838 /* Found a run, assign IRQs and return the first vector. */
839 for (vector = 0; vector < count; vector++)
840 ioint_irqs[first + vector] = irqs[vector];
841 mtx_unlock_spin(&icu_lock);
842 return (first + APIC_IO_INTS);
844 mtx_unlock_spin(&icu_lock);
845 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
850 apic_enable_vector(u_int vector)
853 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
854 KASSERT(ioint_handlers[vector / 32] != NULL,
855 ("No ISR handler for vector %u", vector));
856 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
860 apic_disable_vector(u_int vector)
863 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
864 KASSERT(ioint_handlers[vector / 32] != NULL,
865 ("No ISR handler for vector %u", vector));
866 setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
869 /* Release an APIC vector when it's no longer in use. */
871 apic_free_vector(u_int vector, u_int irq)
873 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
874 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
875 ("Vector %u does not map to an IRQ line", vector));
876 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
877 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
878 mtx_lock_spin(&icu_lock);
879 ioint_irqs[vector - APIC_IO_INTS] = 0;
880 mtx_unlock_spin(&icu_lock);
883 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
885 apic_idt_to_irq(u_int vector)
888 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
889 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
890 ("Vector %u does not map to an IRQ line", vector));
891 return (ioint_irqs[vector - APIC_IO_INTS]);
896 * Dump data about APIC IDT vector mappings.
898 DB_SHOW_COMMAND(apic, db_show_apic)
904 if (strcmp(modif, "vv") == 0)
906 else if (strcmp(modif, "v") == 0)
910 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
912 if (irq != 0 && irq != IRQ_SYSCALL) {
913 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
914 if (irq == IRQ_TIMER)
915 db_printf("lapic timer\n");
916 else if (irq < NUM_IO_INTS) {
917 isrc = intr_lookup_source(irq);
918 if (isrc == NULL || verbose == 0)
919 db_printf("IRQ %u\n", irq);
921 db_dump_intr_event(isrc->is_event,
924 db_printf("IRQ %u ???\n", irq);
930 dump_mask(const char *prefix, uint32_t v, int base)
935 for (i = 0; i < 32; i++)
938 db_printf("%s:", prefix);
941 db_printf(" %02x", base + i);
947 /* Show info from the lapic regs for this CPU. */
948 DB_SHOW_COMMAND(lapic, db_show_lapic)
952 db_printf("lapic ID = %d\n", lapic_id());
954 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
956 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
958 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
959 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
960 db_printf("TPR = %02x\n", lapic->tpr);
962 #define dump_field(prefix, index) \
963 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
966 db_printf("In-service Interrupts:\n");
976 db_printf("TMR Interrupts:\n");
986 db_printf("IRR Interrupts:\n");
1001 * APIC probing support code. This includes code to manage enumerators.
1004 static SLIST_HEAD(, apic_enumerator) enumerators =
1005 SLIST_HEAD_INITIALIZER(enumerators);
1006 static struct apic_enumerator *best_enum;
1009 apic_register_enumerator(struct apic_enumerator *enumerator)
1012 struct apic_enumerator *apic_enum;
1014 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1015 if (apic_enum == enumerator)
1016 panic("%s: Duplicate register of %s", __func__,
1017 enumerator->apic_name);
1020 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1024 * We have to look for CPU's very, very early because certain subsystems
1025 * want to know how many CPU's we have extremely early on in the boot
1029 apic_init(void *dummy __unused)
1031 struct apic_enumerator *enumerator;
1034 /* Don't probe if APIC mode is disabled. */
1035 if (resource_disabled("apic", 0))
1038 /* First, probe all the enumerators to find the best match. */
1041 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1042 retval = enumerator->apic_probe();
1045 if (best_enum == NULL || best < retval) {
1046 best_enum = enumerator;
1050 if (best_enum == NULL) {
1052 printf("APIC: Could not find any APICs.\n");
1057 printf("APIC: Using the %s enumerator.\n",
1058 best_enum->apic_name);
1060 /* Second, probe the CPU's in the system. */
1061 retval = best_enum->apic_probe_cpus();
1063 printf("%s: Failed to probe CPUs: returned %d\n",
1064 best_enum->apic_name, retval);
1066 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1069 * Setup the local APIC. We have to do this prior to starting up the APs
1073 apic_setup_local(void *dummy __unused)
1077 if (best_enum == NULL)
1079 retval = best_enum->apic_setup_local();
1081 printf("%s: Failed to setup the local APIC: returned %d\n",
1082 best_enum->apic_name, retval);
1084 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local,
1088 * Setup the I/O APICs.
1091 apic_setup_io(void *dummy __unused)
1095 if (best_enum == NULL)
1097 retval = best_enum->apic_setup_io();
1099 printf("%s: Failed to setup I/O APICs: returned %d\n",
1100 best_enum->apic_name, retval);
1103 * Finish setting up the local APIC on the BSP once we know how to
1104 * properly program the LINT pins.
1107 intr_register_pic(&lapic_pic);
1111 /* Enable the MSI "pic". */
1114 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1118 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1119 * private to the sys/amd64 code. The public interface for the rest of the
1120 * kernel is defined in mp_machdep.c.
1123 lapic_ipi_wait(int delay)
1128 * Wait delay loops for IPI to be sent. This is highly bogus
1129 * since this is sensitive to CPU clock speed. If delay is
1130 * -1, we wait forever.
1137 for (x = 0; x < delay; x += incr) {
1138 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1146 lapic_ipi_raw(register_t icrlo, u_int dest)
1148 register_t value, eflags;
1150 /* XXX: Need more sanity checking of icrlo? */
1151 KASSERT(lapic != NULL, ("%s called too early", __func__));
1152 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1153 ("%s: invalid dest field", __func__));
1154 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1155 ("%s: reserved bits set in ICR LO register", __func__));
1157 /* Set destination in ICR HI register if it is being used. */
1158 eflags = intr_disable();
1159 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1160 value = lapic->icr_hi;
1161 value &= ~APIC_ID_MASK;
1162 value |= dest << APIC_ID_SHIFT;
1163 lapic->icr_hi = value;
1166 /* Program the contents of the IPI and dispatch it. */
1167 value = lapic->icr_lo;
1168 value &= APIC_ICRLO_RESV_MASK;
1170 lapic->icr_lo = value;
1171 intr_restore(eflags);
1174 #define BEFORE_SPIN 1000000
1175 #ifdef DETECT_DEADLOCK
1176 #define AFTER_SPIN 1000
1180 lapic_ipi_vectored(u_int vector, int dest)
1182 register_t icrlo, destfield;
1184 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1185 ("%s: invalid vector %d", __func__, vector));
1187 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
1188 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
1191 case APIC_IPI_DEST_SELF:
1192 icrlo |= APIC_DEST_SELF;
1194 case APIC_IPI_DEST_ALL:
1195 icrlo |= APIC_DEST_ALLISELF;
1197 case APIC_IPI_DEST_OTHERS:
1198 icrlo |= APIC_DEST_ALLESELF;
1201 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1202 ("%s: invalid destination 0x%x", __func__, dest));
1206 /* Wait for an earlier IPI to finish. */
1207 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1208 if (panicstr != NULL)
1211 panic("APIC: Previous IPI is stuck");
1214 lapic_ipi_raw(icrlo, destfield);
1216 #ifdef DETECT_DEADLOCK
1217 /* Wait for IPI to be delivered. */
1218 if (!lapic_ipi_wait(AFTER_SPIN)) {
1219 #ifdef needsattention
1223 * The above function waits for the message to actually be
1224 * delivered. It breaks out after an arbitrary timeout
1225 * since the message should eventually be delivered (at
1226 * least in theory) and that if it wasn't we would catch
1227 * the failure with the check above when the next IPI is
1230 * We could skip this wait entirely, EXCEPT it probably
1231 * protects us from other routines that assume that the
1232 * message was delivered and acted upon when this function
1235 printf("APIC: IPI might be stuck\n");
1236 #else /* !needsattention */
1237 /* Wait until mesage is sent without a timeout. */
1238 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1240 #endif /* needsattention */
1242 #endif /* DETECT_DEADLOCK */