2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/cpuset.h>
43 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/sysctl.h>
56 #include <vm/vm_param.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cputypes.h>
64 #include <machine/cpufunc.h>
66 #include <machine/md_var.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
72 #include <machine/cpu.h>
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 extern struct pcpu __pcpu[];
86 /* Temporary variables for init_secondary() */
87 char *doublefault_stack;
92 * Local data and functions.
95 static int start_ap(int apic_id);
97 static u_int bootMP_size;
98 static u_int boot_address;
101 * Calculate usable address in base memory for AP trampoline code.
104 mp_bootaddress(u_int basemem)
107 bootMP_size = mptramp_end - mptramp_start;
108 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
109 if (((basemem * 1024) - boot_address) < bootMP_size)
110 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
111 /* 3 levels of page table pages */
112 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
114 return mptramp_pagetables;
118 * Initialize the IPI handlers and start up the AP's.
125 /* Initialize the logical ID to APIC ID table. */
126 for (i = 0; i < MAXCPU; i++) {
127 cpu_apic_ids[i] = -1;
128 cpu_ipi_pending[i] = 0;
131 /* Install an inter-CPU IPI for TLB invalidation */
132 if (pmap_pcid_enabled) {
134 setidt(IPI_INVLTLB, pti ?
135 IDTVEC(invltlb_invpcid_pti_pti) :
136 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
138 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
139 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
140 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
141 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
143 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
144 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
145 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
146 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
147 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
148 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
151 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
152 SDT_SYSIGT, SEL_KPL, 0);
153 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
154 SDT_SYSIGT, SEL_KPL, 0);
155 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
156 SDT_SYSIGT, SEL_KPL, 0);
159 /* Install an inter-CPU IPI for cache invalidation. */
160 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
161 SDT_SYSIGT, SEL_KPL, 0);
163 /* Install an inter-CPU IPI for all-CPU rendezvous */
164 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
165 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
167 /* Install generic inter-CPU IPI handler */
168 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
169 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
171 /* Install an inter-CPU IPI for CPU stop/restart */
172 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
173 SDT_SYSIGT, SEL_KPL, 0);
175 /* Install an inter-CPU IPI for CPU suspend/resume */
176 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
177 SDT_SYSIGT, SEL_KPL, 0);
179 /* Set boot_cpu_id if needed. */
180 if (boot_cpu_id == -1) {
181 boot_cpu_id = PCPU_GET(apic_id);
182 cpu_info[boot_cpu_id].cpu_bsp = 1;
184 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
185 ("BSP's APIC ID doesn't match boot_cpu_id"));
187 /* Probe logical/physical core configuration. */
192 /* Start each Application Processor */
193 init_ops.start_all_aps();
195 set_interrupt_apic_ids();
200 * AP CPU's call this to initialize themselves.
208 int cpu, gsel_tss, x;
209 struct region_descriptor ap_gdt;
211 /* Set by the startup code for us to use */
215 common_tss[cpu] = common_tss[0];
216 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
218 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
220 /* The NMI stack runs on IST2. */
221 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
222 common_tss[cpu].tss_ist2 = (long) np;
224 /* The MC# stack runs on IST3. */
225 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
226 common_tss[cpu].tss_ist3 = (long) np;
228 /* Prepare private GDT */
229 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
230 for (x = 0; x < NGDT; x++) {
231 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
232 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
233 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
235 ssdtosyssd(&gdt_segs[GPROC0_SEL],
236 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
237 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
238 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
239 lgdt(&ap_gdt); /* does magic intra-segment return */
241 /* Get per-cpu data */
244 /* prime data page for it to use */
245 pcpu_init(pc, cpu, sizeof(struct pcpu));
246 dpcpu_init(dpcpu, cpu);
247 pc->pc_apic_id = cpu_apic_ids[cpu];
248 pc->pc_prvspace = pc;
249 pc->pc_curthread = 0;
250 pc->pc_tssp = &common_tss[cpu];
251 pc->pc_commontssp = &common_tss[cpu];
253 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
255 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
256 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
257 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
259 pc->pc_curpmap = kernel_pmap;
261 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
262 common_tss[cpu].tss_rsp0 = pti ? ((vm_offset_t)&pc->pc_pti_stack +
263 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful : 0;
265 /* Save the per-cpu pointer for use by the NMI handler. */
266 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
267 np->np_pcpu = (register_t) pc;
269 /* Save the per-cpu pointer for use by the MC# handler. */
270 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
271 np->np_pcpu = (register_t) pc;
273 wrmsr(MSR_FSBASE, 0); /* User value */
274 wrmsr(MSR_GSBASE, (u_int64_t)pc);
275 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
280 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
284 * Set to a known state:
285 * Set by mpboot.s: CR0_PG, CR0_PE
286 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
289 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
292 amd64_conf_fast_syscall();
294 /* signal our startup to the BSP. */
297 /* Spin until the BSP releases the AP's. */
298 while (atomic_load_acq_int(&aps_ready) == 0)
301 init_secondary_tail();
304 /*******************************************************************
305 * local functions and data
309 * start each AP in our list
312 native_start_all_aps(void)
314 vm_offset_t va = boot_address + KERNBASE;
315 u_int64_t *pt4, *pt3, *pt2;
316 u_int32_t mpbioswarmvec;
320 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
322 /* install the AP 1st level boot code */
323 pmap_kenter(va, boot_address);
324 pmap_invalidate_page(kernel_pmap, va);
325 bcopy(mptramp_start, (void *)va, bootMP_size);
327 /* Locate the page tables, they'll be below the trampoline */
328 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
329 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
330 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
332 /* Create the initial 1GB replicated page tables */
333 for (i = 0; i < 512; i++) {
334 /* Each slot of the level 4 pages points to the same level 3 page */
335 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
336 pt4[i] |= PG_V | PG_RW | PG_U;
338 /* Each slot of the level 3 pages points to the same level 2 page */
339 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
340 pt3[i] |= PG_V | PG_RW | PG_U;
342 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
343 pt2[i] = i * (2 * 1024 * 1024);
344 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
347 /* save the current value of the warm-start vector */
348 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
349 outb(CMOS_REG, BIOS_RESET);
350 mpbiosreason = inb(CMOS_DATA);
352 /* setup a vector to our boot code */
353 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
354 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
355 outb(CMOS_REG, BIOS_RESET);
356 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
359 for (cpu = 1; cpu < mp_ncpus; cpu++) {
360 apic_id = cpu_apic_ids[cpu];
362 /* allocate and set up an idle stack data page */
363 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
364 kstack_pages * PAGE_SIZE, M_WAITOK | M_ZERO);
365 doublefault_stack = (char *)kmem_malloc(kernel_arena,
366 PAGE_SIZE, M_WAITOK | M_ZERO);
367 mce_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
369 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
371 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
374 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
377 /* attempt to start the Application Processor */
378 if (!start_ap(apic_id)) {
379 /* restore the warmstart vector */
380 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
381 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
384 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
387 /* restore the warmstart vector */
388 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
390 outb(CMOS_REG, BIOS_RESET);
391 outb(CMOS_DATA, mpbiosreason);
393 /* number of APs actually started */
399 * This function starts the AP (application processor) identified
400 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
401 * to accomplish this. This is necessary because of the nuances
402 * of the different hardware we might encounter. It isn't pretty,
403 * but it seems to work.
406 start_ap(int apic_id)
411 /* calculate the vector */
412 vector = (boot_address >> 12) & 0xff;
414 /* used as a watchpoint to signal AP startup */
417 ipi_startup(apic_id, vector);
419 /* Wait up to 5 seconds for it to start. */
420 for (ms = 0; ms < 5000; ms++) {
422 return 1; /* return SUCCESS */
425 return 0; /* return FAILURE */
429 invltlb_invpcid_handler(void)
431 struct invpcid_descr d;
434 #ifdef COUNT_XINVLTLB_HITS
435 xhits_gbl[PCPU_GET(cpuid)]++;
436 #endif /* COUNT_XINVLTLB_HITS */
438 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
439 #endif /* COUNT_IPIS */
441 generation = smp_tlb_generation;
442 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
445 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
447 PCPU_SET(smp_tlb_done, generation);
451 invltlb_invpcid_pti_handler(void)
453 struct invpcid_descr d;
456 #ifdef COUNT_XINVLTLB_HITS
457 xhits_gbl[PCPU_GET(cpuid)]++;
458 #endif /* COUNT_XINVLTLB_HITS */
460 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
461 #endif /* COUNT_IPIS */
463 generation = smp_tlb_generation;
464 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
467 if (smp_tlb_pmap == kernel_pmap) {
469 * This invalidation actually needs to clear kernel
470 * mappings from the TLB in the current pmap, but
471 * since we were asked for the flush in the kernel
472 * pmap, achieve it by performing global flush.
474 invpcid(&d, INVPCID_CTXGLOB);
476 invpcid(&d, INVPCID_CTX);
477 d.pcid |= PMAP_PCID_USER_PT;
478 invpcid(&d, INVPCID_CTX);
480 PCPU_SET(smp_tlb_done, generation);
484 invltlb_pcid_handler(void)
487 uint32_t generation, pcid;
489 #ifdef COUNT_XINVLTLB_HITS
490 xhits_gbl[PCPU_GET(cpuid)]++;
491 #endif /* COUNT_XINVLTLB_HITS */
493 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
494 #endif /* COUNT_IPIS */
496 generation = smp_tlb_generation; /* Overlap with serialization */
497 if (smp_tlb_pmap == kernel_pmap) {
501 * The current pmap might not be equal to
502 * smp_tlb_pmap. The clearing of the pm_gen in
503 * pmap_invalidate_all() takes care of TLB
504 * invalidation when switching to the pmap on this
507 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
508 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
509 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
510 ucr3 = smp_tlb_pmap->pm_ucr3;
511 if (ucr3 != PMAP_NO_CR3) {
512 ucr3 |= PMAP_PCID_USER_PT | pcid;
513 pmap_pti_pcid_invalidate(ucr3, kcr3);
518 PCPU_SET(smp_tlb_done, generation);
522 invlpg_invpcid_handler(void)
524 struct invpcid_descr d;
527 #ifdef COUNT_XINVLTLB_HITS
528 xhits_pg[PCPU_GET(cpuid)]++;
529 #endif /* COUNT_XINVLTLB_HITS */
531 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
532 #endif /* COUNT_IPIS */
534 generation = smp_tlb_generation; /* Overlap with serialization */
535 invlpg(smp_tlb_addr1);
536 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
537 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
540 d.addr = smp_tlb_addr1;
541 invpcid(&d, INVPCID_ADDR);
543 PCPU_SET(smp_tlb_done, generation);
547 invlpg_pcid_handler(void)
553 #ifdef COUNT_XINVLTLB_HITS
554 xhits_pg[PCPU_GET(cpuid)]++;
555 #endif /* COUNT_XINVLTLB_HITS */
557 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
558 #endif /* COUNT_IPIS */
560 generation = smp_tlb_generation; /* Overlap with serialization */
561 invlpg(smp_tlb_addr1);
562 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
563 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
564 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
565 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
566 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
567 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
569 PCPU_SET(smp_tlb_done, generation);
573 invlrng_invpcid_handler(void)
575 struct invpcid_descr d;
576 vm_offset_t addr, addr2;
579 #ifdef COUNT_XINVLTLB_HITS
580 xhits_rng[PCPU_GET(cpuid)]++;
581 #endif /* COUNT_XINVLTLB_HITS */
583 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
584 #endif /* COUNT_IPIS */
586 addr = smp_tlb_addr1;
587 addr2 = smp_tlb_addr2;
588 generation = smp_tlb_generation; /* Overlap with serialization */
592 } while (addr < addr2);
593 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
594 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
597 d.addr = smp_tlb_addr1;
599 invpcid(&d, INVPCID_ADDR);
601 } while (d.addr < addr2);
603 PCPU_SET(smp_tlb_done, generation);
607 invlrng_pcid_handler(void)
609 vm_offset_t addr, addr2;
614 #ifdef COUNT_XINVLTLB_HITS
615 xhits_rng[PCPU_GET(cpuid)]++;
616 #endif /* COUNT_XINVLTLB_HITS */
618 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
619 #endif /* COUNT_IPIS */
621 addr = smp_tlb_addr1;
622 addr2 = smp_tlb_addr2;
623 generation = smp_tlb_generation; /* Overlap with serialization */
627 } while (addr < addr2);
628 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
629 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
630 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
631 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
632 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
633 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
635 PCPU_SET(smp_tlb_done, generation);