2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
33 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
42 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/memrange.h>
47 #include <sys/mutex.h>
50 #include <sys/sched.h>
52 #include <sys/sysctl.h>
55 #include <vm/vm_param.h>
57 #include <vm/vm_kern.h>
58 #include <vm/vm_extern.h>
60 #include <machine/apicreg.h>
61 #include <machine/clock.h>
62 #include <machine/cputypes.h>
63 #include <machine/cpufunc.h>
64 #include <machine/mca.h>
65 #include <machine/md_var.h>
66 #include <machine/mp_watchdog.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 /* lock region used by kernel profiling */
85 int mp_naps; /* # of Applications processors */
86 int boot_cpu_id = -1; /* designated BSP */
88 extern struct pcpu __pcpu[];
90 /* AP uses this during bootstrap. Do not staticize. */
94 /* Free these after use */
95 void *bootstacks[MAXCPU];
97 /* Temporary variables for init_secondary() */
98 char *doublefault_stack;
102 struct pcb stoppcbs[MAXCPU];
103 struct pcb **susppcbs = NULL;
105 /* Variables needed for SMP tlb shootdown. */
106 vm_offset_t smp_tlb_addr1;
107 vm_offset_t smp_tlb_addr2;
108 volatile int smp_tlb_wait;
111 /* Interrupt counts. */
112 static u_long *ipi_preempt_counts[MAXCPU];
113 static u_long *ipi_ast_counts[MAXCPU];
114 u_long *ipi_invltlb_counts[MAXCPU];
115 u_long *ipi_invlrng_counts[MAXCPU];
116 u_long *ipi_invlpg_counts[MAXCPU];
117 u_long *ipi_invlcache_counts[MAXCPU];
118 u_long *ipi_rendezvous_counts[MAXCPU];
119 u_long *ipi_lazypmap_counts[MAXCPU];
120 static u_long *ipi_hardclock_counts[MAXCPU];
121 static u_long *ipi_statclock_counts[MAXCPU];
124 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
127 * Local data and functions.
130 static cpumask_t logical_cpus;
131 static volatile cpumask_t ipi_nmi_pending;
133 /* used to hold the AP's until we are ready to release them */
134 static struct mtx ap_boot_mtx;
136 /* Set to 1 once we're ready to let the APs out of the pen. */
137 static volatile int aps_ready = 0;
140 * Store data from cpu_add() until later in the boot when we actually setup
147 int cpu_hyperthread:1;
148 } static cpu_info[MAX_APIC_ID + 1];
149 int cpu_apic_ids[MAXCPU];
150 int apic_cpuids[MAX_APIC_ID + 1];
152 /* Holds pending bitmap based IPIs per CPU */
153 static volatile u_int cpu_ipi_pending[MAXCPU];
155 static u_int boot_address;
156 static int cpu_logical;
157 static int cpu_cores;
159 static void assign_cpu_ids(void);
160 static void set_interrupt_apic_ids(void);
161 static int start_all_aps(void);
162 static int start_ap(int apic_id);
163 static void release_aps(void *dummy);
165 static cpumask_t hlt_logical_cpus;
166 static cpumask_t hyperthreading_cpus;
167 static cpumask_t hyperthreading_cpus_mask;
168 static int hyperthreading_allowed = 1;
169 static struct sysctl_ctx_list logical_cpu_clist;
170 static u_int bootMP_size;
173 mem_range_AP_init(void)
175 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
176 mem_range_softc.mr_op->initAP(&mem_range_softc);
190 /* We only support two levels for now. */
191 for (i = 0; i < 3; i++) {
192 cpuid_count(0x0B, i, p);
194 logical = p[1] &= 0xffff;
195 type = (p[2] >> 8) & 0xff;
196 if (type == 0 || logical == 0)
198 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
199 if (!cpu_info[x].cpu_present ||
200 cpu_info[x].cpu_disabled)
202 if (x >> bits == boot_cpu_id >> bits)
205 if (type == CPUID_TYPE_SMT)
207 else if (type == CPUID_TYPE_CORE)
210 if (cpu_logical == 0)
212 cpu_cores /= cpu_logical;
218 u_int threads_per_cache, p[4];
224 * If this CPU supports HTT or CMP then mention the
225 * number of physical/logical cores it contains.
227 if (cpu_feature & CPUID_HTT)
228 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
229 if (cpu_vendor_id == CPU_VENDOR_AMD && (amd_feature2 & AMDID2_CMP))
230 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
231 else if (cpu_vendor_id == CPU_VENDOR_INTEL && (cpu_high >= 4)) {
232 cpuid_count(4, 0, p);
233 if ((p[0] & 0x1f) != 0)
234 cmp = ((p[0] >> 26) & 0x3f) + 1;
237 cpu_logical = htt / cmp;
239 /* Setup the initial logical CPUs info. */
240 if (cpu_feature & CPUID_HTT)
241 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
244 * Work out if hyperthreading is *really* enabled. This
245 * is made really ugly by the fact that processors lie: Dual
246 * core processors claim to be hyperthreaded even when they're
247 * not, presumably because they want to be treated the same
248 * way as HTT with respect to per-cpu software licensing.
249 * At the time of writing (May 12, 2005) the only hyperthreaded
250 * cpus are from Intel, and Intel's dual-core processors can be
251 * identified via the "deterministic cache parameters" cpuid
255 * First determine if this is an Intel processor which claims
256 * to have hyperthreading support.
258 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
260 * If the "deterministic cache parameters" cpuid calls
261 * are available, use them.
264 /* Ask the processor about the L1 cache. */
265 for (i = 0; i < 1; i++) {
266 cpuid_count(4, i, p);
267 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
268 if (hyperthreading_cpus < threads_per_cache)
269 hyperthreading_cpus = threads_per_cache;
270 if ((p[0] & 0x1f) == 0)
276 * If the deterministic cache parameters are not
277 * available, or if no caches were reported to exist,
278 * just accept what the HTT flag indicated.
280 if (hyperthreading_cpus == 0)
281 hyperthreading_cpus = logical_cpus;
288 static int cpu_topo_probed = 0;
293 logical_cpus = logical_cpus_mask = 0;
299 cpu_cores = mp_ncpus > 0 ? mp_ncpus : 1;
300 if (cpu_logical == 0)
311 * Determine whether any threading flags are
315 if (cpu_logical > 1 && hyperthreading_cpus)
316 cg_flags = CG_FLAG_HTT;
317 else if (cpu_logical > 1)
318 cg_flags = CG_FLAG_SMT;
321 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
322 printf("WARNING: Non-uniform processors.\n");
323 printf("WARNING: Using suboptimal topology.\n");
324 return (smp_topo_none());
327 * No multi-core or hyper-threaded.
329 if (cpu_logical * cpu_cores == 1)
330 return (smp_topo_none());
332 * Only HTT no multi-core.
334 if (cpu_logical > 1 && cpu_cores == 1)
335 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
337 * Only multi-core no HTT.
339 if (cpu_cores > 1 && cpu_logical == 1)
340 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
342 * Both HTT and multi-core.
344 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
345 CG_SHARE_L1, cpu_logical, cg_flags));
349 * Calculate usable address in base memory for AP trampoline code.
352 mp_bootaddress(u_int basemem)
355 bootMP_size = mptramp_end - mptramp_start;
356 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
357 if (((basemem * 1024) - boot_address) < bootMP_size)
358 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
359 /* 3 levels of page table pages */
360 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
362 return mptramp_pagetables;
366 cpu_add(u_int apic_id, char boot_cpu)
369 if (apic_id > MAX_APIC_ID) {
370 panic("SMP: APIC ID %d too high", apic_id);
373 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
375 cpu_info[apic_id].cpu_present = 1;
377 KASSERT(boot_cpu_id == -1,
378 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
380 boot_cpu_id = apic_id;
381 cpu_info[apic_id].cpu_bsp = 1;
383 if (mp_ncpus < MAXCPU) {
385 mp_maxid = mp_ncpus -1;
388 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
393 cpu_mp_setmaxid(void)
397 * mp_maxid should be already set by calls to cpu_add().
398 * Just sanity check its value here.
401 KASSERT(mp_maxid == 0,
402 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
403 else if (mp_ncpus == 1)
406 KASSERT(mp_maxid >= mp_ncpus - 1,
407 ("%s: counters out of sync: max %d, count %d", __func__,
408 mp_maxid, mp_ncpus));
416 * Always record BSP in CPU map so that the mbuf init code works
422 * No CPUs were found, so this must be a UP system. Setup
423 * the variables to represent a system with a single CPU
430 /* At least one CPU was found. */
433 * One CPU was found, so this must be a UP system with
440 /* At least two CPUs were found. */
445 * Initialize the IPI handlers and start up the AP's.
452 /* Initialize the logical ID to APIC ID table. */
453 for (i = 0; i < MAXCPU; i++) {
454 cpu_apic_ids[i] = -1;
455 cpu_ipi_pending[i] = 0;
458 /* Install an inter-CPU IPI for TLB invalidation */
459 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
460 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
461 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
463 /* Install an inter-CPU IPI for cache invalidation. */
464 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
466 /* Install an inter-CPU IPI for all-CPU rendezvous */
467 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
469 /* Install generic inter-CPU IPI handler */
470 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
471 SDT_SYSIGT, SEL_KPL, 0);
473 /* Install an inter-CPU IPI for CPU stop/restart */
474 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
476 /* Install an inter-CPU IPI for CPU suspend/resume */
477 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
479 /* Set boot_cpu_id if needed. */
480 if (boot_cpu_id == -1) {
481 boot_cpu_id = PCPU_GET(apic_id);
482 cpu_info[boot_cpu_id].cpu_bsp = 1;
484 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
485 ("BSP's APIC ID doesn't match boot_cpu_id"));
487 /* Probe logical/physical core configuration. */
492 /* Start each Application Processor */
495 set_interrupt_apic_ids();
500 * Print various information about the SMP system hardware and setup.
503 cpu_mp_announce(void)
505 const char *hyperthread;
508 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
509 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
510 if (hyperthreading_cpus > 1)
511 printf(" x %d HTT threads", cpu_logical);
512 else if (cpu_logical > 1)
513 printf(" x %d SMT threads", cpu_logical);
516 /* List active CPUs first. */
517 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
518 for (i = 1; i < mp_ncpus; i++) {
519 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
523 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
527 /* List disabled CPUs last. */
528 for (i = 0; i <= MAX_APIC_ID; i++) {
529 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
531 if (cpu_info[i].cpu_hyperthread)
535 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
541 * AP CPU's call this to initialize themselves.
549 int cpu, gsel_tss, x;
550 struct region_descriptor ap_gdt;
552 /* Set by the startup code for us to use */
556 common_tss[cpu] = common_tss[0];
557 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
558 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
560 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
562 /* The NMI stack runs on IST2. */
563 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
564 common_tss[cpu].tss_ist2 = (long) np;
566 /* Prepare private GDT */
567 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
568 for (x = 0; x < NGDT; x++) {
569 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
570 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
571 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
573 ssdtosyssd(&gdt_segs[GPROC0_SEL],
574 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
575 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
576 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
577 lgdt(&ap_gdt); /* does magic intra-segment return */
579 /* Get per-cpu data */
582 /* prime data page for it to use */
583 pcpu_init(pc, cpu, sizeof(struct pcpu));
584 dpcpu_init(dpcpu, cpu);
585 pc->pc_apic_id = cpu_apic_ids[cpu];
586 pc->pc_prvspace = pc;
587 pc->pc_curthread = 0;
588 pc->pc_tssp = &common_tss[cpu];
589 pc->pc_commontssp = &common_tss[cpu];
591 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
593 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
594 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
595 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
598 /* Save the per-cpu pointer for use by the NMI handler. */
599 np->np_pcpu = (register_t) pc;
601 wrmsr(MSR_FSBASE, 0); /* User value */
602 wrmsr(MSR_GSBASE, (u_int64_t)pc);
603 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
607 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
611 * Set to a known state:
612 * Set by mpboot.s: CR0_PG, CR0_PE
613 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
616 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
619 /* Set up the fast syscall stuff */
620 msr = rdmsr(MSR_EFER) | EFER_SCE;
621 wrmsr(MSR_EFER, msr);
622 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
623 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
624 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
625 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
626 wrmsr(MSR_STAR, msr);
627 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
629 /* Disable local APIC just to be sure. */
632 /* signal our startup to the BSP. */
635 /* Spin until the BSP releases the AP's. */
639 /* Initialize the PAT MSR. */
642 /* set up CPU registers and state */
645 /* set up SSE/NX registers */
648 /* set up FPU state on the AP */
651 /* A quick check from sanity claus */
652 if (PCPU_GET(apic_id) != lapic_id()) {
653 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
654 printf("SMP: actual apic_id = %d\n", lapic_id());
655 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
656 panic("cpuid mismatch! boom!!");
659 /* Initialize curthread. */
660 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
661 PCPU_SET(curthread, PCPU_GET(idlethread));
665 mtx_lock_spin(&ap_boot_mtx);
667 /* Init local apic for irq's */
670 /* Set memory range attributes for this CPU to match the BSP */
675 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
676 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
678 /* Determine if we are a logical CPU. */
679 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
680 logical_cpus_mask |= PCPU_GET(cpumask);
682 /* Determine if we are a hyperthread. */
683 if (hyperthreading_cpus > 1 &&
684 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
685 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
687 /* Build our map of 'other' CPUs. */
688 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
693 if (smp_cpus == mp_ncpus) {
694 /* enable IPI's, tlb shootdown, freezes etc */
695 atomic_store_rel_int(&smp_started, 1);
696 smp_active = 1; /* historic */
700 * Enable global pages TLB extension
701 * This also implicitly flushes the TLB
704 load_cr4(rcr4() | CR4_PGE);
708 mtx_unlock_spin(&ap_boot_mtx);
710 /* Wait until all the AP's are up. */
711 while (smp_started == 0)
714 /* Start per-CPU event timers. */
719 panic("scheduler returned us to %s", __func__);
723 /*******************************************************************
724 * local functions and data
728 * We tell the I/O APIC code about all the CPUs we want to receive
729 * interrupts. If we don't want certain CPUs to receive IRQs we
730 * can simply not tell the I/O APIC code about them in this function.
731 * We also do not tell it about the BSP since it tells itself about
732 * the BSP internally to work with UP kernels and on UP machines.
735 set_interrupt_apic_ids(void)
739 for (i = 0; i < MAXCPU; i++) {
740 apic_id = cpu_apic_ids[i];
743 if (cpu_info[apic_id].cpu_bsp)
745 if (cpu_info[apic_id].cpu_disabled)
748 /* Don't let hyperthreads service interrupts. */
749 if (hyperthreading_cpus > 1 &&
750 apic_id % hyperthreading_cpus != 0)
758 * Assign logical CPU IDs to local APICs.
765 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
766 &hyperthreading_allowed);
768 /* Check for explicitly disabled CPUs. */
769 for (i = 0; i <= MAX_APIC_ID; i++) {
770 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
773 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
774 cpu_info[i].cpu_hyperthread = 1;
775 #if defined(SCHED_ULE)
777 * Don't use HT CPU if it has been disabled by a
780 if (hyperthreading_allowed == 0) {
781 cpu_info[i].cpu_disabled = 1;
787 /* Don't use this CPU if it has been disabled by a tunable. */
788 if (resource_disabled("lapic", i)) {
789 cpu_info[i].cpu_disabled = 1;
795 * Assign CPU IDs to local APIC IDs and disable any CPUs
796 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
798 * To minimize confusion for userland, we attempt to number
799 * CPUs such that all threads and cores in a package are
800 * grouped together. For now we assume that the BSP is always
801 * the first thread in a package and just start adding APs
802 * starting with the BSP's APIC ID.
805 cpu_apic_ids[0] = boot_cpu_id;
806 apic_cpuids[boot_cpu_id] = 0;
807 for (i = boot_cpu_id + 1; i != boot_cpu_id;
808 i == MAX_APIC_ID ? i = 0 : i++) {
809 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
810 cpu_info[i].cpu_disabled)
813 if (mp_ncpus < MAXCPU) {
814 cpu_apic_ids[mp_ncpus] = i;
815 apic_cpuids[i] = mp_ncpus;
818 cpu_info[i].cpu_disabled = 1;
820 KASSERT(mp_maxid >= mp_ncpus - 1,
821 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
826 * start each AP in our list
831 vm_offset_t va = boot_address + KERNBASE;
832 u_int64_t *pt4, *pt3, *pt2;
833 u_int32_t mpbioswarmvec;
837 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
839 /* install the AP 1st level boot code */
840 pmap_kenter(va, boot_address);
841 pmap_invalidate_page(kernel_pmap, va);
842 bcopy(mptramp_start, (void *)va, bootMP_size);
844 /* Locate the page tables, they'll be below the trampoline */
845 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
846 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
847 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
849 /* Create the initial 1GB replicated page tables */
850 for (i = 0; i < 512; i++) {
851 /* Each slot of the level 4 pages points to the same level 3 page */
852 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
853 pt4[i] |= PG_V | PG_RW | PG_U;
855 /* Each slot of the level 3 pages points to the same level 2 page */
856 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
857 pt3[i] |= PG_V | PG_RW | PG_U;
859 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
860 pt2[i] = i * (2 * 1024 * 1024);
861 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
864 /* save the current value of the warm-start vector */
865 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
866 outb(CMOS_REG, BIOS_RESET);
867 mpbiosreason = inb(CMOS_DATA);
869 /* setup a vector to our boot code */
870 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
871 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
872 outb(CMOS_REG, BIOS_RESET);
873 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
876 for (cpu = 1; cpu < mp_ncpus; cpu++) {
877 apic_id = cpu_apic_ids[cpu];
879 /* allocate and set up an idle stack data page */
880 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
881 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
882 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
883 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
885 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
888 /* attempt to start the Application Processor */
889 if (!start_ap(apic_id)) {
890 /* restore the warmstart vector */
891 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
892 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
895 all_cpus |= (1 << cpu); /* record AP in CPU map */
898 /* build our map of 'other' CPUs */
899 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
901 /* restore the warmstart vector */
902 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
904 outb(CMOS_REG, BIOS_RESET);
905 outb(CMOS_DATA, mpbiosreason);
907 /* number of APs actually started */
913 * This function starts the AP (application processor) identified
914 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
915 * to accomplish this. This is necessary because of the nuances
916 * of the different hardware we might encounter. It isn't pretty,
917 * but it seems to work.
920 start_ap(int apic_id)
925 /* calculate the vector */
926 vector = (boot_address >> 12) & 0xff;
928 /* used as a watchpoint to signal AP startup */
932 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
933 * and running the target CPU. OR this INIT IPI might be latched (P5
934 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
938 /* do an INIT IPI: assert RESET */
939 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
940 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
942 /* wait for pending status end */
945 /* do an INIT IPI: deassert RESET */
946 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
947 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
949 /* wait for pending status end */
950 DELAY(10000); /* wait ~10mS */
954 * next we do a STARTUP IPI: the previous INIT IPI might still be
955 * latched, (P5 bug) this 1st STARTUP would then terminate
956 * immediately, and the previously started INIT IPI would continue. OR
957 * the previous INIT IPI has already run. and this STARTUP IPI will
958 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
962 /* do a STARTUP IPI */
963 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
964 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
967 DELAY(200); /* wait ~200uS */
970 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
971 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
972 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
973 * recognized after hardware RESET or INIT IPI.
976 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
977 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
980 DELAY(200); /* wait ~200uS */
982 /* Wait up to 5 seconds for it to start. */
983 for (ms = 0; ms < 5000; ms++) {
985 return 1; /* return SUCCESS */
988 return 0; /* return FAILURE */
991 #ifdef COUNT_XINVLTLB_HITS
992 u_int xhits_gbl[MAXCPU];
993 u_int xhits_pg[MAXCPU];
994 u_int xhits_rng[MAXCPU];
995 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
996 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
997 sizeof(xhits_gbl), "IU", "");
998 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
999 sizeof(xhits_pg), "IU", "");
1000 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1001 sizeof(xhits_rng), "IU", "");
1006 u_int ipi_range_size;
1007 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1008 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1009 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1010 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1013 u_int ipi_masked_global;
1014 u_int ipi_masked_page;
1015 u_int ipi_masked_range;
1016 u_int ipi_masked_range_size;
1017 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1018 &ipi_masked_global, 0, "");
1019 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1020 &ipi_masked_page, 0, "");
1021 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1022 &ipi_masked_range, 0, "");
1023 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1024 &ipi_masked_range_size, 0, "");
1025 #endif /* COUNT_XINVLTLB_HITS */
1028 * Flush the TLB on all other CPU's
1031 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1035 ncpu = mp_ncpus - 1; /* does not shootdown self */
1037 return; /* no other cpus */
1038 if (!(read_rflags() & PSL_I))
1039 panic("%s: interrupts disabled", __func__);
1040 mtx_lock_spin(&smp_ipi_mtx);
1041 smp_tlb_addr1 = addr1;
1042 smp_tlb_addr2 = addr2;
1043 atomic_store_rel_int(&smp_tlb_wait, 0);
1044 ipi_all_but_self(vector);
1045 while (smp_tlb_wait < ncpu)
1047 mtx_unlock_spin(&smp_ipi_mtx);
1051 smp_targeted_tlb_shootdown(cpumask_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1053 int ncpu, othercpus;
1055 othercpus = mp_ncpus - 1;
1056 if (mask == (cpumask_t)-1) {
1061 mask &= ~PCPU_GET(cpumask);
1064 ncpu = bitcount32(mask);
1065 if (ncpu > othercpus) {
1066 /* XXX this should be a panic offence */
1067 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
1071 /* XXX should be a panic, implied by mask == 0 above */
1075 if (!(read_rflags() & PSL_I))
1076 panic("%s: interrupts disabled", __func__);
1077 mtx_lock_spin(&smp_ipi_mtx);
1078 smp_tlb_addr1 = addr1;
1079 smp_tlb_addr2 = addr2;
1080 atomic_store_rel_int(&smp_tlb_wait, 0);
1081 if (mask == (cpumask_t)-1)
1082 ipi_all_but_self(vector);
1084 ipi_selected(mask, vector);
1085 while (smp_tlb_wait < ncpu)
1087 mtx_unlock_spin(&smp_ipi_mtx);
1091 * Send an IPI to specified CPU handling the bitmap logic.
1094 ipi_send_cpu(int cpu, u_int ipi)
1096 u_int bitmap, old_pending, new_pending;
1098 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1100 if (IPI_IS_BITMAPED(ipi)) {
1102 ipi = IPI_BITMAP_VECTOR;
1104 old_pending = cpu_ipi_pending[cpu];
1105 new_pending = old_pending | bitmap;
1106 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1107 old_pending, new_pending));
1111 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1115 smp_cache_flush(void)
1119 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1127 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1128 #ifdef COUNT_XINVLTLB_HITS
1135 smp_invlpg(vm_offset_t addr)
1139 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1140 #ifdef COUNT_XINVLTLB_HITS
1147 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1151 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1152 #ifdef COUNT_XINVLTLB_HITS
1154 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1160 smp_masked_invltlb(cpumask_t mask)
1164 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1165 #ifdef COUNT_XINVLTLB_HITS
1166 ipi_masked_global++;
1172 smp_masked_invlpg(cpumask_t mask, vm_offset_t addr)
1176 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1177 #ifdef COUNT_XINVLTLB_HITS
1184 smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2)
1188 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1189 #ifdef COUNT_XINVLTLB_HITS
1191 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1197 ipi_bitmap_handler(struct trapframe frame)
1199 int cpu = PCPU_GET(cpuid);
1202 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1204 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1206 (*ipi_preempt_counts[cpu])++;
1208 sched_preempt(curthread);
1210 if (ipi_bitmap & (1 << IPI_AST)) {
1212 (*ipi_ast_counts[cpu])++;
1214 /* Nothing to do for AST */
1216 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1218 (*ipi_hardclock_counts[cpu])++;
1220 hardclockintr(&frame);
1222 if (ipi_bitmap & (1 << IPI_STATCLOCK)) {
1224 (*ipi_statclock_counts[cpu])++;
1226 statclockintr(&frame);
1231 * send an IPI to a set of cpus.
1234 ipi_selected(cpumask_t cpus, u_int ipi)
1239 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1240 * of help in order to understand what is the source.
1241 * Set the mask of receiving CPUs for this purpose.
1243 if (ipi == IPI_STOP_HARD)
1244 atomic_set_int(&ipi_nmi_pending, cpus);
1246 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
1247 while ((cpu = ffs(cpus)) != 0) {
1249 cpus &= ~(1 << cpu);
1250 ipi_send_cpu(cpu, ipi);
1255 * send an IPI to a specific CPU.
1258 ipi_cpu(int cpu, u_int ipi)
1262 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1263 * of help in order to understand what is the source.
1264 * Set the mask of receiving CPUs for this purpose.
1266 if (ipi == IPI_STOP_HARD)
1267 atomic_set_int(&ipi_nmi_pending, 1 << cpu);
1269 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1270 ipi_send_cpu(cpu, ipi);
1274 * send an IPI to all CPUs EXCEPT myself
1277 ipi_all_but_self(u_int ipi)
1280 if (IPI_IS_BITMAPED(ipi)) {
1281 ipi_selected(PCPU_GET(other_cpus), ipi);
1286 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1287 * of help in order to understand what is the source.
1288 * Set the mask of receiving CPUs for this purpose.
1290 if (ipi == IPI_STOP_HARD)
1291 atomic_set_int(&ipi_nmi_pending, PCPU_GET(other_cpus));
1293 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1294 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1303 * As long as there is not a simple way to know about a NMI's
1304 * source, if the bitmask for the current CPU is present in
1305 * the global pending bitword an IPI_STOP_HARD has been issued
1306 * and should be handled.
1308 cpumask = PCPU_GET(cpumask);
1309 if ((ipi_nmi_pending & cpumask) == 0)
1312 atomic_clear_int(&ipi_nmi_pending, cpumask);
1318 * Handle an IPI_STOP by saving our current context and spinning until we
1322 cpustop_handler(void)
1327 cpu = PCPU_GET(cpuid);
1328 cpumask = PCPU_GET(cpumask);
1330 savectx(&stoppcbs[cpu]);
1332 /* Indicate that we are stopped */
1333 atomic_set_int(&stopped_cpus, cpumask);
1335 /* Wait for restart */
1336 while (!(started_cpus & cpumask))
1339 atomic_clear_int(&started_cpus, cpumask);
1340 atomic_clear_int(&stopped_cpus, cpumask);
1342 if (cpu == 0 && cpustop_restartfunc != NULL) {
1343 cpustop_restartfunc();
1344 cpustop_restartfunc = NULL;
1349 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1353 cpususpend_handler(void)
1359 cpu = PCPU_GET(cpuid);
1360 cpumask = PCPU_GET(cpumask);
1362 rf = intr_disable();
1365 if (savectx(susppcbs[cpu])) {
1367 atomic_set_int(&stopped_cpus, cpumask);
1369 PCPU_SET(switchtime, cpu_ticks());
1370 PCPU_SET(switchticks, ticks);
1373 /* Wait for resume */
1374 while (!(started_cpus & cpumask))
1377 atomic_clear_int(&started_cpus, cpumask);
1378 atomic_clear_int(&stopped_cpus, cpumask);
1380 /* Restore CR3 and enable interrupts */
1388 * This is called once the rest of the system is up and running and we're
1389 * ready to let the AP's out of the pen.
1392 release_aps(void *dummy __unused)
1397 atomic_store_rel_int(&aps_ready, 1);
1398 while (smp_started == 0)
1401 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1404 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1409 mask = hlt_cpus_mask;
1410 error = sysctl_handle_int(oidp, &mask, 0, req);
1411 if (error || !req->newptr)
1414 if (logical_cpus_mask != 0 &&
1415 (mask & logical_cpus_mask) == logical_cpus_mask)
1416 hlt_logical_cpus = 1;
1418 hlt_logical_cpus = 0;
1420 if (! hyperthreading_allowed)
1421 mask |= hyperthreading_cpus_mask;
1423 if ((mask & all_cpus) == all_cpus)
1425 hlt_cpus_mask = mask;
1428 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1429 0, 0, sysctl_hlt_cpus, "IU",
1430 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1433 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1437 disable = hlt_logical_cpus;
1438 error = sysctl_handle_int(oidp, &disable, 0, req);
1439 if (error || !req->newptr)
1443 hlt_cpus_mask |= logical_cpus_mask;
1445 hlt_cpus_mask &= ~logical_cpus_mask;
1447 if (! hyperthreading_allowed)
1448 hlt_cpus_mask |= hyperthreading_cpus_mask;
1450 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1451 hlt_cpus_mask &= ~(1<<0);
1453 hlt_logical_cpus = disable;
1458 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1462 allowed = hyperthreading_allowed;
1463 error = sysctl_handle_int(oidp, &allowed, 0, req);
1464 if (error || !req->newptr)
1469 * SCHED_ULE doesn't allow enabling/disabling HT cores at
1472 if (allowed != hyperthreading_allowed)
1478 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1480 hlt_cpus_mask |= hyperthreading_cpus_mask;
1482 if (logical_cpus_mask != 0 &&
1483 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1484 hlt_logical_cpus = 1;
1486 hlt_logical_cpus = 0;
1488 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1489 hlt_cpus_mask &= ~(1<<0);
1491 hyperthreading_allowed = allowed;
1496 cpu_hlt_setup(void *dummy __unused)
1499 if (logical_cpus_mask != 0) {
1500 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1502 sysctl_ctx_init(&logical_cpu_clist);
1503 SYSCTL_ADD_PROC(&logical_cpu_clist,
1504 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1505 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1506 sysctl_hlt_logical_cpus, "IU", "");
1507 SYSCTL_ADD_UINT(&logical_cpu_clist,
1508 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1509 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1510 &logical_cpus_mask, 0, "");
1512 if (hlt_logical_cpus)
1513 hlt_cpus_mask |= logical_cpus_mask;
1516 * If necessary for security purposes, force
1517 * hyperthreading off, regardless of the value
1518 * of hlt_logical_cpus.
1520 if (hyperthreading_cpus_mask) {
1521 SYSCTL_ADD_PROC(&logical_cpu_clist,
1522 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1523 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1524 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1525 if (! hyperthreading_allowed)
1526 hlt_cpus_mask |= hyperthreading_cpus_mask;
1530 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1533 mp_grab_cpu_hlt(void)
1541 mask = PCPU_GET(cpumask);
1543 cpuid = PCPU_GET(cpuid);
1548 while (mask & hlt_cpus_mask) {
1550 __asm __volatile("sti; hlt" : : : "memory");
1557 * Setup interrupt counters for IPI handlers.
1560 mp_ipi_intrcnt(void *dummy)
1566 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1567 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1568 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1569 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1570 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1571 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1572 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1573 intrcnt_add(buf, &ipi_preempt_counts[i]);
1574 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1575 intrcnt_add(buf, &ipi_ast_counts[i]);
1576 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1577 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1578 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i);
1579 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
1580 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1581 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1582 snprintf(buf, sizeof(buf), "cpu%d:statclock", i);
1583 intrcnt_add(buf, &ipi_statclock_counts[i]);
1586 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);