2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
33 #include "opt_sched.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
41 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/memrange.h>
46 #include <sys/mutex.h>
50 #include <sys/sysctl.h>
53 #include <vm/vm_param.h>
55 #include <vm/vm_kern.h>
56 #include <vm/vm_extern.h>
58 #include <machine/apicreg.h>
59 #include <machine/clock.h>
60 #include <machine/md_var.h>
61 #include <machine/mp_watchdog.h>
62 #include <machine/pcb.h>
63 #include <machine/psl.h>
64 #include <machine/smp.h>
65 #include <machine/specialreg.h>
66 #include <machine/tss.h>
68 #define WARMBOOT_TARGET 0
69 #define WARMBOOT_OFF (KERNBASE + 0x0467)
70 #define WARMBOOT_SEG (KERNBASE + 0x0469)
72 #define CMOS_REG (0x70)
73 #define CMOS_DATA (0x71)
74 #define BIOS_RESET (0x0f)
75 #define BIOS_WARM (0x0a)
77 /* lock region used by kernel profiling */
80 int mp_naps; /* # of Applications processors */
81 int boot_cpu_id = -1; /* designated BSP */
85 * CPU topology map datastructures for HTT.
87 static struct cpu_group mp_groups[MAXCPU];
88 static struct cpu_top mp_top;
90 /* AP uses this during bootstrap. Do not staticize. */
94 /* Free these after use */
95 void *bootstacks[MAXCPU];
97 /* Temporary holder for double fault stack */
98 char *doublefault_stack;
100 /* Hotwire a 0->4MB V==P mapping */
101 extern pt_entry_t *KPTphys;
103 /* SMP page table page */
104 extern pt_entry_t *SMPpt;
106 struct pcb stoppcbs[MAXCPU];
108 /* Variables needed for SMP tlb shootdown. */
109 vm_offset_t smp_tlb_addr1;
110 vm_offset_t smp_tlb_addr2;
111 volatile int smp_tlb_wait;
113 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
116 volatile cpumask_t ipi_nmi_pending;
118 static void ipi_nmi_selected(u_int32_t cpus);
122 * Local data and functions.
127 * Provide an alternate method of stopping other CPUs. If another CPU has
128 * disabled interrupts the conventional STOP IPI will be blocked. This
129 * NMI-based stop should get through in that case.
131 static int stop_cpus_with_nmi = 1;
132 SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW,
133 &stop_cpus_with_nmi, 0, "");
134 TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi);
136 #define stop_cpus_with_nmi 0
139 static u_int logical_cpus;
141 /* used to hold the AP's until we are ready to release them */
142 static struct mtx ap_boot_mtx;
144 /* Set to 1 once we're ready to let the APs out of the pen. */
145 static volatile int aps_ready = 0;
148 * Store data from cpu_add() until later in the boot when we actually setup
155 } static cpu_info[MAXCPU];
156 static int cpu_apic_ids[MAXCPU];
158 /* Holds pending bitmap based IPIs per CPU */
159 static volatile u_int cpu_ipi_pending[MAXCPU];
161 static u_int boot_address;
163 static void set_logical_apic_ids(void);
164 static int start_all_aps(void);
165 static int start_ap(int apic_id);
166 static void release_aps(void *dummy);
168 static int hlt_logical_cpus;
169 static u_int hyperthreading_cpus;
170 static cpumask_t hyperthreading_cpus_mask;
171 static int hyperthreading_allowed = 1;
172 static struct sysctl_ctx_list logical_cpu_clist;
173 static u_int bootMP_size;
176 mem_range_AP_init(void)
178 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
179 mem_range_softc.mr_op->initAP(&mem_range_softc);
185 struct cpu_group *group;
191 /* Build the smp_topology map. */
192 /* Nothing to do if there is no HTT support. */
193 if ((cpu_feature & CPUID_HTT) == 0)
195 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
196 if (logical_cpus <= 1)
198 group = &mp_groups[0];
200 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) {
201 if (!cpu_info[apic_id].cpu_present)
204 * If the current group has members and we're not a logical
205 * cpu, create a new group.
207 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) {
212 group->cg_mask |= 1 << cpu;
216 mp_top.ct_count = groups;
217 mp_top.ct_group = mp_groups;
218 smp_topology = &mp_top;
222 * Calculate usable address in base memory for AP trampoline code.
225 mp_bootaddress(u_int basemem)
228 bootMP_size = mptramp_end - mptramp_start;
229 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
230 if (((basemem * 1024) - boot_address) < bootMP_size)
231 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
232 /* 3 levels of page table pages */
233 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
235 return mptramp_pagetables;
239 cpu_add(u_int apic_id, char boot_cpu)
242 if (apic_id >= MAXCPU) {
243 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n",
244 apic_id, MAXCPU - 1);
247 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
249 cpu_info[apic_id].cpu_present = 1;
251 KASSERT(boot_cpu_id == -1,
252 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
254 boot_cpu_id = apic_id;
255 cpu_info[apic_id].cpu_bsp = 1;
258 if (apic_id > mp_maxid)
261 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
267 cpu_mp_setmaxid(void)
271 * mp_maxid should be already set by calls to cpu_add().
272 * Just sanity check its value here.
275 KASSERT(mp_maxid == 0,
276 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
277 else if (mp_ncpus == 1)
280 KASSERT(mp_maxid >= mp_ncpus - 1,
281 ("%s: counters out of sync: max %d, count %d", __func__,
282 mp_maxid, mp_ncpus));
291 * Always record BSP in CPU map so that the mbuf init code works
297 * No CPUs were found, so this must be a UP system. Setup
298 * the variables to represent a system with a single CPU
305 /* At least one CPU was found. */
308 * One CPU was found, so this must be a UP system with
315 /* At least two CPUs were found. */
320 * Initialize the IPI handlers and start up the AP's.
326 u_int threads_per_cache, p[4];
328 /* Initialize the logical ID to APIC ID table. */
329 for (i = 0; i < MAXCPU; i++) {
330 cpu_apic_ids[i] = -1;
331 cpu_ipi_pending[i] = 0;
334 /* Install an inter-CPU IPI for TLB invalidation */
335 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
336 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
337 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
339 /* Install an inter-CPU IPI for all-CPU rendezvous */
340 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
342 /* Install generic inter-CPU IPI handler */
343 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
344 SDT_SYSIGT, SEL_KPL, 0);
346 /* Install an inter-CPU IPI for CPU stop/restart */
347 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
349 /* Set boot_cpu_id if needed. */
350 if (boot_cpu_id == -1) {
351 boot_cpu_id = PCPU_GET(apic_id);
352 cpu_info[boot_cpu_id].cpu_bsp = 1;
354 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
355 ("BSP's APIC ID doesn't match boot_cpu_id"));
356 cpu_apic_ids[0] = boot_cpu_id;
358 /* Start each Application Processor */
361 /* Setup the initial logical CPUs info. */
362 logical_cpus = logical_cpus_mask = 0;
363 if (cpu_feature & CPUID_HTT)
364 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
367 * Work out if hyperthreading is *really* enabled. This
368 * is made really ugly by the fact that processors lie: Dual
369 * core processors claim to be hyperthreaded even when they're
370 * not, presumably because they want to be treated the same
371 * way as HTT with respect to per-cpu software licensing.
372 * At the time of writing (May 12, 2005) the only hyperthreaded
373 * cpus are from Intel, and Intel's dual-core processors can be
374 * identified via the "deterministic cache parameters" cpuid
378 * First determine if this is an Intel processor which claims
379 * to have hyperthreading support.
381 if ((cpu_feature & CPUID_HTT) &&
382 (strcmp(cpu_vendor, "GenuineIntel") == 0)) {
384 * If the "deterministic cache parameters" cpuid calls
385 * are available, use them.
388 /* Ask the processor about up to 32 caches. */
389 for (i = 0; i < 32; i++) {
390 cpuid_count(4, i, p);
391 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
392 if (hyperthreading_cpus < threads_per_cache)
393 hyperthreading_cpus = threads_per_cache;
394 if ((p[0] & 0x1f) == 0)
400 * If the deterministic cache parameters are not
401 * available, or if no caches were reported to exist,
402 * just accept what the HTT flag indicated.
404 if (hyperthreading_cpus == 0)
405 hyperthreading_cpus = logical_cpus;
408 set_logical_apic_ids();
413 * Print various information about the SMP system hardware and setup.
416 cpu_mp_announce(void)
421 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
422 for (i = 1, x = 0; x < MAXCPU; x++) {
423 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp)
425 if (cpu_info[x].cpu_disabled)
426 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x);
428 KASSERT(i < mp_ncpus,
429 ("mp_ncpus and actual cpus are out of whack"));
430 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x);
436 * AP CPU's call this to initialize themselves.
445 /* Set by the startup code for us to use */
449 common_tss[cpu] = common_tss[0];
450 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
451 common_tss[cpu].tss_iobase = sizeof(struct amd64tss);
452 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
454 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
455 ssdtosyssd(&gdt_segs[GPROC0_SEL],
456 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
458 lgdt(&r_gdt); /* does magic intra-segment return */
460 /* Get per-cpu data */
463 /* prime data page for it to use */
464 pcpu_init(pc, cpu, sizeof(struct pcpu));
465 pc->pc_apic_id = cpu_apic_ids[cpu];
466 pc->pc_prvspace = pc;
467 pc->pc_curthread = 0;
468 pc->pc_tssp = &common_tss[cpu];
471 wrmsr(MSR_FSBASE, 0); /* User value */
472 wrmsr(MSR_GSBASE, (u_int64_t)pc);
473 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
477 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
481 * Set to a known state:
482 * Set by mpboot.s: CR0_PG, CR0_PE
483 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
486 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
489 /* Set up the fast syscall stuff */
490 msr = rdmsr(MSR_EFER) | EFER_SCE;
491 wrmsr(MSR_EFER, msr);
492 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
493 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
494 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
495 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
496 wrmsr(MSR_STAR, msr);
497 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
499 /* Disable local APIC just to be sure. */
502 /* signal our startup to the BSP. */
505 /* Spin until the BSP releases the AP's. */
509 /* set up CPU registers and state */
512 /* set up SSE/NX registers */
515 /* set up FPU state on the AP */
518 /* A quick check from sanity claus */
519 if (PCPU_GET(apic_id) != lapic_id()) {
520 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
521 printf("SMP: actual apic_id = %d\n", lapic_id());
522 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
523 panic("cpuid mismatch! boom!!");
526 /* Initialize curthread. */
527 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
528 PCPU_SET(curthread, PCPU_GET(idlethread));
530 mtx_lock_spin(&ap_boot_mtx);
532 /* Init local apic for irq's */
535 /* Set memory range attributes for this CPU to match the BSP */
540 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
541 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
543 /* Determine if we are a logical CPU. */
544 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
545 logical_cpus_mask |= PCPU_GET(cpumask);
547 /* Determine if we are a hyperthread. */
548 if (hyperthreading_cpus > 1 &&
549 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
550 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
552 /* Build our map of 'other' CPUs. */
553 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
558 if (smp_cpus == mp_ncpus) {
559 /* enable IPI's, tlb shootdown, freezes etc */
560 atomic_store_rel_int(&smp_started, 1);
561 smp_active = 1; /* historic */
564 mtx_unlock_spin(&ap_boot_mtx);
566 /* wait until all the AP's are up */
567 while (smp_started == 0)
570 /* ok, now grab sched_lock and enter the scheduler */
571 mtx_lock_spin(&sched_lock);
574 * Correct spinlock nesting. The idle thread context that we are
575 * borrowing was created so that it would start out with a single
576 * spin lock (sched_lock) held in fork_trampoline(). Since we've
577 * explicitly acquired locks in this function, the nesting count
578 * is now 2 rather than 1. Since we are nested, calling
579 * spinlock_exit() will simply adjust the counts without allowing
580 * spin lock using code to interrupt us.
583 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count"));
585 binuptime(PCPU_PTR(switchtime));
586 PCPU_SET(switchticks, ticks);
588 cpu_throw(NULL, choosethread()); /* doesn't return */
590 panic("scheduler returned us to %s", __func__);
594 /*******************************************************************
595 * local functions and data
599 * Set the APIC logical IDs.
601 * We want to cluster logical CPU's within the same APIC ID cluster.
602 * Since logical CPU's are aligned simply filling in the clusters in
603 * APIC ID order works fine. Note that this does not try to balance
604 * the number of CPU's in each cluster. (XXX?)
607 set_logical_apic_ids(void)
609 u_int apic_id, cluster, cluster_id;
611 /* Force us to allocate cluster 0 at the start. */
613 cluster_id = APIC_MAX_INTRACLUSTER_ID;
614 for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
615 if (!cpu_info[apic_id].cpu_present)
617 if (cluster_id == APIC_MAX_INTRACLUSTER_ID) {
618 cluster = ioapic_next_logical_cluster();
623 printf("APIC ID: physical %u, logical %u:%u\n",
624 apic_id, cluster, cluster_id);
625 lapic_set_logical_id(apic_id, cluster, cluster_id);
630 * start each AP in our list
635 vm_offset_t va = boot_address + KERNBASE;
636 u_int64_t *pt4, *pt3, *pt2;
637 u_int32_t mpbioswarmvec;
641 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
643 /* install the AP 1st level boot code */
644 pmap_kenter(va, boot_address);
645 pmap_invalidate_page(kernel_pmap, va);
646 bcopy(mptramp_start, (void *)va, bootMP_size);
648 /* Locate the page tables, they'll be below the trampoline */
649 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
650 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
651 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
653 /* Create the initial 1GB replicated page tables */
654 for (i = 0; i < 512; i++) {
655 /* Each slot of the level 4 pages points to the same level 3 page */
656 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
657 pt4[i] |= PG_V | PG_RW | PG_U;
659 /* Each slot of the level 3 pages points to the same level 2 page */
660 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
661 pt3[i] |= PG_V | PG_RW | PG_U;
663 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
664 pt2[i] = i * (2 * 1024 * 1024);
665 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
668 /* save the current value of the warm-start vector */
669 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
670 outb(CMOS_REG, BIOS_RESET);
671 mpbiosreason = inb(CMOS_DATA);
673 /* setup a vector to our boot code */
674 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
675 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
676 outb(CMOS_REG, BIOS_RESET);
677 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
680 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) {
682 /* Ignore non-existent CPUs and the BSP. */
683 if (!cpu_info[apic_id].cpu_present ||
684 cpu_info[apic_id].cpu_bsp)
687 /* Don't use this CPU if it has been disabled by a tunable. */
688 if (resource_disabled("lapic", apic_id)) {
689 cpu_info[apic_id].cpu_disabled = 1;
696 /* save APIC ID for this logical ID */
697 cpu_apic_ids[cpu] = apic_id;
699 /* allocate and set up an idle stack data page */
700 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
701 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
703 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
706 /* attempt to start the Application Processor */
707 if (!start_ap(apic_id)) {
708 /* restore the warmstart vector */
709 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
710 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
713 all_cpus |= (1 << cpu); /* record AP in CPU map */
716 /* build our map of 'other' CPUs */
717 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
719 /* restore the warmstart vector */
720 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
722 outb(CMOS_REG, BIOS_RESET);
723 outb(CMOS_DATA, mpbiosreason);
725 /* number of APs actually started */
731 * This function starts the AP (application processor) identified
732 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
733 * to accomplish this. This is necessary because of the nuances
734 * of the different hardware we might encounter. It isn't pretty,
735 * but it seems to work.
738 start_ap(int apic_id)
743 /* calculate the vector */
744 vector = (boot_address >> 12) & 0xff;
746 /* used as a watchpoint to signal AP startup */
750 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
751 * and running the target CPU. OR this INIT IPI might be latched (P5
752 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
756 /* do an INIT IPI: assert RESET */
757 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
758 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
760 /* wait for pending status end */
763 /* do an INIT IPI: deassert RESET */
764 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
765 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
767 /* wait for pending status end */
768 DELAY(10000); /* wait ~10mS */
772 * next we do a STARTUP IPI: the previous INIT IPI might still be
773 * latched, (P5 bug) this 1st STARTUP would then terminate
774 * immediately, and the previously started INIT IPI would continue. OR
775 * the previous INIT IPI has already run. and this STARTUP IPI will
776 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
780 /* do a STARTUP IPI */
781 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
782 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
785 DELAY(200); /* wait ~200uS */
788 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
789 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
790 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
791 * recognized after hardware RESET or INIT IPI.
794 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
795 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
798 DELAY(200); /* wait ~200uS */
800 /* Wait up to 5 seconds for it to start. */
801 for (ms = 0; ms < 5000; ms++) {
803 return 1; /* return SUCCESS */
806 return 0; /* return FAILURE */
810 * Flush the TLB on all other CPU's
813 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
817 ncpu = mp_ncpus - 1; /* does not shootdown self */
819 return; /* no other cpus */
820 mtx_assert(&smp_ipi_mtx, MA_OWNED);
821 smp_tlb_addr1 = addr1;
822 smp_tlb_addr2 = addr2;
823 atomic_store_rel_int(&smp_tlb_wait, 0);
824 ipi_all_but_self(vector);
825 while (smp_tlb_wait < ncpu)
830 smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
834 othercpus = mp_ncpus - 1;
835 if (mask == (u_int)-1) {
840 mask &= ~PCPU_GET(cpumask);
843 ncpu = bitcount32(mask);
844 if (ncpu > othercpus) {
845 /* XXX this should be a panic offence */
846 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
850 /* XXX should be a panic, implied by mask == 0 above */
854 mtx_assert(&smp_ipi_mtx, MA_OWNED);
855 smp_tlb_addr1 = addr1;
856 smp_tlb_addr2 = addr2;
857 atomic_store_rel_int(&smp_tlb_wait, 0);
858 if (mask == (u_int)-1)
859 ipi_all_but_self(vector);
861 ipi_selected(mask, vector);
862 while (smp_tlb_wait < ncpu)
871 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
876 smp_invlpg(vm_offset_t addr)
880 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
884 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
888 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
893 smp_masked_invltlb(u_int mask)
897 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
902 smp_masked_invlpg(u_int mask, vm_offset_t addr)
906 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
911 smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
915 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
920 ipi_bitmap_handler(struct trapframe frame)
922 int cpu = PCPU_GET(cpuid);
925 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
927 #ifdef IPI_PREEMPTION
928 if (ipi_bitmap & IPI_PREEMPT) {
929 mtx_lock_spin(&sched_lock);
930 /* Don't preempt the idle thread */
931 if (curthread->td_priority < PRI_MIN_IDLE) {
932 struct thread *running_thread = curthread;
933 if (running_thread->td_critnest > 1)
934 running_thread->td_owepreempt = 1;
936 mi_switch(SW_INVOL | SW_PREEMPT, NULL);
938 mtx_unlock_spin(&sched_lock);
942 /* Nothing to do for AST */
946 * send an IPI to a set of cpus.
949 ipi_selected(u_int32_t cpus, u_int ipi)
956 if (IPI_IS_BITMAPED(ipi)) {
958 ipi = IPI_BITMAP_VECTOR;
962 if (ipi == IPI_STOP && stop_cpus_with_nmi) {
963 ipi_nmi_selected(cpus);
967 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
968 while ((cpu = ffs(cpus)) != 0) {
972 KASSERT(cpu_apic_ids[cpu] != -1,
973 ("IPI to non-existent CPU %d", cpu));
977 old_pending = cpu_ipi_pending[cpu];
978 new_pending = old_pending | bitmap;
979 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending));
985 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
991 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
997 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
998 ipi_selected(all_cpus, ipi);
1001 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1002 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL);
1006 * send an IPI to all CPUs EXCEPT myself
1009 ipi_all_but_self(u_int ipi)
1012 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1013 ipi_selected(PCPU_GET(other_cpus), ipi);
1016 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1017 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1021 * send an IPI to myself
1027 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1028 ipi_selected(PCPU_GET(cpumask), ipi);
1031 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1032 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF);
1037 * send NMI IPI to selected CPUs
1040 #define BEFORE_SPIN 1000000
1043 ipi_nmi_selected(u_int32_t cpus)
1048 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT
1049 | APIC_TRIGMOD_EDGE;
1051 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus);
1053 atomic_set_int(&ipi_nmi_pending, cpus);
1055 while ((cpu = ffs(cpus)) != 0) {
1057 cpus &= ~(1 << cpu);
1059 KASSERT(cpu_apic_ids[cpu] != -1,
1060 ("IPI NMI to non-existent CPU %d", cpu));
1062 /* Wait for an earlier IPI to finish. */
1063 if (!lapic_ipi_wait(BEFORE_SPIN))
1064 panic("ipi_nmi_selected: previous IPI has not cleared");
1066 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]);
1071 ipi_nmi_handler(void)
1073 int cpumask = PCPU_GET(cpumask);
1075 if (!(ipi_nmi_pending & cpumask))
1078 atomic_clear_int(&ipi_nmi_pending, cpumask);
1083 #endif /* STOP_NMI */
1086 * Handle an IPI_STOP by saving our current context and spinning until we
1090 cpustop_handler(void)
1092 int cpu = PCPU_GET(cpuid);
1093 int cpumask = PCPU_GET(cpumask);
1095 savectx(&stoppcbs[cpu]);
1097 /* Indicate that we are stopped */
1098 atomic_set_int(&stopped_cpus, cpumask);
1100 /* Wait for restart */
1101 while (!(started_cpus & cpumask))
1104 atomic_clear_int(&started_cpus, cpumask);
1105 atomic_clear_int(&stopped_cpus, cpumask);
1107 if (cpu == 0 && cpustop_restartfunc != NULL) {
1108 cpustop_restartfunc();
1109 cpustop_restartfunc = NULL;
1114 * This is called once the rest of the system is up and running and we're
1115 * ready to let the AP's out of the pen.
1118 release_aps(void *dummy __unused)
1123 mtx_lock_spin(&sched_lock);
1124 atomic_store_rel_int(&aps_ready, 1);
1125 while (smp_started == 0)
1127 mtx_unlock_spin(&sched_lock);
1129 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1132 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1137 mask = hlt_cpus_mask;
1138 error = sysctl_handle_int(oidp, &mask, 0, req);
1139 if (error || !req->newptr)
1142 if (logical_cpus_mask != 0 &&
1143 (mask & logical_cpus_mask) == logical_cpus_mask)
1144 hlt_logical_cpus = 1;
1146 hlt_logical_cpus = 0;
1148 if (! hyperthreading_allowed)
1149 mask |= hyperthreading_cpus_mask;
1151 if ((mask & all_cpus) == all_cpus)
1153 hlt_cpus_mask = mask;
1156 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1157 0, 0, sysctl_hlt_cpus, "IU",
1158 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1161 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1165 disable = hlt_logical_cpus;
1166 error = sysctl_handle_int(oidp, &disable, 0, req);
1167 if (error || !req->newptr)
1171 hlt_cpus_mask |= logical_cpus_mask;
1173 hlt_cpus_mask &= ~logical_cpus_mask;
1175 if (! hyperthreading_allowed)
1176 hlt_cpus_mask |= hyperthreading_cpus_mask;
1178 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1179 hlt_cpus_mask &= ~(1<<0);
1181 hlt_logical_cpus = disable;
1186 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1190 allowed = hyperthreading_allowed;
1191 error = sysctl_handle_int(oidp, &allowed, 0, req);
1192 if (error || !req->newptr)
1196 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1198 hlt_cpus_mask |= hyperthreading_cpus_mask;
1200 if (logical_cpus_mask != 0 &&
1201 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1202 hlt_logical_cpus = 1;
1204 hlt_logical_cpus = 0;
1206 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1207 hlt_cpus_mask &= ~(1<<0);
1209 hyperthreading_allowed = allowed;
1214 cpu_hlt_setup(void *dummy __unused)
1217 if (logical_cpus_mask != 0) {
1218 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1220 sysctl_ctx_init(&logical_cpu_clist);
1221 SYSCTL_ADD_PROC(&logical_cpu_clist,
1222 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1223 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1224 sysctl_hlt_logical_cpus, "IU", "");
1225 SYSCTL_ADD_UINT(&logical_cpu_clist,
1226 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1227 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1228 &logical_cpus_mask, 0, "");
1230 if (hlt_logical_cpus)
1231 hlt_cpus_mask |= logical_cpus_mask;
1234 * If necessary for security purposes, force
1235 * hyperthreading off, regardless of the value
1236 * of hlt_logical_cpus.
1238 if (hyperthreading_cpus_mask) {
1239 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
1240 &hyperthreading_allowed);
1241 SYSCTL_ADD_PROC(&logical_cpu_clist,
1242 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1243 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1244 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1245 if (! hyperthreading_allowed)
1246 hlt_cpus_mask |= hyperthreading_cpus_mask;
1250 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1253 mp_grab_cpu_hlt(void)
1255 u_int mask = PCPU_GET(cpumask);
1257 u_int cpuid = PCPU_GET(cpuid);
1265 retval = mask & hlt_cpus_mask;
1266 while (mask & hlt_cpus_mask)
1267 __asm __volatile("sti; hlt" : : : "memory");