2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1996, by Steve Passe
5 * Copyright (c) 2003, by Peter Wemm
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
35 #include "opt_sched.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/cpuset.h>
45 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/memrange.h>
50 #include <sys/mutex.h>
53 #include <sys/sched.h>
55 #include <sys/sysctl.h>
58 #include <vm/vm_param.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_extern.h>
63 #include <x86/apicreg.h>
64 #include <machine/clock.h>
65 #include <machine/cputypes.h>
66 #include <machine/cpufunc.h>
68 #include <machine/md_var.h>
69 #include <machine/pcb.h>
70 #include <machine/psl.h>
71 #include <machine/smp.h>
72 #include <machine/specialreg.h>
73 #include <machine/tss.h>
74 #include <machine/cpu.h>
77 #define WARMBOOT_TARGET 0
78 #define WARMBOOT_OFF (KERNBASE + 0x0467)
79 #define WARMBOOT_SEG (KERNBASE + 0x0469)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define GiB(v) (v ## ULL << 30)
88 extern struct pcpu __pcpu[];
90 /* Temporary variables for init_secondary() */
91 char *doublefault_stack;
96 * Local data and functions.
99 static int start_ap(int apic_id);
102 * Calculate usable address in base memory for AP trampoline code.
105 mp_bootaddress(vm_paddr_t *physmap, unsigned int *physmap_idx)
110 alloc_ap_trampoline(physmap, physmap_idx);
113 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
115 * Find a memory region big enough below the 4GB boundary to
116 * store the initial page tables. Note that it needs to be
117 * aligned to a page boundary.
119 if (physmap[i] >= GiB(4) ||
120 (physmap[i + 1] - round_page(physmap[i])) < (PAGE_SIZE * 3))
124 mptramp_pagetables = round_page(physmap[i]);
125 physmap[i] = round_page(physmap[i]) + (PAGE_SIZE * 3);
126 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
127 memmove(&physmap[i], &physmap[i + 2],
128 sizeof(*physmap) * (*physmap_idx - i + 2));
135 mptramp_pagetables = trunc_page(boot_address) - (PAGE_SIZE * 3);
138 "Cannot find enough space for the initial AP page tables, placing them at %#x",
144 * Initialize the IPI handlers and start up the AP's.
151 /* Initialize the logical ID to APIC ID table. */
152 for (i = 0; i < MAXCPU; i++) {
153 cpu_apic_ids[i] = -1;
154 cpu_ipi_pending[i] = 0;
157 /* Install an inter-CPU IPI for TLB invalidation */
158 if (pmap_pcid_enabled) {
160 setidt(IPI_INVLTLB, pti ?
161 IDTVEC(invltlb_invpcid_pti_pti) :
162 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
164 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
165 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
166 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
167 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
169 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
170 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
171 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
172 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
173 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
174 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
177 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
178 SDT_SYSIGT, SEL_KPL, 0);
179 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
180 SDT_SYSIGT, SEL_KPL, 0);
181 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
182 SDT_SYSIGT, SEL_KPL, 0);
185 /* Install an inter-CPU IPI for cache invalidation. */
186 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
187 SDT_SYSIGT, SEL_KPL, 0);
189 /* Install an inter-CPU IPI for all-CPU rendezvous */
190 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
191 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
193 /* Install generic inter-CPU IPI handler */
194 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
195 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
197 /* Install an inter-CPU IPI for CPU stop/restart */
198 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
199 SDT_SYSIGT, SEL_KPL, 0);
201 /* Install an inter-CPU IPI for CPU suspend/resume */
202 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
203 SDT_SYSIGT, SEL_KPL, 0);
205 /* Set boot_cpu_id if needed. */
206 if (boot_cpu_id == -1) {
207 boot_cpu_id = PCPU_GET(apic_id);
208 cpu_info[boot_cpu_id].cpu_bsp = 1;
210 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
211 ("BSP's APIC ID doesn't match boot_cpu_id"));
213 /* Probe logical/physical core configuration. */
218 /* Start each Application Processor */
219 init_ops.start_all_aps();
221 set_interrupt_apic_ids();
226 * AP CPU's call this to initialize themselves.
234 int cpu, gsel_tss, x;
235 struct region_descriptor ap_gdt;
237 /* Set by the startup code for us to use */
241 common_tss[cpu] = common_tss[0];
242 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
244 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
246 /* The NMI stack runs on IST2. */
247 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
248 common_tss[cpu].tss_ist2 = (long) np;
250 /* The MC# stack runs on IST3. */
251 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
252 common_tss[cpu].tss_ist3 = (long) np;
254 /* Prepare private GDT */
255 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
256 for (x = 0; x < NGDT; x++) {
257 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
258 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
259 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
261 ssdtosyssd(&gdt_segs[GPROC0_SEL],
262 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
263 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
264 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
265 lgdt(&ap_gdt); /* does magic intra-segment return */
267 /* Get per-cpu data */
270 /* prime data page for it to use */
271 pcpu_init(pc, cpu, sizeof(struct pcpu));
272 dpcpu_init(dpcpu, cpu);
273 pc->pc_apic_id = cpu_apic_ids[cpu];
274 pc->pc_prvspace = pc;
275 pc->pc_curthread = 0;
276 pc->pc_tssp = &common_tss[cpu];
277 pc->pc_commontssp = &common_tss[cpu];
279 pc->pc_pti_rsp0 = ((vm_offset_t)&pc->pc_pti_stack +
280 PC_PTI_STACK_SZ * sizeof(uint64_t) & ~0xful);
281 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
283 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
284 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
285 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
287 pc->pc_curpmap = kernel_pmap;
289 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
290 common_tss[cpu].tss_rsp0 = 0;
292 /* Save the per-cpu pointer for use by the NMI handler. */
293 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
294 np->np_pcpu = (register_t) pc;
296 /* Save the per-cpu pointer for use by the MC# handler. */
297 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
298 np->np_pcpu = (register_t) pc;
300 wrmsr(MSR_FSBASE, 0); /* User value */
301 wrmsr(MSR_GSBASE, (u_int64_t)pc);
302 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
307 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
311 * Set to a known state:
312 * Set by mpboot.s: CR0_PG, CR0_PE
313 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
316 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
319 amd64_conf_fast_syscall();
321 /* signal our startup to the BSP. */
324 /* Spin until the BSP releases the AP's. */
325 while (atomic_load_acq_int(&aps_ready) == 0)
328 init_secondary_tail();
331 /*******************************************************************
332 * local functions and data
336 * start each AP in our list
339 native_start_all_aps(void)
341 u_int64_t *pt4, *pt3, *pt2;
342 u_int32_t mpbioswarmvec;
346 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
348 /* copy the AP 1st level boot code */
349 bcopy(mptramp_start, (void *)PHYS_TO_DMAP(boot_address), bootMP_size);
351 /* Locate the page tables, they'll be below the trampoline */
352 pt4 = (uint64_t *)PHYS_TO_DMAP(mptramp_pagetables);
353 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
354 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
356 /* Create the initial 1GB replicated page tables */
357 for (i = 0; i < 512; i++) {
358 /* Each slot of the level 4 pages points to the same level 3 page */
359 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
360 pt4[i] |= PG_V | PG_RW | PG_U;
362 /* Each slot of the level 3 pages points to the same level 2 page */
363 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
364 pt3[i] |= PG_V | PG_RW | PG_U;
366 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
367 pt2[i] = i * (2 * 1024 * 1024);
368 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
371 /* save the current value of the warm-start vector */
372 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
373 outb(CMOS_REG, BIOS_RESET);
374 mpbiosreason = inb(CMOS_DATA);
376 /* setup a vector to our boot code */
377 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
378 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
379 outb(CMOS_REG, BIOS_RESET);
380 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
383 for (cpu = 1; cpu < mp_ncpus; cpu++) {
384 apic_id = cpu_apic_ids[cpu];
386 /* allocate and set up an idle stack data page */
387 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
388 kstack_pages * PAGE_SIZE, M_WAITOK | M_ZERO);
389 doublefault_stack = (char *)kmem_malloc(kernel_arena,
390 PAGE_SIZE, M_WAITOK | M_ZERO);
391 mce_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
393 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
395 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
398 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
401 /* attempt to start the Application Processor */
402 if (!start_ap(apic_id)) {
403 /* restore the warmstart vector */
404 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
405 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
408 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
411 /* restore the warmstart vector */
412 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
414 outb(CMOS_REG, BIOS_RESET);
415 outb(CMOS_DATA, mpbiosreason);
417 /* number of APs actually started */
423 * This function starts the AP (application processor) identified
424 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
425 * to accomplish this. This is necessary because of the nuances
426 * of the different hardware we might encounter. It isn't pretty,
427 * but it seems to work.
430 start_ap(int apic_id)
435 /* calculate the vector */
436 vector = (boot_address >> 12) & 0xff;
438 /* used as a watchpoint to signal AP startup */
441 ipi_startup(apic_id, vector);
443 /* Wait up to 5 seconds for it to start. */
444 for (ms = 0; ms < 5000; ms++) {
446 return 1; /* return SUCCESS */
449 return 0; /* return FAILURE */
453 invltlb_invpcid_handler(void)
455 struct invpcid_descr d;
458 #ifdef COUNT_XINVLTLB_HITS
459 xhits_gbl[PCPU_GET(cpuid)]++;
460 #endif /* COUNT_XINVLTLB_HITS */
462 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
463 #endif /* COUNT_IPIS */
465 generation = smp_tlb_generation;
466 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
469 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
471 PCPU_SET(smp_tlb_done, generation);
475 invltlb_invpcid_pti_handler(void)
477 struct invpcid_descr d;
480 #ifdef COUNT_XINVLTLB_HITS
481 xhits_gbl[PCPU_GET(cpuid)]++;
482 #endif /* COUNT_XINVLTLB_HITS */
484 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
485 #endif /* COUNT_IPIS */
487 generation = smp_tlb_generation;
488 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
491 if (smp_tlb_pmap == kernel_pmap) {
493 * This invalidation actually needs to clear kernel
494 * mappings from the TLB in the current pmap, but
495 * since we were asked for the flush in the kernel
496 * pmap, achieve it by performing global flush.
498 invpcid(&d, INVPCID_CTXGLOB);
500 invpcid(&d, INVPCID_CTX);
501 d.pcid |= PMAP_PCID_USER_PT;
502 invpcid(&d, INVPCID_CTX);
504 PCPU_SET(smp_tlb_done, generation);
508 invltlb_pcid_handler(void)
511 uint32_t generation, pcid;
513 #ifdef COUNT_XINVLTLB_HITS
514 xhits_gbl[PCPU_GET(cpuid)]++;
515 #endif /* COUNT_XINVLTLB_HITS */
517 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
518 #endif /* COUNT_IPIS */
520 generation = smp_tlb_generation; /* Overlap with serialization */
521 if (smp_tlb_pmap == kernel_pmap) {
525 * The current pmap might not be equal to
526 * smp_tlb_pmap. The clearing of the pm_gen in
527 * pmap_invalidate_all() takes care of TLB
528 * invalidation when switching to the pmap on this
531 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
532 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
533 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
534 ucr3 = smp_tlb_pmap->pm_ucr3;
535 if (ucr3 != PMAP_NO_CR3) {
536 ucr3 |= PMAP_PCID_USER_PT | pcid;
537 pmap_pti_pcid_invalidate(ucr3, kcr3);
542 PCPU_SET(smp_tlb_done, generation);
546 invlpg_invpcid_handler(void)
548 struct invpcid_descr d;
551 #ifdef COUNT_XINVLTLB_HITS
552 xhits_pg[PCPU_GET(cpuid)]++;
553 #endif /* COUNT_XINVLTLB_HITS */
555 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
556 #endif /* COUNT_IPIS */
558 generation = smp_tlb_generation; /* Overlap with serialization */
559 invlpg(smp_tlb_addr1);
560 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
561 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
564 d.addr = smp_tlb_addr1;
565 invpcid(&d, INVPCID_ADDR);
567 PCPU_SET(smp_tlb_done, generation);
571 invlpg_pcid_handler(void)
577 #ifdef COUNT_XINVLTLB_HITS
578 xhits_pg[PCPU_GET(cpuid)]++;
579 #endif /* COUNT_XINVLTLB_HITS */
581 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
582 #endif /* COUNT_IPIS */
584 generation = smp_tlb_generation; /* Overlap with serialization */
585 invlpg(smp_tlb_addr1);
586 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
587 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
588 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
589 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
590 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
591 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
593 PCPU_SET(smp_tlb_done, generation);
597 invlrng_invpcid_handler(void)
599 struct invpcid_descr d;
600 vm_offset_t addr, addr2;
603 #ifdef COUNT_XINVLTLB_HITS
604 xhits_rng[PCPU_GET(cpuid)]++;
605 #endif /* COUNT_XINVLTLB_HITS */
607 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
608 #endif /* COUNT_IPIS */
610 addr = smp_tlb_addr1;
611 addr2 = smp_tlb_addr2;
612 generation = smp_tlb_generation; /* Overlap with serialization */
616 } while (addr < addr2);
617 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
618 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
621 d.addr = smp_tlb_addr1;
623 invpcid(&d, INVPCID_ADDR);
625 } while (d.addr < addr2);
627 PCPU_SET(smp_tlb_done, generation);
631 invlrng_pcid_handler(void)
633 vm_offset_t addr, addr2;
638 #ifdef COUNT_XINVLTLB_HITS
639 xhits_rng[PCPU_GET(cpuid)]++;
640 #endif /* COUNT_XINVLTLB_HITS */
642 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
643 #endif /* COUNT_IPIS */
645 addr = smp_tlb_addr1;
646 addr2 = smp_tlb_addr2;
647 generation = smp_tlb_generation; /* Overlap with serialization */
651 } while (addr < addr2);
652 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
653 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
654 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
655 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
656 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
657 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
659 PCPU_SET(smp_tlb_done, generation);