2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1996, by Steve Passe
5 * Copyright (c) 2003, by Peter Wemm
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
35 #include "opt_sched.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/cpuset.h>
45 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/memrange.h>
50 #include <sys/mutex.h>
53 #include <sys/sched.h>
55 #include <sys/sysctl.h>
58 #include <vm/vm_param.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_extern.h>
63 #include <x86/apicreg.h>
64 #include <machine/clock.h>
65 #include <machine/cputypes.h>
66 #include <machine/cpufunc.h>
68 #include <machine/md_var.h>
69 #include <machine/pcb.h>
70 #include <machine/psl.h>
71 #include <machine/smp.h>
72 #include <machine/specialreg.h>
73 #include <machine/tss.h>
74 #include <machine/cpu.h>
77 #define WARMBOOT_TARGET 0
78 #define WARMBOOT_OFF (KERNBASE + 0x0467)
79 #define WARMBOOT_SEG (KERNBASE + 0x0469)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 extern struct pcpu __pcpu[];
88 /* Temporary variables for init_secondary() */
89 char *doublefault_stack;
94 * Local data and functions.
97 static int start_ap(int apic_id);
99 static u_int bootMP_size;
100 static u_int boot_address;
103 * Calculate usable address in base memory for AP trampoline code.
106 mp_bootaddress(u_int basemem)
109 bootMP_size = mptramp_end - mptramp_start;
110 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
111 if (((basemem * 1024) - boot_address) < bootMP_size)
112 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
113 /* 3 levels of page table pages */
114 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
116 return mptramp_pagetables;
120 * Initialize the IPI handlers and start up the AP's.
127 /* Initialize the logical ID to APIC ID table. */
128 for (i = 0; i < MAXCPU; i++) {
129 cpu_apic_ids[i] = -1;
130 cpu_ipi_pending[i] = 0;
133 /* Install an inter-CPU IPI for TLB invalidation */
134 if (pmap_pcid_enabled) {
136 setidt(IPI_INVLTLB, pti ?
137 IDTVEC(invltlb_invpcid_pti_pti) :
138 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
140 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
141 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
142 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
143 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
145 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
146 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
147 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
148 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
149 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
150 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
153 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
154 SDT_SYSIGT, SEL_KPL, 0);
155 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
156 SDT_SYSIGT, SEL_KPL, 0);
157 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
158 SDT_SYSIGT, SEL_KPL, 0);
161 /* Install an inter-CPU IPI for cache invalidation. */
162 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
163 SDT_SYSIGT, SEL_KPL, 0);
165 /* Install an inter-CPU IPI for all-CPU rendezvous */
166 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
167 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
169 /* Install generic inter-CPU IPI handler */
170 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
171 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
173 /* Install an inter-CPU IPI for CPU stop/restart */
174 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
175 SDT_SYSIGT, SEL_KPL, 0);
177 /* Install an inter-CPU IPI for CPU suspend/resume */
178 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
179 SDT_SYSIGT, SEL_KPL, 0);
181 /* Set boot_cpu_id if needed. */
182 if (boot_cpu_id == -1) {
183 boot_cpu_id = PCPU_GET(apic_id);
184 cpu_info[boot_cpu_id].cpu_bsp = 1;
186 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
187 ("BSP's APIC ID doesn't match boot_cpu_id"));
189 /* Probe logical/physical core configuration. */
194 /* Start each Application Processor */
195 init_ops.start_all_aps();
197 set_interrupt_apic_ids();
202 * AP CPU's call this to initialize themselves.
210 int cpu, gsel_tss, x;
211 struct region_descriptor ap_gdt;
213 /* Set by the startup code for us to use */
217 common_tss[cpu] = common_tss[0];
218 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
220 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
222 /* The NMI stack runs on IST2. */
223 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
224 common_tss[cpu].tss_ist2 = (long) np;
226 /* The MC# stack runs on IST3. */
227 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
228 common_tss[cpu].tss_ist3 = (long) np;
230 /* Prepare private GDT */
231 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
232 for (x = 0; x < NGDT; x++) {
233 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
234 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
235 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
237 ssdtosyssd(&gdt_segs[GPROC0_SEL],
238 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
239 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
240 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
241 lgdt(&ap_gdt); /* does magic intra-segment return */
243 /* Get per-cpu data */
246 /* prime data page for it to use */
247 pcpu_init(pc, cpu, sizeof(struct pcpu));
248 dpcpu_init(dpcpu, cpu);
249 pc->pc_apic_id = cpu_apic_ids[cpu];
250 pc->pc_prvspace = pc;
251 pc->pc_curthread = 0;
252 pc->pc_tssp = &common_tss[cpu];
253 pc->pc_commontssp = &common_tss[cpu];
255 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
257 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
258 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
259 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
261 pc->pc_curpmap = kernel_pmap;
263 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
264 common_tss[cpu].tss_rsp0 = pti ? ((vm_offset_t)&pc->pc_pti_stack +
265 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful : 0;
267 /* Save the per-cpu pointer for use by the NMI handler. */
268 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
269 np->np_pcpu = (register_t) pc;
271 /* Save the per-cpu pointer for use by the MC# handler. */
272 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
273 np->np_pcpu = (register_t) pc;
275 wrmsr(MSR_FSBASE, 0); /* User value */
276 wrmsr(MSR_GSBASE, (u_int64_t)pc);
277 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
282 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
286 * Set to a known state:
287 * Set by mpboot.s: CR0_PG, CR0_PE
288 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
291 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
294 amd64_conf_fast_syscall();
296 /* signal our startup to the BSP. */
299 /* Spin until the BSP releases the AP's. */
300 while (atomic_load_acq_int(&aps_ready) == 0)
303 init_secondary_tail();
306 /*******************************************************************
307 * local functions and data
311 * start each AP in our list
314 native_start_all_aps(void)
316 vm_offset_t va = boot_address + KERNBASE;
317 u_int64_t *pt4, *pt3, *pt2;
318 u_int32_t mpbioswarmvec;
322 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
324 /* install the AP 1st level boot code */
325 pmap_kenter(va, boot_address);
326 pmap_invalidate_page(kernel_pmap, va);
327 bcopy(mptramp_start, (void *)va, bootMP_size);
329 /* Locate the page tables, they'll be below the trampoline */
330 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
331 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
332 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
334 /* Create the initial 1GB replicated page tables */
335 for (i = 0; i < 512; i++) {
336 /* Each slot of the level 4 pages points to the same level 3 page */
337 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
338 pt4[i] |= PG_V | PG_RW | PG_U;
340 /* Each slot of the level 3 pages points to the same level 2 page */
341 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
342 pt3[i] |= PG_V | PG_RW | PG_U;
344 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
345 pt2[i] = i * (2 * 1024 * 1024);
346 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
349 /* save the current value of the warm-start vector */
350 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
351 outb(CMOS_REG, BIOS_RESET);
352 mpbiosreason = inb(CMOS_DATA);
354 /* setup a vector to our boot code */
355 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
356 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
357 outb(CMOS_REG, BIOS_RESET);
358 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
361 for (cpu = 1; cpu < mp_ncpus; cpu++) {
362 apic_id = cpu_apic_ids[cpu];
364 /* allocate and set up an idle stack data page */
365 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
366 kstack_pages * PAGE_SIZE, M_WAITOK | M_ZERO);
367 doublefault_stack = (char *)kmem_malloc(kernel_arena,
368 PAGE_SIZE, M_WAITOK | M_ZERO);
369 mce_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
371 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
373 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
376 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
379 /* attempt to start the Application Processor */
380 if (!start_ap(apic_id)) {
381 /* restore the warmstart vector */
382 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
383 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
386 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
389 /* restore the warmstart vector */
390 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
392 outb(CMOS_REG, BIOS_RESET);
393 outb(CMOS_DATA, mpbiosreason);
395 /* number of APs actually started */
401 * This function starts the AP (application processor) identified
402 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
403 * to accomplish this. This is necessary because of the nuances
404 * of the different hardware we might encounter. It isn't pretty,
405 * but it seems to work.
408 start_ap(int apic_id)
413 /* calculate the vector */
414 vector = (boot_address >> 12) & 0xff;
416 /* used as a watchpoint to signal AP startup */
419 ipi_startup(apic_id, vector);
421 /* Wait up to 5 seconds for it to start. */
422 for (ms = 0; ms < 5000; ms++) {
424 return 1; /* return SUCCESS */
427 return 0; /* return FAILURE */
431 invltlb_invpcid_handler(void)
433 struct invpcid_descr d;
436 #ifdef COUNT_XINVLTLB_HITS
437 xhits_gbl[PCPU_GET(cpuid)]++;
438 #endif /* COUNT_XINVLTLB_HITS */
440 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
441 #endif /* COUNT_IPIS */
443 generation = smp_tlb_generation;
444 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
447 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
449 PCPU_SET(smp_tlb_done, generation);
453 invltlb_invpcid_pti_handler(void)
455 struct invpcid_descr d;
458 #ifdef COUNT_XINVLTLB_HITS
459 xhits_gbl[PCPU_GET(cpuid)]++;
460 #endif /* COUNT_XINVLTLB_HITS */
462 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
463 #endif /* COUNT_IPIS */
465 generation = smp_tlb_generation;
466 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
469 if (smp_tlb_pmap == kernel_pmap) {
471 * This invalidation actually needs to clear kernel
472 * mappings from the TLB in the current pmap, but
473 * since we were asked for the flush in the kernel
474 * pmap, achieve it by performing global flush.
476 invpcid(&d, INVPCID_CTXGLOB);
478 invpcid(&d, INVPCID_CTX);
479 d.pcid |= PMAP_PCID_USER_PT;
480 invpcid(&d, INVPCID_CTX);
482 PCPU_SET(smp_tlb_done, generation);
486 invltlb_pcid_handler(void)
489 uint32_t generation, pcid;
491 #ifdef COUNT_XINVLTLB_HITS
492 xhits_gbl[PCPU_GET(cpuid)]++;
493 #endif /* COUNT_XINVLTLB_HITS */
495 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
496 #endif /* COUNT_IPIS */
498 generation = smp_tlb_generation; /* Overlap with serialization */
499 if (smp_tlb_pmap == kernel_pmap) {
503 * The current pmap might not be equal to
504 * smp_tlb_pmap. The clearing of the pm_gen in
505 * pmap_invalidate_all() takes care of TLB
506 * invalidation when switching to the pmap on this
509 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
510 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
511 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
512 ucr3 = smp_tlb_pmap->pm_ucr3;
513 if (ucr3 != PMAP_NO_CR3) {
514 ucr3 |= PMAP_PCID_USER_PT | pcid;
515 pmap_pti_pcid_invalidate(ucr3, kcr3);
520 PCPU_SET(smp_tlb_done, generation);
524 invlpg_invpcid_handler(void)
526 struct invpcid_descr d;
529 #ifdef COUNT_XINVLTLB_HITS
530 xhits_pg[PCPU_GET(cpuid)]++;
531 #endif /* COUNT_XINVLTLB_HITS */
533 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
534 #endif /* COUNT_IPIS */
536 generation = smp_tlb_generation; /* Overlap with serialization */
537 invlpg(smp_tlb_addr1);
538 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
539 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
542 d.addr = smp_tlb_addr1;
543 invpcid(&d, INVPCID_ADDR);
545 PCPU_SET(smp_tlb_done, generation);
549 invlpg_pcid_handler(void)
555 #ifdef COUNT_XINVLTLB_HITS
556 xhits_pg[PCPU_GET(cpuid)]++;
557 #endif /* COUNT_XINVLTLB_HITS */
559 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
560 #endif /* COUNT_IPIS */
562 generation = smp_tlb_generation; /* Overlap with serialization */
563 invlpg(smp_tlb_addr1);
564 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
565 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
566 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
567 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
568 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
569 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
571 PCPU_SET(smp_tlb_done, generation);
575 invlrng_invpcid_handler(void)
577 struct invpcid_descr d;
578 vm_offset_t addr, addr2;
581 #ifdef COUNT_XINVLTLB_HITS
582 xhits_rng[PCPU_GET(cpuid)]++;
583 #endif /* COUNT_XINVLTLB_HITS */
585 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
586 #endif /* COUNT_IPIS */
588 addr = smp_tlb_addr1;
589 addr2 = smp_tlb_addr2;
590 generation = smp_tlb_generation; /* Overlap with serialization */
594 } while (addr < addr2);
595 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
596 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
599 d.addr = smp_tlb_addr1;
601 invpcid(&d, INVPCID_ADDR);
603 } while (d.addr < addr2);
605 PCPU_SET(smp_tlb_done, generation);
609 invlrng_pcid_handler(void)
611 vm_offset_t addr, addr2;
616 #ifdef COUNT_XINVLTLB_HITS
617 xhits_rng[PCPU_GET(cpuid)]++;
618 #endif /* COUNT_XINVLTLB_HITS */
620 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
621 #endif /* COUNT_IPIS */
623 addr = smp_tlb_addr1;
624 addr2 = smp_tlb_addr2;
625 generation = smp_tlb_generation; /* Overlap with serialization */
629 } while (addr < addr2);
630 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
631 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
632 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
633 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
634 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
635 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
637 PCPU_SET(smp_tlb_done, generation);