2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1996, by Steve Passe
5 * Copyright (c) 2003, by Peter Wemm
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
35 #include "opt_sched.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/cpuset.h>
45 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/memrange.h>
50 #include <sys/mutex.h>
53 #include <sys/sched.h>
55 #include <sys/sysctl.h>
58 #include <vm/vm_param.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_extern.h>
63 #include <x86/apicreg.h>
64 #include <machine/clock.h>
65 #include <machine/cputypes.h>
66 #include <machine/cpufunc.h>
68 #include <machine/md_var.h>
69 #include <machine/pcb.h>
70 #include <machine/psl.h>
71 #include <machine/smp.h>
72 #include <machine/specialreg.h>
73 #include <machine/tss.h>
74 #include <x86/ucode.h>
75 #include <machine/cpu.h>
78 #define WARMBOOT_TARGET 0
79 #define WARMBOOT_OFF (KERNBASE + 0x0467)
80 #define WARMBOOT_SEG (KERNBASE + 0x0469)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define GiB(v) (v ## ULL << 30)
89 #define AP_BOOTPT_SZ (PAGE_SIZE * 3)
91 extern struct pcpu __pcpu[];
93 /* Temporary variables for init_secondary() */
94 char *doublefault_stack;
100 * Local data and functions.
103 static int start_ap(int apic_id);
106 is_kernel_paddr(vm_paddr_t pa)
109 return (pa >= trunc_2mpage(btext - KERNBASE) &&
110 pa < round_page(_end - KERNBASE));
114 is_mpboot_good(vm_paddr_t start, vm_paddr_t end)
117 return (start + AP_BOOTPT_SZ <= GiB(4) && atop(end) < Maxmem);
121 * Calculate usable address in base memory for AP trampoline code.
124 mp_bootaddress(vm_paddr_t *physmap, unsigned int *physmap_idx)
126 vm_paddr_t start, end;
130 alloc_ap_trampoline(physmap, physmap_idx);
133 * Find a memory region big enough below the 4GB boundary to
134 * store the initial page tables. Region must be mapped by
137 * Note that it needs to be aligned to a page boundary.
140 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
142 * First, try to chomp at the start of the physmap region.
143 * Kernel binary might claim it already.
145 start = round_page(physmap[i]);
146 end = start + AP_BOOTPT_SZ;
147 if (start < end && end <= physmap[i + 1] &&
148 is_mpboot_good(start, end) &&
149 !is_kernel_paddr(start) && !is_kernel_paddr(end - 1)) {
156 * Second, try to chomp at the end. Again, check
159 end = trunc_page(physmap[i + 1]);
160 start = end - AP_BOOTPT_SZ;
161 if (start < end && start >= physmap[i] &&
162 is_mpboot_good(start, end) &&
163 !is_kernel_paddr(start) && !is_kernel_paddr(end - 1)) {
165 physmap[i + 1] = start;
170 mptramp_pagetables = start;
171 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
172 memmove(&physmap[i], &physmap[i + 2],
173 sizeof(*physmap) * (*physmap_idx - i + 2));
177 mptramp_pagetables = trunc_page(boot_address) - AP_BOOTPT_SZ;
180 "Cannot find enough space for the initial AP page tables, placing them at %#x",
186 * Initialize the IPI handlers and start up the AP's.
193 /* Initialize the logical ID to APIC ID table. */
194 for (i = 0; i < MAXCPU; i++) {
195 cpu_apic_ids[i] = -1;
198 /* Install an inter-CPU IPI for TLB invalidation */
199 if (pmap_pcid_enabled) {
201 setidt(IPI_INVLTLB, pti ?
202 IDTVEC(invltlb_invpcid_pti_pti) :
203 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
205 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
206 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
207 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
208 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
210 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
211 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
212 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
213 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
214 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
215 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
218 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
219 SDT_SYSIGT, SEL_KPL, 0);
220 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
221 SDT_SYSIGT, SEL_KPL, 0);
222 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
223 SDT_SYSIGT, SEL_KPL, 0);
226 /* Install an inter-CPU IPI for cache invalidation. */
227 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
228 SDT_SYSIGT, SEL_KPL, 0);
230 /* Install an inter-CPU IPI for all-CPU rendezvous */
231 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
232 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
234 /* Install generic inter-CPU IPI handler */
235 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
236 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
238 /* Install an inter-CPU IPI for CPU stop/restart */
239 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
240 SDT_SYSIGT, SEL_KPL, 0);
242 /* Install an inter-CPU IPI for CPU suspend/resume */
243 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
244 SDT_SYSIGT, SEL_KPL, 0);
246 /* Set boot_cpu_id if needed. */
247 if (boot_cpu_id == -1) {
248 boot_cpu_id = PCPU_GET(apic_id);
249 cpu_info[boot_cpu_id].cpu_bsp = 1;
251 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
252 ("BSP's APIC ID doesn't match boot_cpu_id"));
254 /* Probe logical/physical core configuration. */
259 /* Start each Application Processor */
260 init_ops.start_all_aps();
262 set_interrupt_apic_ids();
267 * AP CPU's call this to initialize themselves.
275 int cpu, gsel_tss, x;
276 struct region_descriptor ap_gdt;
278 /* Set by the startup code for us to use */
281 /* Update microcode before doing anything else. */
285 common_tss[cpu] = common_tss[0];
286 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
288 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
290 /* The NMI stack runs on IST2. */
291 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
292 common_tss[cpu].tss_ist2 = (long) np;
294 /* The MC# stack runs on IST3. */
295 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
296 common_tss[cpu].tss_ist3 = (long) np;
298 /* The DB# stack runs on IST4. */
299 np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
300 common_tss[cpu].tss_ist4 = (long) np;
302 /* Prepare private GDT */
303 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
304 for (x = 0; x < NGDT; x++) {
305 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
306 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
307 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
309 ssdtosyssd(&gdt_segs[GPROC0_SEL],
310 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
311 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
312 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
313 lgdt(&ap_gdt); /* does magic intra-segment return */
315 /* Get per-cpu data */
318 /* prime data page for it to use */
319 pcpu_init(pc, cpu, sizeof(struct pcpu));
320 dpcpu_init(dpcpu, cpu);
321 pc->pc_apic_id = cpu_apic_ids[cpu];
322 pc->pc_prvspace = pc;
323 pc->pc_curthread = 0;
324 pc->pc_tssp = &common_tss[cpu];
325 pc->pc_commontssp = &common_tss[cpu];
327 pc->pc_pti_rsp0 = (((vm_offset_t)&pc->pc_pti_stack +
328 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful);
329 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
331 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
332 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
333 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
335 /* See comment in pmap_bootstrap(). */
336 pc->pc_pcid_next = PMAP_PCID_KERN + 2;
338 common_tss[cpu].tss_rsp0 = 0;
340 /* Save the per-cpu pointer for use by the NMI handler. */
341 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
342 np->np_pcpu = (register_t) pc;
344 /* Save the per-cpu pointer for use by the MC# handler. */
345 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
346 np->np_pcpu = (register_t) pc;
348 /* Save the per-cpu pointer for use by the DB# handler. */
349 np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
350 np->np_pcpu = (register_t) pc;
352 wrmsr(MSR_FSBASE, 0); /* User value */
353 wrmsr(MSR_GSBASE, (u_int64_t)pc);
354 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
359 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
363 * Set to a known state:
364 * Set by mpboot.s: CR0_PG, CR0_PE
365 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
368 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
371 amd64_conf_fast_syscall();
373 /* signal our startup to the BSP. */
376 /* Spin until the BSP releases the AP's. */
377 while (atomic_load_acq_int(&aps_ready) == 0)
380 init_secondary_tail();
383 /*******************************************************************
384 * local functions and data
388 * start each AP in our list
391 native_start_all_aps(void)
393 u_int64_t *pt4, *pt3, *pt2;
394 u_int32_t mpbioswarmvec;
398 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
400 /* copy the AP 1st level boot code */
401 bcopy(mptramp_start, (void *)PHYS_TO_DMAP(boot_address), bootMP_size);
403 /* Locate the page tables, they'll be below the trampoline */
404 pt4 = (uint64_t *)PHYS_TO_DMAP(mptramp_pagetables);
405 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
406 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
408 /* Create the initial 1GB replicated page tables */
409 for (i = 0; i < 512; i++) {
410 /* Each slot of the level 4 pages points to the same level 3 page */
411 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
412 pt4[i] |= PG_V | PG_RW | PG_U;
414 /* Each slot of the level 3 pages points to the same level 2 page */
415 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
416 pt3[i] |= PG_V | PG_RW | PG_U;
418 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
419 pt2[i] = i * (2 * 1024 * 1024);
420 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
423 /* save the current value of the warm-start vector */
424 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
425 outb(CMOS_REG, BIOS_RESET);
426 mpbiosreason = inb(CMOS_DATA);
428 /* setup a vector to our boot code */
429 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
430 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
431 outb(CMOS_REG, BIOS_RESET);
432 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
435 for (cpu = 1; cpu < mp_ncpus; cpu++) {
436 apic_id = cpu_apic_ids[cpu];
438 /* allocate and set up an idle stack data page */
439 bootstacks[cpu] = (void *)kmem_malloc(kstack_pages * PAGE_SIZE,
441 doublefault_stack = (char *)kmem_malloc(PAGE_SIZE, M_WAITOK |
443 mce_stack = (char *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
444 nmi_stack = (char *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
445 dbg_stack = (char *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
446 dpcpu = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
448 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
451 /* attempt to start the Application Processor */
452 if (!start_ap(apic_id)) {
453 /* restore the warmstart vector */
454 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
455 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
458 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
461 /* restore the warmstart vector */
462 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
464 outb(CMOS_REG, BIOS_RESET);
465 outb(CMOS_DATA, mpbiosreason);
467 /* number of APs actually started */
473 * This function starts the AP (application processor) identified
474 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
475 * to accomplish this. This is necessary because of the nuances
476 * of the different hardware we might encounter. It isn't pretty,
477 * but it seems to work.
480 start_ap(int apic_id)
485 /* calculate the vector */
486 vector = (boot_address >> 12) & 0xff;
488 /* used as a watchpoint to signal AP startup */
491 ipi_startup(apic_id, vector);
493 /* Wait up to 5 seconds for it to start. */
494 for (ms = 0; ms < 5000; ms++) {
496 return 1; /* return SUCCESS */
499 return 0; /* return FAILURE */
503 invltlb_invpcid_handler(void)
505 struct invpcid_descr d;
508 #ifdef COUNT_XINVLTLB_HITS
509 xhits_gbl[PCPU_GET(cpuid)]++;
510 #endif /* COUNT_XINVLTLB_HITS */
512 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
513 #endif /* COUNT_IPIS */
515 generation = smp_tlb_generation;
516 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
519 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
521 PCPU_SET(smp_tlb_done, generation);
525 invltlb_invpcid_pti_handler(void)
527 struct invpcid_descr d;
530 #ifdef COUNT_XINVLTLB_HITS
531 xhits_gbl[PCPU_GET(cpuid)]++;
532 #endif /* COUNT_XINVLTLB_HITS */
534 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
535 #endif /* COUNT_IPIS */
537 generation = smp_tlb_generation;
538 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
541 if (smp_tlb_pmap == kernel_pmap) {
543 * This invalidation actually needs to clear kernel
544 * mappings from the TLB in the current pmap, but
545 * since we were asked for the flush in the kernel
546 * pmap, achieve it by performing global flush.
548 invpcid(&d, INVPCID_CTXGLOB);
550 invpcid(&d, INVPCID_CTX);
551 d.pcid |= PMAP_PCID_USER_PT;
552 invpcid(&d, INVPCID_CTX);
554 PCPU_SET(smp_tlb_done, generation);
558 invltlb_pcid_handler(void)
561 uint32_t generation, pcid;
563 #ifdef COUNT_XINVLTLB_HITS
564 xhits_gbl[PCPU_GET(cpuid)]++;
565 #endif /* COUNT_XINVLTLB_HITS */
567 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
568 #endif /* COUNT_IPIS */
570 generation = smp_tlb_generation; /* Overlap with serialization */
571 if (smp_tlb_pmap == kernel_pmap) {
575 * The current pmap might not be equal to
576 * smp_tlb_pmap. The clearing of the pm_gen in
577 * pmap_invalidate_all() takes care of TLB
578 * invalidation when switching to the pmap on this
581 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
582 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
583 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
584 ucr3 = smp_tlb_pmap->pm_ucr3;
585 if (ucr3 != PMAP_NO_CR3) {
586 ucr3 |= PMAP_PCID_USER_PT | pcid;
587 pmap_pti_pcid_invalidate(ucr3, kcr3);
592 PCPU_SET(smp_tlb_done, generation);
596 invlpg_invpcid_handler(void)
598 struct invpcid_descr d;
601 #ifdef COUNT_XINVLTLB_HITS
602 xhits_pg[PCPU_GET(cpuid)]++;
603 #endif /* COUNT_XINVLTLB_HITS */
605 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
606 #endif /* COUNT_IPIS */
608 generation = smp_tlb_generation; /* Overlap with serialization */
609 invlpg(smp_tlb_addr1);
610 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
611 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
614 d.addr = smp_tlb_addr1;
615 invpcid(&d, INVPCID_ADDR);
617 PCPU_SET(smp_tlb_done, generation);
621 invlpg_pcid_handler(void)
627 #ifdef COUNT_XINVLTLB_HITS
628 xhits_pg[PCPU_GET(cpuid)]++;
629 #endif /* COUNT_XINVLTLB_HITS */
631 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
632 #endif /* COUNT_IPIS */
634 generation = smp_tlb_generation; /* Overlap with serialization */
635 invlpg(smp_tlb_addr1);
636 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
637 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
638 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
639 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
640 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
641 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
643 PCPU_SET(smp_tlb_done, generation);
647 invlrng_invpcid_handler(void)
649 struct invpcid_descr d;
650 vm_offset_t addr, addr2;
653 #ifdef COUNT_XINVLTLB_HITS
654 xhits_rng[PCPU_GET(cpuid)]++;
655 #endif /* COUNT_XINVLTLB_HITS */
657 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
658 #endif /* COUNT_IPIS */
660 addr = smp_tlb_addr1;
661 addr2 = smp_tlb_addr2;
662 generation = smp_tlb_generation; /* Overlap with serialization */
666 } while (addr < addr2);
667 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
668 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
671 d.addr = smp_tlb_addr1;
673 invpcid(&d, INVPCID_ADDR);
675 } while (d.addr < addr2);
677 PCPU_SET(smp_tlb_done, generation);
681 invlrng_pcid_handler(void)
683 vm_offset_t addr, addr2;
688 #ifdef COUNT_XINVLTLB_HITS
689 xhits_rng[PCPU_GET(cpuid)]++;
690 #endif /* COUNT_XINVLTLB_HITS */
692 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
693 #endif /* COUNT_IPIS */
695 addr = smp_tlb_addr1;
696 addr2 = smp_tlb_addr2;
697 generation = smp_tlb_generation; /* Overlap with serialization */
701 } while (addr < addr2);
702 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
703 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
704 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
705 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
706 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
707 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
709 PCPU_SET(smp_tlb_done, generation);