2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include "opt_user_ldt.h"
33 #include <machine/smptests.h>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
46 #include <sys/dkstat.h>
48 #include <sys/cons.h> /* cngetc() */
51 #include <vm/vm_param.h>
53 #include <vm/vm_kern.h>
54 #include <vm/vm_extern.h>
57 #include <vm/vm_map.h>
64 #include <machine/smp.h>
65 #include <machine/apic.h>
66 #include <machine/atomic.h>
67 #include <machine/cpufunc.h>
68 #include <machine/mpapic.h>
69 #include <machine/psl.h>
70 #include <machine/segments.h>
71 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
72 #include <machine/tss.h>
73 #include <machine/specialreg.h>
74 #include <machine/globaldata.h>
77 #include <machine/md_var.h> /* setidt() */
78 #include <i386/isa/icu.h> /* IPIs */
79 #include <i386/isa/intr_machdep.h> /* IPIs */
82 #if defined(TEST_DEFAULT_CONFIG)
83 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
85 #define MPFPS_MPFB1 mpfps->mpfb1
86 #endif /* TEST_DEFAULT_CONFIG */
88 #define WARMBOOT_TARGET 0
89 #define WARMBOOT_OFF (KERNBASE + 0x0467)
90 #define WARMBOOT_SEG (KERNBASE + 0x0469)
93 #define BIOS_BASE (0xe8000)
94 #define BIOS_SIZE (0x18000)
96 #define BIOS_BASE (0xf0000)
97 #define BIOS_SIZE (0x10000)
99 #define BIOS_COUNT (BIOS_SIZE/4)
101 #define CMOS_REG (0x70)
102 #define CMOS_DATA (0x71)
103 #define BIOS_RESET (0x0f)
104 #define BIOS_WARM (0x0a)
106 #define PROCENTRY_FLAG_EN 0x01
107 #define PROCENTRY_FLAG_BP 0x02
108 #define IOAPICENTRY_FLAG_EN 0x01
111 /* MP Floating Pointer Structure */
112 typedef struct MPFPS {
125 /* MP Configuration Table Header */
126 typedef struct MPCTH {
128 u_short base_table_length;
132 u_char product_id[12];
133 void *oem_table_pointer;
134 u_short oem_table_size;
137 u_short extended_table_length;
138 u_char extended_table_checksum;
143 typedef struct PROCENTRY {
148 u_long cpu_signature;
149 u_long feature_flags;
154 typedef struct BUSENTRY {
160 typedef struct IOAPICENTRY {
166 } *io_apic_entry_ptr;
168 typedef struct INTENTRY {
178 /* descriptions of MP basetable entries */
179 typedef struct BASETABLE_ENTRY {
186 * this code MUST be enabled here and in mpboot.s.
187 * it follows the very early stages of AP boot by placing values in CMOS ram.
188 * it NORMALLY will never be needed and thus the primitive method for enabling.
193 #if defined(CHECK_POINTS) && !defined(PC98)
194 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
195 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
197 #define CHECK_INIT(D); \
198 CHECK_WRITE(0x34, (D)); \
199 CHECK_WRITE(0x35, (D)); \
200 CHECK_WRITE(0x36, (D)); \
201 CHECK_WRITE(0x37, (D)); \
202 CHECK_WRITE(0x38, (D)); \
203 CHECK_WRITE(0x39, (D));
205 #define CHECK_PRINT(S); \
206 printf("%s: %d, %d, %d, %d, %d, %d\n", \
215 #else /* CHECK_POINTS */
217 #define CHECK_INIT(D)
218 #define CHECK_PRINT(S)
220 #endif /* CHECK_POINTS */
223 * Values to send to the POST hardware.
225 #define MP_BOOTADDRESS_POST 0x10
226 #define MP_PROBE_POST 0x11
227 #define MPTABLE_PASS1_POST 0x12
229 #define MP_START_POST 0x13
230 #define MP_ENABLE_POST 0x14
231 #define MPTABLE_PASS2_POST 0x15
233 #define START_ALL_APS_POST 0x16
234 #define INSTALL_AP_TRAMP_POST 0x17
235 #define START_AP_POST 0x18
237 #define MP_ANNOUNCE_POST 0x19
240 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
241 int current_postcode;
243 /** XXX FIXME: what system files declare these??? */
244 extern struct region_descriptor r_gdt, r_idt;
246 int bsp_apic_ready = 0; /* flags useability of BSP apic */
247 int mp_ncpus; /* # of CPUs, including BSP */
248 int mp_naps; /* # of Applications processors */
249 int mp_nbusses; /* # of busses */
250 int mp_napics; /* # of IO APICs */
251 int boot_cpu_id; /* designated BSP */
252 vm_offset_t cpu_apic_address;
253 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
256 u_int32_t cpu_apic_versions[NCPU];
257 u_int32_t io_apic_versions[NAPIC];
259 #ifdef APIC_INTR_DIAGNOSTIC
260 int apic_itrace_enter[32];
261 int apic_itrace_tryisrlock[32];
262 int apic_itrace_gotisrlock[32];
263 int apic_itrace_active[32];
264 int apic_itrace_masked[32];
265 int apic_itrace_noisrlock[32];
266 int apic_itrace_masked2[32];
267 int apic_itrace_unmask[32];
268 int apic_itrace_noforward[32];
269 int apic_itrace_leave[32];
270 int apic_itrace_enter2[32];
271 int apic_itrace_doreti[32];
272 int apic_itrace_splz[32];
273 int apic_itrace_eoi[32];
274 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
275 unsigned short apic_itrace_debugbuffer[32768];
276 int apic_itrace_debugbuffer_idx;
277 struct simplelock apic_itrace_debuglock;
281 #ifdef APIC_INTR_REORDER
283 volatile int *location;
285 } apic_isrbit_location[32];
288 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
291 * APIC ID logical/physical mapping structures.
292 * We oversize these to simplify boot-time config.
294 int cpu_num_to_apic_id[NAPICID];
295 int io_num_to_apic_id[NAPICID];
296 int apic_id_to_logical[NAPICID];
299 /* Bitmap of all available CPUs */
302 /* AP uses this during bootstrap. Do not staticize. */
306 /* Hotwire a 0->4MB V==P mapping */
307 extern pt_entry_t *KPTphys;
309 /* SMP page table page */
310 extern pt_entry_t *SMPpt;
312 struct pcb stoppcbs[NCPU];
314 int smp_started; /* has the system started? */
317 * Local data and functions.
320 static int mp_capable;
321 static u_int boot_address;
322 static u_int base_memory;
324 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
325 static mpfps_t mpfps;
326 static int search_for_sig(u_int32_t target, int count);
327 static void mp_enable(u_int boot_addr);
329 static int mptable_pass1(void);
330 static int mptable_pass2(void);
331 static void default_mp_table(int type);
332 static void fix_mp_table(void);
333 static void setup_apic_irq_mapping(void);
334 static void init_locks(void);
335 static int start_all_aps(u_int boot_addr);
336 static void install_ap_tramp(u_int boot_addr);
337 static int start_ap(int logicalCpu, u_int boot_addr);
338 static int apic_int_is_bus_type(int intr, int bus_type);
341 * Calculate usable address in base memory for AP trampoline code.
344 mp_bootaddress(u_int basemem)
346 POSTCODE(MP_BOOTADDRESS_POST);
348 base_memory = basemem * 1024; /* convert to bytes */
350 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
351 if ((base_memory - boot_address) < bootMP_size)
352 boot_address -= 4096; /* not enough, lower by 4k */
359 * Look for an Intel MP spec table (ie, SMP capable hardware).
368 POSTCODE(MP_PROBE_POST);
370 /* see if EBDA exists */
371 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
372 /* search first 1K of EBDA */
373 target = (u_int32_t) (segment << 4);
374 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
377 /* last 1K of base memory, effective 'top of base' passed in */
378 target = (u_int32_t) (base_memory - 0x400);
379 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
383 /* search the BIOS */
384 target = (u_int32_t) BIOS_BASE;
385 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
394 /* calculate needed resources */
397 panic("you must reconfigure your kernel");
399 /* flag fact that we are running multiple processors */
406 * Startup the SMP processors.
411 POSTCODE(MP_START_POST);
413 /* look for MP capable motherboard */
415 mp_enable(boot_address);
417 panic("MP hardware not found!");
422 * Print various information about the SMP system hardware and setup.
429 POSTCODE(MP_ANNOUNCE_POST);
431 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
432 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
433 printf(", version: 0x%08x", cpu_apic_versions[0]);
434 printf(", at 0x%08x\n", cpu_apic_address);
435 for (x = 1; x <= mp_naps; ++x) {
436 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
437 printf(", version: 0x%08x", cpu_apic_versions[x]);
438 printf(", at 0x%08x\n", cpu_apic_address);
442 for (x = 0; x < mp_napics; ++x) {
443 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
444 printf(", version: 0x%08x", io_apic_versions[x]);
445 printf(", at 0x%08x\n", io_apic_address[x]);
448 printf(" Warning: APIC I/O disabled\n");
453 * AP cpu's call this to sync up protected mode.
459 int x, myid = bootAP;
461 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
462 gdt_segs[GPROC0_SEL].ssd_base =
463 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
464 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid];
466 for (x = 0; x < NGDT; x++) {
467 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
470 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
471 r_gdt.rd_base = (int) &gdt[myid * NGDT];
472 lgdt(&r_gdt); /* does magic intra-segment return */
478 currentldt = _default_ldt;
481 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
482 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
483 common_tss.tss_esp0 = 0; /* not used until after switch */
484 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
485 common_tss.tss_ioopt = (sizeof common_tss) << 16;
486 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
487 common_tssd = *tss_gdt;
490 load_cr0(0x8005003b); /* XXX! */
498 * Final configuration of the BSP's local APIC:
499 * - disable 'pic mode'.
500 * - disable 'virtual wire mode'.
504 bsp_apic_configure(void)
509 /* leave 'pic mode' if necessary */
511 outb(0x22, 0x70); /* select IMCR */
512 byte = inb(0x23); /* current contents */
513 byte |= 0x01; /* mask external INTR */
514 outb(0x23, byte); /* disconnect 8259s/NMI */
517 /* mask lint0 (the 8259 'virtual wire' connection) */
518 temp = lapic.lvt_lint0;
519 temp |= APIC_LVT_M; /* set the mask */
520 lapic.lvt_lint0 = temp;
522 /* setup lint1 to handle NMI */
523 temp = lapic.lvt_lint1;
524 temp &= ~APIC_LVT_M; /* clear the mask */
525 lapic.lvt_lint1 = temp;
528 apic_dump("bsp_apic_configure()");
533 /*******************************************************************
534 * local functions and data
538 * start the SMP system
541 mp_enable(u_int boot_addr)
549 POSTCODE(MP_ENABLE_POST);
551 /* turn on 4MB of V == P addressing so we can get to MP table */
552 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
555 /* examine the MP table for needed info, uses physical addresses */
561 /* can't process default configs till the CPU APIC is pmapped */
565 /* post scan cleanup */
567 setup_apic_irq_mapping();
571 /* fill the LOGICAL io_apic_versions table */
572 for (apic = 0; apic < mp_napics; ++apic) {
573 ux = io_apic_read(apic, IOAPIC_VER);
574 io_apic_versions[apic] = ux;
577 /* program each IO APIC in the system */
578 for (apic = 0; apic < mp_napics; ++apic)
579 if (io_apic_setup(apic) < 0)
580 panic("IO APIC setup failure");
582 /* install a 'Spurious INTerrupt' vector */
583 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
584 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
586 /* install an inter-CPU IPI for TLB invalidation */
587 setidt(XINVLTLB_OFFSET, Xinvltlb,
588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
591 /* install an inter-CPU IPI for reading processor state */
592 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
593 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
596 /* install an inter-CPU IPI for all-CPU rendezvous */
597 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
598 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
600 /* install an inter-CPU IPI for forcing an additional software trap */
601 setidt(XCPUAST_OFFSET, Xcpuast,
602 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
604 /* install an inter-CPU IPI for interrupt forwarding */
605 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
608 /* install an inter-CPU IPI for CPU stop/restart */
609 setidt(XCPUSTOP_OFFSET, Xcpustop,
610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
612 #if defined(TEST_TEST1)
613 /* install a "fake hardware INTerrupt" vector */
614 setidt(XTEST1_OFFSET, Xtest1,
615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
616 #endif /** TEST_TEST1 */
620 /* initialize all SMP locks */
623 /* start each Application Processor */
624 start_all_aps(boot_addr);
627 * The init process might be started on a different CPU now,
628 * and the boot CPU might not call prepare_usermode to get
629 * cr0 correctly configured. Thus we initialize cr0 here.
631 load_cr0(rcr0() | CR0_WP | CR0_AM);
636 * look for the MP spec signature
639 /* string defined by the Intel MP Spec as identifying the MP table */
640 #define MP_SIG 0x5f504d5f /* _MP_ */
641 #define NEXT(X) ((X) += 4)
643 search_for_sig(u_int32_t target, int count)
646 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
648 for (x = 0; x < count; NEXT(x))
649 if (addr[x] == MP_SIG)
650 /* make array index a byte index */
651 return (target + (x * sizeof(u_int32_t)));
657 static basetable_entry basetable_entry_types[] =
659 {0, 20, "Processor"},
666 typedef struct BUSDATA {
668 enum busTypes bus_type;
671 typedef struct INTDATA {
681 typedef struct BUSTYPENAME {
686 static bus_type_name bus_type_table[] =
692 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
699 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
703 {UNKNOWN_BUSTYPE, "---"},
704 {UNKNOWN_BUSTYPE, "---"},
706 {UNKNOWN_BUSTYPE, "---"}
708 /* from MP spec v1.4, table 5-1 */
709 static int default_data[7][5] =
711 /* nbus, id0, type0, id1, type1 */
712 {1, 0, ISA, 255, 255},
713 {1, 0, EISA, 255, 255},
714 {1, 0, EISA, 255, 255},
715 {1, 0, MCA, 255, 255},
717 {2, 0, EISA, 1, PCI},
723 static bus_datum bus_data[NBUS];
725 /* the IO INT data, one entry per possible APIC INTerrupt */
726 static io_int io_apic_ints[NINTR];
730 static int processor_entry __P((proc_entry_ptr entry, int cpu));
731 static int bus_entry __P((bus_entry_ptr entry, int bus));
732 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
733 static int int_entry __P((int_entry_ptr entry, int intr));
734 static int lookup_bus_type __P((char *name));
738 * 1st pass on motherboard's Intel MP specification table.
744 * cpu_apic_address (common to all CPUs)
762 POSTCODE(MPTABLE_PASS1_POST);
766 /* clear various tables */
767 for (x = 0; x < NAPICID; ++x) {
768 io_apic_address[x] = ~0; /* IO APIC address table */
771 /* init everything to empty */
777 /* check for use of 'default' configuration */
778 if (MPFPS_MPFB1 != 0) {
779 /* use default addresses */
780 cpu_apic_address = DEFAULT_APIC_BASE;
781 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
783 /* fill in with defaults */
784 mp_naps = 2; /* includes BSP */
785 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
792 if ((cth = mpfps->pap) == 0)
793 panic("MP Configuration Table Header MISSING!");
795 cpu_apic_address = (vm_offset_t) cth->apic_address;
797 /* walk the table, recording info of interest */
798 totalSize = cth->base_table_length - sizeof(struct MPCTH);
799 position = (u_char *) cth + sizeof(struct MPCTH);
800 count = cth->entry_count;
803 switch (type = *(u_char *) position) {
804 case 0: /* processor_entry */
805 if (((proc_entry_ptr)position)->cpu_flags
809 case 1: /* bus_entry */
812 case 2: /* io_apic_entry */
813 if (((io_apic_entry_ptr)position)->apic_flags
814 & IOAPICENTRY_FLAG_EN)
815 io_apic_address[mp_napics++] =
816 (vm_offset_t)((io_apic_entry_ptr)
817 position)->apic_address;
819 case 3: /* int_entry */
822 case 4: /* int_entry */
825 panic("mpfps Base Table HOSED!");
829 totalSize -= basetable_entry_types[type].length;
830 (u_char*)position += basetable_entry_types[type].length;
834 /* qualify the numbers */
835 if (mp_naps > NCPU) {
836 printf("Warning: only using %d of %d available CPUs!\n",
840 if (mp_nbusses > NBUS) {
841 printf("found %d busses, increase NBUS\n", mp_nbusses);
844 if (mp_napics > NAPIC) {
845 printf("found %d apics, increase NAPIC\n", mp_napics);
848 if (nintrs > NINTR) {
849 printf("found %d intrs, increase NINTR\n", nintrs);
855 * This is also used as a counter while starting the APs.
859 --mp_naps; /* subtract the BSP */
866 * 2nd pass on motherboard's Intel MP specification table.
870 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
871 * CPU_TO_ID(N), logical CPU to APIC ID table
872 * IO_TO_ID(N), logical IO to APIC ID table
885 int apic, bus, cpu, intr;
887 POSTCODE(MPTABLE_PASS2_POST);
889 /* clear various tables */
890 for (x = 0; x < NAPICID; ++x) {
891 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
892 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
893 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
896 /* clear bus data table */
897 for (x = 0; x < NBUS; ++x)
898 bus_data[x].bus_id = 0xff;
900 /* clear IO APIC INT table */
901 for (x = 0; x < NINTR; ++x) {
902 io_apic_ints[x].int_type = 0xff;
903 io_apic_ints[x].int_vector = 0xff;
906 /* setup the cpu/apic mapping arrays */
909 /* record whether PIC or virtual-wire mode */
910 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
912 /* check for use of 'default' configuration */
913 if (MPFPS_MPFB1 != 0)
914 return MPFPS_MPFB1; /* return default configuration type */
916 if ((cth = mpfps->pap) == 0)
917 panic("MP Configuration Table Header MISSING!");
919 /* walk the table, recording info of interest */
920 totalSize = cth->base_table_length - sizeof(struct MPCTH);
921 position = (u_char *) cth + sizeof(struct MPCTH);
922 count = cth->entry_count;
923 apic = bus = intr = 0;
924 cpu = 1; /* pre-count the BSP */
927 switch (type = *(u_char *) position) {
929 if (processor_entry(position, cpu))
933 if (bus_entry(position, bus))
937 if (io_apic_entry(position, apic))
941 if (int_entry(position, intr))
945 /* int_entry(position); */
948 panic("mpfps Base Table HOSED!");
952 totalSize -= basetable_entry_types[type].length;
953 (u_char *) position += basetable_entry_types[type].length;
956 if (boot_cpu_id == -1)
957 panic("NO BSP found!");
959 /* report fact that its NOT a default configuration */
965 assign_apic_irq(int apic, int intpin, int irq)
969 if (int_to_apicintpin[irq].ioapic != -1)
970 panic("assign_apic_irq: inconsistent table");
972 int_to_apicintpin[irq].ioapic = apic;
973 int_to_apicintpin[irq].int_pin = intpin;
974 int_to_apicintpin[irq].apic_address = ioapic[apic];
975 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
977 for (x = 0; x < nintrs; x++) {
978 if ((io_apic_ints[x].int_type == 0 ||
979 io_apic_ints[x].int_type == 3) &&
980 io_apic_ints[x].int_vector == 0xff &&
981 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
982 io_apic_ints[x].dst_apic_int == intpin)
983 io_apic_ints[x].int_vector = irq;
988 revoke_apic_irq(int irq)
994 if (int_to_apicintpin[irq].ioapic == -1)
995 panic("assign_apic_irq: inconsistent table");
997 oldapic = int_to_apicintpin[irq].ioapic;
998 oldintpin = int_to_apicintpin[irq].int_pin;
1000 int_to_apicintpin[irq].ioapic = -1;
1001 int_to_apicintpin[irq].int_pin = 0;
1002 int_to_apicintpin[irq].apic_address = NULL;
1003 int_to_apicintpin[irq].redirindex = 0;
1005 for (x = 0; x < nintrs; x++) {
1006 if ((io_apic_ints[x].int_type == 0 ||
1007 io_apic_ints[x].int_type == 3) &&
1008 io_apic_ints[x].int_vector == 0xff &&
1009 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1010 io_apic_ints[x].dst_apic_int == oldintpin)
1011 io_apic_ints[x].int_vector = 0xff;
1016 * parse an Intel MP specification table
1023 int bus_0 = 0; /* Stop GCC warning */
1024 int bus_pci = 0; /* Stop GCC warning */
1028 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1029 * did it wrong. The MP spec says that when more than 1 PCI bus
1030 * exists the BIOS must begin with bus entries for the PCI bus and use
1031 * actual PCI bus numbering. This implies that when only 1 PCI bus
1032 * exists the BIOS can choose to ignore this ordering, and indeed many
1033 * MP motherboards do ignore it. This causes a problem when the PCI
1034 * sub-system makes requests of the MP sub-system based on PCI bus
1035 * numbers. So here we look for the situation and renumber the
1036 * busses and associated INTs in an effort to "make it right".
1039 /* find bus 0, PCI bus, count the number of PCI busses */
1040 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1041 if (bus_data[x].bus_id == 0) {
1044 if (bus_data[x].bus_type == PCI) {
1050 * bus_0 == slot of bus with ID of 0
1051 * bus_pci == slot of last PCI bus encountered
1054 /* check the 1 PCI bus case for sanity */
1055 if (num_pci_bus == 1) {
1057 /* if it is number 0 all is well */
1058 if (bus_data[bus_pci].bus_id == 0)
1061 /* mis-numbered, swap with whichever bus uses slot 0 */
1063 /* swap the bus entry types */
1064 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1065 bus_data[bus_0].bus_type = PCI;
1067 /* swap each relavant INTerrupt entry */
1068 id = bus_data[bus_pci].bus_id;
1069 for (x = 0; x < nintrs; ++x) {
1070 if (io_apic_ints[x].src_bus_id == id) {
1071 io_apic_ints[x].src_bus_id = 0;
1073 else if (io_apic_ints[x].src_bus_id == 0) {
1074 io_apic_ints[x].src_bus_id = id;
1081 /* Assign low level interrupt handlers */
1083 setup_apic_irq_mapping(void)
1089 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1090 int_to_apicintpin[x].ioapic = -1;
1091 int_to_apicintpin[x].int_pin = 0;
1092 int_to_apicintpin[x].apic_address = NULL;
1093 int_to_apicintpin[x].redirindex = 0;
1096 /* First assign ISA/EISA interrupts */
1097 for (x = 0; x < nintrs; x++) {
1098 int_vector = io_apic_ints[x].src_bus_irq;
1099 if (int_vector < APIC_INTMAPSIZE &&
1100 io_apic_ints[x].int_vector == 0xff &&
1101 int_to_apicintpin[int_vector].ioapic == -1 &&
1102 (apic_int_is_bus_type(x, ISA) ||
1103 apic_int_is_bus_type(x, EISA)) &&
1104 io_apic_ints[x].int_type == 0) {
1105 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1106 io_apic_ints[x].dst_apic_int,
1111 /* Assign interrupts on first 24 intpins on IOAPIC #0 */
1112 for (x = 0; x < nintrs; x++) {
1113 int_vector = io_apic_ints[x].dst_apic_int;
1114 if (int_vector < APIC_INTMAPSIZE &&
1115 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1116 io_apic_ints[x].int_vector == 0xff &&
1117 int_to_apicintpin[int_vector].ioapic == -1 &&
1118 (io_apic_ints[x].int_type == 0 ||
1119 io_apic_ints[x].int_type == 3)) {
1121 io_apic_ints[x].dst_apic_int,
1126 * Assign interrupts for remaining intpins.
1127 * Skip IOAPIC #0 intpin 0 if the type is ExtInt, since this indicates
1128 * that an entry for ISA/EISA irq 0 exist, and a fallback to mixed mode
1129 * due to 8254 interrupts not being delivered can reuse that low level
1130 * interrupt handler.
1133 while (int_vector < APIC_INTMAPSIZE &&
1134 int_to_apicintpin[int_vector].ioapic != -1)
1136 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1137 if ((io_apic_ints[x].int_type == 0 ||
1138 (io_apic_ints[x].int_type == 3 &&
1139 (io_apic_ints[x].dst_apic_id != IO_TO_ID(0) ||
1140 io_apic_ints[x].dst_apic_int != 0))) &&
1141 io_apic_ints[x].int_vector == 0xff) {
1142 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1143 io_apic_ints[x].dst_apic_int,
1146 while (int_vector < APIC_INTMAPSIZE &&
1147 int_to_apicintpin[int_vector].ioapic != -1)
1155 processor_entry(proc_entry_ptr entry, int cpu)
1157 /* check for usability */
1158 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1161 /* check for BSP flag */
1162 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1163 boot_cpu_id = entry->apic_id;
1164 CPU_TO_ID(0) = entry->apic_id;
1165 ID_TO_CPU(entry->apic_id) = 0;
1166 return 0; /* its already been counted */
1169 /* add another AP to list, if less than max number of CPUs */
1170 else if (cpu < NCPU) {
1171 CPU_TO_ID(cpu) = entry->apic_id;
1172 ID_TO_CPU(entry->apic_id) = cpu;
1181 bus_entry(bus_entry_ptr entry, int bus)
1186 /* encode the name into an index */
1187 for (x = 0; x < 6; ++x) {
1188 if ((c = entry->bus_type[x]) == ' ')
1194 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1195 panic("unknown bus type: '%s'", name);
1197 bus_data[bus].bus_id = entry->bus_id;
1198 bus_data[bus].bus_type = x;
1205 io_apic_entry(io_apic_entry_ptr entry, int apic)
1207 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1210 IO_TO_ID(apic) = entry->apic_id;
1211 ID_TO_IO(entry->apic_id) = apic;
1218 lookup_bus_type(char *name)
1222 for (x = 0; x < MAX_BUSTYPE; ++x)
1223 if (strcmp(bus_type_table[x].name, name) == 0)
1224 return bus_type_table[x].type;
1226 return UNKNOWN_BUSTYPE;
1231 int_entry(int_entry_ptr entry, int intr)
1235 io_apic_ints[intr].int_type = entry->int_type;
1236 io_apic_ints[intr].int_flags = entry->int_flags;
1237 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1238 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1239 if (entry->dst_apic_id == 255) {
1240 /* This signal goes to all IO APICS. Select an IO APIC
1241 with sufficient number of interrupt pins */
1242 for (apic = 0; apic < mp_napics; apic++)
1243 if (((io_apic_read(apic, IOAPIC_VER) &
1244 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1245 entry->dst_apic_int)
1247 if (apic < mp_napics)
1248 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1250 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1252 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1253 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1260 apic_int_is_bus_type(int intr, int bus_type)
1264 for (bus = 0; bus < mp_nbusses; ++bus)
1265 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1266 && ((int) bus_data[bus].bus_type == bus_type))
1274 * Given a traditional ISA INT mask, return an APIC mask.
1277 isa_apic_mask(u_int isa_mask)
1282 #if defined(SKIP_IRQ15_REDIRECT)
1283 if (isa_mask == (1 << 15)) {
1284 printf("skipping ISA IRQ15 redirect\n");
1287 #endif /* SKIP_IRQ15_REDIRECT */
1289 isa_irq = ffs(isa_mask); /* find its bit position */
1290 if (isa_irq == 0) /* doesn't exist */
1292 --isa_irq; /* make it zero based */
1294 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1298 return (1 << apic_pin); /* convert pin# to a mask */
1303 * Determine which APIC pin an ISA/EISA INT is attached to.
1305 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1306 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1307 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1308 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1310 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1312 isa_apic_irq(int isa_irq)
1316 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1317 if (INTTYPE(intr) == 0) { /* standard INT */
1318 if (SRCBUSIRQ(intr) == isa_irq) {
1319 if (apic_int_is_bus_type(intr, ISA) ||
1320 apic_int_is_bus_type(intr, EISA))
1321 return INTIRQ(intr); /* found */
1325 return -1; /* NOT found */
1330 * Determine which APIC pin a PCI INT is attached to.
1332 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1333 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1334 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1336 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1340 --pciInt; /* zero based */
1342 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1343 if ((INTTYPE(intr) == 0) /* standard INT */
1344 && (SRCBUSID(intr) == pciBus)
1345 && (SRCBUSDEVICE(intr) == pciDevice)
1346 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1347 if (apic_int_is_bus_type(intr, PCI))
1348 return INTIRQ(intr); /* exact match */
1350 return -1; /* NOT found */
1354 next_apic_irq(int irq)
1361 for (intr = 0; intr < nintrs; intr++) {
1362 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1364 bus = SRCBUSID(intr);
1365 bustype = apic_bus_type(bus);
1366 if (bustype != ISA &&
1372 if (intr >= nintrs) {
1375 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1376 if (INTTYPE(ointr) != 0)
1378 if (bus != SRCBUSID(ointr))
1380 if (bustype == PCI) {
1381 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1383 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1386 if (bustype == ISA || bustype == EISA) {
1387 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1390 if (INTPIN(intr) == INTPIN(ointr))
1394 if (ointr >= nintrs) {
1397 return INTIRQ(ointr);
1411 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1414 * Exactly what this means is unclear at this point. It is a solution
1415 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1416 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1417 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1421 undirect_isa_irq(int rirq)
1425 printf("Freeing redirected ISA irq %d.\n", rirq);
1426 /** FIXME: tickle the MB redirector chip */
1430 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1437 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1440 undirect_pci_irq(int rirq)
1444 printf("Freeing redirected PCI irq %d.\n", rirq);
1446 /** FIXME: tickle the MB redirector chip */
1450 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1458 * given a bus ID, return:
1459 * the bus type if found
1463 apic_bus_type(int id)
1467 for (x = 0; x < mp_nbusses; ++x)
1468 if (bus_data[x].bus_id == id)
1469 return bus_data[x].bus_type;
1476 * given a LOGICAL APIC# and pin#, return:
1477 * the associated src bus ID if found
1481 apic_src_bus_id(int apic, int pin)
1485 /* search each of the possible INTerrupt sources */
1486 for (x = 0; x < nintrs; ++x)
1487 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1488 (pin == io_apic_ints[x].dst_apic_int))
1489 return (io_apic_ints[x].src_bus_id);
1491 return -1; /* NOT found */
1496 * given a LOGICAL APIC# and pin#, return:
1497 * the associated src bus IRQ if found
1501 apic_src_bus_irq(int apic, int pin)
1505 for (x = 0; x < nintrs; x++)
1506 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1507 (pin == io_apic_ints[x].dst_apic_int))
1508 return (io_apic_ints[x].src_bus_irq);
1510 return -1; /* NOT found */
1515 * given a LOGICAL APIC# and pin#, return:
1516 * the associated INTerrupt type if found
1520 apic_int_type(int apic, int pin)
1524 /* search each of the possible INTerrupt sources */
1525 for (x = 0; x < nintrs; ++x)
1526 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1527 (pin == io_apic_ints[x].dst_apic_int))
1528 return (io_apic_ints[x].int_type);
1530 return -1; /* NOT found */
1534 apic_irq(int apic, int pin)
1539 for (x = 0; x < nintrs; ++x)
1540 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1541 (pin == io_apic_ints[x].dst_apic_int)) {
1542 res = io_apic_ints[x].int_vector;
1545 if (apic != int_to_apicintpin[res].ioapic)
1546 panic("apic_irq: inconsistent table");
1547 if (pin != int_to_apicintpin[res].int_pin)
1548 panic("apic_irq inconsistent table (2)");
1556 * given a LOGICAL APIC# and pin#, return:
1557 * the associated trigger mode if found
1561 apic_trigger(int apic, int pin)
1565 /* search each of the possible INTerrupt sources */
1566 for (x = 0; x < nintrs; ++x)
1567 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1568 (pin == io_apic_ints[x].dst_apic_int))
1569 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1571 return -1; /* NOT found */
1576 * given a LOGICAL APIC# and pin#, return:
1577 * the associated 'active' level if found
1581 apic_polarity(int apic, int pin)
1585 /* search each of the possible INTerrupt sources */
1586 for (x = 0; x < nintrs; ++x)
1587 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1588 (pin == io_apic_ints[x].dst_apic_int))
1589 return (io_apic_ints[x].int_flags & 0x03);
1591 return -1; /* NOT found */
1596 * set data according to MP defaults
1597 * FIXME: probably not complete yet...
1600 default_mp_table(int type)
1603 #if defined(APIC_IO)
1607 #endif /* APIC_IO */
1610 printf(" MP default config type: %d\n", type);
1613 printf(" bus: ISA, APIC: 82489DX\n");
1616 printf(" bus: EISA, APIC: 82489DX\n");
1619 printf(" bus: EISA, APIC: 82489DX\n");
1622 printf(" bus: MCA, APIC: 82489DX\n");
1625 printf(" bus: ISA+PCI, APIC: Integrated\n");
1628 printf(" bus: EISA+PCI, APIC: Integrated\n");
1631 printf(" bus: MCA+PCI, APIC: Integrated\n");
1634 printf(" future type\n");
1640 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1641 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1644 CPU_TO_ID(0) = boot_cpu_id;
1645 ID_TO_CPU(boot_cpu_id) = 0;
1647 /* one and only AP */
1648 CPU_TO_ID(1) = ap_cpu_id;
1649 ID_TO_CPU(ap_cpu_id) = 1;
1651 #if defined(APIC_IO)
1652 /* one and only IO APIC */
1653 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1656 * sanity check, refer to MP spec section 3.6.6, last paragraph
1657 * necessary as some hardware isn't properly setting up the IO APIC
1659 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1660 if (io_apic_id != 2) {
1662 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1663 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1664 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
1665 ux &= ~APIC_ID_MASK; /* clear the ID field */
1666 ux |= 0x02000000; /* set it to '2' */
1667 io_apic_write(0, IOAPIC_ID, ux); /* write new value */
1668 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
1669 if ((ux & APIC_ID_MASK) != 0x02000000)
1670 panic("can't control IO APIC ID, reg: 0x%08x", ux);
1673 IO_TO_ID(0) = io_apic_id;
1674 ID_TO_IO(io_apic_id) = 0;
1675 #endif /* APIC_IO */
1677 /* fill out bus entries */
1686 bus_data[0].bus_id = default_data[type - 1][1];
1687 bus_data[0].bus_type = default_data[type - 1][2];
1688 bus_data[1].bus_id = default_data[type - 1][3];
1689 bus_data[1].bus_type = default_data[type - 1][4];
1692 /* case 4: case 7: MCA NOT supported */
1693 default: /* illegal/reserved */
1694 panic("BAD default MP config: %d", type);
1698 #if defined(APIC_IO)
1699 /* general cases from MP v1.4, table 5-2 */
1700 for (pin = 0; pin < 16; ++pin) {
1701 io_apic_ints[pin].int_type = 0;
1702 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1703 io_apic_ints[pin].src_bus_id = 0;
1704 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1705 io_apic_ints[pin].dst_apic_id = io_apic_id;
1706 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1709 /* special cases from MP v1.4, table 5-2 */
1711 io_apic_ints[2].int_type = 0xff; /* N/C */
1712 io_apic_ints[13].int_type = 0xff; /* N/C */
1713 #if !defined(APIC_MIXED_MODE)
1715 panic("sorry, can't support type 2 default yet");
1716 #endif /* APIC_MIXED_MODE */
1719 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1722 io_apic_ints[0].int_type = 0xff; /* N/C */
1724 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1725 #endif /* APIC_IO */
1730 * initialize all the SMP locks
1733 /* critical region around IO APIC, apic_imen */
1734 struct simplelock imen_lock;
1736 /* critical region around splxx(), cpl, cml, cil, ipending */
1737 struct simplelock cpl_lock;
1739 /* Make FAST_INTR() routines sequential */
1740 struct simplelock fast_intr_lock;
1742 /* critical region around INTR() routines */
1743 struct simplelock intr_lock;
1745 /* lock regions protected in UP kernel via cli/sti */
1746 struct simplelock mpintr_lock;
1748 /* lock region used by kernel profiling */
1749 struct simplelock mcount_lock;
1752 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1753 struct simplelock com_lock;
1754 #endif /* USE_COMLOCK */
1756 #ifdef USE_CLOCKLOCK
1757 /* lock regions around the clock hardware */
1758 struct simplelock clock_lock;
1759 #endif /* USE_CLOCKLOCK */
1761 /* lock around the MP rendezvous */
1762 static struct simplelock smp_rv_lock;
1768 * Get the initial mp_lock with a count of 1 for the BSP.
1769 * This uses a LOGICAL cpu ID, ie BSP == 0.
1771 mp_lock = 0x00000001;
1773 /* ISR uses its own "giant lock" */
1774 isr_lock = FREE_LOCK;
1776 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1777 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1780 s_lock_init((struct simplelock*)&mpintr_lock);
1782 s_lock_init((struct simplelock*)&mcount_lock);
1784 s_lock_init((struct simplelock*)&fast_intr_lock);
1785 s_lock_init((struct simplelock*)&intr_lock);
1786 s_lock_init((struct simplelock*)&imen_lock);
1787 s_lock_init((struct simplelock*)&cpl_lock);
1788 s_lock_init(&smp_rv_lock);
1791 s_lock_init((struct simplelock*)&com_lock);
1792 #endif /* USE_COMLOCK */
1793 #ifdef USE_CLOCKLOCK
1794 s_lock_init((struct simplelock*)&clock_lock);
1795 #endif /* USE_CLOCKLOCK */
1799 /* Wait for all APs to be fully initialized */
1800 extern int wait_ap(unsigned int);
1803 * start each AP in our list
1806 start_all_aps(u_int boot_addr)
1809 u_char mpbiosreason;
1810 u_long mpbioswarmvec;
1811 struct globaldata *gd;
1814 POSTCODE(START_ALL_APS_POST);
1816 /* initialize BSP's local APIC */
1820 /* install the AP 1st level boot code */
1821 install_ap_tramp(boot_addr);
1824 /* save the current value of the warm-start vector */
1825 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1827 outb(CMOS_REG, BIOS_RESET);
1828 mpbiosreason = inb(CMOS_DATA);
1831 /* record BSP in CPU map */
1834 /* set up 0 -> 4MB P==V mapping for AP boot */
1835 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
1839 for (x = 1; x <= mp_naps; ++x) {
1841 /* This is a bit verbose, it will go away soon. */
1843 /* first page of AP's private space */
1844 pg = x * i386_btop(sizeof(struct privatespace));
1846 /* allocate a new private data page */
1847 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1849 /* wire it into the private page table page */
1850 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1852 /* allocate and set up an idle stack data page */
1853 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1854 for (i = 0; i < UPAGES; i++)
1855 SMPpt[pg + 5 + i] = (pt_entry_t)
1856 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1858 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */
1859 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */
1860 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */
1861 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */
1863 /* prime data page for it to use */
1865 gd->gd_cpu_lockid = x << 24;
1866 gd->gd_prv_CMAP1 = &SMPpt[pg + 1];
1867 gd->gd_prv_CMAP2 = &SMPpt[pg + 2];
1868 gd->gd_prv_CMAP3 = &SMPpt[pg + 3];
1869 gd->gd_prv_PMAP1 = &SMPpt[pg + 4];
1870 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1;
1871 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2;
1872 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3;
1873 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1;
1875 /* setup a vector to our boot code */
1876 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1877 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1879 outb(CMOS_REG, BIOS_RESET);
1880 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1883 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
1886 /* attempt to start the Application Processor */
1887 CHECK_INIT(99); /* setup checkpoints */
1888 if (!start_ap(x, boot_addr)) {
1889 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1890 CHECK_PRINT("trace"); /* show checkpoints */
1891 /* better panic as the AP may be running loose */
1892 printf("panic y/n? [y] ");
1893 if (cngetc() != 'n')
1896 CHECK_PRINT("trace"); /* show checkpoints */
1898 /* record its version info */
1899 cpu_apic_versions[x] = cpu_apic_versions[0];
1901 all_cpus |= (1 << x); /* record AP in CPU map */
1904 /* build our map of 'other' CPUs */
1905 other_cpus = all_cpus & ~(1 << cpuid);
1907 /* fill in our (BSP) APIC version */
1908 cpu_apic_versions[0] = lapic.version;
1910 /* restore the warmstart vector */
1911 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1913 outb(CMOS_REG, BIOS_RESET);
1914 outb(CMOS_DATA, mpbiosreason);
1918 * Set up the idle context for the BSP. Similar to above except
1919 * that some was done by locore, some by pmap.c and some is implicit
1920 * because the BSP is cpu#0 and the page is initially zero, and also
1921 * because we can refer to variables by name on the BSP..
1924 /* Allocate and setup BSP idle stack */
1925 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
1926 for (i = 0; i < UPAGES; i++)
1927 SMPpt[5 + i] = (pt_entry_t)
1928 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1933 /* number of APs actually started */
1934 return mp_ncpus - 1;
1939 * load the 1st level AP boot code into base memory.
1942 /* targets for relocation */
1943 extern void bigJump(void);
1944 extern void bootCodeSeg(void);
1945 extern void bootDataSeg(void);
1946 extern void MPentry(void);
1947 extern u_int MP_GDT;
1948 extern u_int mp_gdtbase;
1951 install_ap_tramp(u_int boot_addr)
1954 int size = *(int *) ((u_long) & bootMP_size);
1955 u_char *src = (u_char *) ((u_long) bootMP);
1956 u_char *dst = (u_char *) boot_addr + KERNBASE;
1957 u_int boot_base = (u_int) bootMP;
1962 POSTCODE(INSTALL_AP_TRAMP_POST);
1964 for (x = 0; x < size; ++x)
1968 * modify addresses in code we just moved to basemem. unfortunately we
1969 * need fairly detailed info about mpboot.s for this to work. changes
1970 * to mpboot.s might require changes here.
1973 /* boot code is located in KERNEL space */
1974 dst = (u_char *) boot_addr + KERNBASE;
1976 /* modify the lgdt arg */
1977 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1978 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1980 /* modify the ljmp target for MPentry() */
1981 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1982 *dst32 = ((u_int) MPentry - KERNBASE);
1984 /* modify the target for boot code segment */
1985 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1986 dst8 = (u_int8_t *) (dst16 + 1);
1987 *dst16 = (u_int) boot_addr & 0xffff;
1988 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1990 /* modify the target for boot data segment */
1991 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1992 dst8 = (u_int8_t *) (dst16 + 1);
1993 *dst16 = (u_int) boot_addr & 0xffff;
1994 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1999 * this function starts the AP (application processor) identified
2000 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2001 * to accomplish this. This is necessary because of the nuances
2002 * of the different hardware we might encounter. It ain't pretty,
2003 * but it seems to work.
2006 start_ap(int logical_cpu, u_int boot_addr)
2011 u_long icr_lo, icr_hi;
2013 POSTCODE(START_AP_POST);
2015 /* get the PHYSICAL APIC ID# */
2016 physical_cpu = CPU_TO_ID(logical_cpu);
2018 /* calculate the vector */
2019 vector = (boot_addr >> 12) & 0xff;
2021 /* used as a watchpoint to signal AP startup */
2025 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2026 * and running the target CPU. OR this INIT IPI might be latched (P5
2027 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2031 /* setup the address for the target AP */
2032 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2033 icr_hi |= (physical_cpu << 24);
2034 lapic.icr_hi = icr_hi;
2036 /* do an INIT IPI: assert RESET */
2037 icr_lo = lapic.icr_lo & 0xfff00000;
2038 lapic.icr_lo = icr_lo | 0x0000c500;
2040 /* wait for pending status end */
2041 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2044 /* do an INIT IPI: deassert RESET */
2045 lapic.icr_lo = icr_lo | 0x00008500;
2047 /* wait for pending status end */
2048 u_sleep(10000); /* wait ~10mS */
2049 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2053 * next we do a STARTUP IPI: the previous INIT IPI might still be
2054 * latched, (P5 bug) this 1st STARTUP would then terminate
2055 * immediately, and the previously started INIT IPI would continue. OR
2056 * the previous INIT IPI has already run. and this STARTUP IPI will
2057 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2061 /* do a STARTUP IPI */
2062 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2063 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2065 u_sleep(200); /* wait ~200uS */
2068 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2069 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2070 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2071 * recognized after hardware RESET or INIT IPI.
2074 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2075 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2077 u_sleep(200); /* wait ~200uS */
2079 /* wait for it to start */
2080 set_apic_timer(5000000);/* == 5 seconds */
2081 while (read_apic_timer())
2082 if (mp_ncpus > cpus)
2083 return 1; /* return SUCCESS */
2085 return 0; /* return FAILURE */
2090 * Flush the TLB on all other CPU's
2092 * XXX: Needs to handshake and wait for completion before proceding.
2097 #if defined(APIC_IO)
2098 if (smp_started && invltlb_ok)
2099 all_but_self_ipi(XINVLTLB_OFFSET);
2100 #endif /* APIC_IO */
2106 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2108 /* send a message to the other CPUs */
2118 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2121 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2123 /* send a message to the other CPUs */
2129 * When called the executing CPU will send an IPI to all other CPUs
2130 * requesting that they halt execution.
2132 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2134 * - Signals all CPUs in map to stop.
2135 * - Waits for each to stop.
2142 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2143 * from executing at same time.
2146 stop_cpus(u_int map)
2151 /* send the Xcpustop IPI to all CPUs in map */
2152 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2154 while ((stopped_cpus & map) != map)
2162 * Called by a CPU to restart stopped CPUs.
2164 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2166 * - Signals all CPUs in map to restart.
2167 * - Waits for each to restart.
2175 restart_cpus(u_int map)
2180 started_cpus = map; /* signal other cpus to restart */
2182 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2188 int smp_active = 0; /* are the APs allowed to run? */
2189 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2191 /* XXX maybe should be hw.ncpu */
2192 static int smp_cpus = 1; /* how many cpu's running */
2193 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2195 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2196 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2198 /* Warning: Do not staticize. Used from swtch.s */
2199 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2200 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2201 &do_page_zero_idle, 0, "");
2203 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2204 int forward_irq_enabled = 1;
2205 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2206 &forward_irq_enabled, 0, "");
2208 /* Enable forwarding of a signal to a process running on a different CPU */
2209 static int forward_signal_enabled = 1;
2210 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2211 &forward_signal_enabled, 0, "");
2213 /* Enable forwarding of roundrobin to all other cpus */
2214 static int forward_roundrobin_enabled = 1;
2215 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2216 &forward_roundrobin_enabled, 0, "");
2219 * This is called once the rest of the system is up and running and we're
2220 * ready to let the AP's out of the pen.
2229 /* BSP may have changed PTD while we're waiting for the lock */
2234 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2238 /* Build our map of 'other' CPUs. */
2239 other_cpus = all_cpus & ~(1 << cpuid);
2241 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2243 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
2244 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
2246 /* set up FPU state on the AP */
2247 npxinit(__INITIAL_NPXCW__);
2249 /* A quick check from sanity claus */
2250 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2251 if (cpuid != apic_id) {
2252 printf("SMP: cpuid = %d\n", cpuid);
2253 printf("SMP: apic_id = %d\n", apic_id);
2254 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2255 panic("cpuid mismatch! boom!!");
2258 /* Init local apic for irq's */
2261 /* Set memory range attributes for this CPU to match the BSP */
2262 mem_range_AP_init();
2265 * Activate smp_invltlb, although strictly speaking, this isn't
2266 * quite correct yet. We should have a bitfield for cpus willing
2267 * to accept TLB flush IPI's or something and sync them.
2269 if (smp_cpus == mp_ncpus) {
2271 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2272 smp_active = 1; /* historic */
2278 #define CHECKSTATE_USER 0
2279 #define CHECKSTATE_SYS 1
2280 #define CHECKSTATE_INTR 2
2282 /* Do not staticize. Used from apic_vector.s */
2283 struct proc* checkstate_curproc[NCPU];
2284 int checkstate_cpustate[NCPU];
2285 u_long checkstate_pc[NCPU];
2287 extern long cp_time[CPUSTATES];
2289 #define PC_TO_INDEX(pc, prof) \
2290 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2291 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2294 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2300 pc = checkstate_pc[id];
2301 prof = &p->p_stats->p_prof;
2302 if (pc >= prof->pr_off &&
2303 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2304 if ((p->p_flag & P_OWEUPC) == 0) {
2307 p->p_flag |= P_OWEUPC;
2309 *astmap |= (1 << id);
2314 forwarded_statclock(int id, int pscnt, int *astmap)
2316 struct pstats *pstats;
2323 register struct gmonparam *g;
2327 p = checkstate_curproc[id];
2328 cpustate = checkstate_cpustate[id];
2331 case CHECKSTATE_USER:
2332 if (p->p_flag & P_PROFIL)
2333 addupc_intr_forwarded(p, id, astmap);
2337 if (p->p_nice > NZERO)
2342 case CHECKSTATE_SYS:
2345 * Kernel statistics are just like addupc_intr, only easier.
2348 if (g->state == GMON_PROF_ON) {
2349 i = checkstate_pc[id] - g->lowpc;
2350 if (i < g->textsize) {
2351 i /= HISTFRACTION * sizeof(*g->kcount);
2366 case CHECKSTATE_INTR:
2370 * Kernel statistics are just like addupc_intr, only easier.
2373 if (g->state == GMON_PROF_ON) {
2374 i = checkstate_pc[id] - g->lowpc;
2375 if (i < g->textsize) {
2376 i /= HISTFRACTION * sizeof(*g->kcount);
2390 /* Update resource usage integrals and maximums. */
2391 if ((pstats = p->p_stats) != NULL &&
2392 (ru = &pstats->p_ru) != NULL &&
2393 (vm = p->p_vmspace) != NULL) {
2394 ru->ru_ixrss += pgtok(vm->vm_tsize);
2395 ru->ru_idrss += pgtok(vm->vm_dsize);
2396 ru->ru_isrss += pgtok(vm->vm_ssize);
2397 rss = pgtok(vmspace_resident_count(vm));
2398 if (ru->ru_maxrss < rss)
2399 ru->ru_maxrss = rss;
2405 forward_statclock(int pscnt)
2411 /* Kludge. We don't yet have separate locks for the interrupts
2412 * and the kernel. This means that we cannot let the other processors
2413 * handle complex interrupts while inhibiting them from entering
2414 * the kernel in a non-interrupt context.
2416 * What we can do, without changing the locking mechanisms yet,
2417 * is letting the other processors handle a very simple interrupt
2418 * (wich determines the processor states), and do the main
2422 if (!smp_started || !invltlb_ok || cold || panicstr)
2425 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2427 map = other_cpus & ~stopped_cpus ;
2428 checkstate_probed_cpus = 0;
2430 selected_apic_ipi(map,
2431 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2434 while (checkstate_probed_cpus != map) {
2438 #ifdef BETTER_CLOCK_DIAGNOSTIC
2439 printf("forward_statclock: checkstate %x\n",
2440 checkstate_probed_cpus);
2447 * Step 2: walk through other processors processes, update ticks and
2452 for (id = 0; id < mp_ncpus; id++) {
2455 if (((1 << id) & checkstate_probed_cpus) == 0)
2457 forwarded_statclock(id, pscnt, &map);
2460 checkstate_need_ast |= map;
2461 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2463 while ((checkstate_need_ast & map) != 0) {
2467 #ifdef BETTER_CLOCK_DIAGNOSTIC
2468 printf("forward_statclock: dropped ast 0x%x\n",
2469 checkstate_need_ast & map);
2478 forward_hardclock(int pscnt)
2483 struct pstats *pstats;
2486 /* Kludge. We don't yet have separate locks for the interrupts
2487 * and the kernel. This means that we cannot let the other processors
2488 * handle complex interrupts while inhibiting them from entering
2489 * the kernel in a non-interrupt context.
2491 * What we can do, without changing the locking mechanisms yet,
2492 * is letting the other processors handle a very simple interrupt
2493 * (wich determines the processor states), and do the main
2497 if (!smp_started || !invltlb_ok || cold || panicstr)
2500 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2502 map = other_cpus & ~stopped_cpus ;
2503 checkstate_probed_cpus = 0;
2505 selected_apic_ipi(map,
2506 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2509 while (checkstate_probed_cpus != map) {
2513 #ifdef BETTER_CLOCK_DIAGNOSTIC
2514 printf("forward_hardclock: checkstate %x\n",
2515 checkstate_probed_cpus);
2522 * Step 2: walk through other processors processes, update virtual
2523 * timer and profiling timer. If stathz == 0, also update ticks and
2528 for (id = 0; id < mp_ncpus; id++) {
2531 if (((1 << id) & checkstate_probed_cpus) == 0)
2533 p = checkstate_curproc[id];
2535 pstats = p->p_stats;
2536 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2537 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2538 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2539 psignal(p, SIGVTALRM);
2542 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2543 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2544 psignal(p, SIGPROF);
2549 forwarded_statclock( id, pscnt, &map);
2553 checkstate_need_ast |= map;
2554 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2556 while ((checkstate_need_ast & map) != 0) {
2560 #ifdef BETTER_CLOCK_DIAGNOSTIC
2561 printf("forward_hardclock: dropped ast 0x%x\n",
2562 checkstate_need_ast & map);
2570 #endif /* BETTER_CLOCK */
2573 forward_signal(struct proc *p)
2579 /* Kludge. We don't yet have separate locks for the interrupts
2580 * and the kernel. This means that we cannot let the other processors
2581 * handle complex interrupts while inhibiting them from entering
2582 * the kernel in a non-interrupt context.
2584 * What we can do, without changing the locking mechanisms yet,
2585 * is letting the other processors handle a very simple interrupt
2586 * (wich determines the processor states), and do the main
2590 if (!smp_started || !invltlb_ok || cold || panicstr)
2592 if (!forward_signal_enabled)
2595 if (p->p_stat != SRUN)
2601 checkstate_need_ast |= map;
2602 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2604 while ((checkstate_need_ast & map) != 0) {
2609 printf("forward_signal: dropped ast 0x%x\n",
2610 checkstate_need_ast & map);
2615 if (id == p->p_oncpu)
2621 forward_roundrobin(void)
2626 if (!smp_started || !invltlb_ok || cold || panicstr)
2628 if (!forward_roundrobin_enabled)
2630 resched_cpus |= other_cpus;
2631 map = other_cpus & ~stopped_cpus ;
2633 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2635 (void) all_but_self_ipi(XCPUAST_OFFSET);
2638 while ((checkstate_need_ast & map) != 0) {
2643 printf("forward_roundrobin: dropped ast 0x%x\n",
2644 checkstate_need_ast & map);
2652 #ifdef APIC_INTR_REORDER
2654 * Maintain mapping from softintr vector to isr bit in local apic.
2657 set_lapic_isrloc(int intr, int vector)
2659 if (intr < 0 || intr > 32)
2660 panic("set_apic_isrloc: bad intr argument: %d",intr);
2661 if (vector < ICU_OFFSET || vector > 255)
2662 panic("set_apic_isrloc: bad vector argument: %d",vector);
2663 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2664 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2669 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2670 * (if specified), rendezvous, execute the action function (if specified),
2671 * rendezvous again, execute the teardown function (if specified), and then
2674 * Note that the supplied external functions _must_ be reentrant and aware
2675 * that they are running in parallel and in an unknown lock context.
2677 static void (*smp_rv_setup_func)(void *arg);
2678 static void (*smp_rv_action_func)(void *arg);
2679 static void (*smp_rv_teardown_func)(void *arg);
2680 static void *smp_rv_func_arg;
2681 static volatile int smp_rv_waiters[2];
2684 smp_rendezvous_action(void)
2686 /* setup function */
2687 if (smp_rv_setup_func != NULL)
2688 smp_rv_setup_func(smp_rv_func_arg);
2689 /* spin on entry rendezvous */
2690 atomic_add_int(&smp_rv_waiters[0], 1);
2691 while (smp_rv_waiters[0] < mp_ncpus)
2693 /* action function */
2694 if (smp_rv_action_func != NULL)
2695 smp_rv_action_func(smp_rv_func_arg);
2696 /* spin on exit rendezvous */
2697 atomic_add_int(&smp_rv_waiters[1], 1);
2698 while (smp_rv_waiters[1] < mp_ncpus)
2700 /* teardown function */
2701 if (smp_rv_teardown_func != NULL)
2702 smp_rv_teardown_func(smp_rv_func_arg);
2706 smp_rendezvous(void (* setup_func)(void *),
2707 void (* action_func)(void *),
2708 void (* teardown_func)(void *),
2713 /* obtain rendezvous lock */
2714 s_lock(&smp_rv_lock); /* XXX sleep here? NOWAIT flag? */
2716 /* set static function pointers */
2717 smp_rv_setup_func = setup_func;
2718 smp_rv_action_func = action_func;
2719 smp_rv_teardown_func = teardown_func;
2720 smp_rv_func_arg = arg;
2721 smp_rv_waiters[0] = 0;
2722 smp_rv_waiters[1] = 0;
2724 /* disable interrupts on this CPU, save interrupt status */
2725 efl = read_eflags();
2726 write_eflags(efl & ~PSL_I);
2728 /* signal other processors, which will enter the IPI with interrupts off */
2729 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2731 /* call executor function */
2732 smp_rendezvous_action();
2734 /* restore interrupt flag */
2738 s_unlock(&smp_rv_lock);