2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1996, by Steve Passe
5 * Copyright (c) 2003, by Peter Wemm
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
35 #include "opt_sched.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/cpuset.h>
42 #include <sys/domainset.h>
46 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/memrange.h>
51 #include <sys/mutex.h>
54 #include <sys/sched.h>
56 #include <sys/sysctl.h>
59 #include <vm/vm_param.h>
61 #include <vm/vm_kern.h>
62 #include <vm/vm_extern.h>
63 #include <vm/vm_page.h>
64 #include <vm/vm_phys.h>
66 #include <x86/apicreg.h>
67 #include <machine/clock.h>
68 #include <machine/cputypes.h>
69 #include <machine/cpufunc.h>
71 #include <machine/md_var.h>
72 #include <machine/pcb.h>
73 #include <machine/psl.h>
74 #include <machine/smp.h>
75 #include <machine/specialreg.h>
76 #include <machine/tss.h>
77 #include <x86/ucode.h>
78 #include <machine/cpu.h>
81 #include <contrib/dev/acpica/include/acpi.h>
82 #include <dev/acpica/acpivar.h>
84 #define WARMBOOT_TARGET 0
85 #define WARMBOOT_OFF (KERNBASE + 0x0467)
86 #define WARMBOOT_SEG (KERNBASE + 0x0469)
88 #define CMOS_REG (0x70)
89 #define CMOS_DATA (0x71)
90 #define BIOS_RESET (0x0f)
91 #define BIOS_WARM (0x0a)
93 #define GiB(v) (v ## ULL << 30)
95 #define AP_BOOTPT_SZ (PAGE_SIZE * 3)
97 /* Temporary variables for init_secondary() */
98 char *doublefault_stack;
104 * Local data and functions.
107 static int start_ap(int apic_id);
110 is_kernel_paddr(vm_paddr_t pa)
113 return (pa >= trunc_2mpage(btext - KERNBASE) &&
114 pa < round_page(_end - KERNBASE));
118 is_mpboot_good(vm_paddr_t start, vm_paddr_t end)
121 return (start + AP_BOOTPT_SZ <= GiB(4) && atop(end) < Maxmem);
125 * Calculate usable address in base memory for AP trampoline code.
128 mp_bootaddress(vm_paddr_t *physmap, unsigned int *physmap_idx)
130 vm_paddr_t start, end;
134 alloc_ap_trampoline(physmap, physmap_idx);
137 * Find a memory region big enough below the 4GB boundary to
138 * store the initial page tables. Region must be mapped by
141 * Note that it needs to be aligned to a page boundary.
144 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
146 * First, try to chomp at the start of the physmap region.
147 * Kernel binary might claim it already.
149 start = round_page(physmap[i]);
150 end = start + AP_BOOTPT_SZ;
151 if (start < end && end <= physmap[i + 1] &&
152 is_mpboot_good(start, end) &&
153 !is_kernel_paddr(start) && !is_kernel_paddr(end - 1)) {
160 * Second, try to chomp at the end. Again, check
163 end = trunc_page(physmap[i + 1]);
164 start = end - AP_BOOTPT_SZ;
165 if (start < end && start >= physmap[i] &&
166 is_mpboot_good(start, end) &&
167 !is_kernel_paddr(start) && !is_kernel_paddr(end - 1)) {
169 physmap[i + 1] = start;
174 mptramp_pagetables = start;
175 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
176 memmove(&physmap[i], &physmap[i + 2],
177 sizeof(*physmap) * (*physmap_idx - i + 2));
181 mptramp_pagetables = trunc_page(boot_address) - AP_BOOTPT_SZ;
184 "Cannot find enough space for the initial AP page tables, placing them at %#x",
190 * Initialize the IPI handlers and start up the AP's.
197 /* Initialize the logical ID to APIC ID table. */
198 for (i = 0; i < MAXCPU; i++) {
199 cpu_apic_ids[i] = -1;
202 /* Install an inter-CPU IPI for TLB invalidation */
203 if (pmap_pcid_enabled) {
205 setidt(IPI_INVLTLB, pti ?
206 IDTVEC(invltlb_invpcid_pti_pti) :
207 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
209 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
210 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
211 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
212 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
214 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
215 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
216 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
217 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
218 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
219 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
222 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
223 SDT_SYSIGT, SEL_KPL, 0);
224 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
225 SDT_SYSIGT, SEL_KPL, 0);
226 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
227 SDT_SYSIGT, SEL_KPL, 0);
230 /* Install an inter-CPU IPI for cache invalidation. */
231 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
232 SDT_SYSIGT, SEL_KPL, 0);
234 /* Install an inter-CPU IPI for all-CPU rendezvous */
235 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
236 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
238 /* Install generic inter-CPU IPI handler */
239 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
240 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
242 /* Install an inter-CPU IPI for CPU stop/restart */
243 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
244 SDT_SYSIGT, SEL_KPL, 0);
246 /* Install an inter-CPU IPI for CPU suspend/resume */
247 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
248 SDT_SYSIGT, SEL_KPL, 0);
250 /* Set boot_cpu_id if needed. */
251 if (boot_cpu_id == -1) {
252 boot_cpu_id = PCPU_GET(apic_id);
253 cpu_info[boot_cpu_id].cpu_bsp = 1;
255 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
256 ("BSP's APIC ID doesn't match boot_cpu_id"));
258 /* Probe logical/physical core configuration. */
263 /* Start each Application Processor */
264 init_ops.start_all_aps();
266 set_interrupt_apic_ids();
268 acpi_pxm_set_cpu_locality();
272 * AP CPU's call this to initialize themselves.
279 struct user_segment_descriptor *gdt;
280 struct region_descriptor ap_gdt;
282 int cpu, gsel_tss, x;
284 /* Set by the startup code for us to use */
287 /* Update microcode before doing anything else. */
290 /* Get per-cpu data and save */
293 /* prime data page for it to use */
294 pcpu_init(pc, cpu, sizeof(struct pcpu));
295 dpcpu_init(dpcpu, cpu);
296 pc->pc_apic_id = cpu_apic_ids[cpu];
297 pc->pc_prvspace = pc;
298 pc->pc_curthread = 0;
299 pc->pc_tssp = &pc->pc_common_tss;
301 pc->pc_pti_rsp0 = (((vm_offset_t)&pc->pc_pti_stack +
302 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful);
304 pc->pc_tss = (struct system_segment_descriptor *)&gdt[GPROC0_SEL];
305 pc->pc_fs32p = &gdt[GUFS32_SEL];
306 pc->pc_gs32p = &gdt[GUGS32_SEL];
307 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL];
308 /* See comment in pmap_bootstrap(). */
309 pc->pc_pcid_next = PMAP_PCID_KERN + 2;
313 pc->pc_common_tss = __pcpu[0].pc_common_tss;
314 pc->pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
316 pc->pc_common_tss.tss_rsp0 = 0;
318 /* The doublefault stack runs on IST1. */
319 np = ((struct nmi_pcpu *)&doublefault_stack[PAGE_SIZE]) - 1;
320 np->np_pcpu = (register_t)pc;
321 pc->pc_common_tss.tss_ist1 = (long)np;
323 /* The NMI stack runs on IST2. */
324 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
325 np->np_pcpu = (register_t)pc;
326 pc->pc_common_tss.tss_ist2 = (long)np;
328 /* The MC# stack runs on IST3. */
329 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
330 np->np_pcpu = (register_t)pc;
331 pc->pc_common_tss.tss_ist3 = (long)np;
333 /* The DB# stack runs on IST4. */
334 np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
335 np->np_pcpu = (register_t)pc;
336 pc->pc_common_tss.tss_ist4 = (long)np;
338 /* Prepare private GDT */
339 gdt_segs[GPROC0_SEL].ssd_base = (long)&pc->pc_common_tss;
340 for (x = 0; x < NGDT; x++) {
341 if (x != GPROC0_SEL && x != GPROC0_SEL + 1 &&
342 x != GUSERLDT_SEL && x != GUSERLDT_SEL + 1)
343 ssdtosd(&gdt_segs[x], &gdt[x]);
345 ssdtosyssd(&gdt_segs[GPROC0_SEL],
346 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
347 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
348 ap_gdt.rd_base = (u_long)gdt;
349 lgdt(&ap_gdt); /* does magic intra-segment return */
351 wrmsr(MSR_FSBASE, 0); /* User value */
352 wrmsr(MSR_GSBASE, (u_int64_t)pc);
353 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
358 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
362 * Set to a known state:
363 * Set by mpboot.s: CR0_PG, CR0_PE
364 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
367 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
370 amd64_conf_fast_syscall();
372 /* signal our startup to the BSP. */
375 /* Spin until the BSP releases the AP's. */
376 while (atomic_load_acq_int(&aps_ready) == 0)
379 init_secondary_tail();
382 /*******************************************************************
383 * local functions and data
388 mp_realloc_pcpu(int cpuid, int domain)
393 oa = (vm_offset_t)&__pcpu[cpuid];
394 if (_vm_phys_domain(pmap_kextract(oa)) == domain)
396 m = vm_page_alloc_domain(NULL, 0, domain,
397 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
400 na = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
401 pagecopy((void *)oa, (void *)na);
402 pmap_qenter((vm_offset_t)&__pcpu[cpuid], &m, 1);
403 /* XXX old pcpu page leaked. */
408 * start each AP in our list
411 native_start_all_aps(void)
413 u_int64_t *pt4, *pt3, *pt2;
414 u_int32_t mpbioswarmvec;
415 int apic_id, cpu, domain, i;
418 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
420 /* copy the AP 1st level boot code */
421 bcopy(mptramp_start, (void *)PHYS_TO_DMAP(boot_address), bootMP_size);
423 /* Locate the page tables, they'll be below the trampoline */
424 pt4 = (uint64_t *)PHYS_TO_DMAP(mptramp_pagetables);
425 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
426 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
428 /* Create the initial 1GB replicated page tables */
429 for (i = 0; i < 512; i++) {
430 /* Each slot of the level 4 pages points to the same level 3 page */
431 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
432 pt4[i] |= PG_V | PG_RW | PG_U;
434 /* Each slot of the level 3 pages points to the same level 2 page */
435 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
436 pt3[i] |= PG_V | PG_RW | PG_U;
438 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
439 pt2[i] = i * (2 * 1024 * 1024);
440 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
443 /* save the current value of the warm-start vector */
444 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
445 outb(CMOS_REG, BIOS_RESET);
446 mpbiosreason = inb(CMOS_DATA);
448 /* setup a vector to our boot code */
449 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
450 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
451 outb(CMOS_REG, BIOS_RESET);
452 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
454 /* Relocate pcpu areas to the correct domain. */
457 for (cpu = 1; cpu < mp_ncpus; cpu++) {
458 apic_id = cpu_apic_ids[cpu];
459 domain = acpi_pxm_get_cpu_locality(apic_id);
460 mp_realloc_pcpu(cpu, domain);
466 for (cpu = 1; cpu < mp_ncpus; cpu++) {
467 apic_id = cpu_apic_ids[cpu];
470 domain = acpi_pxm_get_cpu_locality(apic_id);
472 /* allocate and set up an idle stack data page */
473 bootstacks[cpu] = (void *)kmem_malloc(kstack_pages * PAGE_SIZE,
475 doublefault_stack = (char *)kmem_malloc(PAGE_SIZE, M_WAITOK |
477 mce_stack = (char *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
478 nmi_stack = (char *)kmem_malloc_domainset(
479 DOMAINSET_PREF(domain), PAGE_SIZE, M_WAITOK | M_ZERO);
480 dbg_stack = (char *)kmem_malloc_domainset(
481 DOMAINSET_PREF(domain), PAGE_SIZE, M_WAITOK | M_ZERO);
482 dpcpu = (void *)kmem_malloc_domainset(DOMAINSET_PREF(domain),
483 DPCPU_SIZE, M_WAITOK | M_ZERO);
485 bootSTK = (char *)bootstacks[cpu] +
486 kstack_pages * PAGE_SIZE - 8;
489 /* attempt to start the Application Processor */
490 if (!start_ap(apic_id)) {
491 /* restore the warmstart vector */
492 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
493 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
496 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
499 /* restore the warmstart vector */
500 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
502 outb(CMOS_REG, BIOS_RESET);
503 outb(CMOS_DATA, mpbiosreason);
505 /* number of APs actually started */
511 * This function starts the AP (application processor) identified
512 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
513 * to accomplish this. This is necessary because of the nuances
514 * of the different hardware we might encounter. It isn't pretty,
515 * but it seems to work.
518 start_ap(int apic_id)
523 /* calculate the vector */
524 vector = (boot_address >> 12) & 0xff;
526 /* used as a watchpoint to signal AP startup */
529 ipi_startup(apic_id, vector);
531 /* Wait up to 5 seconds for it to start. */
532 for (ms = 0; ms < 5000; ms++) {
534 return 1; /* return SUCCESS */
537 return 0; /* return FAILURE */
541 invltlb_invpcid_handler(void)
543 struct invpcid_descr d;
546 #ifdef COUNT_XINVLTLB_HITS
547 xhits_gbl[PCPU_GET(cpuid)]++;
548 #endif /* COUNT_XINVLTLB_HITS */
550 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
551 #endif /* COUNT_IPIS */
553 generation = smp_tlb_generation;
554 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
557 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
559 PCPU_SET(smp_tlb_done, generation);
563 invltlb_invpcid_pti_handler(void)
565 struct invpcid_descr d;
568 #ifdef COUNT_XINVLTLB_HITS
569 xhits_gbl[PCPU_GET(cpuid)]++;
570 #endif /* COUNT_XINVLTLB_HITS */
572 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
573 #endif /* COUNT_IPIS */
575 generation = smp_tlb_generation;
576 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
579 if (smp_tlb_pmap == kernel_pmap) {
581 * This invalidation actually needs to clear kernel
582 * mappings from the TLB in the current pmap, but
583 * since we were asked for the flush in the kernel
584 * pmap, achieve it by performing global flush.
586 invpcid(&d, INVPCID_CTXGLOB);
588 invpcid(&d, INVPCID_CTX);
589 d.pcid |= PMAP_PCID_USER_PT;
590 invpcid(&d, INVPCID_CTX);
592 PCPU_SET(smp_tlb_done, generation);
596 invltlb_pcid_handler(void)
599 uint32_t generation, pcid;
601 #ifdef COUNT_XINVLTLB_HITS
602 xhits_gbl[PCPU_GET(cpuid)]++;
603 #endif /* COUNT_XINVLTLB_HITS */
605 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
606 #endif /* COUNT_IPIS */
608 generation = smp_tlb_generation; /* Overlap with serialization */
609 if (smp_tlb_pmap == kernel_pmap) {
613 * The current pmap might not be equal to
614 * smp_tlb_pmap. The clearing of the pm_gen in
615 * pmap_invalidate_all() takes care of TLB
616 * invalidation when switching to the pmap on this
619 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
620 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
621 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
622 ucr3 = smp_tlb_pmap->pm_ucr3;
623 if (ucr3 != PMAP_NO_CR3) {
624 ucr3 |= PMAP_PCID_USER_PT | pcid;
625 pmap_pti_pcid_invalidate(ucr3, kcr3);
630 PCPU_SET(smp_tlb_done, generation);
634 invlpg_invpcid_handler(void)
636 struct invpcid_descr d;
639 #ifdef COUNT_XINVLTLB_HITS
640 xhits_pg[PCPU_GET(cpuid)]++;
641 #endif /* COUNT_XINVLTLB_HITS */
643 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
644 #endif /* COUNT_IPIS */
646 generation = smp_tlb_generation; /* Overlap with serialization */
647 invlpg(smp_tlb_addr1);
648 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
649 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
652 d.addr = smp_tlb_addr1;
653 invpcid(&d, INVPCID_ADDR);
655 PCPU_SET(smp_tlb_done, generation);
659 invlpg_pcid_handler(void)
665 #ifdef COUNT_XINVLTLB_HITS
666 xhits_pg[PCPU_GET(cpuid)]++;
667 #endif /* COUNT_XINVLTLB_HITS */
669 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
670 #endif /* COUNT_IPIS */
672 generation = smp_tlb_generation; /* Overlap with serialization */
673 invlpg(smp_tlb_addr1);
674 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
675 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
676 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
677 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
678 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
679 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
681 PCPU_SET(smp_tlb_done, generation);
685 invlrng_invpcid_handler(void)
687 struct invpcid_descr d;
688 vm_offset_t addr, addr2;
691 #ifdef COUNT_XINVLTLB_HITS
692 xhits_rng[PCPU_GET(cpuid)]++;
693 #endif /* COUNT_XINVLTLB_HITS */
695 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
696 #endif /* COUNT_IPIS */
698 addr = smp_tlb_addr1;
699 addr2 = smp_tlb_addr2;
700 generation = smp_tlb_generation; /* Overlap with serialization */
704 } while (addr < addr2);
705 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
706 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
709 d.addr = smp_tlb_addr1;
711 invpcid(&d, INVPCID_ADDR);
713 } while (d.addr < addr2);
715 PCPU_SET(smp_tlb_done, generation);
719 invlrng_pcid_handler(void)
721 vm_offset_t addr, addr2;
726 #ifdef COUNT_XINVLTLB_HITS
727 xhits_rng[PCPU_GET(cpuid)]++;
728 #endif /* COUNT_XINVLTLB_HITS */
730 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
731 #endif /* COUNT_IPIS */
733 addr = smp_tlb_addr1;
734 addr2 = smp_tlb_addr2;
735 generation = smp_tlb_generation; /* Overlap with serialization */
739 } while (addr < addr2);
740 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
741 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
742 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
743 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
744 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
745 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
747 PCPU_SET(smp_tlb_done, generation);