2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $Id: mp_machdep.c,v 1.103 1999/06/22 20:54:25 msmith Exp $
30 #include "opt_user_ldt.h"
33 #include <machine/smptests.h>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
46 #include <sys/dkstat.h>
50 #include <vm/vm_param.h>
52 #include <vm/vm_kern.h>
53 #include <vm/vm_extern.h>
56 #include <vm/vm_map.h>
63 #include <machine/smp.h>
64 #include <machine/apic.h>
65 #include <machine/mpapic.h>
66 #include <machine/segments.h>
67 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
68 #include <machine/tss.h>
69 #include <machine/specialreg.h>
70 #include <machine/cputypes.h>
71 #include <machine/globaldata.h>
73 #include <i386/i386/cons.h> /* cngetc() */
76 #include <machine/md_var.h> /* setidt() */
77 #include <i386/isa/icu.h> /* IPIs */
78 #include <i386/isa/intr_machdep.h> /* IPIs */
81 #if defined(TEST_DEFAULT_CONFIG)
82 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
84 #define MPFPS_MPFB1 mpfps->mpfb1
85 #endif /* TEST_DEFAULT_CONFIG */
87 #define WARMBOOT_TARGET 0
88 #define WARMBOOT_OFF (KERNBASE + 0x0467)
89 #define WARMBOOT_SEG (KERNBASE + 0x0469)
92 #define BIOS_BASE (0xe8000)
93 #define BIOS_SIZE (0x18000)
95 #define BIOS_BASE (0xf0000)
96 #define BIOS_SIZE (0x10000)
98 #define BIOS_COUNT (BIOS_SIZE/4)
100 #define CMOS_REG (0x70)
101 #define CMOS_DATA (0x71)
102 #define BIOS_RESET (0x0f)
103 #define BIOS_WARM (0x0a)
105 #define PROCENTRY_FLAG_EN 0x01
106 #define PROCENTRY_FLAG_BP 0x02
107 #define IOAPICENTRY_FLAG_EN 0x01
110 /* MP Floating Pointer Structure */
111 typedef struct MPFPS {
124 /* MP Configuration Table Header */
125 typedef struct MPCTH {
127 u_short base_table_length;
131 u_char product_id[12];
132 void *oem_table_pointer;
133 u_short oem_table_size;
136 u_short extended_table_length;
137 u_char extended_table_checksum;
142 typedef struct PROCENTRY {
147 u_long cpu_signature;
148 u_long feature_flags;
153 typedef struct BUSENTRY {
159 typedef struct IOAPICENTRY {
165 } *io_apic_entry_ptr;
167 typedef struct INTENTRY {
177 /* descriptions of MP basetable entries */
178 typedef struct BASETABLE_ENTRY {
185 * this code MUST be enabled here and in mpboot.s.
186 * it follows the very early stages of AP boot by placing values in CMOS ram.
187 * it NORMALLY will never be needed and thus the primitive method for enabling.
192 #if defined(CHECK_POINTS) && !defined(PC98)
193 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
194 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
196 #define CHECK_INIT(D); \
197 CHECK_WRITE(0x34, (D)); \
198 CHECK_WRITE(0x35, (D)); \
199 CHECK_WRITE(0x36, (D)); \
200 CHECK_WRITE(0x37, (D)); \
201 CHECK_WRITE(0x38, (D)); \
202 CHECK_WRITE(0x39, (D));
204 #define CHECK_PRINT(S); \
205 printf("%s: %d, %d, %d, %d, %d, %d\n", \
214 #else /* CHECK_POINTS */
216 #define CHECK_INIT(D)
217 #define CHECK_PRINT(S)
219 #endif /* CHECK_POINTS */
222 * Values to send to the POST hardware.
224 #define MP_BOOTADDRESS_POST 0x10
225 #define MP_PROBE_POST 0x11
226 #define MPTABLE_PASS1_POST 0x12
228 #define MP_START_POST 0x13
229 #define MP_ENABLE_POST 0x14
230 #define MPTABLE_PASS2_POST 0x15
232 #define START_ALL_APS_POST 0x16
233 #define INSTALL_AP_TRAMP_POST 0x17
234 #define START_AP_POST 0x18
236 #define MP_ANNOUNCE_POST 0x19
239 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
240 int current_postcode;
242 /** XXX FIXME: what system files declare these??? */
243 extern struct region_descriptor r_gdt, r_idt;
245 int bsp_apic_ready = 0; /* flags useability of BSP apic */
246 int mp_ncpus; /* # of CPUs, including BSP */
247 int mp_naps; /* # of Applications processors */
248 int mp_nbusses; /* # of busses */
249 int mp_napics; /* # of IO APICs */
250 int boot_cpu_id; /* designated BSP */
251 vm_offset_t cpu_apic_address;
252 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
255 u_int32_t cpu_apic_versions[NCPU];
256 u_int32_t io_apic_versions[NAPIC];
258 #ifdef APIC_INTR_DIAGNOSTIC
259 int apic_itrace_enter[32];
260 int apic_itrace_tryisrlock[32];
261 int apic_itrace_gotisrlock[32];
262 int apic_itrace_active[32];
263 int apic_itrace_masked[32];
264 int apic_itrace_noisrlock[32];
265 int apic_itrace_masked2[32];
266 int apic_itrace_unmask[32];
267 int apic_itrace_noforward[32];
268 int apic_itrace_leave[32];
269 int apic_itrace_enter2[32];
270 int apic_itrace_doreti[32];
271 int apic_itrace_splz[32];
272 int apic_itrace_eoi[32];
273 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
274 unsigned short apic_itrace_debugbuffer[32768];
275 int apic_itrace_debugbuffer_idx;
276 struct simplelock apic_itrace_debuglock;
280 #ifdef APIC_INTR_REORDER
282 volatile int *location;
284 } apic_isrbit_location[32];
287 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
290 * APIC ID logical/physical mapping structures.
291 * We oversize these to simplify boot-time config.
293 int cpu_num_to_apic_id[NAPICID];
294 int io_num_to_apic_id[NAPICID];
295 int apic_id_to_logical[NAPICID];
298 /* Bitmap of all available CPUs */
301 /* AP uses this during bootstrap. Do not staticize. */
305 /* Hotwire a 0->4MB V==P mapping */
306 extern pt_entry_t *KPTphys;
308 /* SMP page table page */
309 extern pt_entry_t *SMPpt;
311 struct pcb stoppcbs[NCPU];
313 int smp_started; /* has the system started? */
316 * Local data and functions.
319 static int mp_capable;
320 static u_int boot_address;
321 static u_int base_memory;
323 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
324 static mpfps_t mpfps;
325 static int search_for_sig(u_int32_t target, int count);
326 static void mp_enable(u_int boot_addr);
328 static int mptable_pass1(void);
329 static int mptable_pass2(void);
330 static void default_mp_table(int type);
331 static void fix_mp_table(void);
332 static void setup_apic_irq_mapping(void);
333 static void init_locks(void);
334 static int start_all_aps(u_int boot_addr);
335 static void install_ap_tramp(u_int boot_addr);
336 static int start_ap(int logicalCpu, u_int boot_addr);
339 * Calculate usable address in base memory for AP trampoline code.
342 mp_bootaddress(u_int basemem)
344 POSTCODE(MP_BOOTADDRESS_POST);
346 base_memory = basemem * 1024; /* convert to bytes */
348 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
349 if ((base_memory - boot_address) < bootMP_size)
350 boot_address -= 4096; /* not enough, lower by 4k */
357 * Look for an Intel MP spec table (ie, SMP capable hardware).
366 POSTCODE(MP_PROBE_POST);
368 /* see if EBDA exists */
369 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
370 /* search first 1K of EBDA */
371 target = (u_int32_t) (segment << 4);
372 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
375 /* last 1K of base memory, effective 'top of base' passed in */
376 target = (u_int32_t) (base_memory - 0x400);
377 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
381 /* search the BIOS */
382 target = (u_int32_t) BIOS_BASE;
383 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
392 /* calculate needed resources */
395 panic("you must reconfigure your kernel");
397 /* flag fact that we are running multiple processors */
404 * Startup the SMP processors.
409 POSTCODE(MP_START_POST);
411 /* look for MP capable motherboard */
413 mp_enable(boot_address);
415 panic("MP hardware not found!");
420 * Print various information about the SMP system hardware and setup.
427 POSTCODE(MP_ANNOUNCE_POST);
429 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
430 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
431 printf(", version: 0x%08x", cpu_apic_versions[0]);
432 printf(", at 0x%08x\n", cpu_apic_address);
433 for (x = 1; x <= mp_naps; ++x) {
434 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
435 printf(", version: 0x%08x", cpu_apic_versions[x]);
436 printf(", at 0x%08x\n", cpu_apic_address);
440 for (x = 0; x < mp_napics; ++x) {
441 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
442 printf(", version: 0x%08x", io_apic_versions[x]);
443 printf(", at 0x%08x\n", io_apic_address[x]);
446 printf(" Warning: APIC I/O disabled\n");
451 * AP cpu's call this to sync up protected mode.
457 int x, myid = bootAP;
459 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
460 gdt_segs[GPROC0_SEL].ssd_base =
461 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
462 SMP_prvspace[myid].globaldata.gd_prvspace = &SMP_prvspace[myid];
464 for (x = 0; x < NGDT; x++) {
465 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
468 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
469 r_gdt.rd_base = (int) &gdt[myid * NGDT];
470 lgdt(&r_gdt); /* does magic intra-segment return */
476 currentldt = _default_ldt;
479 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
480 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
481 common_tss.tss_esp0 = 0; /* not used until after switch */
482 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
483 common_tss.tss_ioopt = (sizeof common_tss) << 16;
484 tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
485 common_tssd = *tss_gdt;
488 load_cr0(0x8005003b); /* XXX! */
496 * Final configuration of the BSP's local APIC:
497 * - disable 'pic mode'.
498 * - disable 'virtual wire mode'.
502 bsp_apic_configure(void)
507 /* leave 'pic mode' if necessary */
509 outb(0x22, 0x70); /* select IMCR */
510 byte = inb(0x23); /* current contents */
511 byte |= 0x01; /* mask external INTR */
512 outb(0x23, byte); /* disconnect 8259s/NMI */
515 /* mask lint0 (the 8259 'virtual wire' connection) */
516 temp = lapic.lvt_lint0;
517 temp |= APIC_LVT_M; /* set the mask */
518 lapic.lvt_lint0 = temp;
520 /* setup lint1 to handle NMI */
521 temp = lapic.lvt_lint1;
522 temp &= ~APIC_LVT_M; /* clear the mask */
523 lapic.lvt_lint1 = temp;
526 apic_dump("bsp_apic_configure()");
531 /*******************************************************************
532 * local functions and data
536 * start the SMP system
539 mp_enable(u_int boot_addr)
547 POSTCODE(MP_ENABLE_POST);
549 /* turn on 4MB of V == P addressing so we can get to MP table */
550 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
553 /* examine the MP table for needed info, uses physical addresses */
559 /* can't process default configs till the CPU APIC is pmapped */
563 /* post scan cleanup */
565 setup_apic_irq_mapping();
569 /* fill the LOGICAL io_apic_versions table */
570 for (apic = 0; apic < mp_napics; ++apic) {
571 ux = io_apic_read(apic, IOAPIC_VER);
572 io_apic_versions[apic] = ux;
575 /* program each IO APIC in the system */
576 for (apic = 0; apic < mp_napics; ++apic)
577 if (io_apic_setup(apic) < 0)
578 panic("IO APIC setup failure");
580 /* install a 'Spurious INTerrupt' vector */
581 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
582 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
584 /* install an inter-CPU IPI for TLB invalidation */
585 setidt(XINVLTLB_OFFSET, Xinvltlb,
586 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
589 /* install an inter-CPU IPI for reading processor state */
590 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
594 /* install an inter-CPU IPI for forcing an additional software trap */
595 setidt(XCPUAST_OFFSET, Xcpuast,
596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
598 /* install an inter-CPU IPI for interrupt forwarding */
599 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
600 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
602 /* install an inter-CPU IPI for CPU stop/restart */
603 setidt(XCPUSTOP_OFFSET, Xcpustop,
604 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
606 #if defined(TEST_TEST1)
607 /* install a "fake hardware INTerrupt" vector */
608 setidt(XTEST1_OFFSET, Xtest1,
609 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
610 #endif /** TEST_TEST1 */
614 /* initialize all SMP locks */
617 /* start each Application Processor */
618 start_all_aps(boot_addr);
621 * The init process might be started on a different CPU now,
622 * and the boot CPU might not call prepare_usermode to get
623 * cr0 correctly configured. Thus we initialize cr0 here.
625 load_cr0(rcr0() | CR0_WP | CR0_AM);
630 * look for the MP spec signature
633 /* string defined by the Intel MP Spec as identifying the MP table */
634 #define MP_SIG 0x5f504d5f /* _MP_ */
635 #define NEXT(X) ((X) += 4)
637 search_for_sig(u_int32_t target, int count)
640 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
642 for (x = 0; x < count; NEXT(x))
643 if (addr[x] == MP_SIG)
644 /* make array index a byte index */
645 return (target + (x * sizeof(u_int32_t)));
651 static basetable_entry basetable_entry_types[] =
653 {0, 20, "Processor"},
660 typedef struct BUSDATA {
662 enum busTypes bus_type;
665 typedef struct INTDATA {
675 typedef struct BUSTYPENAME {
680 static bus_type_name bus_type_table[] =
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"}
702 /* from MP spec v1.4, table 5-1 */
703 static int default_data[7][5] =
705 /* nbus, id0, type0, id1, type1 */
706 {1, 0, ISA, 255, 255},
707 {1, 0, EISA, 255, 255},
708 {1, 0, EISA, 255, 255},
709 {0, 255, 255, 255, 255},/* MCA not supported */
711 {2, 0, EISA, 1, PCI},
712 {0, 255, 255, 255, 255} /* MCA not supported */
717 static bus_datum bus_data[NBUS];
719 /* the IO INT data, one entry per possible APIC INTerrupt */
720 static io_int io_apic_ints[NINTR];
724 static int processor_entry __P((proc_entry_ptr entry, int cpu));
725 static int bus_entry __P((bus_entry_ptr entry, int bus));
726 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
727 static int int_entry __P((int_entry_ptr entry, int intr));
728 static int lookup_bus_type __P((char *name));
732 * 1st pass on motherboard's Intel MP specification table.
738 * cpu_apic_address (common to all CPUs)
756 POSTCODE(MPTABLE_PASS1_POST);
760 /* clear various tables */
761 for (x = 0; x < NAPICID; ++x) {
762 io_apic_address[x] = ~0; /* IO APIC address table */
765 /* init everything to empty */
771 /* check for use of 'default' configuration */
772 if (MPFPS_MPFB1 != 0) {
773 /* use default addresses */
774 cpu_apic_address = DEFAULT_APIC_BASE;
775 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
777 /* fill in with defaults */
778 mp_naps = 2; /* includes BSP */
779 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
786 if ((cth = mpfps->pap) == 0)
787 panic("MP Configuration Table Header MISSING!");
789 cpu_apic_address = (vm_offset_t) cth->apic_address;
791 /* walk the table, recording info of interest */
792 totalSize = cth->base_table_length - sizeof(struct MPCTH);
793 position = (u_char *) cth + sizeof(struct MPCTH);
794 count = cth->entry_count;
797 switch (type = *(u_char *) position) {
798 case 0: /* processor_entry */
799 if (((proc_entry_ptr)position)->cpu_flags
803 case 1: /* bus_entry */
806 case 2: /* io_apic_entry */
807 if (((io_apic_entry_ptr)position)->apic_flags
808 & IOAPICENTRY_FLAG_EN)
809 io_apic_address[mp_napics++] =
810 (vm_offset_t)((io_apic_entry_ptr)
811 position)->apic_address;
813 case 3: /* int_entry */
816 case 4: /* int_entry */
819 panic("mpfps Base Table HOSED!");
823 totalSize -= basetable_entry_types[type].length;
824 (u_char*)position += basetable_entry_types[type].length;
828 /* qualify the numbers */
830 #if 0 /* XXX FIXME: kern/4255 */
831 printf("Warning: only using %d of %d available CPUs!\n",
835 printf("NCPU cannot be different than actual CPU count.\n");
836 printf(" add 'options NCPU=%d' to your kernel config file,\n",
838 printf(" then rerun config & rebuild your SMP kernel\n");
841 #endif /* XXX FIXME: kern/4255 */
842 if (mp_nbusses > NBUS) {
843 printf("found %d busses, increase NBUS\n", mp_nbusses);
846 if (mp_napics > NAPIC) {
847 printf("found %d apics, increase NAPIC\n", mp_napics);
850 if (nintrs > NINTR) {
851 printf("found %d intrs, increase NINTR\n", nintrs);
857 * This is also used as a counter while starting the APs.
861 --mp_naps; /* subtract the BSP */
868 * 2nd pass on motherboard's Intel MP specification table.
872 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
873 * CPU_TO_ID(N), logical CPU to APIC ID table
874 * IO_TO_ID(N), logical IO to APIC ID table
887 int apic, bus, cpu, intr;
889 POSTCODE(MPTABLE_PASS2_POST);
891 /* clear various tables */
892 for (x = 0; x < NAPICID; ++x) {
893 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
894 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
895 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
898 /* clear bus data table */
899 for (x = 0; x < NBUS; ++x)
900 bus_data[x].bus_id = 0xff;
902 /* clear IO APIC INT table */
903 for (x = 0; x < NINTR; ++x) {
904 io_apic_ints[x].int_type = 0xff;
905 io_apic_ints[x].int_vector = 0xff;
908 /* setup the cpu/apic mapping arrays */
911 /* record whether PIC or virtual-wire mode */
912 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
914 /* check for use of 'default' configuration */
915 if (MPFPS_MPFB1 != 0)
916 return MPFPS_MPFB1; /* return default configuration type */
918 if ((cth = mpfps->pap) == 0)
919 panic("MP Configuration Table Header MISSING!");
921 /* walk the table, recording info of interest */
922 totalSize = cth->base_table_length - sizeof(struct MPCTH);
923 position = (u_char *) cth + sizeof(struct MPCTH);
924 count = cth->entry_count;
925 apic = bus = intr = 0;
926 cpu = 1; /* pre-count the BSP */
929 switch (type = *(u_char *) position) {
931 if (processor_entry(position, cpu))
935 if (bus_entry(position, bus))
939 if (io_apic_entry(position, apic))
943 if (int_entry(position, intr))
947 /* int_entry(position); */
950 panic("mpfps Base Table HOSED!");
954 totalSize -= basetable_entry_types[type].length;
955 (u_char *) position += basetable_entry_types[type].length;
958 if (boot_cpu_id == -1)
959 panic("NO BSP found!");
961 /* report fact that its NOT a default configuration */
967 assign_apic_irq(int apic, int intpin, int irq)
971 if (int_to_apicintpin[irq].ioapic != -1)
972 panic("assign_apic_irq: inconsistent table");
974 int_to_apicintpin[irq].ioapic = apic;
975 int_to_apicintpin[irq].int_pin = intpin;
976 int_to_apicintpin[irq].apic_address = ioapic[apic];
977 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
979 for (x = 0; x < nintrs; x++) {
980 if ((io_apic_ints[x].int_type == 0 ||
981 io_apic_ints[x].int_type == 3) &&
982 io_apic_ints[x].int_vector == 0xff &&
983 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
984 io_apic_ints[x].dst_apic_int == intpin)
985 io_apic_ints[x].int_vector = irq;
990 * parse an Intel MP specification table
997 int bus_0 = 0; /* Stop GCC warning */
998 int bus_pci = 0; /* Stop GCC warning */
1002 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1003 * did it wrong. The MP spec says that when more than 1 PCI bus
1004 * exists the BIOS must begin with bus entries for the PCI bus and use
1005 * actual PCI bus numbering. This implies that when only 1 PCI bus
1006 * exists the BIOS can choose to ignore this ordering, and indeed many
1007 * MP motherboards do ignore it. This causes a problem when the PCI
1008 * sub-system makes requests of the MP sub-system based on PCI bus
1009 * numbers. So here we look for the situation and renumber the
1010 * busses and associated INTs in an effort to "make it right".
1013 /* find bus 0, PCI bus, count the number of PCI busses */
1014 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1015 if (bus_data[x].bus_id == 0) {
1018 if (bus_data[x].bus_type == PCI) {
1024 * bus_0 == slot of bus with ID of 0
1025 * bus_pci == slot of last PCI bus encountered
1028 /* check the 1 PCI bus case for sanity */
1029 if (num_pci_bus == 1) {
1031 /* if it is number 0 all is well */
1032 if (bus_data[bus_pci].bus_id == 0)
1035 /* mis-numbered, swap with whichever bus uses slot 0 */
1037 /* swap the bus entry types */
1038 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1039 bus_data[bus_0].bus_type = PCI;
1041 /* swap each relavant INTerrupt entry */
1042 id = bus_data[bus_pci].bus_id;
1043 for (x = 0; x < nintrs; ++x) {
1044 if (io_apic_ints[x].src_bus_id == id) {
1045 io_apic_ints[x].src_bus_id = 0;
1047 else if (io_apic_ints[x].src_bus_id == 0) {
1048 io_apic_ints[x].src_bus_id = id;
1052 /* sanity check if more than 1 PCI bus */
1053 else if (num_pci_bus > 1) {
1054 for (x = 0; x < mp_nbusses; ++x) {
1055 if (bus_data[x].bus_type != PCI)
1063 setup_apic_irq_mapping(void)
1068 /* Assign low level interrupt handlers */
1069 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1070 int_to_apicintpin[x].ioapic = -1;
1071 int_to_apicintpin[x].int_pin = 0;
1072 int_to_apicintpin[x].apic_address = NULL;
1073 int_to_apicintpin[x].redirindex = 0;
1075 for (x = 0; x < nintrs; x++) {
1076 if (io_apic_ints[x].dst_apic_int < APIC_INTMAPSIZE &&
1077 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1078 io_apic_ints[x].int_vector == 0xff &&
1079 (io_apic_ints[x].int_type == 0 ||
1080 io_apic_ints[x].int_type == 3)) {
1082 io_apic_ints[x].dst_apic_int,
1083 io_apic_ints[x].dst_apic_int);
1087 while (int_vector < APIC_INTMAPSIZE &&
1088 int_to_apicintpin[int_vector].ioapic != -1)
1090 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1091 if ((io_apic_ints[x].int_type == 0 ||
1092 io_apic_ints[x].int_type == 3) &&
1093 io_apic_ints[x].int_vector == 0xff) {
1094 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1095 io_apic_ints[x].dst_apic_int,
1098 while (int_vector < APIC_INTMAPSIZE &&
1099 int_to_apicintpin[int_vector].ioapic != -1)
1107 processor_entry(proc_entry_ptr entry, int cpu)
1109 /* check for usability */
1110 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN))
1113 /* check for BSP flag */
1114 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1115 boot_cpu_id = entry->apic_id;
1116 CPU_TO_ID(0) = entry->apic_id;
1117 ID_TO_CPU(entry->apic_id) = 0;
1118 return 0; /* its already been counted */
1121 /* add another AP to list, if less than max number of CPUs */
1123 CPU_TO_ID(cpu) = entry->apic_id;
1124 ID_TO_CPU(entry->apic_id) = cpu;
1131 bus_entry(bus_entry_ptr entry, int bus)
1136 /* encode the name into an index */
1137 for (x = 0; x < 6; ++x) {
1138 if ((c = entry->bus_type[x]) == ' ')
1144 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1145 panic("unknown bus type: '%s'", name);
1147 bus_data[bus].bus_id = entry->bus_id;
1148 bus_data[bus].bus_type = x;
1155 io_apic_entry(io_apic_entry_ptr entry, int apic)
1157 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1160 IO_TO_ID(apic) = entry->apic_id;
1161 ID_TO_IO(entry->apic_id) = apic;
1168 lookup_bus_type(char *name)
1172 for (x = 0; x < MAX_BUSTYPE; ++x)
1173 if (strcmp(bus_type_table[x].name, name) == 0)
1174 return bus_type_table[x].type;
1176 return UNKNOWN_BUSTYPE;
1181 int_entry(int_entry_ptr entry, int intr)
1185 io_apic_ints[intr].int_type = entry->int_type;
1186 io_apic_ints[intr].int_flags = entry->int_flags;
1187 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1188 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1189 if (entry->dst_apic_id == 255) {
1190 /* This signal goes to all IO APICS. Select an IO APIC
1191 with sufficient number of interrupt pins */
1192 for (apic = 0; apic < mp_napics; apic++)
1193 if (((io_apic_read(apic, IOAPIC_VER) &
1194 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1195 entry->dst_apic_int)
1197 if (apic < mp_napics)
1198 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1200 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1202 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1203 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1210 apic_int_is_bus_type(int intr, int bus_type)
1214 for (bus = 0; bus < mp_nbusses; ++bus)
1215 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1216 && ((int) bus_data[bus].bus_type == bus_type))
1224 * Given a traditional ISA INT mask, return an APIC mask.
1227 isa_apic_mask(u_int isa_mask)
1232 #if defined(SKIP_IRQ15_REDIRECT)
1233 if (isa_mask == (1 << 15)) {
1234 printf("skipping ISA IRQ15 redirect\n");
1237 #endif /* SKIP_IRQ15_REDIRECT */
1239 isa_irq = ffs(isa_mask); /* find its bit position */
1240 if (isa_irq == 0) /* doesn't exist */
1242 --isa_irq; /* make it zero based */
1244 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1248 return (1 << apic_pin); /* convert pin# to a mask */
1253 * Determine which APIC pin an ISA/EISA INT is attached to.
1255 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1256 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1257 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1258 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1260 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1262 isa_apic_irq(int isa_irq)
1266 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1267 if (INTTYPE(intr) == 0) { /* standard INT */
1268 if (SRCBUSIRQ(intr) == isa_irq) {
1269 if (apic_int_is_bus_type(intr, ISA) ||
1270 apic_int_is_bus_type(intr, EISA))
1271 return INTIRQ(intr); /* found */
1275 return -1; /* NOT found */
1280 * Determine which APIC pin a PCI INT is attached to.
1282 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1283 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1284 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1286 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1290 --pciInt; /* zero based */
1292 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1293 if ((INTTYPE(intr) == 0) /* standard INT */
1294 && (SRCBUSID(intr) == pciBus)
1295 && (SRCBUSDEVICE(intr) == pciDevice)
1296 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1297 if (apic_int_is_bus_type(intr, PCI))
1298 return INTIRQ(intr); /* exact match */
1300 return -1; /* NOT found */
1304 next_apic_irq(int irq)
1311 for (intr = 0; intr < nintrs; intr++) {
1312 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1314 bus = SRCBUSID(intr);
1315 bustype = apic_bus_type(bus);
1316 if (bustype != ISA &&
1322 if (intr >= nintrs) {
1325 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1326 if (INTTYPE(ointr) != 0)
1328 if (bus != SRCBUSID(ointr))
1330 if (bustype == PCI) {
1331 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1333 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1336 if (bustype == ISA || bustype == EISA) {
1337 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1340 if (INTPIN(intr) == INTPIN(ointr))
1344 if (ointr >= nintrs) {
1347 return INTIRQ(ointr);
1361 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1364 * Exactly what this means is unclear at this point. It is a solution
1365 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1366 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1367 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1371 undirect_isa_irq(int rirq)
1375 printf("Freeing redirected ISA irq %d.\n", rirq);
1376 /** FIXME: tickle the MB redirector chip */
1380 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1387 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1390 undirect_pci_irq(int rirq)
1394 printf("Freeing redirected PCI irq %d.\n", rirq);
1396 /** FIXME: tickle the MB redirector chip */
1400 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1408 * given a bus ID, return:
1409 * the bus type if found
1413 apic_bus_type(int id)
1417 for (x = 0; x < mp_nbusses; ++x)
1418 if (bus_data[x].bus_id == id)
1419 return bus_data[x].bus_type;
1426 * given a LOGICAL APIC# and pin#, return:
1427 * the associated src bus ID if found
1431 apic_src_bus_id(int apic, int pin)
1435 /* search each of the possible INTerrupt sources */
1436 for (x = 0; x < nintrs; ++x)
1437 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1438 (pin == io_apic_ints[x].dst_apic_int))
1439 return (io_apic_ints[x].src_bus_id);
1441 return -1; /* NOT found */
1446 * given a LOGICAL APIC# and pin#, return:
1447 * the associated src bus IRQ if found
1451 apic_src_bus_irq(int apic, int pin)
1455 for (x = 0; x < nintrs; x++)
1456 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1457 (pin == io_apic_ints[x].dst_apic_int))
1458 return (io_apic_ints[x].src_bus_irq);
1460 return -1; /* NOT found */
1465 * given a LOGICAL APIC# and pin#, return:
1466 * the associated INTerrupt type if found
1470 apic_int_type(int apic, int pin)
1474 /* search each of the possible INTerrupt sources */
1475 for (x = 0; x < nintrs; ++x)
1476 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1477 (pin == io_apic_ints[x].dst_apic_int))
1478 return (io_apic_ints[x].int_type);
1480 return -1; /* NOT found */
1484 apic_irq(int apic, int pin)
1489 for (x = 0; x < nintrs; ++x)
1490 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1491 (pin == io_apic_ints[x].dst_apic_int)) {
1492 res = io_apic_ints[x].int_vector;
1495 if (apic != int_to_apicintpin[res].ioapic)
1496 panic("apic_irq: inconsistent table");
1497 if (pin != int_to_apicintpin[res].int_pin)
1498 panic("apic_irq inconsistent table (2)");
1506 * given a LOGICAL APIC# and pin#, return:
1507 * the associated trigger mode if found
1511 apic_trigger(int apic, int pin)
1515 /* search each of the possible INTerrupt sources */
1516 for (x = 0; x < nintrs; ++x)
1517 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1518 (pin == io_apic_ints[x].dst_apic_int))
1519 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1521 return -1; /* NOT found */
1526 * given a LOGICAL APIC# and pin#, return:
1527 * the associated 'active' level if found
1531 apic_polarity(int apic, int pin)
1535 /* search each of the possible INTerrupt sources */
1536 for (x = 0; x < nintrs; ++x)
1537 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1538 (pin == io_apic_ints[x].dst_apic_int))
1539 return (io_apic_ints[x].int_flags & 0x03);
1541 return -1; /* NOT found */
1546 * set data according to MP defaults
1547 * FIXME: probably not complete yet...
1550 default_mp_table(int type)
1553 #if defined(APIC_IO)
1557 #endif /* APIC_IO */
1560 printf(" MP default config type: %d\n", type);
1563 printf(" bus: ISA, APIC: 82489DX\n");
1566 printf(" bus: EISA, APIC: 82489DX\n");
1569 printf(" bus: EISA, APIC: 82489DX\n");
1572 printf(" bus: MCA, APIC: 82489DX\n");
1575 printf(" bus: ISA+PCI, APIC: Integrated\n");
1578 printf(" bus: EISA+PCI, APIC: Integrated\n");
1581 printf(" bus: MCA+PCI, APIC: Integrated\n");
1584 printf(" future type\n");
1590 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1591 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1594 CPU_TO_ID(0) = boot_cpu_id;
1595 ID_TO_CPU(boot_cpu_id) = 0;
1597 /* one and only AP */
1598 CPU_TO_ID(1) = ap_cpu_id;
1599 ID_TO_CPU(ap_cpu_id) = 1;
1601 #if defined(APIC_IO)
1602 /* one and only IO APIC */
1603 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1606 * sanity check, refer to MP spec section 3.6.6, last paragraph
1607 * necessary as some hardware isn't properly setting up the IO APIC
1609 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1610 if (io_apic_id != 2) {
1612 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1613 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1614 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
1615 ux &= ~APIC_ID_MASK; /* clear the ID field */
1616 ux |= 0x02000000; /* set it to '2' */
1617 io_apic_write(0, IOAPIC_ID, ux); /* write new value */
1618 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
1619 if ((ux & APIC_ID_MASK) != 0x02000000)
1620 panic("can't control IO APIC ID, reg: 0x%08x", ux);
1623 IO_TO_ID(0) = io_apic_id;
1624 ID_TO_IO(io_apic_id) = 0;
1625 #endif /* APIC_IO */
1627 /* fill out bus entries */
1634 bus_data[0].bus_id = default_data[type - 1][1];
1635 bus_data[0].bus_type = default_data[type - 1][2];
1636 bus_data[1].bus_id = default_data[type - 1][3];
1637 bus_data[1].bus_type = default_data[type - 1][4];
1640 /* case 4: case 7: MCA NOT supported */
1641 default: /* illegal/reserved */
1642 panic("BAD default MP config: %d", type);
1646 #if defined(APIC_IO)
1647 /* general cases from MP v1.4, table 5-2 */
1648 for (pin = 0; pin < 16; ++pin) {
1649 io_apic_ints[pin].int_type = 0;
1650 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1651 io_apic_ints[pin].src_bus_id = 0;
1652 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1653 io_apic_ints[pin].dst_apic_id = io_apic_id;
1654 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1657 /* special cases from MP v1.4, table 5-2 */
1659 io_apic_ints[2].int_type = 0xff; /* N/C */
1660 io_apic_ints[13].int_type = 0xff; /* N/C */
1661 #if !defined(APIC_MIXED_MODE)
1663 panic("sorry, can't support type 2 default yet");
1664 #endif /* APIC_MIXED_MODE */
1667 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1670 io_apic_ints[0].int_type = 0xff; /* N/C */
1672 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1673 #endif /* APIC_IO */
1678 * initialize all the SMP locks
1681 /* critical region around IO APIC, apic_imen */
1682 struct simplelock imen_lock;
1684 /* critical region around splxx(), cpl, cml, cil, ipending */
1685 struct simplelock cpl_lock;
1687 /* Make FAST_INTR() routines sequential */
1688 struct simplelock fast_intr_lock;
1690 /* critical region around INTR() routines */
1691 struct simplelock intr_lock;
1693 /* lock regions protected in UP kernel via cli/sti */
1694 struct simplelock mpintr_lock;
1696 /* lock region used by kernel profiling */
1697 struct simplelock mcount_lock;
1700 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1701 struct simplelock com_lock;
1702 #endif /* USE_COMLOCK */
1704 #ifdef USE_CLOCKLOCK
1705 /* lock regions around the clock hardware */
1706 struct simplelock clock_lock;
1707 #endif /* USE_CLOCKLOCK */
1713 * Get the initial mp_lock with a count of 1 for the BSP.
1714 * This uses a LOGICAL cpu ID, ie BSP == 0.
1716 mp_lock = 0x00000001;
1718 /* ISR uses its own "giant lock" */
1719 isr_lock = FREE_LOCK;
1721 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1722 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1725 s_lock_init((struct simplelock*)&mpintr_lock);
1727 s_lock_init((struct simplelock*)&mcount_lock);
1729 s_lock_init((struct simplelock*)&fast_intr_lock);
1730 s_lock_init((struct simplelock*)&intr_lock);
1731 s_lock_init((struct simplelock*)&imen_lock);
1732 s_lock_init((struct simplelock*)&cpl_lock);
1735 s_lock_init((struct simplelock*)&com_lock);
1736 #endif /* USE_COMLOCK */
1737 #ifdef USE_CLOCKLOCK
1738 s_lock_init((struct simplelock*)&clock_lock);
1739 #endif /* USE_CLOCKLOCK */
1743 /* Wait for all APs to be fully initialized */
1744 extern int wait_ap(unsigned int);
1747 * start each AP in our list
1750 start_all_aps(u_int boot_addr)
1753 u_char mpbiosreason;
1754 u_long mpbioswarmvec;
1755 struct globaldata *gd;
1758 POSTCODE(START_ALL_APS_POST);
1760 /* initialize BSP's local APIC */
1764 /* install the AP 1st level boot code */
1765 install_ap_tramp(boot_addr);
1768 /* save the current value of the warm-start vector */
1769 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1771 outb(CMOS_REG, BIOS_RESET);
1772 mpbiosreason = inb(CMOS_DATA);
1775 /* record BSP in CPU map */
1778 /* set up 0 -> 4MB P==V mapping for AP boot */
1779 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
1783 for (x = 1; x <= mp_naps; ++x) {
1785 /* This is a bit verbose, it will go away soon. */
1787 /* first page of AP's private space */
1788 pg = x * i386_btop(sizeof(struct privatespace));
1790 /* allocate a new private data page */
1791 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1793 /* wire it into the private page table page */
1794 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1796 /* allocate and set up an idle stack data page */
1797 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1798 for (i = 0; i < UPAGES; i++)
1799 SMPpt[pg + 5 + i] = (pt_entry_t)
1800 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1802 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */
1803 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */
1804 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */
1805 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */
1807 /* prime data page for it to use */
1809 gd->gd_cpu_lockid = x << 24;
1810 gd->gd_prv_CMAP1 = &SMPpt[pg + 1];
1811 gd->gd_prv_CMAP2 = &SMPpt[pg + 2];
1812 gd->gd_prv_CMAP3 = &SMPpt[pg + 3];
1813 gd->gd_prv_PMAP1 = &SMPpt[pg + 4];
1814 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1;
1815 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2;
1816 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3;
1817 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1;
1819 /* setup a vector to our boot code */
1820 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1821 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1823 outb(CMOS_REG, BIOS_RESET);
1824 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1827 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
1830 /* attempt to start the Application Processor */
1831 CHECK_INIT(99); /* setup checkpoints */
1832 if (!start_ap(x, boot_addr)) {
1833 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1834 CHECK_PRINT("trace"); /* show checkpoints */
1835 /* better panic as the AP may be running loose */
1836 printf("panic y/n? [y] ");
1837 if (cngetc() != 'n')
1840 CHECK_PRINT("trace"); /* show checkpoints */
1842 /* record its version info */
1843 cpu_apic_versions[x] = cpu_apic_versions[0];
1845 all_cpus |= (1 << x); /* record AP in CPU map */
1848 /* build our map of 'other' CPUs */
1849 other_cpus = all_cpus & ~(1 << cpuid);
1851 /* fill in our (BSP) APIC version */
1852 cpu_apic_versions[0] = lapic.version;
1854 /* restore the warmstart vector */
1855 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1857 outb(CMOS_REG, BIOS_RESET);
1858 outb(CMOS_DATA, mpbiosreason);
1862 * Set up the idle context for the BSP. Similar to above except
1863 * that some was done by locore, some by pmap.c and some is implicit
1864 * because the BSP is cpu#0 and the page is initially zero, and also
1865 * because we can refer to variables by name on the BSP..
1868 /* Allocate and setup BSP idle stack */
1869 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
1870 for (i = 0; i < UPAGES; i++)
1871 SMPpt[5 + i] = (pt_entry_t)
1872 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1877 /* number of APs actually started */
1878 return mp_ncpus - 1;
1883 * load the 1st level AP boot code into base memory.
1886 /* targets for relocation */
1887 extern void bigJump(void);
1888 extern void bootCodeSeg(void);
1889 extern void bootDataSeg(void);
1890 extern void MPentry(void);
1891 extern u_int MP_GDT;
1892 extern u_int mp_gdtbase;
1895 install_ap_tramp(u_int boot_addr)
1898 int size = *(int *) ((u_long) & bootMP_size);
1899 u_char *src = (u_char *) ((u_long) bootMP);
1900 u_char *dst = (u_char *) boot_addr + KERNBASE;
1901 u_int boot_base = (u_int) bootMP;
1906 POSTCODE(INSTALL_AP_TRAMP_POST);
1908 for (x = 0; x < size; ++x)
1912 * modify addresses in code we just moved to basemem. unfortunately we
1913 * need fairly detailed info about mpboot.s for this to work. changes
1914 * to mpboot.s might require changes here.
1917 /* boot code is located in KERNEL space */
1918 dst = (u_char *) boot_addr + KERNBASE;
1920 /* modify the lgdt arg */
1921 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1922 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1924 /* modify the ljmp target for MPentry() */
1925 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1926 *dst32 = ((u_int) MPentry - KERNBASE);
1928 /* modify the target for boot code segment */
1929 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1930 dst8 = (u_int8_t *) (dst16 + 1);
1931 *dst16 = (u_int) boot_addr & 0xffff;
1932 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1934 /* modify the target for boot data segment */
1935 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1936 dst8 = (u_int8_t *) (dst16 + 1);
1937 *dst16 = (u_int) boot_addr & 0xffff;
1938 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1943 * this function starts the AP (application processor) identified
1944 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1945 * to accomplish this. This is necessary because of the nuances
1946 * of the different hardware we might encounter. It ain't pretty,
1947 * but it seems to work.
1950 start_ap(int logical_cpu, u_int boot_addr)
1955 u_long icr_lo, icr_hi;
1957 POSTCODE(START_AP_POST);
1959 /* get the PHYSICAL APIC ID# */
1960 physical_cpu = CPU_TO_ID(logical_cpu);
1962 /* calculate the vector */
1963 vector = (boot_addr >> 12) & 0xff;
1965 /* used as a watchpoint to signal AP startup */
1969 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1970 * and running the target CPU. OR this INIT IPI might be latched (P5
1971 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1975 /* setup the address for the target AP */
1976 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1977 icr_hi |= (physical_cpu << 24);
1978 lapic.icr_hi = icr_hi;
1980 /* do an INIT IPI: assert RESET */
1981 icr_lo = lapic.icr_lo & 0xfff00000;
1982 lapic.icr_lo = icr_lo | 0x0000c500;
1984 /* wait for pending status end */
1985 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1988 /* do an INIT IPI: deassert RESET */
1989 lapic.icr_lo = icr_lo | 0x00008500;
1991 /* wait for pending status end */
1992 u_sleep(10000); /* wait ~10mS */
1993 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1997 * next we do a STARTUP IPI: the previous INIT IPI might still be
1998 * latched, (P5 bug) this 1st STARTUP would then terminate
1999 * immediately, and the previously started INIT IPI would continue. OR
2000 * the previous INIT IPI has already run. and this STARTUP IPI will
2001 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2005 /* do a STARTUP IPI */
2006 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2007 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2009 u_sleep(200); /* wait ~200uS */
2012 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2013 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2014 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2015 * recognized after hardware RESET or INIT IPI.
2018 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2019 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2021 u_sleep(200); /* wait ~200uS */
2023 /* wait for it to start */
2024 set_apic_timer(5000000);/* == 5 seconds */
2025 while (read_apic_timer())
2026 if (mp_ncpus > cpus)
2027 return 1; /* return SUCCESS */
2029 return 0; /* return FAILURE */
2034 * Flush the TLB on all other CPU's
2036 * XXX: Needs to handshake and wait for completion before proceding.
2041 #if defined(APIC_IO)
2042 if (smp_started && invltlb_ok)
2043 all_but_self_ipi(XINVLTLB_OFFSET);
2044 #endif /* APIC_IO */
2050 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2052 /* send a message to the other CPUs */
2062 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2065 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2067 /* send a message to the other CPUs */
2073 * When called the executing CPU will send an IPI to all other CPUs
2074 * requesting that they halt execution.
2076 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2078 * - Signals all CPUs in map to stop.
2079 * - Waits for each to stop.
2086 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2087 * from executing at same time.
2090 stop_cpus(u_int map)
2095 /* send the Xcpustop IPI to all CPUs in map */
2096 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2098 while ((stopped_cpus & map) != map)
2106 * Called by a CPU to restart stopped CPUs.
2108 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2110 * - Signals all CPUs in map to restart.
2111 * - Waits for each to restart.
2119 restart_cpus(u_int map)
2124 started_cpus = map; /* signal other cpus to restart */
2126 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2132 int smp_active = 0; /* are the APs allowed to run? */
2133 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2135 /* XXX maybe should be hw.ncpu */
2136 static int smp_cpus = 1; /* how many cpu's running */
2137 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2139 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2140 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2142 /* Warning: Do not staticize. Used from swtch.s */
2143 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2144 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2145 &do_page_zero_idle, 0, "");
2147 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2148 int forward_irq_enabled = 1;
2149 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2150 &forward_irq_enabled, 0, "");
2152 /* Enable forwarding of a signal to a process running on a different CPU */
2153 static int forward_signal_enabled = 1;
2154 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2155 &forward_signal_enabled, 0, "");
2157 /* Enable forwarding of roundrobin to all other cpus */
2158 static int forward_roundrobin_enabled = 1;
2159 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2160 &forward_roundrobin_enabled, 0, "");
2163 * This is called once the rest of the system is up and running and we're
2164 * ready to let the AP's out of the pen.
2173 /* BSP may have changed PTD while we're waiting for the lock */
2178 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2182 /* Build our map of 'other' CPUs. */
2183 other_cpus = all_cpus & ~(1 << cpuid);
2185 printf("SMP: AP CPU #%d Launched!\n", cpuid);
2187 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
2188 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
2190 /* A quick check from sanity claus */
2191 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2192 if (cpuid != apic_id) {
2193 printf("SMP: cpuid = %d\n", cpuid);
2194 printf("SMP: apic_id = %d\n", apic_id);
2195 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2196 panic("cpuid mismatch! boom!!");
2199 /* Init local apic for irq's */
2202 /* Set memory range attributes for this CPU to match the BSP */
2203 mem_range_AP_init();
2206 * Activate smp_invltlb, although strictly speaking, this isn't
2207 * quite correct yet. We should have a bitfield for cpus willing
2208 * to accept TLB flush IPI's or something and sync them.
2210 if (smp_cpus == mp_ncpus) {
2212 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2213 smp_active = 1; /* historic */
2219 #define CHECKSTATE_USER 0
2220 #define CHECKSTATE_SYS 1
2221 #define CHECKSTATE_INTR 2
2223 /* Do not staticize. Used from apic_vector.s */
2224 struct proc* checkstate_curproc[NCPU];
2225 int checkstate_cpustate[NCPU];
2226 u_long checkstate_pc[NCPU];
2228 extern long cp_time[CPUSTATES];
2230 #define PC_TO_INDEX(pc, prof) \
2231 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2232 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2235 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2241 pc = checkstate_pc[id];
2242 prof = &p->p_stats->p_prof;
2243 if (pc >= prof->pr_off &&
2244 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2245 if ((p->p_flag & P_OWEUPC) == 0) {
2248 p->p_flag |= P_OWEUPC;
2250 *astmap |= (1 << id);
2255 forwarded_statclock(int id, int pscnt, int *astmap)
2257 struct pstats *pstats;
2264 register struct gmonparam *g;
2268 p = checkstate_curproc[id];
2269 cpustate = checkstate_cpustate[id];
2272 case CHECKSTATE_USER:
2273 if (p->p_flag & P_PROFIL)
2274 addupc_intr_forwarded(p, id, astmap);
2278 if (p->p_nice > NZERO)
2283 case CHECKSTATE_SYS:
2286 * Kernel statistics are just like addupc_intr, only easier.
2289 if (g->state == GMON_PROF_ON) {
2290 i = checkstate_pc[id] - g->lowpc;
2291 if (i < g->textsize) {
2292 i /= HISTFRACTION * sizeof(*g->kcount);
2307 case CHECKSTATE_INTR:
2311 * Kernel statistics are just like addupc_intr, only easier.
2314 if (g->state == GMON_PROF_ON) {
2315 i = checkstate_pc[id] - g->lowpc;
2316 if (i < g->textsize) {
2317 i /= HISTFRACTION * sizeof(*g->kcount);
2330 if (++p->p_estcpu == 0)
2332 if ((p->p_estcpu & 3) == 0) {
2334 if (p->p_priority >= PUSER)
2335 p->p_priority = p->p_usrpri;
2338 /* Update resource usage integrals and maximums. */
2339 if ((pstats = p->p_stats) != NULL &&
2340 (ru = &pstats->p_ru) != NULL &&
2341 (vm = p->p_vmspace) != NULL) {
2342 ru->ru_ixrss += pgtok(vm->vm_tsize);
2343 ru->ru_idrss += pgtok(vm->vm_dsize);
2344 ru->ru_isrss += pgtok(vm->vm_ssize);
2345 rss = pgtok(vmspace_resident_count(vm));
2346 if (ru->ru_maxrss < rss)
2347 ru->ru_maxrss = rss;
2353 forward_statclock(int pscnt)
2359 /* Kludge. We don't yet have separate locks for the interrupts
2360 * and the kernel. This means that we cannot let the other processors
2361 * handle complex interrupts while inhibiting them from entering
2362 * the kernel in a non-interrupt context.
2364 * What we can do, without changing the locking mechanisms yet,
2365 * is letting the other processors handle a very simple interrupt
2366 * (wich determines the processor states), and do the main
2370 if (!smp_started || !invltlb_ok || cold || panicstr)
2373 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2375 map = other_cpus & ~stopped_cpus ;
2376 checkstate_probed_cpus = 0;
2378 selected_apic_ipi(map,
2379 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2382 while (checkstate_probed_cpus != map) {
2386 #ifdef BETTER_CLOCK_DIAGNOSTIC
2387 printf("forward_statclock: checkstate %x\n",
2388 checkstate_probed_cpus);
2395 * Step 2: walk through other processors processes, update ticks and
2400 for (id = 0; id < mp_ncpus; id++) {
2403 if (((1 << id) & checkstate_probed_cpus) == 0)
2405 forwarded_statclock(id, pscnt, &map);
2408 checkstate_need_ast |= map;
2409 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2411 while ((checkstate_need_ast & map) != 0) {
2415 #ifdef BETTER_CLOCK_DIAGNOSTIC
2416 printf("forward_statclock: dropped ast 0x%x\n",
2417 checkstate_need_ast & map);
2426 forward_hardclock(int pscnt)
2431 struct pstats *pstats;
2434 /* Kludge. We don't yet have separate locks for the interrupts
2435 * and the kernel. This means that we cannot let the other processors
2436 * handle complex interrupts while inhibiting them from entering
2437 * the kernel in a non-interrupt context.
2439 * What we can do, without changing the locking mechanisms yet,
2440 * is letting the other processors handle a very simple interrupt
2441 * (wich determines the processor states), and do the main
2445 if (!smp_started || !invltlb_ok || cold || panicstr)
2448 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2450 map = other_cpus & ~stopped_cpus ;
2451 checkstate_probed_cpus = 0;
2453 selected_apic_ipi(map,
2454 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2457 while (checkstate_probed_cpus != map) {
2461 #ifdef BETTER_CLOCK_DIAGNOSTIC
2462 printf("forward_hardclock: checkstate %x\n",
2463 checkstate_probed_cpus);
2470 * Step 2: walk through other processors processes, update virtual
2471 * timer and profiling timer. If stathz == 0, also update ticks and
2476 for (id = 0; id < mp_ncpus; id++) {
2479 if (((1 << id) & checkstate_probed_cpus) == 0)
2481 p = checkstate_curproc[id];
2483 pstats = p->p_stats;
2484 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2485 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2486 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2487 psignal(p, SIGVTALRM);
2490 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2491 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2492 psignal(p, SIGPROF);
2497 forwarded_statclock( id, pscnt, &map);
2501 checkstate_need_ast |= map;
2502 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2504 while ((checkstate_need_ast & map) != 0) {
2508 #ifdef BETTER_CLOCK_DIAGNOSTIC
2509 printf("forward_hardclock: dropped ast 0x%x\n",
2510 checkstate_need_ast & map);
2518 #endif /* BETTER_CLOCK */
2521 forward_signal(struct proc *p)
2527 /* Kludge. We don't yet have separate locks for the interrupts
2528 * and the kernel. This means that we cannot let the other processors
2529 * handle complex interrupts while inhibiting them from entering
2530 * the kernel in a non-interrupt context.
2532 * What we can do, without changing the locking mechanisms yet,
2533 * is letting the other processors handle a very simple interrupt
2534 * (wich determines the processor states), and do the main
2538 if (!smp_started || !invltlb_ok || cold || panicstr)
2540 if (!forward_signal_enabled)
2543 if (p->p_stat != SRUN)
2549 checkstate_need_ast |= map;
2550 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2552 while ((checkstate_need_ast & map) != 0) {
2557 printf("forward_signal: dropped ast 0x%x\n",
2558 checkstate_need_ast & map);
2563 if (id == p->p_oncpu)
2569 forward_roundrobin(void)
2574 if (!smp_started || !invltlb_ok || cold || panicstr)
2576 if (!forward_roundrobin_enabled)
2578 resched_cpus |= other_cpus;
2579 map = other_cpus & ~stopped_cpus ;
2581 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2583 (void) all_but_self_ipi(XCPUAST_OFFSET);
2586 while ((checkstate_need_ast & map) != 0) {
2591 printf("forward_roundrobin: dropped ast 0x%x\n",
2592 checkstate_need_ast & map);
2600 #ifdef APIC_INTR_REORDER
2602 * Maintain mapping from softintr vector to isr bit in local apic.
2605 set_lapic_isrloc(int intr, int vector)
2607 if (intr < 0 || intr > 32)
2608 panic("set_apic_isrloc: bad intr argument: %d",intr);
2609 if (vector < ICU_OFFSET || vector > 255)
2610 panic("set_apic_isrloc: bad vector argument: %d",vector);
2611 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2612 apic_isrbit_location[intr].bit = (1<<(vector & 31));