2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/cpuset.h>
43 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/sysctl.h>
56 #include <vm/vm_param.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cputypes.h>
64 #include <machine/cpufunc.h>
66 #include <machine/md_var.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
72 #include <machine/cpu.h>
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 /* lock region used by kernel profiling */
87 int mp_naps; /* # of Applications processors */
88 int boot_cpu_id = -1; /* designated BSP */
90 extern struct pcpu __pcpu[];
92 /* AP uses this during bootstrap. Do not staticize. */
96 /* Free these after use */
97 void *bootstacks[MAXCPU];
99 /* Temporary variables for init_secondary() */
100 char *doublefault_stack;
104 struct pcb stoppcbs[MAXCPU];
105 struct susppcb **susppcbs;
107 /* Variables needed for SMP tlb shootdown. */
108 vm_offset_t smp_tlb_addr2;
109 struct invpcid_descr smp_tlb_invpcid;
110 volatile int smp_tlb_wait;
113 extern int invpcid_works;
116 /* Interrupt counts. */
117 static u_long *ipi_preempt_counts[MAXCPU];
118 static u_long *ipi_ast_counts[MAXCPU];
119 u_long *ipi_invltlb_counts[MAXCPU];
120 u_long *ipi_invlrng_counts[MAXCPU];
121 u_long *ipi_invlpg_counts[MAXCPU];
122 u_long *ipi_invlcache_counts[MAXCPU];
123 u_long *ipi_rendezvous_counts[MAXCPU];
124 static u_long *ipi_hardclock_counts[MAXCPU];
127 /* Default cpu_ops implementation. */
128 struct cpu_ops cpu_ops;
130 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
132 extern int pmap_pcid_enabled;
135 * Local data and functions.
138 static volatile cpuset_t ipi_nmi_pending;
140 /* used to hold the AP's until we are ready to release them */
141 struct mtx ap_boot_mtx;
143 /* Set to 1 once we're ready to let the APs out of the pen. */
144 static volatile int aps_ready = 0;
147 * Store data from cpu_add() until later in the boot when we actually setup
154 int cpu_hyperthread:1;
155 } static cpu_info[MAX_APIC_ID + 1];
156 int cpu_apic_ids[MAXCPU];
157 int apic_cpuids[MAX_APIC_ID + 1];
159 /* Holds pending bitmap based IPIs per CPU */
160 volatile u_int cpu_ipi_pending[MAXCPU];
162 static u_int boot_address;
163 static int cpu_logical; /* logical cpus per core */
164 static int cpu_cores; /* cores per package */
166 static void assign_cpu_ids(void);
167 static void set_interrupt_apic_ids(void);
168 static int start_ap(int apic_id);
169 static void release_aps(void *dummy);
171 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
172 static int hyperthreading_allowed = 1;
173 static u_int bootMP_size;
176 mem_range_AP_init(void)
178 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
179 mem_range_softc.mr_op->initAP(&mem_range_softc);
188 /* AMD processors do not support HTT. */
191 if ((amd_feature2 & AMDID2_CMP) == 0) {
196 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
197 AMDID_COREID_SIZE_SHIFT;
198 if (core_id_bits == 0) {
199 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
203 /* Fam 10h and newer should get here. */
204 for (id = 0; id <= MAX_APIC_ID; id++) {
205 /* Check logical CPU availability. */
206 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
208 /* Check if logical CPU has the same package ID. */
209 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
216 * Round up to the next power of two, if necessary, and then
218 * Returns -1 if argument is zero.
224 return (fls(x << (1 - powerof2(x))) - 1);
237 /* Both zero and one here mean one logical processor per package. */
238 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
239 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
240 if (max_logical <= 1)
244 * Because of uniformity assumption we examine only
245 * those logical processors that belong to the same
246 * package as BSP. Further, we count number of
247 * logical processors that belong to the same core
248 * as BSP thus deducing number of threads per core.
250 if (cpu_high >= 0x4) {
251 cpuid_count(0x04, 0, p);
252 max_cores = ((p[0] >> 26) & 0x3f) + 1;
255 core_id_bits = mask_width(max_logical/max_cores);
256 if (core_id_bits < 0)
258 pkg_id_bits = core_id_bits + mask_width(max_cores);
260 for (id = 0; id <= MAX_APIC_ID; id++) {
261 /* Check logical CPU availability. */
262 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
264 /* Check if logical CPU has the same package ID. */
265 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
268 /* Check if logical CPU has the same package and core IDs. */
269 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
273 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
274 ("topo_probe_0x4 couldn't find BSP"));
276 cpu_cores /= cpu_logical;
277 hyperthreading_cpus = cpu_logical;
291 /* We only support three levels for now. */
292 for (i = 0; i < 3; i++) {
293 cpuid_count(0x0b, i, p);
295 /* Fall back if CPU leaf 11 doesn't really exist. */
296 if (i == 0 && p[1] == 0) {
302 logical = p[1] &= 0xffff;
303 type = (p[2] >> 8) & 0xff;
304 if (type == 0 || logical == 0)
307 * Because of uniformity assumption we examine only
308 * those logical processors that belong to the same
311 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
312 if (!cpu_info[x].cpu_present ||
313 cpu_info[x].cpu_disabled)
315 if (x >> bits == boot_cpu_id >> bits)
318 if (type == CPUID_TYPE_SMT)
320 else if (type == CPUID_TYPE_CORE)
323 if (cpu_logical == 0)
325 cpu_cores /= cpu_logical;
329 * Both topology discovery code and code that consumes topology
330 * information assume top-down uniformity of the topology.
331 * That is, all physical packages must be identical and each
332 * core in a package must have the same number of threads.
333 * Topology information is queried only on BSP, on which this
334 * code runs and for which it can query CPUID information.
335 * Then topology is extrapolated on all packages using the
336 * uniformity assumption.
341 static int cpu_topo_probed = 0;
346 CPU_ZERO(&logical_cpus_mask);
348 cpu_cores = cpu_logical = 1;
349 else if (cpu_vendor_id == CPU_VENDOR_AMD)
351 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
353 * See Intel(R) 64 Architecture Processor
354 * Topology Enumeration article for details.
356 * Note that 0x1 <= cpu_high < 4 case should be
357 * compatible with topo_probe_0x4() logic when
358 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
359 * or it should trigger the fallback otherwise.
363 else if (cpu_high >= 0x1)
368 * Fallback: assume each logical CPU is in separate
369 * physical package. That is, no multi-core, no SMT.
371 if (cpu_cores == 0 || cpu_logical == 0)
372 cpu_cores = cpu_logical = 1;
382 * Determine whether any threading flags are
386 if (cpu_logical > 1 && hyperthreading_cpus)
387 cg_flags = CG_FLAG_HTT;
388 else if (cpu_logical > 1)
389 cg_flags = CG_FLAG_SMT;
392 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
393 printf("WARNING: Non-uniform processors.\n");
394 printf("WARNING: Using suboptimal topology.\n");
395 return (smp_topo_none());
398 * No multi-core or hyper-threaded.
400 if (cpu_logical * cpu_cores == 1)
401 return (smp_topo_none());
403 * Only HTT no multi-core.
405 if (cpu_logical > 1 && cpu_cores == 1)
406 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
408 * Only multi-core no HTT.
410 if (cpu_cores > 1 && cpu_logical == 1)
411 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
413 * Both HTT and multi-core.
415 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
416 CG_SHARE_L1, cpu_logical, cg_flags));
420 * Calculate usable address in base memory for AP trampoline code.
423 mp_bootaddress(u_int basemem)
426 bootMP_size = mptramp_end - mptramp_start;
427 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
428 if (((basemem * 1024) - boot_address) < bootMP_size)
429 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
430 /* 3 levels of page table pages */
431 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
433 return mptramp_pagetables;
437 cpu_add(u_int apic_id, char boot_cpu)
440 if (apic_id > MAX_APIC_ID) {
441 panic("SMP: APIC ID %d too high", apic_id);
444 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
446 cpu_info[apic_id].cpu_present = 1;
448 KASSERT(boot_cpu_id == -1,
449 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
451 boot_cpu_id = apic_id;
452 cpu_info[apic_id].cpu_bsp = 1;
454 if (mp_ncpus < MAXCPU) {
456 mp_maxid = mp_ncpus - 1;
459 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
464 cpu_mp_setmaxid(void)
468 * mp_maxid should be already set by calls to cpu_add().
469 * Just sanity check its value here.
472 KASSERT(mp_maxid == 0,
473 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
474 else if (mp_ncpus == 1)
477 KASSERT(mp_maxid >= mp_ncpus - 1,
478 ("%s: counters out of sync: max %d, count %d", __func__,
479 mp_maxid, mp_ncpus));
487 * Always record BSP in CPU map so that the mbuf init code works
490 CPU_SETOF(0, &all_cpus);
493 * No CPUs were found, so this must be a UP system. Setup
494 * the variables to represent a system with a single CPU
501 /* At least one CPU was found. */
504 * One CPU was found, so this must be a UP system with
511 /* At least two CPUs were found. */
516 * Initialize the IPI handlers and start up the AP's.
523 /* Initialize the logical ID to APIC ID table. */
524 for (i = 0; i < MAXCPU; i++) {
525 cpu_apic_ids[i] = -1;
526 cpu_ipi_pending[i] = 0;
529 /* Install an inter-CPU IPI for TLB invalidation */
530 if (pmap_pcid_enabled) {
531 setidt(IPI_INVLTLB, IDTVEC(invltlb_pcid), SDT_SYSIGT,
533 setidt(IPI_INVLPG, IDTVEC(invlpg_pcid), SDT_SYSIGT,
536 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
537 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
539 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
541 /* Install an inter-CPU IPI for cache invalidation. */
542 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
544 /* Install an inter-CPU IPI for all-CPU rendezvous */
545 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
547 /* Install generic inter-CPU IPI handler */
548 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
549 SDT_SYSIGT, SEL_KPL, 0);
551 /* Install an inter-CPU IPI for CPU stop/restart */
552 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
554 /* Install an inter-CPU IPI for CPU suspend/resume */
555 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
557 /* Set boot_cpu_id if needed. */
558 if (boot_cpu_id == -1) {
559 boot_cpu_id = PCPU_GET(apic_id);
560 cpu_info[boot_cpu_id].cpu_bsp = 1;
562 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
563 ("BSP's APIC ID doesn't match boot_cpu_id"));
565 /* Probe logical/physical core configuration. */
570 /* Start each Application Processor */
571 init_ops.start_all_aps();
573 set_interrupt_apic_ids();
578 * Print various information about the SMP system hardware and setup.
581 cpu_mp_announce(void)
583 const char *hyperthread;
586 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
587 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
588 if (hyperthreading_cpus > 1)
589 printf(" x %d HTT threads", cpu_logical);
590 else if (cpu_logical > 1)
591 printf(" x %d SMT threads", cpu_logical);
594 /* List active CPUs first. */
595 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
596 for (i = 1; i < mp_ncpus; i++) {
597 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
601 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
605 /* List disabled CPUs last. */
606 for (i = 0; i <= MAX_APIC_ID; i++) {
607 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
609 if (cpu_info[i].cpu_hyperthread)
613 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
619 * AP CPU's call this to initialize themselves.
628 int cpu, gsel_tss, x;
629 struct region_descriptor ap_gdt;
631 /* Set by the startup code for us to use */
635 common_tss[cpu] = common_tss[0];
636 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
637 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
639 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
641 /* The NMI stack runs on IST2. */
642 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
643 common_tss[cpu].tss_ist2 = (long) np;
645 /* Prepare private GDT */
646 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
647 for (x = 0; x < NGDT; x++) {
648 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
649 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
650 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
652 ssdtosyssd(&gdt_segs[GPROC0_SEL],
653 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
654 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
655 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
656 lgdt(&ap_gdt); /* does magic intra-segment return */
658 /* Get per-cpu data */
661 /* prime data page for it to use */
662 pcpu_init(pc, cpu, sizeof(struct pcpu));
663 dpcpu_init(dpcpu, cpu);
664 pc->pc_apic_id = cpu_apic_ids[cpu];
665 pc->pc_prvspace = pc;
666 pc->pc_curthread = 0;
667 pc->pc_tssp = &common_tss[cpu];
668 pc->pc_commontssp = &common_tss[cpu];
670 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
672 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
673 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
674 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
677 /* Save the per-cpu pointer for use by the NMI handler. */
678 np->np_pcpu = (register_t) pc;
680 wrmsr(MSR_FSBASE, 0); /* User value */
681 wrmsr(MSR_GSBASE, (u_int64_t)pc);
682 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
686 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
690 * Set to a known state:
691 * Set by mpboot.s: CR0_PG, CR0_PE
692 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
695 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
698 /* Set up the fast syscall stuff */
699 msr = rdmsr(MSR_EFER) | EFER_SCE;
700 wrmsr(MSR_EFER, msr);
701 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
702 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
703 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
704 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
705 wrmsr(MSR_STAR, msr);
706 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
708 /* signal our startup to the BSP. */
711 /* Spin until the BSP releases the AP's. */
716 * On real hardware, switch to x2apic mode if possible. Do it
717 * after aps_ready was signalled, to avoid manipulating the
718 * mode while BSP might still want to send some IPI to us
719 * (second startup IPI is ignored on modern hardware etc).
723 /* Initialize the PAT MSR. */
726 /* set up CPU registers and state */
732 /* set up FPU state on the AP */
735 if (cpu_ops.cpu_init)
738 /* A quick check from sanity claus */
739 cpuid = PCPU_GET(cpuid);
740 if (PCPU_GET(apic_id) != lapic_id()) {
741 printf("SMP: cpuid = %d\n", cpuid);
742 printf("SMP: actual apic_id = %d\n", lapic_id());
743 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
744 panic("cpuid mismatch! boom!!");
747 /* Initialize curthread. */
748 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
749 PCPU_SET(curthread, PCPU_GET(idlethread));
753 mtx_lock_spin(&ap_boot_mtx);
755 /* Init local apic for irq's */
758 /* Set memory range attributes for this CPU to match the BSP */
763 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
764 printf("SMP: AP CPU #%d Launched!\n", cpuid);
766 /* Determine if we are a logical CPU. */
767 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
768 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
769 CPU_SET(cpuid, &logical_cpus_mask);
774 if (smp_cpus == mp_ncpus) {
775 /* enable IPI's, tlb shootdown, freezes etc */
776 atomic_store_rel_int(&smp_started, 1);
780 * Enable global pages TLB extension
781 * This also implicitly flushes the TLB
784 load_cr4(rcr4() | CR4_PGE);
785 if (pmap_pcid_enabled)
786 load_cr4(rcr4() | CR4_PCIDE);
790 mtx_unlock_spin(&ap_boot_mtx);
792 /* Wait until all the AP's are up. */
793 while (smp_started == 0)
796 /* Start per-CPU event timers. */
801 panic("scheduler returned us to %s", __func__);
805 /*******************************************************************
806 * local functions and data
810 * We tell the I/O APIC code about all the CPUs we want to receive
811 * interrupts. If we don't want certain CPUs to receive IRQs we
812 * can simply not tell the I/O APIC code about them in this function.
813 * We also do not tell it about the BSP since it tells itself about
814 * the BSP internally to work with UP kernels and on UP machines.
817 set_interrupt_apic_ids(void)
821 for (i = 0; i < MAXCPU; i++) {
822 apic_id = cpu_apic_ids[i];
825 if (cpu_info[apic_id].cpu_bsp)
827 if (cpu_info[apic_id].cpu_disabled)
830 /* Don't let hyperthreads service interrupts. */
831 if (cpu_logical > 1 &&
832 apic_id % cpu_logical != 0)
840 * Assign logical CPU IDs to local APICs.
847 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
848 &hyperthreading_allowed);
850 /* Check for explicitly disabled CPUs. */
851 for (i = 0; i <= MAX_APIC_ID; i++) {
852 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
855 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
856 cpu_info[i].cpu_hyperthread = 1;
859 * Don't use HT CPU if it has been disabled by a
862 if (hyperthreading_allowed == 0) {
863 cpu_info[i].cpu_disabled = 1;
868 /* Don't use this CPU if it has been disabled by a tunable. */
869 if (resource_disabled("lapic", i)) {
870 cpu_info[i].cpu_disabled = 1;
875 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
876 hyperthreading_cpus = 0;
881 * Assign CPU IDs to local APIC IDs and disable any CPUs
882 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
884 * To minimize confusion for userland, we attempt to number
885 * CPUs such that all threads and cores in a package are
886 * grouped together. For now we assume that the BSP is always
887 * the first thread in a package and just start adding APs
888 * starting with the BSP's APIC ID.
891 cpu_apic_ids[0] = boot_cpu_id;
892 apic_cpuids[boot_cpu_id] = 0;
893 for (i = boot_cpu_id + 1; i != boot_cpu_id;
894 i == MAX_APIC_ID ? i = 0 : i++) {
895 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
896 cpu_info[i].cpu_disabled)
899 if (mp_ncpus < MAXCPU) {
900 cpu_apic_ids[mp_ncpus] = i;
901 apic_cpuids[i] = mp_ncpus;
904 cpu_info[i].cpu_disabled = 1;
906 KASSERT(mp_maxid >= mp_ncpus - 1,
907 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
912 * start each AP in our list
915 native_start_all_aps(void)
917 vm_offset_t va = boot_address + KERNBASE;
918 u_int64_t *pt4, *pt3, *pt2;
919 u_int32_t mpbioswarmvec;
923 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
925 /* install the AP 1st level boot code */
926 pmap_kenter(va, boot_address);
927 pmap_invalidate_page(kernel_pmap, va);
928 bcopy(mptramp_start, (void *)va, bootMP_size);
930 /* Locate the page tables, they'll be below the trampoline */
931 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
932 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
933 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
935 /* Create the initial 1GB replicated page tables */
936 for (i = 0; i < 512; i++) {
937 /* Each slot of the level 4 pages points to the same level 3 page */
938 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
939 pt4[i] |= PG_V | PG_RW | PG_U;
941 /* Each slot of the level 3 pages points to the same level 2 page */
942 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
943 pt3[i] |= PG_V | PG_RW | PG_U;
945 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
946 pt2[i] = i * (2 * 1024 * 1024);
947 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
950 /* save the current value of the warm-start vector */
951 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
952 outb(CMOS_REG, BIOS_RESET);
953 mpbiosreason = inb(CMOS_DATA);
955 /* setup a vector to our boot code */
956 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
957 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
958 outb(CMOS_REG, BIOS_RESET);
959 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
962 for (cpu = 1; cpu < mp_ncpus; cpu++) {
963 apic_id = cpu_apic_ids[cpu];
965 /* allocate and set up an idle stack data page */
966 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
967 KSTACK_PAGES * PAGE_SIZE, M_WAITOK | M_ZERO);
968 doublefault_stack = (char *)kmem_malloc(kernel_arena,
969 PAGE_SIZE, M_WAITOK | M_ZERO);
970 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
972 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
975 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
978 /* attempt to start the Application Processor */
979 if (!start_ap(apic_id)) {
980 /* restore the warmstart vector */
981 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
982 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
985 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
988 /* restore the warmstart vector */
989 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
991 outb(CMOS_REG, BIOS_RESET);
992 outb(CMOS_DATA, mpbiosreason);
994 /* number of APs actually started */
1000 * This function starts the AP (application processor) identified
1001 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1002 * to accomplish this. This is necessary because of the nuances
1003 * of the different hardware we might encounter. It isn't pretty,
1004 * but it seems to work.
1007 start_ap(int apic_id)
1012 /* calculate the vector */
1013 vector = (boot_address >> 12) & 0xff;
1015 /* used as a watchpoint to signal AP startup */
1018 ipi_startup(apic_id, vector);
1020 /* Wait up to 5 seconds for it to start. */
1021 for (ms = 0; ms < 5000; ms++) {
1023 return 1; /* return SUCCESS */
1026 return 0; /* return FAILURE */
1029 #ifdef COUNT_XINVLTLB_HITS
1030 u_int xhits_gbl[MAXCPU];
1031 u_int xhits_pg[MAXCPU];
1032 u_int xhits_rng[MAXCPU];
1033 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1034 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1035 sizeof(xhits_gbl), "IU", "");
1036 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1037 sizeof(xhits_pg), "IU", "");
1038 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1039 sizeof(xhits_rng), "IU", "");
1044 u_int ipi_range_size;
1045 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1046 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1047 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1048 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW,
1049 &ipi_range_size, 0, "");
1051 u_int ipi_masked_global;
1052 u_int ipi_masked_page;
1053 u_int ipi_masked_range;
1054 u_int ipi_masked_range_size;
1055 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1056 &ipi_masked_global, 0, "");
1057 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1058 &ipi_masked_page, 0, "");
1059 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1060 &ipi_masked_range, 0, "");
1061 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1062 &ipi_masked_range_size, 0, "");
1063 #endif /* COUNT_XINVLTLB_HITS */
1066 * Init and startup IPI.
1069 ipi_startup(int apic_id, int vector)
1073 * This attempts to follow the algorithm described in the
1074 * Intel Multiprocessor Specification v1.4 in section B.4.
1075 * For each IPI, we allow the local APIC ~20us to deliver the
1076 * IPI. If that times out, we panic.
1080 * first we do an INIT IPI: this INIT IPI might be run, resetting
1081 * and running the target CPU. OR this INIT IPI might be latched (P5
1082 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1085 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1086 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1089 /* Explicitly deassert the INIT IPI. */
1090 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1091 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1094 DELAY(10000); /* wait ~10mS */
1097 * next we do a STARTUP IPI: the previous INIT IPI might still be
1098 * latched, (P5 bug) this 1st STARTUP would then terminate
1099 * immediately, and the previously started INIT IPI would continue. OR
1100 * the previous INIT IPI has already run. and this STARTUP IPI will
1101 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1104 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1105 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1107 if (!lapic_ipi_wait(20))
1108 panic("Failed to deliver first STARTUP IPI to APIC %d",
1110 DELAY(200); /* wait ~200uS */
1113 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1114 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1115 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1116 * recognized after hardware RESET or INIT IPI.
1118 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1119 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1121 if (!lapic_ipi_wait(20))
1122 panic("Failed to deliver second STARTUP IPI to APIC %d",
1125 DELAY(200); /* wait ~200uS */
1129 * Send an IPI to specified CPU handling the bitmap logic.
1132 ipi_send_cpu(int cpu, u_int ipi)
1134 u_int bitmap, old_pending, new_pending;
1136 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1138 if (IPI_IS_BITMAPED(ipi)) {
1140 ipi = IPI_BITMAP_VECTOR;
1142 old_pending = cpu_ipi_pending[cpu];
1143 new_pending = old_pending | bitmap;
1144 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1145 old_pending, new_pending));
1149 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1153 * Flush the TLB on all other CPU's
1156 smp_tlb_shootdown(u_int vector, pmap_t pmap, vm_offset_t addr1,
1161 ncpu = mp_ncpus - 1; /* does not shootdown self */
1163 return; /* no other cpus */
1164 if (!(read_rflags() & PSL_I))
1165 panic("%s: interrupts disabled", __func__);
1166 mtx_lock_spin(&smp_ipi_mtx);
1167 smp_tlb_invpcid.addr = addr1;
1169 smp_tlb_invpcid.pcid = 0;
1171 smp_tlb_invpcid.pcid = pmap->pm_pcid;
1172 pcid_cr3 = pmap->pm_cr3;
1174 smp_tlb_addr2 = addr2;
1175 smp_tlb_pmap = pmap;
1176 atomic_store_rel_int(&smp_tlb_wait, 0);
1177 ipi_all_but_self(vector);
1178 while (smp_tlb_wait < ncpu)
1180 mtx_unlock_spin(&smp_ipi_mtx);
1184 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1185 vm_offset_t addr1, vm_offset_t addr2)
1187 int cpu, ncpu, othercpus;
1189 othercpus = mp_ncpus - 1;
1190 if (CPU_ISFULLSET(&mask)) {
1194 CPU_CLR(PCPU_GET(cpuid), &mask);
1195 if (CPU_EMPTY(&mask))
1198 if (!(read_rflags() & PSL_I))
1199 panic("%s: interrupts disabled", __func__);
1200 mtx_lock_spin(&smp_ipi_mtx);
1201 smp_tlb_invpcid.addr = addr1;
1203 smp_tlb_invpcid.pcid = 0;
1205 smp_tlb_invpcid.pcid = pmap->pm_pcid;
1206 pcid_cr3 = pmap->pm_cr3;
1208 smp_tlb_addr2 = addr2;
1209 smp_tlb_pmap = pmap;
1210 atomic_store_rel_int(&smp_tlb_wait, 0);
1211 if (CPU_ISFULLSET(&mask)) {
1213 ipi_all_but_self(vector);
1216 while ((cpu = CPU_FFS(&mask)) != 0) {
1218 CPU_CLR(cpu, &mask);
1219 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1221 ipi_send_cpu(cpu, vector);
1225 while (smp_tlb_wait < ncpu)
1227 mtx_unlock_spin(&smp_ipi_mtx);
1231 smp_cache_flush(void)
1235 smp_tlb_shootdown(IPI_INVLCACHE, NULL, 0, 0);
1239 smp_invltlb(pmap_t pmap)
1243 smp_tlb_shootdown(IPI_INVLTLB, pmap, 0, 0);
1244 #ifdef COUNT_XINVLTLB_HITS
1251 smp_invlpg(pmap_t pmap, vm_offset_t addr)
1255 smp_tlb_shootdown(IPI_INVLPG, pmap, addr, 0);
1256 #ifdef COUNT_XINVLTLB_HITS
1263 smp_invlpg_range(pmap_t pmap, vm_offset_t addr1, vm_offset_t addr2)
1267 smp_tlb_shootdown(IPI_INVLRNG, pmap, addr1, addr2);
1268 #ifdef COUNT_XINVLTLB_HITS
1270 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1276 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1280 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1281 #ifdef COUNT_XINVLTLB_HITS
1282 ipi_masked_global++;
1288 smp_masked_invlpg(cpuset_t mask, pmap_t pmap, vm_offset_t addr)
1292 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0);
1293 #ifdef COUNT_XINVLTLB_HITS
1300 smp_masked_invlpg_range(cpuset_t mask, pmap_t pmap, vm_offset_t addr1,
1305 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, addr1,
1307 #ifdef COUNT_XINVLTLB_HITS
1309 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1315 ipi_bitmap_handler(struct trapframe frame)
1317 struct trapframe *oldframe;
1319 int cpu = PCPU_GET(cpuid);
1324 td->td_intr_nesting_level++;
1325 oldframe = td->td_intr_frame;
1326 td->td_intr_frame = &frame;
1327 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1328 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1330 (*ipi_preempt_counts[cpu])++;
1334 if (ipi_bitmap & (1 << IPI_AST)) {
1336 (*ipi_ast_counts[cpu])++;
1338 /* Nothing to do for AST */
1340 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1342 (*ipi_hardclock_counts[cpu])++;
1346 td->td_intr_frame = oldframe;
1347 td->td_intr_nesting_level--;
1352 * send an IPI to a set of cpus.
1355 ipi_selected(cpuset_t cpus, u_int ipi)
1360 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1361 * of help in order to understand what is the source.
1362 * Set the mask of receiving CPUs for this purpose.
1364 if (ipi == IPI_STOP_HARD)
1365 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
1367 while ((cpu = CPU_FFS(&cpus)) != 0) {
1369 CPU_CLR(cpu, &cpus);
1370 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1371 ipi_send_cpu(cpu, ipi);
1376 * send an IPI to a specific CPU.
1379 ipi_cpu(int cpu, u_int ipi)
1383 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1384 * of help in order to understand what is the source.
1385 * Set the mask of receiving CPUs for this purpose.
1387 if (ipi == IPI_STOP_HARD)
1388 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
1390 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1391 ipi_send_cpu(cpu, ipi);
1395 * send an IPI to all CPUs EXCEPT myself
1398 ipi_all_but_self(u_int ipi)
1400 cpuset_t other_cpus;
1402 other_cpus = all_cpus;
1403 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1405 if (IPI_IS_BITMAPED(ipi)) {
1406 ipi_selected(other_cpus, ipi);
1411 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1412 * of help in order to understand what is the source.
1413 * Set the mask of receiving CPUs for this purpose.
1415 if (ipi == IPI_STOP_HARD)
1416 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
1418 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1419 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1428 * As long as there is not a simple way to know about a NMI's
1429 * source, if the bitmask for the current CPU is present in
1430 * the global pending bitword an IPI_STOP_HARD has been issued
1431 * and should be handled.
1433 cpuid = PCPU_GET(cpuid);
1434 if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
1437 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
1443 * Handle an IPI_STOP by saving our current context and spinning until we
1447 cpustop_handler(void)
1451 cpu = PCPU_GET(cpuid);
1453 savectx(&stoppcbs[cpu]);
1455 /* Indicate that we are stopped */
1456 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1458 /* Wait for restart */
1459 while (!CPU_ISSET(cpu, &started_cpus))
1462 CPU_CLR_ATOMIC(cpu, &started_cpus);
1463 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1466 amd64_db_resume_dbreg();
1469 if (cpu == 0 && cpustop_restartfunc != NULL) {
1470 cpustop_restartfunc();
1471 cpustop_restartfunc = NULL;
1476 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1480 cpususpend_handler(void)
1484 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1486 cpu = PCPU_GET(cpuid);
1487 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1488 fpususpend(susppcbs[cpu]->sp_fpususpend);
1490 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1492 fpuresume(susppcbs[cpu]->sp_fpususpend);
1495 PCPU_SET(switchtime, 0);
1496 PCPU_SET(switchticks, ticks);
1498 /* Indicate that we are resumed */
1499 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1502 /* Wait for resume */
1503 while (!CPU_ISSET(cpu, &started_cpus))
1506 if (cpu_ops.cpu_resume)
1507 cpu_ops.cpu_resume();
1511 /* Resume MCA and local APIC */
1516 CPU_CLR_ATOMIC(cpu, &started_cpus);
1517 /* Indicate that we are resumed */
1518 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1522 * Handlers for TLB related IPIs
1525 invltlb_handler(void)
1527 #ifdef COUNT_XINVLTLB_HITS
1528 xhits_gbl[PCPU_GET(cpuid)]++;
1529 #endif /* COUNT_XINVLTLB_HITS */
1531 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1532 #endif /* COUNT_IPIS */
1535 atomic_add_int(&smp_tlb_wait, 1);
1539 invltlb_pcid_handler(void)
1543 #ifdef COUNT_XINVLTLB_HITS
1544 xhits_gbl[PCPU_GET(cpuid)]++;
1545 #endif /* COUNT_XINVLTLB_HITS */
1547 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1548 #endif /* COUNT_IPIS */
1550 if (smp_tlb_invpcid.pcid != (uint64_t)-1 &&
1551 smp_tlb_invpcid.pcid != 0) {
1552 if (invpcid_works) {
1553 invpcid(&smp_tlb_invpcid, INVPCID_CTX);
1555 /* Otherwise reload %cr3 twice. */
1557 if (cr3 != pcid_cr3) {
1559 cr3 |= CR3_PCID_SAVE;
1566 if (smp_tlb_pmap != NULL) {
1567 cpuid = PCPU_GET(cpuid);
1568 if (!CPU_ISSET(cpuid, &smp_tlb_pmap->pm_active))
1569 CPU_CLR_ATOMIC(cpuid, &smp_tlb_pmap->pm_save);
1572 atomic_add_int(&smp_tlb_wait, 1);
1576 invlpg_handler(void)
1578 #ifdef COUNT_XINVLTLB_HITS
1579 xhits_pg[PCPU_GET(cpuid)]++;
1580 #endif /* COUNT_XINVLTLB_HITS */
1582 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1583 #endif /* COUNT_IPIS */
1585 invlpg(smp_tlb_invpcid.addr);
1586 atomic_add_int(&smp_tlb_wait, 1);
1590 invlpg_pcid_handler(void)
1593 #ifdef COUNT_XINVLTLB_HITS
1594 xhits_pg[PCPU_GET(cpuid)]++;
1595 #endif /* COUNT_XINVLTLB_HITS */
1597 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1598 #endif /* COUNT_IPIS */
1600 if (smp_tlb_invpcid.pcid == (uint64_t)-1) {
1602 } else if (smp_tlb_invpcid.pcid == 0) {
1603 invlpg(smp_tlb_invpcid.addr);
1604 } else if (invpcid_works) {
1605 invpcid(&smp_tlb_invpcid, INVPCID_ADDR);
1608 * PCID supported, but INVPCID is not.
1609 * Temporarily switch to the target address
1610 * space and do INVLPG.
1613 if (cr3 != pcid_cr3)
1614 load_cr3(pcid_cr3 | CR3_PCID_SAVE);
1615 invlpg(smp_tlb_invpcid.addr);
1616 load_cr3(cr3 | CR3_PCID_SAVE);
1619 atomic_add_int(&smp_tlb_wait, 1);
1623 invlpg_range(vm_offset_t start, vm_offset_t end)
1629 } while (start < end);
1633 invlrng_handler(void)
1635 struct invpcid_descr d;
1639 #ifdef COUNT_XINVLTLB_HITS
1640 xhits_rng[PCPU_GET(cpuid)]++;
1641 #endif /* COUNT_XINVLTLB_HITS */
1643 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1644 #endif /* COUNT_IPIS */
1646 addr = smp_tlb_invpcid.addr;
1647 if (pmap_pcid_enabled) {
1648 if (smp_tlb_invpcid.pcid == 0) {
1650 * kernel pmap - use invlpg to invalidate
1653 invlpg_range(addr, smp_tlb_addr2);
1654 } else if (smp_tlb_invpcid.pcid == (uint64_t)-1) {
1656 if (smp_tlb_pmap != NULL) {
1657 cpuid = PCPU_GET(cpuid);
1658 if (!CPU_ISSET(cpuid, &smp_tlb_pmap->pm_active))
1659 CPU_CLR_ATOMIC(cpuid,
1660 &smp_tlb_pmap->pm_save);
1662 } else if (invpcid_works) {
1663 d = smp_tlb_invpcid;
1665 invpcid(&d, INVPCID_ADDR);
1666 d.addr += PAGE_SIZE;
1667 } while (d.addr <= smp_tlb_addr2);
1670 if (cr3 != pcid_cr3)
1671 load_cr3(pcid_cr3 | CR3_PCID_SAVE);
1672 invlpg_range(addr, smp_tlb_addr2);
1673 load_cr3(cr3 | CR3_PCID_SAVE);
1676 invlpg_range(addr, smp_tlb_addr2);
1679 atomic_add_int(&smp_tlb_wait, 1);
1683 invlcache_handler(void)
1686 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1687 #endif /* COUNT_IPIS */
1690 atomic_add_int(&smp_tlb_wait, 1);
1694 * This is called once the rest of the system is up and running and we're
1695 * ready to let the AP's out of the pen.
1698 release_aps(void *dummy __unused)
1703 atomic_store_rel_int(&aps_ready, 1);
1704 while (smp_started == 0)
1707 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1711 * Setup interrupt counters for IPI handlers.
1714 mp_ipi_intrcnt(void *dummy)
1720 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1721 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1722 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1723 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1724 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1725 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1726 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1727 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1728 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1729 intrcnt_add(buf, &ipi_preempt_counts[i]);
1730 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1731 intrcnt_add(buf, &ipi_ast_counts[i]);
1732 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1733 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1734 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1735 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1738 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);