2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1996, by Steve Passe
5 * Copyright (c) 2003, by Peter Wemm
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
35 #include "opt_sched.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/cpuset.h>
45 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/memrange.h>
50 #include <sys/mutex.h>
53 #include <sys/sched.h>
55 #include <sys/sysctl.h>
58 #include <vm/vm_param.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_extern.h>
63 #include <x86/apicreg.h>
64 #include <machine/clock.h>
65 #include <machine/cputypes.h>
66 #include <machine/cpufunc.h>
68 #include <machine/md_var.h>
69 #include <machine/pcb.h>
70 #include <machine/psl.h>
71 #include <machine/smp.h>
72 #include <machine/specialreg.h>
73 #include <machine/tss.h>
74 #include <machine/cpu.h>
77 #define WARMBOOT_TARGET 0
78 #define WARMBOOT_OFF (KERNBASE + 0x0467)
79 #define WARMBOOT_SEG (KERNBASE + 0x0469)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 extern struct pcpu __pcpu[];
88 /* Temporary variables for init_secondary() */
89 char *doublefault_stack;
94 * Local data and functions.
97 static int start_ap(int apic_id);
100 * Calculate usable address in base memory for AP trampoline code.
103 mp_bootaddress(vm_paddr_t *physmap, unsigned int *physmap_idx)
108 alloc_ap_trampoline(physmap, physmap_idx);
111 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
113 * Find a memory region big enough below the 4GB boundary to
114 * store the initial page tables. Note that it needs to be
115 * aligned to a page boundary.
117 if (physmap[i] >= GiB(4) ||
118 (physmap[i + 1] - round_page(physmap[i])) < (PAGE_SIZE * 3))
122 mptramp_pagetables = round_page(physmap[i]);
123 physmap[i] = round_page(physmap[i]) + (PAGE_SIZE * 3);
124 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
125 memmove(&physmap[i], &physmap[i + 2],
126 sizeof(*physmap) * (*physmap_idx - i + 2));
132 mptramp_pagetables = trunc_page(boot_address) - (PAGE_SIZE * 3);
135 "Cannot find enough space for the initial AP page tables, placing them at %#x",
141 * Initialize the IPI handlers and start up the AP's.
148 /* Initialize the logical ID to APIC ID table. */
149 for (i = 0; i < MAXCPU; i++) {
150 cpu_apic_ids[i] = -1;
151 cpu_ipi_pending[i] = 0;
154 /* Install an inter-CPU IPI for TLB invalidation */
155 if (pmap_pcid_enabled) {
157 setidt(IPI_INVLTLB, pti ?
158 IDTVEC(invltlb_invpcid_pti_pti) :
159 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
161 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
162 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
163 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
164 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
166 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
167 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
168 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
169 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
170 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
171 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
174 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
175 SDT_SYSIGT, SEL_KPL, 0);
176 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
177 SDT_SYSIGT, SEL_KPL, 0);
178 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
179 SDT_SYSIGT, SEL_KPL, 0);
182 /* Install an inter-CPU IPI for cache invalidation. */
183 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
184 SDT_SYSIGT, SEL_KPL, 0);
186 /* Install an inter-CPU IPI for all-CPU rendezvous */
187 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
188 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
190 /* Install generic inter-CPU IPI handler */
191 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
192 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
194 /* Install an inter-CPU IPI for CPU stop/restart */
195 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
196 SDT_SYSIGT, SEL_KPL, 0);
198 /* Install an inter-CPU IPI for CPU suspend/resume */
199 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
200 SDT_SYSIGT, SEL_KPL, 0);
202 /* Set boot_cpu_id if needed. */
203 if (boot_cpu_id == -1) {
204 boot_cpu_id = PCPU_GET(apic_id);
205 cpu_info[boot_cpu_id].cpu_bsp = 1;
207 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
208 ("BSP's APIC ID doesn't match boot_cpu_id"));
210 /* Probe logical/physical core configuration. */
215 /* Start each Application Processor */
216 init_ops.start_all_aps();
218 set_interrupt_apic_ids();
223 * AP CPU's call this to initialize themselves.
231 int cpu, gsel_tss, x;
232 struct region_descriptor ap_gdt;
234 /* Set by the startup code for us to use */
238 common_tss[cpu] = common_tss[0];
239 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
241 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
243 /* The NMI stack runs on IST2. */
244 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
245 common_tss[cpu].tss_ist2 = (long) np;
247 /* The MC# stack runs on IST3. */
248 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
249 common_tss[cpu].tss_ist3 = (long) np;
251 /* Prepare private GDT */
252 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
253 for (x = 0; x < NGDT; x++) {
254 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
255 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
256 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
258 ssdtosyssd(&gdt_segs[GPROC0_SEL],
259 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
260 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
261 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
262 lgdt(&ap_gdt); /* does magic intra-segment return */
264 /* Get per-cpu data */
267 /* prime data page for it to use */
268 pcpu_init(pc, cpu, sizeof(struct pcpu));
269 dpcpu_init(dpcpu, cpu);
270 pc->pc_apic_id = cpu_apic_ids[cpu];
271 pc->pc_prvspace = pc;
272 pc->pc_curthread = 0;
273 pc->pc_tssp = &common_tss[cpu];
274 pc->pc_commontssp = &common_tss[cpu];
276 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
278 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
279 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
280 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
282 pc->pc_curpmap = kernel_pmap;
284 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
285 common_tss[cpu].tss_rsp0 = pti ? ((vm_offset_t)&pc->pc_pti_stack +
286 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful : 0;
288 /* Save the per-cpu pointer for use by the NMI handler. */
289 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
290 np->np_pcpu = (register_t) pc;
292 /* Save the per-cpu pointer for use by the MC# handler. */
293 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
294 np->np_pcpu = (register_t) pc;
296 wrmsr(MSR_FSBASE, 0); /* User value */
297 wrmsr(MSR_GSBASE, (u_int64_t)pc);
298 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
303 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
307 * Set to a known state:
308 * Set by mpboot.s: CR0_PG, CR0_PE
309 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
312 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
315 amd64_conf_fast_syscall();
317 /* signal our startup to the BSP. */
320 /* Spin until the BSP releases the AP's. */
321 while (atomic_load_acq_int(&aps_ready) == 0)
324 init_secondary_tail();
327 /*******************************************************************
328 * local functions and data
332 * start each AP in our list
335 native_start_all_aps(void)
337 vm_offset_t va = boot_address + KERNBASE;
338 u_int64_t *pt4, *pt3, *pt2;
339 u_int32_t mpbioswarmvec;
343 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
345 /* install the AP 1st level boot code */
346 pmap_kenter(va, boot_address);
347 pmap_invalidate_page(kernel_pmap, va);
348 bcopy(mptramp_start, (void *)va, bootMP_size);
350 /* Locate the page tables, they'll be below the trampoline */
351 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
352 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
353 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
355 /* Create the initial 1GB replicated page tables */
356 for (i = 0; i < 512; i++) {
357 /* Each slot of the level 4 pages points to the same level 3 page */
358 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
359 pt4[i] |= PG_V | PG_RW | PG_U;
361 /* Each slot of the level 3 pages points to the same level 2 page */
362 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
363 pt3[i] |= PG_V | PG_RW | PG_U;
365 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
366 pt2[i] = i * (2 * 1024 * 1024);
367 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
370 /* save the current value of the warm-start vector */
371 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
372 outb(CMOS_REG, BIOS_RESET);
373 mpbiosreason = inb(CMOS_DATA);
375 /* setup a vector to our boot code */
376 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
377 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
378 outb(CMOS_REG, BIOS_RESET);
379 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
382 for (cpu = 1; cpu < mp_ncpus; cpu++) {
383 apic_id = cpu_apic_ids[cpu];
385 /* allocate and set up an idle stack data page */
386 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
387 kstack_pages * PAGE_SIZE, M_WAITOK | M_ZERO);
388 doublefault_stack = (char *)kmem_malloc(kernel_arena,
389 PAGE_SIZE, M_WAITOK | M_ZERO);
390 mce_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
392 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
394 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
397 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
400 /* attempt to start the Application Processor */
401 if (!start_ap(apic_id)) {
402 /* restore the warmstart vector */
403 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
404 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
407 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
410 /* restore the warmstart vector */
411 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
413 outb(CMOS_REG, BIOS_RESET);
414 outb(CMOS_DATA, mpbiosreason);
416 /* number of APs actually started */
422 * This function starts the AP (application processor) identified
423 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
424 * to accomplish this. This is necessary because of the nuances
425 * of the different hardware we might encounter. It isn't pretty,
426 * but it seems to work.
429 start_ap(int apic_id)
434 /* calculate the vector */
435 vector = (boot_address >> 12) & 0xff;
437 /* used as a watchpoint to signal AP startup */
440 ipi_startup(apic_id, vector);
442 /* Wait up to 5 seconds for it to start. */
443 for (ms = 0; ms < 5000; ms++) {
445 return 1; /* return SUCCESS */
448 return 0; /* return FAILURE */
452 invltlb_invpcid_handler(void)
454 struct invpcid_descr d;
457 #ifdef COUNT_XINVLTLB_HITS
458 xhits_gbl[PCPU_GET(cpuid)]++;
459 #endif /* COUNT_XINVLTLB_HITS */
461 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
462 #endif /* COUNT_IPIS */
464 generation = smp_tlb_generation;
465 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
468 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
470 PCPU_SET(smp_tlb_done, generation);
474 invltlb_invpcid_pti_handler(void)
476 struct invpcid_descr d;
479 #ifdef COUNT_XINVLTLB_HITS
480 xhits_gbl[PCPU_GET(cpuid)]++;
481 #endif /* COUNT_XINVLTLB_HITS */
483 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
484 #endif /* COUNT_IPIS */
486 generation = smp_tlb_generation;
487 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
490 if (smp_tlb_pmap == kernel_pmap) {
492 * This invalidation actually needs to clear kernel
493 * mappings from the TLB in the current pmap, but
494 * since we were asked for the flush in the kernel
495 * pmap, achieve it by performing global flush.
497 invpcid(&d, INVPCID_CTXGLOB);
499 invpcid(&d, INVPCID_CTX);
500 d.pcid |= PMAP_PCID_USER_PT;
501 invpcid(&d, INVPCID_CTX);
503 PCPU_SET(smp_tlb_done, generation);
507 invltlb_pcid_handler(void)
510 uint32_t generation, pcid;
512 #ifdef COUNT_XINVLTLB_HITS
513 xhits_gbl[PCPU_GET(cpuid)]++;
514 #endif /* COUNT_XINVLTLB_HITS */
516 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
517 #endif /* COUNT_IPIS */
519 generation = smp_tlb_generation; /* Overlap with serialization */
520 if (smp_tlb_pmap == kernel_pmap) {
524 * The current pmap might not be equal to
525 * smp_tlb_pmap. The clearing of the pm_gen in
526 * pmap_invalidate_all() takes care of TLB
527 * invalidation when switching to the pmap on this
530 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
531 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
532 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
533 ucr3 = smp_tlb_pmap->pm_ucr3;
534 if (ucr3 != PMAP_NO_CR3) {
535 ucr3 |= PMAP_PCID_USER_PT | pcid;
536 pmap_pti_pcid_invalidate(ucr3, kcr3);
541 PCPU_SET(smp_tlb_done, generation);
545 invlpg_invpcid_handler(void)
547 struct invpcid_descr d;
550 #ifdef COUNT_XINVLTLB_HITS
551 xhits_pg[PCPU_GET(cpuid)]++;
552 #endif /* COUNT_XINVLTLB_HITS */
554 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
555 #endif /* COUNT_IPIS */
557 generation = smp_tlb_generation; /* Overlap with serialization */
558 invlpg(smp_tlb_addr1);
559 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
560 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
563 d.addr = smp_tlb_addr1;
564 invpcid(&d, INVPCID_ADDR);
566 PCPU_SET(smp_tlb_done, generation);
570 invlpg_pcid_handler(void)
576 #ifdef COUNT_XINVLTLB_HITS
577 xhits_pg[PCPU_GET(cpuid)]++;
578 #endif /* COUNT_XINVLTLB_HITS */
580 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
581 #endif /* COUNT_IPIS */
583 generation = smp_tlb_generation; /* Overlap with serialization */
584 invlpg(smp_tlb_addr1);
585 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
586 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
587 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
588 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
589 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
590 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
592 PCPU_SET(smp_tlb_done, generation);
596 invlrng_invpcid_handler(void)
598 struct invpcid_descr d;
599 vm_offset_t addr, addr2;
602 #ifdef COUNT_XINVLTLB_HITS
603 xhits_rng[PCPU_GET(cpuid)]++;
604 #endif /* COUNT_XINVLTLB_HITS */
606 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
607 #endif /* COUNT_IPIS */
609 addr = smp_tlb_addr1;
610 addr2 = smp_tlb_addr2;
611 generation = smp_tlb_generation; /* Overlap with serialization */
615 } while (addr < addr2);
616 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
617 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
620 d.addr = smp_tlb_addr1;
622 invpcid(&d, INVPCID_ADDR);
624 } while (d.addr < addr2);
626 PCPU_SET(smp_tlb_done, generation);
630 invlrng_pcid_handler(void)
632 vm_offset_t addr, addr2;
637 #ifdef COUNT_XINVLTLB_HITS
638 xhits_rng[PCPU_GET(cpuid)]++;
639 #endif /* COUNT_XINVLTLB_HITS */
641 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
642 #endif /* COUNT_IPIS */
644 addr = smp_tlb_addr1;
645 addr2 = smp_tlb_addr2;
646 generation = smp_tlb_generation; /* Overlap with serialization */
650 } while (addr < addr2);
651 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
652 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
653 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
654 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
655 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
656 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
658 PCPU_SET(smp_tlb_done, generation);