2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
40 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
45 #include <sys/mutex.h>
49 #include <sys/sysctl.h>
52 #include <vm/vm_param.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_extern.h>
57 #include <machine/apicreg.h>
58 #include <machine/clock.h>
59 #include <machine/md_var.h>
60 #include <machine/mp_watchdog.h>
61 #include <machine/pcb.h>
62 #include <machine/psl.h>
63 #include <machine/smp.h>
64 #include <machine/specialreg.h>
65 #include <machine/tss.h>
67 #define WARMBOOT_TARGET 0
68 #define WARMBOOT_OFF (KERNBASE + 0x0467)
69 #define WARMBOOT_SEG (KERNBASE + 0x0469)
71 #define CMOS_REG (0x70)
72 #define CMOS_DATA (0x71)
73 #define BIOS_RESET (0x0f)
74 #define BIOS_WARM (0x0a)
76 /* lock region used by kernel profiling */
79 int mp_naps; /* # of Applications processors */
80 int boot_cpu_id = -1; /* designated BSP */
84 * CPU topology map datastructures for HTT.
86 static struct cpu_group mp_groups[MAXCPU];
87 static struct cpu_top mp_top;
89 /* AP uses this during bootstrap. Do not staticize. */
93 /* Free these after use */
94 void *bootstacks[MAXCPU];
96 /* Hotwire a 0->4MB V==P mapping */
97 extern pt_entry_t *KPTphys;
99 /* SMP page table page */
100 extern pt_entry_t *SMPpt;
102 struct pcb stoppcbs[MAXCPU];
104 /* Variables needed for SMP tlb shootdown. */
105 vm_offset_t smp_tlb_addr1;
106 vm_offset_t smp_tlb_addr2;
107 volatile int smp_tlb_wait;
109 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
112 * Local data and functions.
115 static u_int logical_cpus;
117 /* used to hold the AP's until we are ready to release them */
118 static struct mtx ap_boot_mtx;
120 /* Set to 1 once we're ready to let the APs out of the pen. */
121 static volatile int aps_ready = 0;
124 * Store data from cpu_add() until later in the boot when we actually setup
131 } static cpu_info[MAXCPU];
132 static int cpu_apic_ids[MAXCPU];
134 static u_int boot_address;
136 static void set_logical_apic_ids(void);
137 static int start_all_aps(void);
138 static int start_ap(int apic_id);
139 static void release_aps(void *dummy);
141 static int hlt_logical_cpus;
142 static struct sysctl_ctx_list logical_cpu_clist;
143 static u_int bootMP_size;
146 mem_range_AP_init(void)
148 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
149 mem_range_softc.mr_op->initAP(&mem_range_softc);
155 struct cpu_group *group;
161 /* Build the smp_topology map. */
162 /* Nothing to do if there is no HTT support. */
163 if ((cpu_feature & CPUID_HTT) == 0)
165 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
166 if (logical_cpus <= 1)
168 group = &mp_groups[0];
170 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) {
171 if (!cpu_info[apic_id].cpu_present)
174 * If the current group has members and we're not a logical
175 * cpu, create a new group.
177 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) {
182 group->cg_mask |= 1 << cpu;
186 mp_top.ct_count = groups;
187 mp_top.ct_group = mp_groups;
188 smp_topology = &mp_top;
193 * Calculate usable address in base memory for AP trampoline code.
196 mp_bootaddress(u_int basemem)
199 bootMP_size = mptramp_end - mptramp_start;
200 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
201 if (((basemem * 1024) - boot_address) < bootMP_size)
202 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
203 /* 3 levels of page table pages */
204 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
206 return mptramp_pagetables;
210 cpu_add(u_int apic_id, char boot_cpu)
213 if (apic_id >= MAXCPU) {
214 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n",
215 apic_id, MAXCPU - 1);
218 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
220 cpu_info[apic_id].cpu_present = 1;
222 KASSERT(boot_cpu_id == -1,
223 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
225 boot_cpu_id = apic_id;
226 cpu_info[apic_id].cpu_bsp = 1;
229 if (apic_id > mp_maxid)
232 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
238 cpu_mp_setmaxid(void)
242 * mp_maxid should be already set by calls to cpu_add().
243 * Just sanity check its value here.
246 KASSERT(mp_maxid == 0,
247 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
248 else if (mp_ncpus == 1)
251 KASSERT(mp_maxid >= mp_ncpus - 1,
252 ("%s: counters out of sync: max %d, count %d", __func__,
253 mp_maxid, mp_ncpus));
262 * Always record BSP in CPU map so that the mbuf init code works
268 * No CPUs were found, so this must be a UP system. Setup
269 * the variables to represent a system with a single CPU
276 /* At least one CPU was found. */
279 * One CPU was found, so this must be a UP system with
286 /* At least two CPUs were found. */
291 * Initialize the IPI handlers and start up the AP's.
298 /* Initialize the logical ID to APIC ID table. */
299 for (i = 0; i < MAXCPU; i++)
300 cpu_apic_ids[i] = -1;
302 /* Install an inter-CPU IPI for TLB invalidation */
303 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
304 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
305 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
307 /* Install an inter-CPU IPI for forwarding hardclock() */
308 setidt(IPI_HARDCLOCK, IDTVEC(hardclock), SDT_SYSIGT, SEL_KPL, 0);
310 /* Install an inter-CPU IPI for forwarding statclock() */
311 setidt(IPI_STATCLOCK, IDTVEC(statclock), SDT_SYSIGT, SEL_KPL, 0);
313 /* Install an inter-CPU IPI for all-CPU rendezvous */
314 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
316 /* Install an inter-CPU IPI for forcing an additional software trap */
317 setidt(IPI_AST, IDTVEC(cpuast), SDT_SYSIGT, SEL_KPL, 0);
319 /* Install an inter-CPU IPI for CPU stop/restart */
320 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
322 /* Set boot_cpu_id if needed. */
323 if (boot_cpu_id == -1) {
324 boot_cpu_id = PCPU_GET(apic_id);
325 cpu_info[boot_cpu_id].cpu_bsp = 1;
327 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
328 ("BSP's APIC ID doesn't match boot_cpu_id"));
329 cpu_apic_ids[0] = boot_cpu_id;
331 /* Start each Application Processor */
334 /* Setup the initial logical CPUs info. */
335 logical_cpus = logical_cpus_mask = 0;
336 if (cpu_feature & CPUID_HTT)
337 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
339 set_logical_apic_ids();
344 * Print various information about the SMP system hardware and setup.
347 cpu_mp_announce(void)
352 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
353 for (i = 1, x = 0; x < MAXCPU; x++) {
354 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp)
356 if (cpu_info[x].cpu_disabled)
357 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x);
359 KASSERT(i < mp_ncpus,
360 ("mp_ncpus and actual cpus are out of whack"));
361 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x);
367 * AP CPU's call this to initialize themselves.
376 /* Set by the startup code for us to use */
380 common_tss[cpu] = common_tss[0];
381 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
383 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
384 ssdtosyssd(&gdt_segs[GPROC0_SEL],
385 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
387 lgdt(&r_gdt); /* does magic intra-segment return */
389 /* Get per-cpu data */
392 /* prime data page for it to use */
393 pcpu_init(pc, cpu, sizeof(struct pcpu));
394 pc->pc_apic_id = cpu_apic_ids[cpu];
395 pc->pc_prvspace = pc;
396 pc->pc_curthread = 0;
397 pc->pc_tssp = &common_tss[cpu];
400 wrmsr(MSR_FSBASE, 0); /* User value */
401 wrmsr(MSR_GSBASE, (u_int64_t)pc);
402 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
406 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
410 * Set to a known state:
411 * Set by mpboot.s: CR0_PG, CR0_PE
412 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
415 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
418 /* Set up the fast syscall stuff */
419 msr = rdmsr(MSR_EFER) | EFER_SCE;
420 wrmsr(MSR_EFER, msr);
421 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
422 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
423 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
424 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
425 wrmsr(MSR_STAR, msr);
426 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
428 /* Disable local apic just to be sure. */
431 /* signal our startup to the BSP. */
434 /* Spin until the BSP releases the AP's. */
438 /* set up CPU registers and state */
441 /* set up SSE/NX registers */
444 /* set up FPU state on the AP */
447 /* A quick check from sanity claus */
448 if (PCPU_GET(apic_id) != lapic_id()) {
449 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
450 printf("SMP: actual apic_id = %d\n", lapic_id());
451 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
452 panic("cpuid mismatch! boom!!");
455 mtx_lock_spin(&ap_boot_mtx);
457 /* Init local apic for irq's */
460 /* Set memory range attributes for this CPU to match the BSP */
465 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
466 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
468 /* Determine if we are a logical CPU. */
469 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
470 logical_cpus_mask |= PCPU_GET(cpumask);
472 /* Build our map of 'other' CPUs. */
473 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
478 if (smp_cpus == mp_ncpus) {
479 /* enable IPI's, tlb shootdown, freezes etc */
480 atomic_store_rel_int(&smp_started, 1);
481 smp_active = 1; /* historic */
484 mtx_unlock_spin(&ap_boot_mtx);
486 /* wait until all the AP's are up */
487 while (smp_started == 0)
490 /* ok, now grab sched_lock and enter the scheduler */
491 mtx_lock_spin(&sched_lock);
493 binuptime(PCPU_PTR(switchtime));
494 PCPU_SET(switchticks, ticks);
496 cpu_throw(NULL, choosethread()); /* doesn't return */
498 panic("scheduler returned us to %s", __func__);
502 /*******************************************************************
503 * local functions and data
507 * Set the APIC logical IDs.
509 * We want to cluster logical CPU's within the same APIC ID cluster.
510 * Since logical CPU's are aligned simply filling in the clusters in
511 * APIC ID order works fine. Note that this does not try to balance
512 * the number of CPU's in each cluster. (XXX?)
515 set_logical_apic_ids(void)
517 u_int apic_id, cluster, cluster_id;
519 /* Force us to allocate cluster 0 at the start. */
521 cluster_id = APIC_MAX_INTRACLUSTER_ID;
522 for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
523 if (!cpu_info[apic_id].cpu_present)
525 if (cluster_id == APIC_MAX_INTRACLUSTER_ID) {
526 cluster = ioapic_next_logical_cluster();
531 printf("APIC ID: physical %u, logical %u:%u\n",
532 apic_id, cluster, cluster_id);
533 lapic_set_logical_id(apic_id, cluster, cluster_id);
538 * start each AP in our list
544 u_int32_t mpbioswarmvec;
546 u_int64_t *pt4, *pt3, *pt2;
547 vm_offset_t va = boot_address + KERNBASE;
549 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
551 /* install the AP 1st level boot code */
552 pmap_kenter(va, boot_address);
553 pmap_invalidate_page(kernel_pmap, va);
554 bcopy(mptramp_start, (void *)va, bootMP_size);
556 /* Locate the page tables, they'll be below the trampoline */
557 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
558 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
559 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
561 /* Create the initial 1GB replicated page tables */
562 for (i = 0; i < 512; i++) {
563 /* Each slot of the level 4 pages points to the same level 3 page */
564 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
565 pt4[i] |= PG_V | PG_RW | PG_U;
567 /* Each slot of the level 3 pages points to the same level 2 page */
568 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
569 pt3[i] |= PG_V | PG_RW | PG_U;
571 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
572 pt2[i] = i * (2 * 1024 * 1024);
573 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
576 /* save the current value of the warm-start vector */
577 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
578 outb(CMOS_REG, BIOS_RESET);
579 mpbiosreason = inb(CMOS_DATA);
581 /* setup a vector to our boot code */
582 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
583 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
584 outb(CMOS_REG, BIOS_RESET);
585 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
589 for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
591 /* Ignore non-existent CPUs and the BSP. */
592 if (!cpu_info[apic_id].cpu_present ||
593 cpu_info[apic_id].cpu_bsp)
596 /* Don't use this CPU if it has been disabled by a tunable. */
597 if (resource_disabled("lapic", apic_id)) {
598 cpu_info[apic_id].cpu_disabled = 1;
605 /* save APIC ID for this logical ID */
606 cpu_apic_ids[cpu] = apic_id;
608 /* allocate and set up an idle stack data page */
609 bootstacks[cpu] = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
611 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
614 /* attempt to start the Application Processor */
615 if (!start_ap(apic_id)) {
616 /* restore the warmstart vector */
617 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
618 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
621 all_cpus |= (1 << cpu); /* record AP in CPU map */
624 /* build our map of 'other' CPUs */
625 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
627 /* restore the warmstart vector */
628 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
630 outb(CMOS_REG, BIOS_RESET);
631 outb(CMOS_DATA, mpbiosreason);
633 /* number of APs actually started */
639 * This function starts the AP (application processor) identified
640 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
641 * to accomplish this. This is necessary because of the nuances
642 * of the different hardware we might encounter. It isn't pretty,
643 * but it seems to work.
646 start_ap(int apic_id)
651 /* calculate the vector */
652 vector = (boot_address >> 12) & 0xff;
654 /* used as a watchpoint to signal AP startup */
658 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
659 * and running the target CPU. OR this INIT IPI might be latched (P5
660 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
664 /* do an INIT IPI: assert RESET */
665 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
666 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
668 /* wait for pending status end */
671 /* do an INIT IPI: deassert RESET */
672 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
673 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
675 /* wait for pending status end */
676 DELAY(10000); /* wait ~10mS */
680 * next we do a STARTUP IPI: the previous INIT IPI might still be
681 * latched, (P5 bug) this 1st STARTUP would then terminate
682 * immediately, and the previously started INIT IPI would continue. OR
683 * the previous INIT IPI has already run. and this STARTUP IPI will
684 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
688 /* do a STARTUP IPI */
689 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
690 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
693 DELAY(200); /* wait ~200uS */
696 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
697 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
698 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
699 * recognized after hardware RESET or INIT IPI.
702 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
703 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
706 DELAY(200); /* wait ~200uS */
708 /* Wait up to 5 seconds for it to start. */
709 for (ms = 0; ms < 50; ms++) {
711 return 1; /* return SUCCESS */
714 return 0; /* return FAILURE */
718 * Flush the TLB on all other CPU's
721 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
725 ncpu = mp_ncpus - 1; /* does not shootdown self */
727 return; /* no other cpus */
728 mtx_assert(&smp_ipi_mtx, MA_OWNED);
729 smp_tlb_addr1 = addr1;
730 smp_tlb_addr2 = addr2;
731 atomic_store_rel_int(&smp_tlb_wait, 0);
732 ipi_all_but_self(vector);
733 while (smp_tlb_wait < ncpu)
738 * This is about as magic as it gets. fortune(1) has got similar code
739 * for reversing bits in a word. Who thinks up this stuff??
741 * Yes, it does appear to be consistently faster than:
742 * while (i = ffs(m)) {
747 * while (lsb = (m & -m)) { // This is magic too
748 * m &= ~lsb; // or: m ^= lsb
751 * Both of these latter forms do some very strange things on gcc-3.1 with
752 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2.
753 * There is probably an SSE or MMX popcnt instruction.
755 * I wonder if this should be in libkern?
757 * XXX Stop the presses! Another one:
758 * static __inline u_int32_t
759 * popcnt1(u_int32_t v)
761 * v -= ((v >> 1) & 0x55555555);
762 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
763 * v = (v + (v >> 4)) & 0x0F0F0F0F;
764 * return (v * 0x01010101) >> 24;
766 * The downside is that it has a multiply. With a pentium3 with
767 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use
768 * an imull, and in that case it is faster. In most other cases
769 * it appears slightly slower.
771 * Another variant (also from fortune):
772 * #define BITCOUNT(x) (((BX_(x)+(BX_(x)>>4)) & 0x0F0F0F0F) % 255)
773 * #define BX_(x) ((x) - (((x)>>1)&0x77777777) \
774 * - (((x)>>2)&0x33333333) \
775 * - (((x)>>3)&0x11111111))
777 static __inline u_int32_t
781 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1);
782 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2);
783 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4);
784 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8);
785 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16);
790 smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
794 othercpus = mp_ncpus - 1;
795 if (mask == (u_int)-1) {
800 mask &= ~PCPU_GET(cpumask);
804 if (ncpu > othercpus) {
805 /* XXX this should be a panic offence */
806 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
810 /* XXX should be a panic, implied by mask == 0 above */
814 mtx_assert(&smp_ipi_mtx, MA_OWNED);
815 smp_tlb_addr1 = addr1;
816 smp_tlb_addr2 = addr2;
817 atomic_store_rel_int(&smp_tlb_wait, 0);
818 if (mask == (u_int)-1)
819 ipi_all_but_self(vector);
821 ipi_selected(mask, vector);
822 while (smp_tlb_wait < ncpu)
831 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
835 smp_invlpg(vm_offset_t addr)
839 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
843 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
847 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
851 smp_masked_invltlb(u_int mask)
855 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
859 smp_masked_invlpg(u_int mask, vm_offset_t addr)
863 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
867 smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
871 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
876 * For statclock, we send an IPI to all CPU's to have them call this
880 forwarded_statclock(struct clockframe frame)
884 CTR0(KTR_SMP, "forwarded_statclock");
886 td->td_intr_nesting_level++;
891 td->td_intr_nesting_level--;
895 forward_statclock(void)
899 CTR0(KTR_SMP, "forward_statclock");
901 if (!smp_started || cold || panicstr)
904 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask);
906 ipi_selected(map, IPI_STATCLOCK);
910 * For each hardclock(), we send an IPI to all other CPU's to have them
911 * execute this function. It would be nice to reduce contention on
912 * sched_lock if we could simply peek at the CPU to determine the user/kernel
913 * state and call hardclock_process() on the CPU receiving the clock interrupt
914 * and then just use a simple IPI to handle any ast's if needed.
917 forwarded_hardclock(struct clockframe frame)
921 CTR0(KTR_SMP, "forwarded_hardclock");
923 td->td_intr_nesting_level++;
924 hardclock_process(&frame);
925 td->td_intr_nesting_level--;
929 forward_hardclock(void)
933 CTR0(KTR_SMP, "forward_hardclock");
935 if (!smp_started || cold || panicstr)
938 map = PCPU_GET(other_cpus) & ~(stopped_cpus|hlt_cpus_mask);
940 ipi_selected(map, IPI_HARDCLOCK);
944 * send an IPI to a set of cpus.
947 ipi_selected(u_int32_t cpus, u_int ipi)
951 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
952 while ((cpu = ffs(cpus)) != 0) {
954 KASSERT(cpu_apic_ids[cpu] != -1,
955 ("IPI to non-existent CPU %d", cpu));
956 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
962 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
968 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
969 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL);
973 * send an IPI to all CPUs EXCEPT myself
976 ipi_all_but_self(u_int ipi)
979 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
980 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
984 * send an IPI to myself
990 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
991 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF);
995 * This is called once the rest of the system is up and running and we're
996 * ready to let the AP's out of the pen.
999 release_aps(void *dummy __unused)
1004 mtx_lock_spin(&sched_lock);
1005 atomic_store_rel_int(&aps_ready, 1);
1006 while (smp_started == 0)
1008 mtx_unlock_spin(&sched_lock);
1010 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1013 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1018 mask = hlt_cpus_mask;
1019 error = sysctl_handle_int(oidp, &mask, 0, req);
1020 if (error || !req->newptr)
1023 if (logical_cpus_mask != 0 &&
1024 (mask & logical_cpus_mask) == logical_cpus_mask)
1025 hlt_logical_cpus = 1;
1027 hlt_logical_cpus = 0;
1029 if ((mask & all_cpus) == all_cpus)
1031 hlt_cpus_mask = mask;
1034 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1035 0, 0, sysctl_hlt_cpus, "IU",
1036 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1039 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1043 disable = hlt_logical_cpus;
1044 error = sysctl_handle_int(oidp, &disable, 0, req);
1045 if (error || !req->newptr)
1049 hlt_cpus_mask |= logical_cpus_mask;
1051 hlt_cpus_mask &= ~logical_cpus_mask;
1053 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1054 hlt_cpus_mask &= ~(1<<0);
1056 hlt_logical_cpus = disable;
1061 cpu_hlt_setup(void *dummy __unused)
1064 if (logical_cpus_mask != 0) {
1065 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1067 sysctl_ctx_init(&logical_cpu_clist);
1068 SYSCTL_ADD_PROC(&logical_cpu_clist,
1069 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1070 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1071 sysctl_hlt_logical_cpus, "IU", "");
1072 SYSCTL_ADD_UINT(&logical_cpu_clist,
1073 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1074 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1075 &logical_cpus_mask, 0, "");
1077 if (hlt_logical_cpus)
1078 hlt_cpus_mask |= logical_cpus_mask;
1081 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1084 mp_grab_cpu_hlt(void)
1086 u_int mask = PCPU_GET(cpumask);
1088 u_int cpuid = PCPU_GET(cpuid);
1096 retval = mask & hlt_cpus_mask;
1097 while (mask & hlt_cpus_mask)
1098 __asm __volatile("sti; hlt" : : : "memory");