2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <machine/smptests.h>
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/cons.h> /* cngetc() */
40 #include <sys/dkstat.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
52 #include <sys/sysctl.h>
56 #include <vm/vm_param.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_map.h>
62 #include <machine/apic.h>
63 #include <machine/atomic.h>
64 #include <machine/cpu.h>
65 #include <machine/cpufunc.h>
66 #include <machine/mpapic.h>
67 #include <machine/psl.h>
68 #include <machine/segments.h>
69 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
70 #include <machine/tss.h>
71 #include <machine/specialreg.h>
72 #include <machine/globaldata.h>
75 #include <machine/md_var.h> /* setidt() */
76 #include <i386/isa/icu.h> /* IPIs */
77 #include <i386/isa/intr_machdep.h> /* IPIs */
80 #if defined(TEST_DEFAULT_CONFIG)
81 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
83 #define MPFPS_MPFB1 mpfps->mpfb1
84 #endif /* TEST_DEFAULT_CONFIG */
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
91 #define BIOS_BASE (0xe8000)
92 #define BIOS_SIZE (0x18000)
94 #define BIOS_BASE (0xf0000)
95 #define BIOS_SIZE (0x10000)
97 #define BIOS_COUNT (BIOS_SIZE/4)
99 #define CMOS_REG (0x70)
100 #define CMOS_DATA (0x71)
101 #define BIOS_RESET (0x0f)
102 #define BIOS_WARM (0x0a)
104 #define PROCENTRY_FLAG_EN 0x01
105 #define PROCENTRY_FLAG_BP 0x02
106 #define IOAPICENTRY_FLAG_EN 0x01
109 /* MP Floating Pointer Structure */
110 typedef struct MPFPS {
123 /* MP Configuration Table Header */
124 typedef struct MPCTH {
126 u_short base_table_length;
130 u_char product_id[12];
131 void *oem_table_pointer;
132 u_short oem_table_size;
135 u_short extended_table_length;
136 u_char extended_table_checksum;
141 typedef struct PROCENTRY {
146 u_long cpu_signature;
147 u_long feature_flags;
152 typedef struct BUSENTRY {
158 typedef struct IOAPICENTRY {
164 } *io_apic_entry_ptr;
166 typedef struct INTENTRY {
176 /* descriptions of MP basetable entries */
177 typedef struct BASETABLE_ENTRY {
184 * this code MUST be enabled here and in mpboot.s.
185 * it follows the very early stages of AP boot by placing values in CMOS ram.
186 * it NORMALLY will never be needed and thus the primitive method for enabling.
191 #if defined(CHECK_POINTS) && !defined(PC98)
192 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
193 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
195 #define CHECK_INIT(D); \
196 CHECK_WRITE(0x34, (D)); \
197 CHECK_WRITE(0x35, (D)); \
198 CHECK_WRITE(0x36, (D)); \
199 CHECK_WRITE(0x37, (D)); \
200 CHECK_WRITE(0x38, (D)); \
201 CHECK_WRITE(0x39, (D));
203 #define CHECK_PRINT(S); \
204 printf("%s: %d, %d, %d, %d, %d, %d\n", \
213 #else /* CHECK_POINTS */
215 #define CHECK_INIT(D)
216 #define CHECK_PRINT(S)
218 #endif /* CHECK_POINTS */
221 * Values to send to the POST hardware.
223 #define MP_BOOTADDRESS_POST 0x10
224 #define MP_PROBE_POST 0x11
225 #define MPTABLE_PASS1_POST 0x12
227 #define MP_START_POST 0x13
228 #define MP_ENABLE_POST 0x14
229 #define MPTABLE_PASS2_POST 0x15
231 #define START_ALL_APS_POST 0x16
232 #define INSTALL_AP_TRAMP_POST 0x17
233 #define START_AP_POST 0x18
235 #define MP_ANNOUNCE_POST 0x19
237 /* used to hold the AP's until we are ready to release them */
238 static struct mtx ap_boot_mtx;
240 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
241 int current_postcode;
243 /** XXX FIXME: what system files declare these??? */
244 extern struct region_descriptor r_gdt, r_idt;
246 int bsp_apic_ready = 0; /* flags useability of BSP apic */
247 int mp_naps; /* # of Applications processors */
248 int mp_nbusses; /* # of busses */
249 int mp_napics; /* # of IO APICs */
250 int boot_cpu_id; /* designated BSP */
251 vm_offset_t cpu_apic_address;
252 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
255 u_int32_t cpu_apic_versions[MAXCPU];
256 u_int32_t *io_apic_versions;
258 #ifdef APIC_INTR_REORDER
260 volatile int *location;
262 } apic_isrbit_location[32];
265 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
268 * APIC ID logical/physical mapping structures.
269 * We oversize these to simplify boot-time config.
271 int cpu_num_to_apic_id[NAPICID];
272 int io_num_to_apic_id[NAPICID];
273 int apic_id_to_logical[NAPICID];
276 /* AP uses this during bootstrap. Do not staticize. */
280 /* Hotwire a 0->4MB V==P mapping */
281 extern pt_entry_t *KPTphys;
283 /* SMP page table page */
284 extern pt_entry_t *SMPpt;
286 struct pcb stoppcbs[MAXCPU];
288 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
289 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
292 * Local data and functions.
295 /* Set to 1 once we're ready to let the APs out of the pen. */
296 static volatile int aps_ready = 0;
298 static int mp_capable;
299 static u_int boot_address;
300 static u_int base_memory;
302 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
303 static mpfps_t mpfps;
304 static int search_for_sig(u_int32_t target, int count);
305 static void mp_enable(u_int boot_addr);
307 static void mptable_pass1(void);
308 static int mptable_pass2(void);
309 static void default_mp_table(int type);
310 static void fix_mp_table(void);
311 static void setup_apic_irq_mapping(void);
312 static void init_locks(void);
313 static int start_all_aps(u_int boot_addr);
314 static void install_ap_tramp(u_int boot_addr);
315 static int start_ap(int logicalCpu, u_int boot_addr);
317 static int apic_int_is_bus_type(int intr, int bus_type);
318 static void release_aps(void *dummy);
321 * initialize all the SMP locks
324 /* critical region around IO APIC, apic_imen */
327 /* lock region used by kernel profiling */
328 struct mtx mcount_mtx;
331 /* locks com (tty) data/hardware accesses: a FASTINTR() */
333 #endif /* USE_COMLOCK */
339 * XXX The mcount mutex probably needs to be statically initialized,
340 * since it will be used even in the function calls that get us to this
343 mtx_init(&mcount_mtx, "mcount", MTX_DEF);
346 mtx_init(&com_mtx, "com", MTX_SPIN);
347 #endif /* USE_COMLOCK */
351 * Calculate usable address in base memory for AP trampoline code.
354 mp_bootaddress(u_int basemem)
356 POSTCODE(MP_BOOTADDRESS_POST);
358 base_memory = basemem * 1024; /* convert to bytes */
360 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
361 if ((base_memory - boot_address) < bootMP_size)
362 boot_address -= 4096; /* not enough, lower by 4k */
369 * Look for an Intel MP spec table (ie, SMP capable hardware).
378 POSTCODE(MP_PROBE_POST);
380 /* see if EBDA exists */
381 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
382 /* search first 1K of EBDA */
383 target = (u_int32_t) (segment << 4);
384 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
387 /* last 1K of base memory, effective 'top of base' passed in */
388 target = (u_int32_t) (base_memory - 0x400);
389 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
393 /* search the BIOS */
394 target = (u_int32_t) BIOS_BASE;
395 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
404 /* calculate needed resources */
408 /* flag fact that we are running multiple processors */
419 * Initialize the SMP hardware and the APIC and start up the AP's.
424 POSTCODE(MP_START_POST);
426 /* look for MP capable motherboard */
428 mp_enable(boot_address);
430 panic("MP hardware not found!");
437 * Print various information about the SMP system hardware and setup.
440 cpu_mp_announce(void)
444 POSTCODE(MP_ANNOUNCE_POST);
446 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
447 printf(", version: 0x%08x", cpu_apic_versions[0]);
448 printf(", at 0x%08x\n", cpu_apic_address);
449 for (x = 1; x <= mp_naps; ++x) {
450 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
451 printf(", version: 0x%08x", cpu_apic_versions[x]);
452 printf(", at 0x%08x\n", cpu_apic_address);
456 for (x = 0; x < mp_napics; ++x) {
457 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
458 printf(", version: 0x%08x", io_apic_versions[x]);
459 printf(", at 0x%08x\n", io_apic_address[x]);
462 printf(" Warning: APIC I/O disabled\n");
467 * AP cpu's call this to sync up protected mode.
473 int x, myid = bootAP;
475 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
476 gdt_segs[GPROC0_SEL].ssd_base =
477 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
478 SMP_prvspace[myid].globaldata.gd_prvspace =
479 &SMP_prvspace[myid].globaldata;
481 for (x = 0; x < NGDT; x++) {
482 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
485 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
486 r_gdt.rd_base = (int) &gdt[myid * NGDT];
487 lgdt(&r_gdt); /* does magic intra-segment return */
492 PCPU_SET(currentldt, _default_ldt);
494 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
495 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
496 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
497 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
498 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
499 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
500 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
509 * Final configuration of the BSP's local APIC:
510 * - disable 'pic mode'.
511 * - disable 'virtual wire mode'.
515 bsp_apic_configure(void)
520 /* leave 'pic mode' if necessary */
522 outb(0x22, 0x70); /* select IMCR */
523 byte = inb(0x23); /* current contents */
524 byte |= 0x01; /* mask external INTR */
525 outb(0x23, byte); /* disconnect 8259s/NMI */
528 /* mask lint0 (the 8259 'virtual wire' connection) */
529 temp = lapic.lvt_lint0;
530 temp |= APIC_LVT_M; /* set the mask */
531 lapic.lvt_lint0 = temp;
533 /* setup lint1 to handle NMI */
534 temp = lapic.lvt_lint1;
535 temp &= ~APIC_LVT_M; /* clear the mask */
536 lapic.lvt_lint1 = temp;
539 apic_dump("bsp_apic_configure()");
544 /*******************************************************************
545 * local functions and data
549 * start the SMP system
552 mp_enable(u_int boot_addr)
560 POSTCODE(MP_ENABLE_POST);
562 /* turn on 4MB of V == P addressing so we can get to MP table */
563 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
566 /* examine the MP table for needed info, uses physical addresses */
572 /* can't process default configs till the CPU APIC is pmapped */
576 /* post scan cleanup */
578 setup_apic_irq_mapping();
582 /* fill the LOGICAL io_apic_versions table */
583 for (apic = 0; apic < mp_napics; ++apic) {
584 ux = io_apic_read(apic, IOAPIC_VER);
585 io_apic_versions[apic] = ux;
586 io_apic_set_id(apic, IO_TO_ID(apic));
589 /* program each IO APIC in the system */
590 for (apic = 0; apic < mp_napics; ++apic)
591 if (io_apic_setup(apic) < 0)
592 panic("IO APIC setup failure");
594 /* install a 'Spurious INTerrupt' vector */
595 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
598 /* install an inter-CPU IPI for TLB invalidation */
599 setidt(XINVLTLB_OFFSET, Xinvltlb,
600 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
602 /* install an inter-CPU IPI for forwarding hardclock() */
603 setidt(XHARDCLOCK_OFFSET, Xhardclock,
604 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
606 /* install an inter-CPU IPI for forwarding statclock() */
607 setidt(XSTATCLOCK_OFFSET, Xstatclock,
608 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
610 /* install an inter-CPU IPI for all-CPU rendezvous */
611 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
612 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
614 /* install an inter-CPU IPI for forcing an additional software trap */
615 setidt(XCPUAST_OFFSET, Xcpuast,
616 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
618 /* install an inter-CPU IPI for CPU stop/restart */
619 setidt(XCPUSTOP_OFFSET, Xcpustop,
620 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
622 #if defined(TEST_TEST1)
623 /* install a "fake hardware INTerrupt" vector */
624 setidt(XTEST1_OFFSET, Xtest1,
625 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
626 #endif /** TEST_TEST1 */
630 /* initialize all SMP locks */
633 /* start each Application Processor */
634 start_all_aps(boot_addr);
639 * look for the MP spec signature
642 /* string defined by the Intel MP Spec as identifying the MP table */
643 #define MP_SIG 0x5f504d5f /* _MP_ */
644 #define NEXT(X) ((X) += 4)
646 search_for_sig(u_int32_t target, int count)
649 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
651 for (x = 0; x < count; NEXT(x))
652 if (addr[x] == MP_SIG)
653 /* make array index a byte index */
654 return (target + (x * sizeof(u_int32_t)));
660 static basetable_entry basetable_entry_types[] =
662 {0, 20, "Processor"},
669 typedef struct BUSDATA {
671 enum busTypes bus_type;
674 typedef struct INTDATA {
684 typedef struct BUSTYPENAME {
689 static bus_type_name bus_type_table[] =
695 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
699 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
704 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"},
706 {UNKNOWN_BUSTYPE, "---"},
707 {UNKNOWN_BUSTYPE, "---"},
709 {UNKNOWN_BUSTYPE, "---"}
711 /* from MP spec v1.4, table 5-1 */
712 static int default_data[7][5] =
714 /* nbus, id0, type0, id1, type1 */
715 {1, 0, ISA, 255, 255},
716 {1, 0, EISA, 255, 255},
717 {1, 0, EISA, 255, 255},
718 {1, 0, MCA, 255, 255},
720 {2, 0, EISA, 1, PCI},
726 static bus_datum *bus_data;
728 /* the IO INT data, one entry per possible APIC INTerrupt */
729 static io_int *io_apic_ints;
733 static int processor_entry __P((proc_entry_ptr entry, int cpu));
734 static int bus_entry __P((bus_entry_ptr entry, int bus));
735 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
736 static int int_entry __P((int_entry_ptr entry, int intr));
737 static int lookup_bus_type __P((char *name));
741 * 1st pass on motherboard's Intel MP specification table.
747 * cpu_apic_address (common to all CPUs)
764 POSTCODE(MPTABLE_PASS1_POST);
766 /* clear various tables */
767 for (x = 0; x < NAPICID; ++x) {
768 io_apic_address[x] = ~0; /* IO APIC address table */
771 /* init everything to empty */
777 /* check for use of 'default' configuration */
778 if (MPFPS_MPFB1 != 0) {
779 /* use default addresses */
780 cpu_apic_address = DEFAULT_APIC_BASE;
781 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
783 /* fill in with defaults */
784 mp_naps = 2; /* includes BSP */
785 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
792 if ((cth = mpfps->pap) == 0)
793 panic("MP Configuration Table Header MISSING!");
795 cpu_apic_address = (vm_offset_t) cth->apic_address;
797 /* walk the table, recording info of interest */
798 totalSize = cth->base_table_length - sizeof(struct MPCTH);
799 position = (u_char *) cth + sizeof(struct MPCTH);
800 count = cth->entry_count;
803 switch (type = *(u_char *) position) {
804 case 0: /* processor_entry */
805 if (((proc_entry_ptr)position)->cpu_flags
809 case 1: /* bus_entry */
812 case 2: /* io_apic_entry */
813 if (((io_apic_entry_ptr)position)->apic_flags
814 & IOAPICENTRY_FLAG_EN)
815 io_apic_address[mp_napics++] =
816 (vm_offset_t)((io_apic_entry_ptr)
817 position)->apic_address;
819 case 3: /* int_entry */
822 case 4: /* int_entry */
825 panic("mpfps Base Table HOSED!");
829 totalSize -= basetable_entry_types[type].length;
830 (u_char*)position += basetable_entry_types[type].length;
834 /* qualify the numbers */
835 if (mp_naps > MAXCPU) {
836 printf("Warning: only using %d of %d available CPUs!\n",
843 * This is also used as a counter while starting the APs.
847 --mp_naps; /* subtract the BSP */
852 * 2nd pass on motherboard's Intel MP specification table.
856 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
857 * CPU_TO_ID(N), logical CPU to APIC ID table
858 * IO_TO_ID(N), logical IO to APIC ID table
871 int apic, bus, cpu, intr;
875 POSTCODE(MPTABLE_PASS2_POST);
877 pgeflag = 0; /* XXX - Not used under SMP yet. */
879 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
881 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
883 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
885 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
888 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
890 for (i = 0; i < mp_napics; i++) {
891 for (j = 0; j < mp_napics; j++) {
892 /* same page frame as a previous IO apic? */
893 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
894 (io_apic_address[i] & PG_FRAME)) {
895 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
896 + (NPTEPG-2-j) * PAGE_SIZE
897 + (io_apic_address[i] & PAGE_MASK));
900 /* use this slot if available */
901 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
902 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
903 pgeflag | (io_apic_address[i] & PG_FRAME));
904 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
905 + (NPTEPG-2-j) * PAGE_SIZE
906 + (io_apic_address[i] & PAGE_MASK));
912 /* clear various tables */
913 for (x = 0; x < NAPICID; ++x) {
914 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
915 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
916 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
919 /* clear bus data table */
920 for (x = 0; x < mp_nbusses; ++x)
921 bus_data[x].bus_id = 0xff;
923 /* clear IO APIC INT table */
924 for (x = 0; x < (nintrs + 1); ++x) {
925 io_apic_ints[x].int_type = 0xff;
926 io_apic_ints[x].int_vector = 0xff;
929 /* setup the cpu/apic mapping arrays */
932 /* record whether PIC or virtual-wire mode */
933 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
935 /* check for use of 'default' configuration */
936 if (MPFPS_MPFB1 != 0)
937 return MPFPS_MPFB1; /* return default configuration type */
939 if ((cth = mpfps->pap) == 0)
940 panic("MP Configuration Table Header MISSING!");
942 /* walk the table, recording info of interest */
943 totalSize = cth->base_table_length - sizeof(struct MPCTH);
944 position = (u_char *) cth + sizeof(struct MPCTH);
945 count = cth->entry_count;
946 apic = bus = intr = 0;
947 cpu = 1; /* pre-count the BSP */
950 switch (type = *(u_char *) position) {
952 if (processor_entry(position, cpu))
956 if (bus_entry(position, bus))
960 if (io_apic_entry(position, apic))
964 if (int_entry(position, intr))
968 /* int_entry(position); */
971 panic("mpfps Base Table HOSED!");
975 totalSize -= basetable_entry_types[type].length;
976 (u_char *) position += basetable_entry_types[type].length;
979 if (boot_cpu_id == -1)
980 panic("NO BSP found!");
982 /* report fact that its NOT a default configuration */
988 assign_apic_irq(int apic, int intpin, int irq)
992 if (int_to_apicintpin[irq].ioapic != -1)
993 panic("assign_apic_irq: inconsistent table");
995 int_to_apicintpin[irq].ioapic = apic;
996 int_to_apicintpin[irq].int_pin = intpin;
997 int_to_apicintpin[irq].apic_address = ioapic[apic];
998 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1000 for (x = 0; x < nintrs; x++) {
1001 if ((io_apic_ints[x].int_type == 0 ||
1002 io_apic_ints[x].int_type == 3) &&
1003 io_apic_ints[x].int_vector == 0xff &&
1004 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1005 io_apic_ints[x].dst_apic_int == intpin)
1006 io_apic_ints[x].int_vector = irq;
1011 revoke_apic_irq(int irq)
1017 if (int_to_apicintpin[irq].ioapic == -1)
1018 panic("assign_apic_irq: inconsistent table");
1020 oldapic = int_to_apicintpin[irq].ioapic;
1021 oldintpin = int_to_apicintpin[irq].int_pin;
1023 int_to_apicintpin[irq].ioapic = -1;
1024 int_to_apicintpin[irq].int_pin = 0;
1025 int_to_apicintpin[irq].apic_address = NULL;
1026 int_to_apicintpin[irq].redirindex = 0;
1028 for (x = 0; x < nintrs; x++) {
1029 if ((io_apic_ints[x].int_type == 0 ||
1030 io_apic_ints[x].int_type == 3) &&
1031 io_apic_ints[x].int_vector == 0xff &&
1032 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1033 io_apic_ints[x].dst_apic_int == oldintpin)
1034 io_apic_ints[x].int_vector = 0xff;
1040 allocate_apic_irq(int intr)
1046 if (io_apic_ints[intr].int_vector != 0xff)
1047 return; /* Interrupt handler already assigned */
1049 if (io_apic_ints[intr].int_type != 0 &&
1050 (io_apic_ints[intr].int_type != 3 ||
1051 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1052 io_apic_ints[intr].dst_apic_int == 0)))
1053 return; /* Not INT or ExtInt on != (0, 0) */
1056 while (irq < APIC_INTMAPSIZE &&
1057 int_to_apicintpin[irq].ioapic != -1)
1060 if (irq >= APIC_INTMAPSIZE)
1061 return; /* No free interrupt handlers */
1063 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1064 intpin = io_apic_ints[intr].dst_apic_int;
1066 assign_apic_irq(apic, intpin, irq);
1067 io_apic_setup_intpin(apic, intpin);
1072 swap_apic_id(int apic, int oldid, int newid)
1079 return; /* Nothing to do */
1081 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1082 apic, oldid, newid);
1084 /* Swap physical APIC IDs in interrupt entries */
1085 for (x = 0; x < nintrs; x++) {
1086 if (io_apic_ints[x].dst_apic_id == oldid)
1087 io_apic_ints[x].dst_apic_id = newid;
1088 else if (io_apic_ints[x].dst_apic_id == newid)
1089 io_apic_ints[x].dst_apic_id = oldid;
1092 /* Swap physical APIC IDs in IO_TO_ID mappings */
1093 for (oapic = 0; oapic < mp_napics; oapic++)
1094 if (IO_TO_ID(oapic) == newid)
1097 if (oapic < mp_napics) {
1098 printf("Changing APIC ID for IO APIC #%d from "
1099 "%d to %d in MP table\n",
1100 oapic, newid, oldid);
1101 IO_TO_ID(oapic) = oldid;
1103 IO_TO_ID(apic) = newid;
1108 fix_id_to_io_mapping(void)
1112 for (x = 0; x < NAPICID; x++)
1115 for (x = 0; x <= mp_naps; x++)
1116 if (CPU_TO_ID(x) < NAPICID)
1117 ID_TO_IO(CPU_TO_ID(x)) = x;
1119 for (x = 0; x < mp_napics; x++)
1120 if (IO_TO_ID(x) < NAPICID)
1121 ID_TO_IO(IO_TO_ID(x)) = x;
1126 first_free_apic_id(void)
1130 for (freeid = 0; freeid < NAPICID; freeid++) {
1131 for (x = 0; x <= mp_naps; x++)
1132 if (CPU_TO_ID(x) == freeid)
1136 for (x = 0; x < mp_napics; x++)
1137 if (IO_TO_ID(x) == freeid)
1148 io_apic_id_acceptable(int apic, int id)
1150 int cpu; /* Logical CPU number */
1151 int oapic; /* Logical IO APIC number for other IO APIC */
1154 return 0; /* Out of range */
1156 for (cpu = 0; cpu <= mp_naps; cpu++)
1157 if (CPU_TO_ID(cpu) == id)
1158 return 0; /* Conflict with CPU */
1160 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1161 if (IO_TO_ID(oapic) == id)
1162 return 0; /* Conflict with other APIC */
1164 return 1; /* ID is acceptable for IO APIC */
1169 * parse an Intel MP specification table
1176 int bus_0 = 0; /* Stop GCC warning */
1177 int bus_pci = 0; /* Stop GCC warning */
1179 int apic; /* IO APIC unit number */
1180 int freeid; /* Free physical APIC ID */
1181 int physid; /* Current physical IO APIC ID */
1184 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1185 * did it wrong. The MP spec says that when more than 1 PCI bus
1186 * exists the BIOS must begin with bus entries for the PCI bus and use
1187 * actual PCI bus numbering. This implies that when only 1 PCI bus
1188 * exists the BIOS can choose to ignore this ordering, and indeed many
1189 * MP motherboards do ignore it. This causes a problem when the PCI
1190 * sub-system makes requests of the MP sub-system based on PCI bus
1191 * numbers. So here we look for the situation and renumber the
1192 * busses and associated INTs in an effort to "make it right".
1195 /* find bus 0, PCI bus, count the number of PCI busses */
1196 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1197 if (bus_data[x].bus_id == 0) {
1200 if (bus_data[x].bus_type == PCI) {
1206 * bus_0 == slot of bus with ID of 0
1207 * bus_pci == slot of last PCI bus encountered
1210 /* check the 1 PCI bus case for sanity */
1211 /* if it is number 0 all is well */
1212 if (num_pci_bus == 1 &&
1213 bus_data[bus_pci].bus_id != 0) {
1215 /* mis-numbered, swap with whichever bus uses slot 0 */
1217 /* swap the bus entry types */
1218 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1219 bus_data[bus_0].bus_type = PCI;
1221 /* swap each relavant INTerrupt entry */
1222 id = bus_data[bus_pci].bus_id;
1223 for (x = 0; x < nintrs; ++x) {
1224 if (io_apic_ints[x].src_bus_id == id) {
1225 io_apic_ints[x].src_bus_id = 0;
1227 else if (io_apic_ints[x].src_bus_id == 0) {
1228 io_apic_ints[x].src_bus_id = id;
1233 /* Assign IO APIC IDs.
1235 * First try the existing ID. If a conflict is detected, try
1236 * the ID in the MP table. If a conflict is still detected, find
1239 * We cannot use the ID_TO_IO table before all conflicts has been
1240 * resolved and the table has been corrected.
1242 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1244 /* First try to use the value set by the BIOS */
1245 physid = io_apic_get_id(apic);
1246 if (io_apic_id_acceptable(apic, physid)) {
1247 if (IO_TO_ID(apic) != physid)
1248 swap_apic_id(apic, IO_TO_ID(apic), physid);
1252 /* Then check if the value in the MP table is acceptable */
1253 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1256 /* Last resort, find a free APIC ID and use it */
1257 freeid = first_free_apic_id();
1258 if (freeid >= NAPICID)
1259 panic("No free physical APIC IDs found");
1261 if (io_apic_id_acceptable(apic, freeid)) {
1262 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1265 panic("Free physical APIC ID not usable");
1267 fix_id_to_io_mapping();
1269 /* detect and fix broken Compaq MP table */
1270 if (apic_int_type(0, 0) == -1) {
1271 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1272 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1273 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1274 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1275 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1276 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1282 /* Assign low level interrupt handlers */
1284 setup_apic_irq_mapping(void)
1290 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1291 int_to_apicintpin[x].ioapic = -1;
1292 int_to_apicintpin[x].int_pin = 0;
1293 int_to_apicintpin[x].apic_address = NULL;
1294 int_to_apicintpin[x].redirindex = 0;
1297 /* First assign ISA/EISA interrupts */
1298 for (x = 0; x < nintrs; x++) {
1299 int_vector = io_apic_ints[x].src_bus_irq;
1300 if (int_vector < APIC_INTMAPSIZE &&
1301 io_apic_ints[x].int_vector == 0xff &&
1302 int_to_apicintpin[int_vector].ioapic == -1 &&
1303 (apic_int_is_bus_type(x, ISA) ||
1304 apic_int_is_bus_type(x, EISA)) &&
1305 io_apic_ints[x].int_type == 0) {
1306 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1307 io_apic_ints[x].dst_apic_int,
1312 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1313 for (x = 0; x < nintrs; x++) {
1314 if (io_apic_ints[x].dst_apic_int == 0 &&
1315 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1316 io_apic_ints[x].int_vector == 0xff &&
1317 int_to_apicintpin[0].ioapic == -1 &&
1318 io_apic_ints[x].int_type == 3) {
1319 assign_apic_irq(0, 0, 0);
1323 /* PCI interrupt assignment is deferred */
1328 processor_entry(proc_entry_ptr entry, int cpu)
1330 /* check for usability */
1331 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1334 if(entry->apic_id >= NAPICID)
1335 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1336 /* check for BSP flag */
1337 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1338 boot_cpu_id = entry->apic_id;
1339 CPU_TO_ID(0) = entry->apic_id;
1340 ID_TO_CPU(entry->apic_id) = 0;
1341 return 0; /* its already been counted */
1344 /* add another AP to list, if less than max number of CPUs */
1345 else if (cpu < MAXCPU) {
1346 CPU_TO_ID(cpu) = entry->apic_id;
1347 ID_TO_CPU(entry->apic_id) = cpu;
1356 bus_entry(bus_entry_ptr entry, int bus)
1361 /* encode the name into an index */
1362 for (x = 0; x < 6; ++x) {
1363 if ((c = entry->bus_type[x]) == ' ')
1369 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1370 panic("unknown bus type: '%s'", name);
1372 bus_data[bus].bus_id = entry->bus_id;
1373 bus_data[bus].bus_type = x;
1380 io_apic_entry(io_apic_entry_ptr entry, int apic)
1382 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1385 IO_TO_ID(apic) = entry->apic_id;
1386 if (entry->apic_id < NAPICID)
1387 ID_TO_IO(entry->apic_id) = apic;
1394 lookup_bus_type(char *name)
1398 for (x = 0; x < MAX_BUSTYPE; ++x)
1399 if (strcmp(bus_type_table[x].name, name) == 0)
1400 return bus_type_table[x].type;
1402 return UNKNOWN_BUSTYPE;
1407 int_entry(int_entry_ptr entry, int intr)
1411 io_apic_ints[intr].int_type = entry->int_type;
1412 io_apic_ints[intr].int_flags = entry->int_flags;
1413 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1414 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1415 if (entry->dst_apic_id == 255) {
1416 /* This signal goes to all IO APICS. Select an IO APIC
1417 with sufficient number of interrupt pins */
1418 for (apic = 0; apic < mp_napics; apic++)
1419 if (((io_apic_read(apic, IOAPIC_VER) &
1420 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1421 entry->dst_apic_int)
1423 if (apic < mp_napics)
1424 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1426 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1428 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1429 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1436 apic_int_is_bus_type(int intr, int bus_type)
1440 for (bus = 0; bus < mp_nbusses; ++bus)
1441 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1442 && ((int) bus_data[bus].bus_type == bus_type))
1450 * Given a traditional ISA INT mask, return an APIC mask.
1453 isa_apic_mask(u_int isa_mask)
1458 #if defined(SKIP_IRQ15_REDIRECT)
1459 if (isa_mask == (1 << 15)) {
1460 printf("skipping ISA IRQ15 redirect\n");
1463 #endif /* SKIP_IRQ15_REDIRECT */
1465 isa_irq = ffs(isa_mask); /* find its bit position */
1466 if (isa_irq == 0) /* doesn't exist */
1468 --isa_irq; /* make it zero based */
1470 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1474 return (1 << apic_pin); /* convert pin# to a mask */
1479 * Determine which APIC pin an ISA/EISA INT is attached to.
1481 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1482 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1483 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1484 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1486 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1488 isa_apic_irq(int isa_irq)
1492 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1493 if (INTTYPE(intr) == 0) { /* standard INT */
1494 if (SRCBUSIRQ(intr) == isa_irq) {
1495 if (apic_int_is_bus_type(intr, ISA) ||
1496 apic_int_is_bus_type(intr, EISA)) {
1497 if (INTIRQ(intr) == 0xff)
1498 return -1; /* unassigned */
1499 return INTIRQ(intr); /* found */
1504 return -1; /* NOT found */
1509 * Determine which APIC pin a PCI INT is attached to.
1511 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1512 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1513 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1515 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1519 --pciInt; /* zero based */
1521 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1522 if ((INTTYPE(intr) == 0) /* standard INT */
1523 && (SRCBUSID(intr) == pciBus)
1524 && (SRCBUSDEVICE(intr) == pciDevice)
1525 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1526 if (apic_int_is_bus_type(intr, PCI)) {
1527 if (INTIRQ(intr) == 0xff)
1528 allocate_apic_irq(intr);
1529 if (INTIRQ(intr) == 0xff)
1530 return -1; /* unassigned */
1531 return INTIRQ(intr); /* exact match */
1534 return -1; /* NOT found */
1538 next_apic_irq(int irq)
1545 for (intr = 0; intr < nintrs; intr++) {
1546 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1548 bus = SRCBUSID(intr);
1549 bustype = apic_bus_type(bus);
1550 if (bustype != ISA &&
1556 if (intr >= nintrs) {
1559 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1560 if (INTTYPE(ointr) != 0)
1562 if (bus != SRCBUSID(ointr))
1564 if (bustype == PCI) {
1565 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1567 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1570 if (bustype == ISA || bustype == EISA) {
1571 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1574 if (INTPIN(intr) == INTPIN(ointr))
1578 if (ointr >= nintrs) {
1581 return INTIRQ(ointr);
1595 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1598 * Exactly what this means is unclear at this point. It is a solution
1599 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1600 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1601 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1605 undirect_isa_irq(int rirq)
1609 printf("Freeing redirected ISA irq %d.\n", rirq);
1610 /** FIXME: tickle the MB redirector chip */
1614 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1621 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1624 undirect_pci_irq(int rirq)
1628 printf("Freeing redirected PCI irq %d.\n", rirq);
1630 /** FIXME: tickle the MB redirector chip */
1634 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1642 * given a bus ID, return:
1643 * the bus type if found
1647 apic_bus_type(int id)
1651 for (x = 0; x < mp_nbusses; ++x)
1652 if (bus_data[x].bus_id == id)
1653 return bus_data[x].bus_type;
1660 * given a LOGICAL APIC# and pin#, return:
1661 * the associated src bus ID if found
1665 apic_src_bus_id(int apic, int pin)
1669 /* search each of the possible INTerrupt sources */
1670 for (x = 0; x < nintrs; ++x)
1671 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1672 (pin == io_apic_ints[x].dst_apic_int))
1673 return (io_apic_ints[x].src_bus_id);
1675 return -1; /* NOT found */
1680 * given a LOGICAL APIC# and pin#, return:
1681 * the associated src bus IRQ if found
1685 apic_src_bus_irq(int apic, int pin)
1689 for (x = 0; x < nintrs; x++)
1690 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1691 (pin == io_apic_ints[x].dst_apic_int))
1692 return (io_apic_ints[x].src_bus_irq);
1694 return -1; /* NOT found */
1699 * given a LOGICAL APIC# and pin#, return:
1700 * the associated INTerrupt type if found
1704 apic_int_type(int apic, int pin)
1708 /* search each of the possible INTerrupt sources */
1709 for (x = 0; x < nintrs; ++x)
1710 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1711 (pin == io_apic_ints[x].dst_apic_int))
1712 return (io_apic_ints[x].int_type);
1714 return -1; /* NOT found */
1718 apic_irq(int apic, int pin)
1723 for (x = 0; x < nintrs; ++x)
1724 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1725 (pin == io_apic_ints[x].dst_apic_int)) {
1726 res = io_apic_ints[x].int_vector;
1729 if (apic != int_to_apicintpin[res].ioapic)
1730 panic("apic_irq: inconsistent table");
1731 if (pin != int_to_apicintpin[res].int_pin)
1732 panic("apic_irq inconsistent table (2)");
1740 * given a LOGICAL APIC# and pin#, return:
1741 * the associated trigger mode if found
1745 apic_trigger(int apic, int pin)
1749 /* search each of the possible INTerrupt sources */
1750 for (x = 0; x < nintrs; ++x)
1751 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1752 (pin == io_apic_ints[x].dst_apic_int))
1753 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1755 return -1; /* NOT found */
1760 * given a LOGICAL APIC# and pin#, return:
1761 * the associated 'active' level if found
1765 apic_polarity(int apic, int pin)
1769 /* search each of the possible INTerrupt sources */
1770 for (x = 0; x < nintrs; ++x)
1771 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1772 (pin == io_apic_ints[x].dst_apic_int))
1773 return (io_apic_ints[x].int_flags & 0x03);
1775 return -1; /* NOT found */
1780 * set data according to MP defaults
1781 * FIXME: probably not complete yet...
1784 default_mp_table(int type)
1787 #if defined(APIC_IO)
1790 #endif /* APIC_IO */
1793 printf(" MP default config type: %d\n", type);
1796 printf(" bus: ISA, APIC: 82489DX\n");
1799 printf(" bus: EISA, APIC: 82489DX\n");
1802 printf(" bus: EISA, APIC: 82489DX\n");
1805 printf(" bus: MCA, APIC: 82489DX\n");
1808 printf(" bus: ISA+PCI, APIC: Integrated\n");
1811 printf(" bus: EISA+PCI, APIC: Integrated\n");
1814 printf(" bus: MCA+PCI, APIC: Integrated\n");
1817 printf(" future type\n");
1823 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1824 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1827 CPU_TO_ID(0) = boot_cpu_id;
1828 ID_TO_CPU(boot_cpu_id) = 0;
1830 /* one and only AP */
1831 CPU_TO_ID(1) = ap_cpu_id;
1832 ID_TO_CPU(ap_cpu_id) = 1;
1834 #if defined(APIC_IO)
1835 /* one and only IO APIC */
1836 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1839 * sanity check, refer to MP spec section 3.6.6, last paragraph
1840 * necessary as some hardware isn't properly setting up the IO APIC
1842 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1843 if (io_apic_id != 2) {
1845 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1846 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1847 io_apic_set_id(0, 2);
1850 IO_TO_ID(0) = io_apic_id;
1851 ID_TO_IO(io_apic_id) = 0;
1852 #endif /* APIC_IO */
1854 /* fill out bus entries */
1863 bus_data[0].bus_id = default_data[type - 1][1];
1864 bus_data[0].bus_type = default_data[type - 1][2];
1865 bus_data[1].bus_id = default_data[type - 1][3];
1866 bus_data[1].bus_type = default_data[type - 1][4];
1869 /* case 4: case 7: MCA NOT supported */
1870 default: /* illegal/reserved */
1871 panic("BAD default MP config: %d", type);
1875 #if defined(APIC_IO)
1876 /* general cases from MP v1.4, table 5-2 */
1877 for (pin = 0; pin < 16; ++pin) {
1878 io_apic_ints[pin].int_type = 0;
1879 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1880 io_apic_ints[pin].src_bus_id = 0;
1881 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1882 io_apic_ints[pin].dst_apic_id = io_apic_id;
1883 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1886 /* special cases from MP v1.4, table 5-2 */
1888 io_apic_ints[2].int_type = 0xff; /* N/C */
1889 io_apic_ints[13].int_type = 0xff; /* N/C */
1890 #if !defined(APIC_MIXED_MODE)
1892 panic("sorry, can't support type 2 default yet");
1893 #endif /* APIC_MIXED_MODE */
1896 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1899 io_apic_ints[0].int_type = 0xff; /* N/C */
1901 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1902 #endif /* APIC_IO */
1907 * start each AP in our list
1910 start_all_aps(u_int boot_addr)
1913 u_char mpbiosreason;
1914 u_long mpbioswarmvec;
1915 struct globaldata *gd;
1919 POSTCODE(START_ALL_APS_POST);
1921 mtx_init(&ap_boot_mtx, "ap boot", MTX_SPIN);
1923 /* initialize BSP's local APIC */
1927 /* install the AP 1st level boot code */
1928 install_ap_tramp(boot_addr);
1931 /* save the current value of the warm-start vector */
1932 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1934 outb(CMOS_REG, BIOS_RESET);
1935 mpbiosreason = inb(CMOS_DATA);
1938 /* record BSP in CPU map */
1941 /* set up temporary P==V mapping for AP boot */
1942 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1943 kptbase = (uintptr_t)(void *)KPTphys;
1944 for (x = 0; x < NKPT; x++)
1945 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1946 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1950 for (x = 1; x <= mp_naps; ++x) {
1952 /* This is a bit verbose, it will go away soon. */
1954 /* first page of AP's private space */
1955 pg = x * i386_btop(sizeof(struct privatespace));
1957 /* allocate a new private data page */
1958 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1960 /* wire it into the private page table page */
1961 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1963 /* allocate and set up an idle stack data page */
1964 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1965 for (i = 0; i < UPAGES; i++)
1966 SMPpt[pg + 1 + i] = (pt_entry_t)
1967 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1969 /* prime data page for it to use */
1971 globaldata_register(gd);
1973 /* setup a vector to our boot code */
1974 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1975 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1977 outb(CMOS_REG, BIOS_RESET);
1978 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1981 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
1984 /* attempt to start the Application Processor */
1985 CHECK_INIT(99); /* setup checkpoints */
1986 if (!start_ap(x, boot_addr)) {
1987 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1988 CHECK_PRINT("trace"); /* show checkpoints */
1989 /* better panic as the AP may be running loose */
1990 printf("panic y/n? [y] ");
1991 if (cngetc() != 'n')
1994 CHECK_PRINT("trace"); /* show checkpoints */
1996 /* record its version info */
1997 cpu_apic_versions[x] = cpu_apic_versions[0];
1999 all_cpus |= (1 << x); /* record AP in CPU map */
2002 /* build our map of 'other' CPUs */
2003 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2005 /* fill in our (BSP) APIC version */
2006 cpu_apic_versions[0] = lapic.version;
2008 /* restore the warmstart vector */
2009 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2011 outb(CMOS_REG, BIOS_RESET);
2012 outb(CMOS_DATA, mpbiosreason);
2016 * Set up the idle context for the BSP. Similar to above except
2017 * that some was done by locore, some by pmap.c and some is implicit
2018 * because the BSP is cpu#0 and the page is initially zero, and also
2019 * because we can refer to variables by name on the BSP..
2022 /* Allocate and setup BSP idle stack */
2023 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2024 for (i = 0; i < UPAGES; i++)
2025 SMPpt[1 + i] = (pt_entry_t)
2026 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2028 for (x = 0; x < NKPT; x++)
2032 /* number of APs actually started */
2033 return mp_ncpus - 1;
2038 * load the 1st level AP boot code into base memory.
2041 /* targets for relocation */
2042 extern void bigJump(void);
2043 extern void bootCodeSeg(void);
2044 extern void bootDataSeg(void);
2045 extern void MPentry(void);
2046 extern u_int MP_GDT;
2047 extern u_int mp_gdtbase;
2050 install_ap_tramp(u_int boot_addr)
2053 int size = *(int *) ((u_long) & bootMP_size);
2054 u_char *src = (u_char *) ((u_long) bootMP);
2055 u_char *dst = (u_char *) boot_addr + KERNBASE;
2056 u_int boot_base = (u_int) bootMP;
2061 POSTCODE(INSTALL_AP_TRAMP_POST);
2063 for (x = 0; x < size; ++x)
2067 * modify addresses in code we just moved to basemem. unfortunately we
2068 * need fairly detailed info about mpboot.s for this to work. changes
2069 * to mpboot.s might require changes here.
2072 /* boot code is located in KERNEL space */
2073 dst = (u_char *) boot_addr + KERNBASE;
2075 /* modify the lgdt arg */
2076 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2077 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2079 /* modify the ljmp target for MPentry() */
2080 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2081 *dst32 = ((u_int) MPentry - KERNBASE);
2083 /* modify the target for boot code segment */
2084 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2085 dst8 = (u_int8_t *) (dst16 + 1);
2086 *dst16 = (u_int) boot_addr & 0xffff;
2087 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2089 /* modify the target for boot data segment */
2090 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2091 dst8 = (u_int8_t *) (dst16 + 1);
2092 *dst16 = (u_int) boot_addr & 0xffff;
2093 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2098 * this function starts the AP (application processor) identified
2099 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2100 * to accomplish this. This is necessary because of the nuances
2101 * of the different hardware we might encounter. It ain't pretty,
2102 * but it seems to work.
2105 start_ap(int logical_cpu, u_int boot_addr)
2110 u_long icr_lo, icr_hi;
2112 POSTCODE(START_AP_POST);
2114 /* get the PHYSICAL APIC ID# */
2115 physical_cpu = CPU_TO_ID(logical_cpu);
2117 /* calculate the vector */
2118 vector = (boot_addr >> 12) & 0xff;
2120 /* used as a watchpoint to signal AP startup */
2124 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2125 * and running the target CPU. OR this INIT IPI might be latched (P5
2126 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2130 /* setup the address for the target AP */
2131 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2132 icr_hi |= (physical_cpu << 24);
2133 lapic.icr_hi = icr_hi;
2135 /* do an INIT IPI: assert RESET */
2136 icr_lo = lapic.icr_lo & 0xfff00000;
2137 lapic.icr_lo = icr_lo | 0x0000c500;
2139 /* wait for pending status end */
2140 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2143 /* do an INIT IPI: deassert RESET */
2144 lapic.icr_lo = icr_lo | 0x00008500;
2146 /* wait for pending status end */
2147 u_sleep(10000); /* wait ~10mS */
2148 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2152 * next we do a STARTUP IPI: the previous INIT IPI might still be
2153 * latched, (P5 bug) this 1st STARTUP would then terminate
2154 * immediately, and the previously started INIT IPI would continue. OR
2155 * the previous INIT IPI has already run. and this STARTUP IPI will
2156 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2160 /* do a STARTUP IPI */
2161 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2162 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2164 u_sleep(200); /* wait ~200uS */
2167 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2168 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2169 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2170 * recognized after hardware RESET or INIT IPI.
2173 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2174 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2176 u_sleep(200); /* wait ~200uS */
2178 /* wait for it to start */
2179 set_apic_timer(5000000);/* == 5 seconds */
2180 while (read_apic_timer())
2181 if (mp_ncpus > cpus)
2182 return 1; /* return SUCCESS */
2184 return 0; /* return FAILURE */
2188 * Flush the TLB on all other CPU's
2190 * XXX: Needs to handshake and wait for completion before proceding.
2195 #if defined(APIC_IO)
2196 if (smp_started && invltlb_ok)
2197 ipi_all_but_self(IPI_INVLTLB);
2198 #endif /* APIC_IO */
2204 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2206 /* send a message to the other CPUs */
2216 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2219 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2221 /* send a message to the other CPUs */
2227 * This is called once the rest of the system is up and running and we're
2228 * ready to let the AP's out of the pen.
2235 /* spin until all the AP's are ready */
2240 * Set curproc to our per-cpu idleproc so that mutexes have
2241 * something unique to lock with.
2243 PCPU_SET(curproc, PCPU_GET(idleproc));
2244 PCPU_SET(spinlocks, NULL);
2246 /* lock against other AP's that are waking up */
2247 mtx_lock_spin(&ap_boot_mtx);
2249 /* BSP may have changed PTD while we're waiting for the lock */
2254 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2258 /* Build our map of 'other' CPUs. */
2259 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2261 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2263 /* set up CPU registers and state */
2266 /* set up FPU state on the AP */
2267 npxinit(__INITIAL_NPXCW__);
2269 /* A quick check from sanity claus */
2270 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2271 if (PCPU_GET(cpuid) != apic_id) {
2272 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2273 printf("SMP: apic_id = %d\n", apic_id);
2274 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2275 panic("cpuid mismatch! boom!!");
2278 /* Init local apic for irq's */
2281 /* Set memory range attributes for this CPU to match the BSP */
2282 mem_range_AP_init();
2285 * Activate smp_invltlb, although strictly speaking, this isn't
2286 * quite correct yet. We should have a bitfield for cpus willing
2287 * to accept TLB flush IPI's or something and sync them.
2289 if (smp_cpus == mp_ncpus) {
2291 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2292 smp_active = 1; /* historic */
2295 /* let other AP's wake up now */
2296 mtx_unlock_spin(&ap_boot_mtx);
2298 /* wait until all the AP's are up */
2299 while (smp_started == 0)
2302 microuptime(PCPU_PTR(switchtime));
2303 PCPU_SET(switchticks, ticks);
2305 /* ok, now grab sched_lock and enter the scheduler */
2307 mtx_lock_spin(&sched_lock);
2308 cpu_throw(); /* doesn't return */
2310 panic("scheduler returned us to ap_init");
2314 * For statclock, we send an IPI to all CPU's to have them call this
2318 forwarded_statclock(struct trapframe frame)
2321 mtx_lock_spin(&sched_lock);
2322 statclock_process(curproc, TRAPF_PC(&frame), TRAPF_USERMODE(&frame));
2323 mtx_unlock_spin(&sched_lock);
2327 forward_statclock(void)
2331 CTR0(KTR_SMP, "forward_statclock");
2333 if (!smp_started || !invltlb_ok || cold || panicstr)
2336 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2338 ipi_selected(map, IPI_STATCLOCK);
2342 * For each hardclock(), we send an IPI to all other CPU's to have them
2343 * execute this function. It would be nice to reduce contention on
2344 * sched_lock if we could simply peek at the CPU to determine the user/kernel
2345 * state and call hardclock_process() on the CPU receiving the clock interrupt
2346 * and then just use a simple IPI to handle any ast's if needed.
2349 forwarded_hardclock(struct trapframe frame)
2352 mtx_lock_spin(&sched_lock);
2353 hardclock_process(curproc, TRAPF_USERMODE(&frame));
2354 mtx_unlock_spin(&sched_lock);
2358 forward_hardclock(void)
2362 CTR0(KTR_SMP, "forward_hardclock");
2364 if (!smp_started || !invltlb_ok || cold || panicstr)
2367 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2369 ipi_selected(map, IPI_HARDCLOCK);
2372 #ifdef APIC_INTR_REORDER
2374 * Maintain mapping from softintr vector to isr bit in local apic.
2377 set_lapic_isrloc(int intr, int vector)
2379 if (intr < 0 || intr > 32)
2380 panic("set_apic_isrloc: bad intr argument: %d",intr);
2381 if (vector < ICU_OFFSET || vector > 255)
2382 panic("set_apic_isrloc: bad vector argument: %d",vector);
2383 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2384 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2389 * send an IPI to a set of cpus.
2392 ipi_selected(u_int32_t cpus, u_int ipi)
2395 CTR2(KTR_SMP, __func__ ": cpus: %x ipi: %x", cpus, ipi);
2396 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED);
2400 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
2406 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi);
2407 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED);
2411 * send an IPI to all CPUs EXCEPT myself
2414 ipi_all_but_self(u_int ipi)
2417 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi);
2418 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED);
2422 * send an IPI to myself
2428 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi);
2429 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED);
2433 release_aps(void *dummy __unused)
2435 atomic_store_rel_int(&aps_ready, 1);
2438 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);