2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/cpuset.h>
43 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/sysctl.h>
56 #include <vm/vm_param.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cputypes.h>
64 #include <machine/cpufunc.h>
66 #include <machine/md_var.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
72 #include <machine/cpu.h>
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 extern struct pcpu __pcpu[];
86 /* Temporary variables for init_secondary() */
87 char *doublefault_stack;
90 /* Variables needed for SMP tlb shootdown. */
91 static vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
92 static pmap_t smp_tlb_pmap;
93 volatile int smp_tlb_wait;
95 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
98 * Local data and functions.
101 static int start_ap(int apic_id);
103 static u_int bootMP_size;
104 static u_int boot_address;
107 * Calculate usable address in base memory for AP trampoline code.
110 mp_bootaddress(u_int basemem)
113 bootMP_size = mptramp_end - mptramp_start;
114 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
115 if (((basemem * 1024) - boot_address) < bootMP_size)
116 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
117 /* 3 levels of page table pages */
118 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
120 return mptramp_pagetables;
124 * Initialize the IPI handlers and start up the AP's.
131 /* Initialize the logical ID to APIC ID table. */
132 for (i = 0; i < MAXCPU; i++) {
133 cpu_apic_ids[i] = -1;
134 cpu_ipi_pending[i] = 0;
137 /* Install an inter-CPU IPI for TLB invalidation */
138 if (pmap_pcid_enabled) {
140 setidt(IPI_INVLTLB, IDTVEC(invltlb_invpcid),
141 SDT_SYSIGT, SEL_KPL, 0);
143 setidt(IPI_INVLTLB, IDTVEC(invltlb_pcid), SDT_SYSIGT,
147 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
149 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
150 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
152 /* Install an inter-CPU IPI for cache invalidation. */
153 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
155 /* Install an inter-CPU IPI for all-CPU rendezvous */
156 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
158 /* Install generic inter-CPU IPI handler */
159 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
160 SDT_SYSIGT, SEL_KPL, 0);
162 /* Install an inter-CPU IPI for CPU stop/restart */
163 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
165 /* Install an inter-CPU IPI for CPU suspend/resume */
166 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
168 /* Set boot_cpu_id if needed. */
169 if (boot_cpu_id == -1) {
170 boot_cpu_id = PCPU_GET(apic_id);
171 cpu_info[boot_cpu_id].cpu_bsp = 1;
173 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
174 ("BSP's APIC ID doesn't match boot_cpu_id"));
176 /* Probe logical/physical core configuration. */
181 /* Start each Application Processor */
182 init_ops.start_all_aps();
184 set_interrupt_apic_ids();
189 * AP CPU's call this to initialize themselves.
197 int cpu, gsel_tss, x;
198 struct region_descriptor ap_gdt;
200 /* Set by the startup code for us to use */
204 common_tss[cpu] = common_tss[0];
205 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
206 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
208 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
210 /* The NMI stack runs on IST2. */
211 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
212 common_tss[cpu].tss_ist2 = (long) np;
214 /* Prepare private GDT */
215 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
216 for (x = 0; x < NGDT; x++) {
217 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
218 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
219 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
221 ssdtosyssd(&gdt_segs[GPROC0_SEL],
222 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
223 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
224 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
225 lgdt(&ap_gdt); /* does magic intra-segment return */
227 /* Get per-cpu data */
230 /* prime data page for it to use */
231 pcpu_init(pc, cpu, sizeof(struct pcpu));
232 dpcpu_init(dpcpu, cpu);
233 pc->pc_apic_id = cpu_apic_ids[cpu];
234 pc->pc_prvspace = pc;
235 pc->pc_curthread = 0;
236 pc->pc_tssp = &common_tss[cpu];
237 pc->pc_commontssp = &common_tss[cpu];
239 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
241 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
242 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
243 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
245 pc->pc_curpmap = kernel_pmap;
247 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
249 /* Save the per-cpu pointer for use by the NMI handler. */
250 np->np_pcpu = (register_t) pc;
252 wrmsr(MSR_FSBASE, 0); /* User value */
253 wrmsr(MSR_GSBASE, (u_int64_t)pc);
254 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
259 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
263 * Set to a known state:
264 * Set by mpboot.s: CR0_PG, CR0_PE
265 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
268 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
271 /* Set up the fast syscall stuff */
272 msr = rdmsr(MSR_EFER) | EFER_SCE;
273 wrmsr(MSR_EFER, msr);
274 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
275 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
276 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
277 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
278 wrmsr(MSR_STAR, msr);
279 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
281 /* signal our startup to the BSP. */
284 /* Spin until the BSP releases the AP's. */
288 init_secondary_tail();
291 /*******************************************************************
292 * local functions and data
296 * start each AP in our list
299 native_start_all_aps(void)
301 vm_offset_t va = boot_address + KERNBASE;
302 u_int64_t *pt4, *pt3, *pt2;
303 u_int32_t mpbioswarmvec;
307 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
309 /* install the AP 1st level boot code */
310 pmap_kenter(va, boot_address);
311 pmap_invalidate_page(kernel_pmap, va);
312 bcopy(mptramp_start, (void *)va, bootMP_size);
314 /* Locate the page tables, they'll be below the trampoline */
315 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
316 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
317 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
319 /* Create the initial 1GB replicated page tables */
320 for (i = 0; i < 512; i++) {
321 /* Each slot of the level 4 pages points to the same level 3 page */
322 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
323 pt4[i] |= PG_V | PG_RW | PG_U;
325 /* Each slot of the level 3 pages points to the same level 2 page */
326 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
327 pt3[i] |= PG_V | PG_RW | PG_U;
329 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
330 pt2[i] = i * (2 * 1024 * 1024);
331 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
334 /* save the current value of the warm-start vector */
335 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
336 outb(CMOS_REG, BIOS_RESET);
337 mpbiosreason = inb(CMOS_DATA);
339 /* setup a vector to our boot code */
340 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
341 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
342 outb(CMOS_REG, BIOS_RESET);
343 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
346 for (cpu = 1; cpu < mp_ncpus; cpu++) {
347 apic_id = cpu_apic_ids[cpu];
349 /* allocate and set up an idle stack data page */
350 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
351 KSTACK_PAGES * PAGE_SIZE, M_WAITOK | M_ZERO);
352 doublefault_stack = (char *)kmem_malloc(kernel_arena,
353 PAGE_SIZE, M_WAITOK | M_ZERO);
354 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
356 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
359 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
362 /* attempt to start the Application Processor */
363 if (!start_ap(apic_id)) {
364 /* restore the warmstart vector */
365 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
366 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
369 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
372 /* restore the warmstart vector */
373 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
375 outb(CMOS_REG, BIOS_RESET);
376 outb(CMOS_DATA, mpbiosreason);
378 /* number of APs actually started */
384 * This function starts the AP (application processor) identified
385 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
386 * to accomplish this. This is necessary because of the nuances
387 * of the different hardware we might encounter. It isn't pretty,
388 * but it seems to work.
391 start_ap(int apic_id)
396 /* calculate the vector */
397 vector = (boot_address >> 12) & 0xff;
399 /* used as a watchpoint to signal AP startup */
402 ipi_startup(apic_id, vector);
404 /* Wait up to 5 seconds for it to start. */
405 for (ms = 0; ms < 5000; ms++) {
407 return 1; /* return SUCCESS */
410 return 0; /* return FAILURE */
414 * Flush the TLB on other CPU's
418 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
419 vm_offset_t addr1, vm_offset_t addr2)
421 int cpu, ncpu, othercpus;
423 othercpus = mp_ncpus - 1; /* does not shootdown self */
426 * Check for other cpus. Return if none.
428 if (CPU_ISFULLSET(&mask)) {
432 CPU_CLR(PCPU_GET(cpuid), &mask);
433 if (CPU_EMPTY(&mask))
437 if (!(read_rflags() & PSL_I))
438 panic("%s: interrupts disabled", __func__);
439 mtx_lock_spin(&smp_ipi_mtx);
440 smp_tlb_addr1 = addr1;
441 smp_tlb_addr2 = addr2;
443 atomic_store_rel_int(&smp_tlb_wait, 0);
444 if (CPU_ISFULLSET(&mask)) {
446 ipi_all_but_self(vector);
449 while ((cpu = CPU_FFS(&mask)) != 0) {
452 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
454 ipi_send_cpu(cpu, vector);
458 while (smp_tlb_wait < ncpu)
460 mtx_unlock_spin(&smp_ipi_mtx);
464 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
468 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
469 #ifdef COUNT_XINVLTLB_HITS
476 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
480 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, NULL, addr, 0);
481 #ifdef COUNT_XINVLTLB_HITS
488 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
492 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, NULL,
494 #ifdef COUNT_XINVLTLB_HITS
496 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
502 smp_cache_flush(void)
506 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
512 * Handlers for TLB related IPIs
515 invltlb_handler(void)
517 #ifdef COUNT_XINVLTLB_HITS
518 xhits_gbl[PCPU_GET(cpuid)]++;
519 #endif /* COUNT_XINVLTLB_HITS */
521 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
522 #endif /* COUNT_IPIS */
525 atomic_add_int(&smp_tlb_wait, 1);
529 invltlb_invpcid_handler(void)
531 struct invpcid_descr d;
533 #ifdef COUNT_XINVLTLB_HITS
534 xhits_gbl[PCPU_GET(cpuid)]++;
535 #endif /* COUNT_XINVLTLB_HITS */
537 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
538 #endif /* COUNT_IPIS */
540 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
543 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
545 atomic_add_int(&smp_tlb_wait, 1);
549 invltlb_pcid_handler(void)
551 #ifdef COUNT_XINVLTLB_HITS
552 xhits_gbl[PCPU_GET(cpuid)]++;
553 #endif /* COUNT_XINVLTLB_HITS */
555 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
556 #endif /* COUNT_IPIS */
558 if (smp_tlb_pmap == kernel_pmap) {
562 * The current pmap might not be equal to
563 * smp_tlb_pmap. The clearing of the pm_gen in
564 * pmap_invalidate_all() takes care of TLB
565 * invalidation when switching to the pmap on this
568 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
569 load_cr3(smp_tlb_pmap->pm_cr3 |
570 smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid);
573 atomic_add_int(&smp_tlb_wait, 1);
579 #ifdef COUNT_XINVLTLB_HITS
580 xhits_pg[PCPU_GET(cpuid)]++;
581 #endif /* COUNT_XINVLTLB_HITS */
583 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
584 #endif /* COUNT_IPIS */
586 invlpg(smp_tlb_addr1);
587 atomic_add_int(&smp_tlb_wait, 1);
591 invlrng_handler(void)
595 #ifdef COUNT_XINVLTLB_HITS
596 xhits_rng[PCPU_GET(cpuid)]++;
597 #endif /* COUNT_XINVLTLB_HITS */
599 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
600 #endif /* COUNT_IPIS */
602 addr = smp_tlb_addr1;
606 } while (addr < smp_tlb_addr2);
608 atomic_add_int(&smp_tlb_wait, 1);