2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include "opt_user_ldt.h"
32 #include <machine/smptests.h>
37 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
45 #include <sys/mutex.h>
47 #include <sys/dkstat.h>
49 #include <sys/cons.h> /* cngetc() */
52 #include <vm/vm_param.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_extern.h>
58 #include <vm/vm_map.h>
65 #include <machine/smp.h>
66 #include <machine/apic.h>
67 #include <machine/atomic.h>
68 #include <machine/cpufunc.h>
69 #include <machine/mpapic.h>
70 #include <machine/psl.h>
71 #include <machine/segments.h>
72 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
73 #include <machine/tss.h>
74 #include <machine/specialreg.h>
75 #include <machine/globaldata.h>
78 #include <machine/md_var.h> /* setidt() */
79 #include <i386/isa/icu.h> /* IPIs */
80 #include <i386/isa/intr_machdep.h> /* IPIs */
83 #if defined(TEST_DEFAULT_CONFIG)
84 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
86 #define MPFPS_MPFB1 mpfps->mpfb1
87 #endif /* TEST_DEFAULT_CONFIG */
89 #define WARMBOOT_TARGET 0
90 #define WARMBOOT_OFF (KERNBASE + 0x0467)
91 #define WARMBOOT_SEG (KERNBASE + 0x0469)
94 #define BIOS_BASE (0xe8000)
95 #define BIOS_SIZE (0x18000)
97 #define BIOS_BASE (0xf0000)
98 #define BIOS_SIZE (0x10000)
100 #define BIOS_COUNT (BIOS_SIZE/4)
102 #define CMOS_REG (0x70)
103 #define CMOS_DATA (0x71)
104 #define BIOS_RESET (0x0f)
105 #define BIOS_WARM (0x0a)
107 #define PROCENTRY_FLAG_EN 0x01
108 #define PROCENTRY_FLAG_BP 0x02
109 #define IOAPICENTRY_FLAG_EN 0x01
112 /* MP Floating Pointer Structure */
113 typedef struct MPFPS {
126 /* MP Configuration Table Header */
127 typedef struct MPCTH {
129 u_short base_table_length;
133 u_char product_id[12];
134 void *oem_table_pointer;
135 u_short oem_table_size;
138 u_short extended_table_length;
139 u_char extended_table_checksum;
144 typedef struct PROCENTRY {
149 u_long cpu_signature;
150 u_long feature_flags;
155 typedef struct BUSENTRY {
161 typedef struct IOAPICENTRY {
167 } *io_apic_entry_ptr;
169 typedef struct INTENTRY {
179 /* descriptions of MP basetable entries */
180 typedef struct BASETABLE_ENTRY {
187 * this code MUST be enabled here and in mpboot.s.
188 * it follows the very early stages of AP boot by placing values in CMOS ram.
189 * it NORMALLY will never be needed and thus the primitive method for enabling.
194 #if defined(CHECK_POINTS) && !defined(PC98)
195 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
196 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
198 #define CHECK_INIT(D); \
199 CHECK_WRITE(0x34, (D)); \
200 CHECK_WRITE(0x35, (D)); \
201 CHECK_WRITE(0x36, (D)); \
202 CHECK_WRITE(0x37, (D)); \
203 CHECK_WRITE(0x38, (D)); \
204 CHECK_WRITE(0x39, (D));
206 #define CHECK_PRINT(S); \
207 printf("%s: %d, %d, %d, %d, %d, %d\n", \
216 #else /* CHECK_POINTS */
218 #define CHECK_INIT(D)
219 #define CHECK_PRINT(S)
221 #endif /* CHECK_POINTS */
224 * Values to send to the POST hardware.
226 #define MP_BOOTADDRESS_POST 0x10
227 #define MP_PROBE_POST 0x11
228 #define MPTABLE_PASS1_POST 0x12
230 #define MP_START_POST 0x13
231 #define MP_ENABLE_POST 0x14
232 #define MPTABLE_PASS2_POST 0x15
234 #define START_ALL_APS_POST 0x16
235 #define INSTALL_AP_TRAMP_POST 0x17
236 #define START_AP_POST 0x18
238 #define MP_ANNOUNCE_POST 0x19
240 /* used to hold the AP's until we are ready to release them */
241 struct simplelock ap_boot_lock;
243 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
244 int current_postcode;
246 /** XXX FIXME: what system files declare these??? */
247 extern struct region_descriptor r_gdt, r_idt;
249 int bsp_apic_ready = 0; /* flags useability of BSP apic */
250 int mp_ncpus; /* # of CPUs, including BSP */
251 int mp_naps; /* # of Applications processors */
252 int mp_nbusses; /* # of busses */
253 int mp_napics; /* # of IO APICs */
254 int boot_cpu_id; /* designated BSP */
255 vm_offset_t cpu_apic_address;
256 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
259 u_int32_t cpu_apic_versions[MAXCPU];
260 u_int32_t *io_apic_versions;
262 #ifdef APIC_INTR_DIAGNOSTIC
263 int apic_itrace_enter[32];
264 int apic_itrace_tryisrlock[32];
265 int apic_itrace_gotisrlock[32];
266 int apic_itrace_active[32];
267 int apic_itrace_masked[32];
268 int apic_itrace_noisrlock[32];
269 int apic_itrace_masked2[32];
270 int apic_itrace_unmask[32];
271 int apic_itrace_noforward[32];
272 int apic_itrace_leave[32];
273 int apic_itrace_enter2[32];
274 int apic_itrace_doreti[32];
275 int apic_itrace_splz[32];
276 int apic_itrace_eoi[32];
277 #ifdef APIC_INTR_DIAGNOSTIC_IRQ
278 unsigned short apic_itrace_debugbuffer[32768];
279 int apic_itrace_debugbuffer_idx;
280 struct simplelock apic_itrace_debuglock;
284 #ifdef APIC_INTR_REORDER
286 volatile int *location;
288 } apic_isrbit_location[32];
291 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
294 * APIC ID logical/physical mapping structures.
295 * We oversize these to simplify boot-time config.
297 int cpu_num_to_apic_id[NAPICID];
298 int io_num_to_apic_id[NAPICID];
299 int apic_id_to_logical[NAPICID];
302 /* Bitmap of all available CPUs */
305 /* AP uses this during bootstrap. Do not staticize. */
309 /* Hotwire a 0->4MB V==P mapping */
310 extern pt_entry_t *KPTphys;
312 /* SMP page table page */
313 extern pt_entry_t *SMPpt;
315 struct pcb stoppcbs[MAXCPU];
317 int smp_started; /* has the system started? */
320 * Local data and functions.
323 static int mp_capable;
324 static u_int boot_address;
325 static u_int base_memory;
327 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
328 static mpfps_t mpfps;
329 static int search_for_sig(u_int32_t target, int count);
330 static void mp_enable(u_int boot_addr);
332 static void mptable_pass1(void);
333 static int mptable_pass2(void);
334 static void default_mp_table(int type);
335 static void fix_mp_table(void);
336 static void setup_apic_irq_mapping(void);
337 static void init_locks(void);
338 static int start_all_aps(u_int boot_addr);
339 static void install_ap_tramp(u_int boot_addr);
340 static int start_ap(int logicalCpu, u_int boot_addr);
341 static int apic_int_is_bus_type(int intr, int bus_type);
342 static void release_aps(void *dummy);
345 * Calculate usable address in base memory for AP trampoline code.
348 mp_bootaddress(u_int basemem)
350 POSTCODE(MP_BOOTADDRESS_POST);
352 base_memory = basemem * 1024; /* convert to bytes */
354 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
355 if ((base_memory - boot_address) < bootMP_size)
356 boot_address -= 4096; /* not enough, lower by 4k */
363 * Look for an Intel MP spec table (ie, SMP capable hardware).
372 POSTCODE(MP_PROBE_POST);
374 /* see if EBDA exists */
375 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
376 /* search first 1K of EBDA */
377 target = (u_int32_t) (segment << 4);
378 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
381 /* last 1K of base memory, effective 'top of base' passed in */
382 target = (u_int32_t) (base_memory - 0x400);
383 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
387 /* search the BIOS */
388 target = (u_int32_t) BIOS_BASE;
389 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
398 /* calculate needed resources */
402 /* flag fact that we are running multiple processors */
409 * Initialize the SMP hardware and the APIC and start up the AP's.
414 POSTCODE(MP_START_POST);
416 /* look for MP capable motherboard */
418 mp_enable(boot_address);
420 panic("MP hardware not found!");
425 * Print various information about the SMP system hardware and setup.
432 POSTCODE(MP_ANNOUNCE_POST);
434 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
435 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
436 printf(", version: 0x%08x", cpu_apic_versions[0]);
437 printf(", at 0x%08x\n", cpu_apic_address);
438 for (x = 1; x <= mp_naps; ++x) {
439 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
440 printf(", version: 0x%08x", cpu_apic_versions[x]);
441 printf(", at 0x%08x\n", cpu_apic_address);
445 for (x = 0; x < mp_napics; ++x) {
446 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
447 printf(", version: 0x%08x", io_apic_versions[x]);
448 printf(", at 0x%08x\n", io_apic_address[x]);
451 printf(" Warning: APIC I/O disabled\n");
456 * AP cpu's call this to sync up protected mode.
462 int x, myid = bootAP;
464 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
465 gdt_segs[GPROC0_SEL].ssd_base =
466 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
467 SMP_prvspace[myid].globaldata.gd_prvspace =
468 &SMP_prvspace[myid].globaldata;
470 for (x = 0; x < NGDT; x++) {
471 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
474 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
475 r_gdt.rd_base = (int) &gdt[myid * NGDT];
476 lgdt(&r_gdt); /* does magic intra-segment return */
482 PCPU_SET(currentldt, _default_ldt);
485 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
486 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
487 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
488 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
489 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
490 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
491 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
500 * Final configuration of the BSP's local APIC:
501 * - disable 'pic mode'.
502 * - disable 'virtual wire mode'.
506 bsp_apic_configure(void)
511 /* leave 'pic mode' if necessary */
513 outb(0x22, 0x70); /* select IMCR */
514 byte = inb(0x23); /* current contents */
515 byte |= 0x01; /* mask external INTR */
516 outb(0x23, byte); /* disconnect 8259s/NMI */
519 /* mask lint0 (the 8259 'virtual wire' connection) */
520 temp = lapic.lvt_lint0;
521 temp |= APIC_LVT_M; /* set the mask */
522 lapic.lvt_lint0 = temp;
524 /* setup lint1 to handle NMI */
525 temp = lapic.lvt_lint1;
526 temp &= ~APIC_LVT_M; /* clear the mask */
527 lapic.lvt_lint1 = temp;
530 apic_dump("bsp_apic_configure()");
535 /*******************************************************************
536 * local functions and data
540 * start the SMP system
543 mp_enable(u_int boot_addr)
551 POSTCODE(MP_ENABLE_POST);
553 /* turn on 4MB of V == P addressing so we can get to MP table */
554 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
557 /* examine the MP table for needed info, uses physical addresses */
563 /* can't process default configs till the CPU APIC is pmapped */
567 /* post scan cleanup */
569 setup_apic_irq_mapping();
573 /* fill the LOGICAL io_apic_versions table */
574 for (apic = 0; apic < mp_napics; ++apic) {
575 ux = io_apic_read(apic, IOAPIC_VER);
576 io_apic_versions[apic] = ux;
577 io_apic_set_id(apic, IO_TO_ID(apic));
580 /* program each IO APIC in the system */
581 for (apic = 0; apic < mp_napics; ++apic)
582 if (io_apic_setup(apic) < 0)
583 panic("IO APIC setup failure");
585 /* install a 'Spurious INTerrupt' vector */
586 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
587 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
589 /* install an inter-CPU IPI for TLB invalidation */
590 setidt(XINVLTLB_OFFSET, Xinvltlb,
591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
594 /* install an inter-CPU IPI for reading processor state */
595 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599 /* install an inter-CPU IPI for all-CPU rendezvous */
600 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
603 /* install an inter-CPU IPI for forcing an additional software trap */
604 setidt(XCPUAST_OFFSET, Xcpuast,
605 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
607 /* install an inter-CPU IPI for interrupt forwarding */
608 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
609 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
611 /* install an inter-CPU IPI for CPU stop/restart */
612 setidt(XCPUSTOP_OFFSET, Xcpustop,
613 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
615 #if defined(TEST_TEST1)
616 /* install a "fake hardware INTerrupt" vector */
617 setidt(XTEST1_OFFSET, Xtest1,
618 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
619 #endif /** TEST_TEST1 */
623 /* initialize all SMP locks */
626 /* obtain the ap_boot_lock */
627 s_lock(&ap_boot_lock);
629 /* start each Application Processor */
630 start_all_aps(boot_addr);
635 * look for the MP spec signature
638 /* string defined by the Intel MP Spec as identifying the MP table */
639 #define MP_SIG 0x5f504d5f /* _MP_ */
640 #define NEXT(X) ((X) += 4)
642 search_for_sig(u_int32_t target, int count)
645 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
647 for (x = 0; x < count; NEXT(x))
648 if (addr[x] == MP_SIG)
649 /* make array index a byte index */
650 return (target + (x * sizeof(u_int32_t)));
656 static basetable_entry basetable_entry_types[] =
658 {0, 20, "Processor"},
665 typedef struct BUSDATA {
667 enum busTypes bus_type;
670 typedef struct INTDATA {
680 typedef struct BUSTYPENAME {
685 static bus_type_name bus_type_table[] =
691 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
698 {UNKNOWN_BUSTYPE, "---"},
700 {UNKNOWN_BUSTYPE, "---"},
701 {UNKNOWN_BUSTYPE, "---"},
702 {UNKNOWN_BUSTYPE, "---"},
703 {UNKNOWN_BUSTYPE, "---"},
705 {UNKNOWN_BUSTYPE, "---"}
707 /* from MP spec v1.4, table 5-1 */
708 static int default_data[7][5] =
710 /* nbus, id0, type0, id1, type1 */
711 {1, 0, ISA, 255, 255},
712 {1, 0, EISA, 255, 255},
713 {1, 0, EISA, 255, 255},
714 {1, 0, MCA, 255, 255},
716 {2, 0, EISA, 1, PCI},
722 static bus_datum *bus_data;
724 /* the IO INT data, one entry per possible APIC INTerrupt */
725 static io_int *io_apic_ints;
729 static int processor_entry __P((proc_entry_ptr entry, int cpu));
730 static int bus_entry __P((bus_entry_ptr entry, int bus));
731 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
732 static int int_entry __P((int_entry_ptr entry, int intr));
733 static int lookup_bus_type __P((char *name));
737 * 1st pass on motherboard's Intel MP specification table.
743 * cpu_apic_address (common to all CPUs)
760 POSTCODE(MPTABLE_PASS1_POST);
762 /* clear various tables */
763 for (x = 0; x < NAPICID; ++x) {
764 io_apic_address[x] = ~0; /* IO APIC address table */
767 /* init everything to empty */
773 /* check for use of 'default' configuration */
774 if (MPFPS_MPFB1 != 0) {
775 /* use default addresses */
776 cpu_apic_address = DEFAULT_APIC_BASE;
777 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
779 /* fill in with defaults */
780 mp_naps = 2; /* includes BSP */
781 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
788 if ((cth = mpfps->pap) == 0)
789 panic("MP Configuration Table Header MISSING!");
791 cpu_apic_address = (vm_offset_t) cth->apic_address;
793 /* walk the table, recording info of interest */
794 totalSize = cth->base_table_length - sizeof(struct MPCTH);
795 position = (u_char *) cth + sizeof(struct MPCTH);
796 count = cth->entry_count;
799 switch (type = *(u_char *) position) {
800 case 0: /* processor_entry */
801 if (((proc_entry_ptr)position)->cpu_flags
805 case 1: /* bus_entry */
808 case 2: /* io_apic_entry */
809 if (((io_apic_entry_ptr)position)->apic_flags
810 & IOAPICENTRY_FLAG_EN)
811 io_apic_address[mp_napics++] =
812 (vm_offset_t)((io_apic_entry_ptr)
813 position)->apic_address;
815 case 3: /* int_entry */
818 case 4: /* int_entry */
821 panic("mpfps Base Table HOSED!");
825 totalSize -= basetable_entry_types[type].length;
826 (u_char*)position += basetable_entry_types[type].length;
830 /* qualify the numbers */
831 if (mp_naps > MAXCPU) {
832 printf("Warning: only using %d of %d available CPUs!\n",
839 * This is also used as a counter while starting the APs.
843 --mp_naps; /* subtract the BSP */
848 * 2nd pass on motherboard's Intel MP specification table.
852 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
853 * CPU_TO_ID(N), logical CPU to APIC ID table
854 * IO_TO_ID(N), logical IO to APIC ID table
867 int apic, bus, cpu, intr;
871 POSTCODE(MPTABLE_PASS2_POST);
873 pgeflag = 0; /* XXX - Not used under SMP yet. */
875 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
877 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
879 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
881 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
884 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
886 for (i = 0; i < mp_napics; i++) {
887 for (j = 0; j < mp_napics; j++) {
888 /* same page frame as a previous IO apic? */
889 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
890 (io_apic_address[i] & PG_FRAME)) {
891 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
892 + (NPTEPG-2-j) * PAGE_SIZE
893 + (io_apic_address[i] & PAGE_MASK));
896 /* use this slot if available */
897 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
898 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
899 pgeflag | (io_apic_address[i] & PG_FRAME));
900 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
901 + (NPTEPG-2-j) * PAGE_SIZE
902 + (io_apic_address[i] & PAGE_MASK));
908 /* clear various tables */
909 for (x = 0; x < NAPICID; ++x) {
910 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
911 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
912 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
915 /* clear bus data table */
916 for (x = 0; x < mp_nbusses; ++x)
917 bus_data[x].bus_id = 0xff;
919 /* clear IO APIC INT table */
920 for (x = 0; x < (nintrs + 1); ++x) {
921 io_apic_ints[x].int_type = 0xff;
922 io_apic_ints[x].int_vector = 0xff;
925 /* setup the cpu/apic mapping arrays */
928 /* record whether PIC or virtual-wire mode */
929 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
931 /* check for use of 'default' configuration */
932 if (MPFPS_MPFB1 != 0)
933 return MPFPS_MPFB1; /* return default configuration type */
935 if ((cth = mpfps->pap) == 0)
936 panic("MP Configuration Table Header MISSING!");
938 /* walk the table, recording info of interest */
939 totalSize = cth->base_table_length - sizeof(struct MPCTH);
940 position = (u_char *) cth + sizeof(struct MPCTH);
941 count = cth->entry_count;
942 apic = bus = intr = 0;
943 cpu = 1; /* pre-count the BSP */
946 switch (type = *(u_char *) position) {
948 if (processor_entry(position, cpu))
952 if (bus_entry(position, bus))
956 if (io_apic_entry(position, apic))
960 if (int_entry(position, intr))
964 /* int_entry(position); */
967 panic("mpfps Base Table HOSED!");
971 totalSize -= basetable_entry_types[type].length;
972 (u_char *) position += basetable_entry_types[type].length;
975 if (boot_cpu_id == -1)
976 panic("NO BSP found!");
978 /* report fact that its NOT a default configuration */
984 assign_apic_irq(int apic, int intpin, int irq)
988 if (int_to_apicintpin[irq].ioapic != -1)
989 panic("assign_apic_irq: inconsistent table");
991 int_to_apicintpin[irq].ioapic = apic;
992 int_to_apicintpin[irq].int_pin = intpin;
993 int_to_apicintpin[irq].apic_address = ioapic[apic];
994 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
996 for (x = 0; x < nintrs; x++) {
997 if ((io_apic_ints[x].int_type == 0 ||
998 io_apic_ints[x].int_type == 3) &&
999 io_apic_ints[x].int_vector == 0xff &&
1000 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1001 io_apic_ints[x].dst_apic_int == intpin)
1002 io_apic_ints[x].int_vector = irq;
1007 revoke_apic_irq(int irq)
1013 if (int_to_apicintpin[irq].ioapic == -1)
1014 panic("assign_apic_irq: inconsistent table");
1016 oldapic = int_to_apicintpin[irq].ioapic;
1017 oldintpin = int_to_apicintpin[irq].int_pin;
1019 int_to_apicintpin[irq].ioapic = -1;
1020 int_to_apicintpin[irq].int_pin = 0;
1021 int_to_apicintpin[irq].apic_address = NULL;
1022 int_to_apicintpin[irq].redirindex = 0;
1024 for (x = 0; x < nintrs; x++) {
1025 if ((io_apic_ints[x].int_type == 0 ||
1026 io_apic_ints[x].int_type == 3) &&
1027 io_apic_ints[x].int_vector == 0xff &&
1028 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1029 io_apic_ints[x].dst_apic_int == oldintpin)
1030 io_apic_ints[x].int_vector = 0xff;
1037 swap_apic_id(int apic, int oldid, int newid)
1044 return; /* Nothing to do */
1046 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1047 apic, oldid, newid);
1049 /* Swap physical APIC IDs in interrupt entries */
1050 for (x = 0; x < nintrs; x++) {
1051 if (io_apic_ints[x].dst_apic_id == oldid)
1052 io_apic_ints[x].dst_apic_id = newid;
1053 else if (io_apic_ints[x].dst_apic_id == newid)
1054 io_apic_ints[x].dst_apic_id = oldid;
1057 /* Swap physical APIC IDs in IO_TO_ID mappings */
1058 for (oapic = 0; oapic < mp_napics; oapic++)
1059 if (IO_TO_ID(oapic) == newid)
1062 if (oapic < mp_napics) {
1063 printf("Changing APIC ID for IO APIC #%d from "
1064 "%d to %d in MP table\n",
1065 oapic, newid, oldid);
1066 IO_TO_ID(oapic) = oldid;
1068 IO_TO_ID(apic) = newid;
1073 fix_id_to_io_mapping(void)
1077 for (x = 0; x < NAPICID; x++)
1080 for (x = 0; x <= mp_naps; x++)
1081 if (CPU_TO_ID(x) < NAPICID)
1082 ID_TO_IO(CPU_TO_ID(x)) = x;
1084 for (x = 0; x < mp_napics; x++)
1085 if (IO_TO_ID(x) < NAPICID)
1086 ID_TO_IO(IO_TO_ID(x)) = x;
1091 first_free_apic_id(void)
1095 for (freeid = 0; freeid < NAPICID; freeid++) {
1096 for (x = 0; x <= mp_naps; x++)
1097 if (CPU_TO_ID(x) == freeid)
1101 for (x = 0; x < mp_napics; x++)
1102 if (IO_TO_ID(x) == freeid)
1113 io_apic_id_acceptable(int apic, int id)
1115 int cpu; /* Logical CPU number */
1116 int oapic; /* Logical IO APIC number for other IO APIC */
1119 return 0; /* Out of range */
1121 for (cpu = 0; cpu <= mp_naps; cpu++)
1122 if (CPU_TO_ID(cpu) == id)
1123 return 0; /* Conflict with CPU */
1125 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1126 if (IO_TO_ID(oapic) == id)
1127 return 0; /* Conflict with other APIC */
1129 return 1; /* ID is acceptable for IO APIC */
1134 * parse an Intel MP specification table
1141 int bus_0 = 0; /* Stop GCC warning */
1142 int bus_pci = 0; /* Stop GCC warning */
1144 int apic; /* IO APIC unit number */
1145 int freeid; /* Free physical APIC ID */
1146 int physid; /* Current physical IO APIC ID */
1149 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1150 * did it wrong. The MP spec says that when more than 1 PCI bus
1151 * exists the BIOS must begin with bus entries for the PCI bus and use
1152 * actual PCI bus numbering. This implies that when only 1 PCI bus
1153 * exists the BIOS can choose to ignore this ordering, and indeed many
1154 * MP motherboards do ignore it. This causes a problem when the PCI
1155 * sub-system makes requests of the MP sub-system based on PCI bus
1156 * numbers. So here we look for the situation and renumber the
1157 * busses and associated INTs in an effort to "make it right".
1160 /* find bus 0, PCI bus, count the number of PCI busses */
1161 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1162 if (bus_data[x].bus_id == 0) {
1165 if (bus_data[x].bus_type == PCI) {
1171 * bus_0 == slot of bus with ID of 0
1172 * bus_pci == slot of last PCI bus encountered
1175 /* check the 1 PCI bus case for sanity */
1176 /* if it is number 0 all is well */
1177 if (num_pci_bus == 1 &&
1178 bus_data[bus_pci].bus_id != 0) {
1180 /* mis-numbered, swap with whichever bus uses slot 0 */
1182 /* swap the bus entry types */
1183 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1184 bus_data[bus_0].bus_type = PCI;
1186 /* swap each relavant INTerrupt entry */
1187 id = bus_data[bus_pci].bus_id;
1188 for (x = 0; x < nintrs; ++x) {
1189 if (io_apic_ints[x].src_bus_id == id) {
1190 io_apic_ints[x].src_bus_id = 0;
1192 else if (io_apic_ints[x].src_bus_id == 0) {
1193 io_apic_ints[x].src_bus_id = id;
1198 /* Assign IO APIC IDs.
1200 * First try the existing ID. If a conflict is detected, try
1201 * the ID in the MP table. If a conflict is still detected, find
1204 * We cannot use the ID_TO_IO table before all conflicts has been
1205 * resolved and the table has been corrected.
1207 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1209 /* First try to use the value set by the BIOS */
1210 physid = io_apic_get_id(apic);
1211 if (io_apic_id_acceptable(apic, physid)) {
1212 if (IO_TO_ID(apic) != physid)
1213 swap_apic_id(apic, IO_TO_ID(apic), physid);
1217 /* Then check if the value in the MP table is acceptable */
1218 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1221 /* Last resort, find a free APIC ID and use it */
1222 freeid = first_free_apic_id();
1223 if (freeid >= NAPICID)
1224 panic("No free physical APIC IDs found");
1226 if (io_apic_id_acceptable(apic, freeid)) {
1227 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1230 panic("Free physical APIC ID not usable");
1232 fix_id_to_io_mapping();
1234 /* detect and fix broken Compaq MP table */
1235 if (apic_int_type(0, 0) == -1) {
1236 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1237 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1238 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1239 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1240 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1241 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1247 /* Assign low level interrupt handlers */
1249 setup_apic_irq_mapping(void)
1255 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1256 int_to_apicintpin[x].ioapic = -1;
1257 int_to_apicintpin[x].int_pin = 0;
1258 int_to_apicintpin[x].apic_address = NULL;
1259 int_to_apicintpin[x].redirindex = 0;
1262 /* First assign ISA/EISA interrupts */
1263 for (x = 0; x < nintrs; x++) {
1264 int_vector = io_apic_ints[x].src_bus_irq;
1265 if (int_vector < APIC_INTMAPSIZE &&
1266 io_apic_ints[x].int_vector == 0xff &&
1267 int_to_apicintpin[int_vector].ioapic == -1 &&
1268 (apic_int_is_bus_type(x, ISA) ||
1269 apic_int_is_bus_type(x, EISA)) &&
1270 io_apic_ints[x].int_type == 0) {
1271 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1272 io_apic_ints[x].dst_apic_int,
1277 /* Assign first set of interrupts to intpins on IOAPIC #0 */
1278 for (x = 0; x < nintrs; x++) {
1279 int_vector = io_apic_ints[x].dst_apic_int;
1280 if (int_vector < APIC_INTMAPSIZE &&
1281 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1282 io_apic_ints[x].int_vector == 0xff &&
1283 int_to_apicintpin[int_vector].ioapic == -1 &&
1284 (io_apic_ints[x].int_type == 0 ||
1285 io_apic_ints[x].int_type == 3)) {
1287 io_apic_ints[x].dst_apic_int,
1292 * Assign interrupts for remaining intpins.
1293 * Skip IOAPIC #0 intpin 0 if the type is ExtInt, since this indicates
1294 * that an entry for ISA/EISA irq 0 exist, and a fallback to mixed mode
1295 * due to 8254 interrupts not being delivered can reuse that low level
1296 * interrupt handler.
1299 while (int_vector < APIC_INTMAPSIZE &&
1300 int_to_apicintpin[int_vector].ioapic != -1)
1302 for (x = 0; x < nintrs && int_vector < APIC_INTMAPSIZE; x++) {
1303 if ((io_apic_ints[x].int_type == 0 ||
1304 (io_apic_ints[x].int_type == 3 &&
1305 (io_apic_ints[x].dst_apic_id != IO_TO_ID(0) ||
1306 io_apic_ints[x].dst_apic_int != 0))) &&
1307 io_apic_ints[x].int_vector == 0xff) {
1308 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1309 io_apic_ints[x].dst_apic_int,
1312 while (int_vector < APIC_INTMAPSIZE &&
1313 int_to_apicintpin[int_vector].ioapic != -1)
1321 processor_entry(proc_entry_ptr entry, int cpu)
1323 /* check for usability */
1324 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1327 if(entry->apic_id >= NAPICID)
1328 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1329 /* check for BSP flag */
1330 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1331 boot_cpu_id = entry->apic_id;
1332 CPU_TO_ID(0) = entry->apic_id;
1333 ID_TO_CPU(entry->apic_id) = 0;
1334 return 0; /* its already been counted */
1337 /* add another AP to list, if less than max number of CPUs */
1338 else if (cpu < MAXCPU) {
1339 CPU_TO_ID(cpu) = entry->apic_id;
1340 ID_TO_CPU(entry->apic_id) = cpu;
1349 bus_entry(bus_entry_ptr entry, int bus)
1354 /* encode the name into an index */
1355 for (x = 0; x < 6; ++x) {
1356 if ((c = entry->bus_type[x]) == ' ')
1362 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1363 panic("unknown bus type: '%s'", name);
1365 bus_data[bus].bus_id = entry->bus_id;
1366 bus_data[bus].bus_type = x;
1373 io_apic_entry(io_apic_entry_ptr entry, int apic)
1375 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1378 IO_TO_ID(apic) = entry->apic_id;
1379 if (entry->apic_id < NAPICID)
1380 ID_TO_IO(entry->apic_id) = apic;
1387 lookup_bus_type(char *name)
1391 for (x = 0; x < MAX_BUSTYPE; ++x)
1392 if (strcmp(bus_type_table[x].name, name) == 0)
1393 return bus_type_table[x].type;
1395 return UNKNOWN_BUSTYPE;
1400 int_entry(int_entry_ptr entry, int intr)
1404 io_apic_ints[intr].int_type = entry->int_type;
1405 io_apic_ints[intr].int_flags = entry->int_flags;
1406 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1407 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1408 if (entry->dst_apic_id == 255) {
1409 /* This signal goes to all IO APICS. Select an IO APIC
1410 with sufficient number of interrupt pins */
1411 for (apic = 0; apic < mp_napics; apic++)
1412 if (((io_apic_read(apic, IOAPIC_VER) &
1413 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1414 entry->dst_apic_int)
1416 if (apic < mp_napics)
1417 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1419 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1421 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1422 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1429 apic_int_is_bus_type(int intr, int bus_type)
1433 for (bus = 0; bus < mp_nbusses; ++bus)
1434 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1435 && ((int) bus_data[bus].bus_type == bus_type))
1443 * Given a traditional ISA INT mask, return an APIC mask.
1446 isa_apic_mask(u_int isa_mask)
1451 #if defined(SKIP_IRQ15_REDIRECT)
1452 if (isa_mask == (1 << 15)) {
1453 printf("skipping ISA IRQ15 redirect\n");
1456 #endif /* SKIP_IRQ15_REDIRECT */
1458 isa_irq = ffs(isa_mask); /* find its bit position */
1459 if (isa_irq == 0) /* doesn't exist */
1461 --isa_irq; /* make it zero based */
1463 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1467 return (1 << apic_pin); /* convert pin# to a mask */
1472 * Determine which APIC pin an ISA/EISA INT is attached to.
1474 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1475 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1476 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1477 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1479 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1481 isa_apic_irq(int isa_irq)
1485 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1486 if (INTTYPE(intr) == 0) { /* standard INT */
1487 if (SRCBUSIRQ(intr) == isa_irq) {
1488 if (apic_int_is_bus_type(intr, ISA) ||
1489 apic_int_is_bus_type(intr, EISA))
1490 return INTIRQ(intr); /* found */
1494 return -1; /* NOT found */
1499 * Determine which APIC pin a PCI INT is attached to.
1501 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1502 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1503 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1505 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1509 --pciInt; /* zero based */
1511 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1512 if ((INTTYPE(intr) == 0) /* standard INT */
1513 && (SRCBUSID(intr) == pciBus)
1514 && (SRCBUSDEVICE(intr) == pciDevice)
1515 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1516 if (apic_int_is_bus_type(intr, PCI))
1517 return INTIRQ(intr); /* exact match */
1519 return -1; /* NOT found */
1523 next_apic_irq(int irq)
1530 for (intr = 0; intr < nintrs; intr++) {
1531 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1533 bus = SRCBUSID(intr);
1534 bustype = apic_bus_type(bus);
1535 if (bustype != ISA &&
1541 if (intr >= nintrs) {
1544 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1545 if (INTTYPE(ointr) != 0)
1547 if (bus != SRCBUSID(ointr))
1549 if (bustype == PCI) {
1550 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1552 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1555 if (bustype == ISA || bustype == EISA) {
1556 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1559 if (INTPIN(intr) == INTPIN(ointr))
1563 if (ointr >= nintrs) {
1566 return INTIRQ(ointr);
1580 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1583 * Exactly what this means is unclear at this point. It is a solution
1584 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1585 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1586 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1590 undirect_isa_irq(int rirq)
1594 printf("Freeing redirected ISA irq %d.\n", rirq);
1595 /** FIXME: tickle the MB redirector chip */
1599 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1606 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1609 undirect_pci_irq(int rirq)
1613 printf("Freeing redirected PCI irq %d.\n", rirq);
1615 /** FIXME: tickle the MB redirector chip */
1619 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1627 * given a bus ID, return:
1628 * the bus type if found
1632 apic_bus_type(int id)
1636 for (x = 0; x < mp_nbusses; ++x)
1637 if (bus_data[x].bus_id == id)
1638 return bus_data[x].bus_type;
1645 * given a LOGICAL APIC# and pin#, return:
1646 * the associated src bus ID if found
1650 apic_src_bus_id(int apic, int pin)
1654 /* search each of the possible INTerrupt sources */
1655 for (x = 0; x < nintrs; ++x)
1656 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1657 (pin == io_apic_ints[x].dst_apic_int))
1658 return (io_apic_ints[x].src_bus_id);
1660 return -1; /* NOT found */
1665 * given a LOGICAL APIC# and pin#, return:
1666 * the associated src bus IRQ if found
1670 apic_src_bus_irq(int apic, int pin)
1674 for (x = 0; x < nintrs; x++)
1675 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1676 (pin == io_apic_ints[x].dst_apic_int))
1677 return (io_apic_ints[x].src_bus_irq);
1679 return -1; /* NOT found */
1684 * given a LOGICAL APIC# and pin#, return:
1685 * the associated INTerrupt type if found
1689 apic_int_type(int apic, int pin)
1693 /* search each of the possible INTerrupt sources */
1694 for (x = 0; x < nintrs; ++x)
1695 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1696 (pin == io_apic_ints[x].dst_apic_int))
1697 return (io_apic_ints[x].int_type);
1699 return -1; /* NOT found */
1703 apic_irq(int apic, int pin)
1708 for (x = 0; x < nintrs; ++x)
1709 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1710 (pin == io_apic_ints[x].dst_apic_int)) {
1711 res = io_apic_ints[x].int_vector;
1714 if (apic != int_to_apicintpin[res].ioapic)
1715 panic("apic_irq: inconsistent table");
1716 if (pin != int_to_apicintpin[res].int_pin)
1717 panic("apic_irq inconsistent table (2)");
1725 * given a LOGICAL APIC# and pin#, return:
1726 * the associated trigger mode if found
1730 apic_trigger(int apic, int pin)
1734 /* search each of the possible INTerrupt sources */
1735 for (x = 0; x < nintrs; ++x)
1736 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1737 (pin == io_apic_ints[x].dst_apic_int))
1738 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1740 return -1; /* NOT found */
1745 * given a LOGICAL APIC# and pin#, return:
1746 * the associated 'active' level if found
1750 apic_polarity(int apic, int pin)
1754 /* search each of the possible INTerrupt sources */
1755 for (x = 0; x < nintrs; ++x)
1756 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1757 (pin == io_apic_ints[x].dst_apic_int))
1758 return (io_apic_ints[x].int_flags & 0x03);
1760 return -1; /* NOT found */
1765 * set data according to MP defaults
1766 * FIXME: probably not complete yet...
1769 default_mp_table(int type)
1772 #if defined(APIC_IO)
1775 #endif /* APIC_IO */
1778 printf(" MP default config type: %d\n", type);
1781 printf(" bus: ISA, APIC: 82489DX\n");
1784 printf(" bus: EISA, APIC: 82489DX\n");
1787 printf(" bus: EISA, APIC: 82489DX\n");
1790 printf(" bus: MCA, APIC: 82489DX\n");
1793 printf(" bus: ISA+PCI, APIC: Integrated\n");
1796 printf(" bus: EISA+PCI, APIC: Integrated\n");
1799 printf(" bus: MCA+PCI, APIC: Integrated\n");
1802 printf(" future type\n");
1808 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1809 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1812 CPU_TO_ID(0) = boot_cpu_id;
1813 ID_TO_CPU(boot_cpu_id) = 0;
1815 /* one and only AP */
1816 CPU_TO_ID(1) = ap_cpu_id;
1817 ID_TO_CPU(ap_cpu_id) = 1;
1819 #if defined(APIC_IO)
1820 /* one and only IO APIC */
1821 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1824 * sanity check, refer to MP spec section 3.6.6, last paragraph
1825 * necessary as some hardware isn't properly setting up the IO APIC
1827 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1828 if (io_apic_id != 2) {
1830 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1831 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1832 io_apic_set_id(0, 2);
1835 IO_TO_ID(0) = io_apic_id;
1836 ID_TO_IO(io_apic_id) = 0;
1837 #endif /* APIC_IO */
1839 /* fill out bus entries */
1848 bus_data[0].bus_id = default_data[type - 1][1];
1849 bus_data[0].bus_type = default_data[type - 1][2];
1850 bus_data[1].bus_id = default_data[type - 1][3];
1851 bus_data[1].bus_type = default_data[type - 1][4];
1854 /* case 4: case 7: MCA NOT supported */
1855 default: /* illegal/reserved */
1856 panic("BAD default MP config: %d", type);
1860 #if defined(APIC_IO)
1861 /* general cases from MP v1.4, table 5-2 */
1862 for (pin = 0; pin < 16; ++pin) {
1863 io_apic_ints[pin].int_type = 0;
1864 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1865 io_apic_ints[pin].src_bus_id = 0;
1866 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1867 io_apic_ints[pin].dst_apic_id = io_apic_id;
1868 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1871 /* special cases from MP v1.4, table 5-2 */
1873 io_apic_ints[2].int_type = 0xff; /* N/C */
1874 io_apic_ints[13].int_type = 0xff; /* N/C */
1875 #if !defined(APIC_MIXED_MODE)
1877 panic("sorry, can't support type 2 default yet");
1878 #endif /* APIC_MIXED_MODE */
1881 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1884 io_apic_ints[0].int_type = 0xff; /* N/C */
1886 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1887 #endif /* APIC_IO */
1892 * initialize all the SMP locks
1895 /* critical region around IO APIC, apic_imen */
1896 struct simplelock imen_lock;
1898 /* critical region around splxx(), cpl, cml, cil, ipending */
1899 struct simplelock cpl_lock;
1901 /* Make FAST_INTR() routines sequential */
1902 struct simplelock fast_intr_lock;
1904 /* critical region around INTR() routines */
1905 struct simplelock intr_lock;
1907 /* lock region used by kernel profiling */
1908 struct simplelock mcount_lock;
1911 /* locks com (tty) data/hardware accesses: a FASTINTR() */
1912 struct simplelock com_lock;
1913 #endif /* USE_COMLOCK */
1915 /* lock around the MP rendezvous */
1916 static struct simplelock smp_rv_lock;
1918 /* only 1 CPU can panic at a time :) */
1919 struct simplelock panic_lock;
1924 #if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ)
1925 s_lock_init((struct simplelock*)&apic_itrace_debuglock);
1928 s_lock_init((struct simplelock*)&mcount_lock);
1930 s_lock_init((struct simplelock*)&fast_intr_lock);
1931 s_lock_init((struct simplelock*)&intr_lock);
1932 s_lock_init((struct simplelock*)&imen_lock);
1933 s_lock_init((struct simplelock*)&cpl_lock);
1934 s_lock_init(&smp_rv_lock);
1935 s_lock_init(&panic_lock);
1938 s_lock_init((struct simplelock*)&com_lock);
1939 #endif /* USE_COMLOCK */
1941 s_lock_init(&ap_boot_lock);
1945 * start each AP in our list
1948 start_all_aps(u_int boot_addr)
1951 u_char mpbiosreason;
1952 u_long mpbioswarmvec;
1953 struct globaldata *gd;
1956 POSTCODE(START_ALL_APS_POST);
1958 /* initialize BSP's local APIC */
1962 /* install the AP 1st level boot code */
1963 install_ap_tramp(boot_addr);
1966 /* save the current value of the warm-start vector */
1967 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1969 outb(CMOS_REG, BIOS_RESET);
1970 mpbiosreason = inb(CMOS_DATA);
1973 /* record BSP in CPU map */
1976 /* set up 0 -> 4MB P==V mapping for AP boot */
1977 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
1981 for (x = 1; x <= mp_naps; ++x) {
1983 /* This is a bit verbose, it will go away soon. */
1985 /* first page of AP's private space */
1986 pg = x * i386_btop(sizeof(struct privatespace));
1988 /* allocate a new private data page */
1989 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1991 /* wire it into the private page table page */
1992 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1994 /* allocate and set up an idle stack data page */
1995 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1996 for (i = 0; i < UPAGES; i++)
1997 SMPpt[pg + 5 + i] = (pt_entry_t)
1998 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2000 SMPpt[pg + 1] = 0; /* *prv_CMAP1 */
2001 SMPpt[pg + 2] = 0; /* *prv_CMAP2 */
2002 SMPpt[pg + 3] = 0; /* *prv_CMAP3 */
2003 SMPpt[pg + 4] = 0; /* *prv_PMAP1 */
2005 /* prime data page for it to use */
2006 SLIST_INSERT_HEAD(&cpuhead, gd, gd_allcpu);
2008 gd->gd_cpu_lockid = x << 24;
2009 gd->gd_prv_CMAP1 = &SMPpt[pg + 1];
2010 gd->gd_prv_CMAP2 = &SMPpt[pg + 2];
2011 gd->gd_prv_CMAP3 = &SMPpt[pg + 3];
2012 gd->gd_prv_PMAP1 = &SMPpt[pg + 4];
2013 gd->gd_prv_CADDR1 = SMP_prvspace[x].CPAGE1;
2014 gd->gd_prv_CADDR2 = SMP_prvspace[x].CPAGE2;
2015 gd->gd_prv_CADDR3 = SMP_prvspace[x].CPAGE3;
2016 gd->gd_prv_PADDR1 = (unsigned *)SMP_prvspace[x].PPAGE1;
2018 /* setup a vector to our boot code */
2019 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2020 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2022 outb(CMOS_REG, BIOS_RESET);
2023 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2026 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
2029 /* attempt to start the Application Processor */
2030 CHECK_INIT(99); /* setup checkpoints */
2031 if (!start_ap(x, boot_addr)) {
2032 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2033 CHECK_PRINT("trace"); /* show checkpoints */
2034 /* better panic as the AP may be running loose */
2035 printf("panic y/n? [y] ");
2036 if (cngetc() != 'n')
2039 CHECK_PRINT("trace"); /* show checkpoints */
2041 /* record its version info */
2042 cpu_apic_versions[x] = cpu_apic_versions[0];
2044 all_cpus |= (1 << x); /* record AP in CPU map */
2047 /* build our map of 'other' CPUs */
2048 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2050 /* fill in our (BSP) APIC version */
2051 cpu_apic_versions[0] = lapic.version;
2053 /* restore the warmstart vector */
2054 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2056 outb(CMOS_REG, BIOS_RESET);
2057 outb(CMOS_DATA, mpbiosreason);
2061 * Set up the idle context for the BSP. Similar to above except
2062 * that some was done by locore, some by pmap.c and some is implicit
2063 * because the BSP is cpu#0 and the page is initially zero, and also
2064 * because we can refer to variables by name on the BSP..
2067 /* Allocate and setup BSP idle stack */
2068 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2069 for (i = 0; i < UPAGES; i++)
2070 SMPpt[5 + i] = (pt_entry_t)
2071 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2076 /* number of APs actually started */
2077 return mp_ncpus - 1;
2082 * load the 1st level AP boot code into base memory.
2085 /* targets for relocation */
2086 extern void bigJump(void);
2087 extern void bootCodeSeg(void);
2088 extern void bootDataSeg(void);
2089 extern void MPentry(void);
2090 extern u_int MP_GDT;
2091 extern u_int mp_gdtbase;
2094 install_ap_tramp(u_int boot_addr)
2097 int size = *(int *) ((u_long) & bootMP_size);
2098 u_char *src = (u_char *) ((u_long) bootMP);
2099 u_char *dst = (u_char *) boot_addr + KERNBASE;
2100 u_int boot_base = (u_int) bootMP;
2105 POSTCODE(INSTALL_AP_TRAMP_POST);
2107 for (x = 0; x < size; ++x)
2111 * modify addresses in code we just moved to basemem. unfortunately we
2112 * need fairly detailed info about mpboot.s for this to work. changes
2113 * to mpboot.s might require changes here.
2116 /* boot code is located in KERNEL space */
2117 dst = (u_char *) boot_addr + KERNBASE;
2119 /* modify the lgdt arg */
2120 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2121 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2123 /* modify the ljmp target for MPentry() */
2124 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2125 *dst32 = ((u_int) MPentry - KERNBASE);
2127 /* modify the target for boot code segment */
2128 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2129 dst8 = (u_int8_t *) (dst16 + 1);
2130 *dst16 = (u_int) boot_addr & 0xffff;
2131 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2133 /* modify the target for boot data segment */
2134 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2135 dst8 = (u_int8_t *) (dst16 + 1);
2136 *dst16 = (u_int) boot_addr & 0xffff;
2137 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2142 * this function starts the AP (application processor) identified
2143 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2144 * to accomplish this. This is necessary because of the nuances
2145 * of the different hardware we might encounter. It ain't pretty,
2146 * but it seems to work.
2149 start_ap(int logical_cpu, u_int boot_addr)
2154 u_long icr_lo, icr_hi;
2156 POSTCODE(START_AP_POST);
2158 /* get the PHYSICAL APIC ID# */
2159 physical_cpu = CPU_TO_ID(logical_cpu);
2161 /* calculate the vector */
2162 vector = (boot_addr >> 12) & 0xff;
2164 /* used as a watchpoint to signal AP startup */
2168 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2169 * and running the target CPU. OR this INIT IPI might be latched (P5
2170 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2174 /* setup the address for the target AP */
2175 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2176 icr_hi |= (physical_cpu << 24);
2177 lapic.icr_hi = icr_hi;
2179 /* do an INIT IPI: assert RESET */
2180 icr_lo = lapic.icr_lo & 0xfff00000;
2181 lapic.icr_lo = icr_lo | 0x0000c500;
2183 /* wait for pending status end */
2184 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2187 /* do an INIT IPI: deassert RESET */
2188 lapic.icr_lo = icr_lo | 0x00008500;
2190 /* wait for pending status end */
2191 u_sleep(10000); /* wait ~10mS */
2192 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2196 * next we do a STARTUP IPI: the previous INIT IPI might still be
2197 * latched, (P5 bug) this 1st STARTUP would then terminate
2198 * immediately, and the previously started INIT IPI would continue. OR
2199 * the previous INIT IPI has already run. and this STARTUP IPI will
2200 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2204 /* do a STARTUP IPI */
2205 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2206 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2208 u_sleep(200); /* wait ~200uS */
2211 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2212 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2213 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2214 * recognized after hardware RESET or INIT IPI.
2217 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2218 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2220 u_sleep(200); /* wait ~200uS */
2222 /* wait for it to start */
2223 set_apic_timer(5000000);/* == 5 seconds */
2224 while (read_apic_timer())
2225 if (mp_ncpus > cpus)
2226 return 1; /* return SUCCESS */
2228 return 0; /* return FAILURE */
2232 * Flush the TLB on all other CPU's
2234 * XXX: Needs to handshake and wait for completion before proceding.
2239 #if defined(APIC_IO)
2240 if (smp_started && invltlb_ok)
2241 all_but_self_ipi(XINVLTLB_OFFSET);
2242 #endif /* APIC_IO */
2248 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2250 /* send a message to the other CPUs */
2260 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2263 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2265 /* send a message to the other CPUs */
2271 * When called the executing CPU will send an IPI to all other CPUs
2272 * requesting that they halt execution.
2274 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2276 * - Signals all CPUs in map to stop.
2277 * - Waits for each to stop.
2284 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2285 * from executing at same time.
2288 stop_cpus(u_int map)
2295 /* send the Xcpustop IPI to all CPUs in map */
2296 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2298 while (count++ < 100000 && (stopped_cpus & map) != map)
2302 if ((stopped_cpus & map) != map)
2303 printf("Warning: CPUs 0x%x did not stop!\n",
2304 (~(stopped_cpus & map)) & map);
2312 * Called by a CPU to restart stopped CPUs.
2314 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2316 * - Signals all CPUs in map to restart.
2317 * - Waits for each to restart.
2325 restart_cpus(u_int map)
2332 started_cpus = map; /* signal other cpus to restart */
2334 /* wait for each to clear its bit */
2335 while (count++ < 100000 && (stopped_cpus & map) != 0)
2339 if ((stopped_cpus & map) != 0)
2340 printf("Warning: CPUs 0x%x did not restart!\n",
2341 (~(stopped_cpus & map)) & map);
2347 int smp_active = 0; /* are the APs allowed to run? */
2348 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2350 /* XXX maybe should be hw.ncpu */
2351 static int smp_cpus = 1; /* how many cpu's running */
2352 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2354 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2355 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2357 /* Warning: Do not staticize. Used from swtch.s */
2358 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2359 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2360 &do_page_zero_idle, 0, "");
2362 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2363 int forward_irq_enabled = 1;
2364 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2365 &forward_irq_enabled, 0, "");
2367 /* Enable forwarding of a signal to a process running on a different CPU */
2368 static int forward_signal_enabled = 1;
2369 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2370 &forward_signal_enabled, 0, "");
2372 /* Enable forwarding of roundrobin to all other cpus */
2373 static int forward_roundrobin_enabled = 1;
2374 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2375 &forward_roundrobin_enabled, 0, "");
2378 * This is called once the rest of the system is up and running and we're
2379 * ready to let the AP's out of the pen.
2388 /* lock against other AP's that are waking up */
2389 s_lock(&ap_boot_lock);
2391 /* BSP may have changed PTD while we're waiting for the lock */
2396 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2400 /* Build our map of 'other' CPUs. */
2401 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2403 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2405 /* set up CPU registers and state */
2408 /* set up FPU state on the AP */
2409 npxinit(__INITIAL_NPXCW__);
2411 /* A quick check from sanity claus */
2412 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2413 if (PCPU_GET(cpuid) != apic_id) {
2414 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2415 printf("SMP: apic_id = %d\n", apic_id);
2416 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2417 panic("cpuid mismatch! boom!!");
2420 /* Init local apic for irq's */
2423 /* Set memory range attributes for this CPU to match the BSP */
2424 mem_range_AP_init();
2427 * Activate smp_invltlb, although strictly speaking, this isn't
2428 * quite correct yet. We should have a bitfield for cpus willing
2429 * to accept TLB flush IPI's or something and sync them.
2431 if (smp_cpus == mp_ncpus) {
2433 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2434 smp_active = 1; /* historic */
2437 /* let other AP's wake up now */
2438 s_unlock(&ap_boot_lock);
2440 /* wait until all the AP's are up */
2441 while (smp_started == 0)
2445 * Set curproc to our per-cpu idleproc so that mutexes have
2446 * something unique to lock with.
2448 PCPU_SET(curproc, PCPU_GET(idleproc));
2450 microuptime(PCPU_PTR(switchtime));
2451 PCPU_SET(switchticks, ticks);
2453 /* ok, now grab sched_lock and enter the scheduler */
2455 mtx_enter(&sched_lock, MTX_SPIN);
2456 cpu_throw(); /* doesn't return */
2458 panic("scheduler returned us to ap_init");
2463 #define CHECKSTATE_USER 0
2464 #define CHECKSTATE_SYS 1
2465 #define CHECKSTATE_INTR 2
2467 /* Do not staticize. Used from apic_vector.s */
2468 struct proc* checkstate_curproc[MAXCPU];
2469 int checkstate_cpustate[MAXCPU];
2470 u_long checkstate_pc[MAXCPU];
2472 #define PC_TO_INDEX(pc, prof) \
2473 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2474 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2477 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2483 pc = checkstate_pc[id];
2484 prof = &p->p_stats->p_prof;
2485 if (pc >= prof->pr_off &&
2486 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2487 if ((p->p_flag & P_OWEUPC) == 0) {
2490 p->p_flag |= P_OWEUPC;
2492 *astmap |= (1 << id);
2497 forwarded_statclock(int id, int pscnt, int *astmap)
2499 struct pstats *pstats;
2506 register struct gmonparam *g;
2510 p = checkstate_curproc[id];
2511 cpustate = checkstate_cpustate[id];
2515 cpustate = CHECKSTATE_INTR;
2516 else if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2517 cpustate = CHECKSTATE_SYS;
2520 case CHECKSTATE_USER:
2521 if (p->p_flag & P_PROFIL)
2522 addupc_intr_forwarded(p, id, astmap);
2526 if (p->p_nice > NZERO)
2531 case CHECKSTATE_SYS:
2534 * Kernel statistics are just like addupc_intr, only easier.
2537 if (g->state == GMON_PROF_ON) {
2538 i = checkstate_pc[id] - g->lowpc;
2539 if (i < g->textsize) {
2540 i /= HISTFRACTION * sizeof(*g->kcount);
2549 if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2554 case CHECKSTATE_INTR:
2558 * Kernel statistics are just like addupc_intr, only easier.
2561 if (g->state == GMON_PROF_ON) {
2562 i = checkstate_pc[id] - g->lowpc;
2563 if (i < g->textsize) {
2564 i /= HISTFRACTION * sizeof(*g->kcount);
2577 /* Update resource usage integrals and maximums. */
2578 if ((pstats = p->p_stats) != NULL &&
2579 (ru = &pstats->p_ru) != NULL &&
2580 (vm = p->p_vmspace) != NULL) {
2581 ru->ru_ixrss += pgtok(vm->vm_tsize);
2582 ru->ru_idrss += pgtok(vm->vm_dsize);
2583 ru->ru_isrss += pgtok(vm->vm_ssize);
2584 rss = pgtok(vmspace_resident_count(vm));
2585 if (ru->ru_maxrss < rss)
2586 ru->ru_maxrss = rss;
2591 forward_statclock(int pscnt)
2597 /* Kludge. We don't yet have separate locks for the interrupts
2598 * and the kernel. This means that we cannot let the other processors
2599 * handle complex interrupts while inhibiting them from entering
2600 * the kernel in a non-interrupt context.
2602 * What we can do, without changing the locking mechanisms yet,
2603 * is letting the other processors handle a very simple interrupt
2604 * (wich determines the processor states), and do the main
2608 if (!smp_started || !invltlb_ok || cold || panicstr)
2611 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2613 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2614 checkstate_probed_cpus = 0;
2616 selected_apic_ipi(map,
2617 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2620 while (checkstate_probed_cpus != map) {
2624 #ifdef BETTER_CLOCK_DIAGNOSTIC
2625 printf("forward_statclock: checkstate %x\n",
2626 checkstate_probed_cpus);
2633 * Step 2: walk through other processors processes, update ticks and
2638 for (id = 0; id < mp_ncpus; id++) {
2639 if (id == PCPU_GET(cpuid))
2641 if (((1 << id) & checkstate_probed_cpus) == 0)
2643 forwarded_statclock(id, pscnt, &map);
2646 checkstate_need_ast |= map;
2647 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2649 while ((checkstate_need_ast & map) != 0) {
2653 #ifdef BETTER_CLOCK_DIAGNOSTIC
2654 printf("forward_statclock: dropped ast 0x%x\n",
2655 checkstate_need_ast & map);
2664 forward_hardclock(int pscnt)
2669 struct pstats *pstats;
2672 /* Kludge. We don't yet have separate locks for the interrupts
2673 * and the kernel. This means that we cannot let the other processors
2674 * handle complex interrupts while inhibiting them from entering
2675 * the kernel in a non-interrupt context.
2677 * What we can do, without changing the locking mechanisms yet,
2678 * is letting the other processors handle a very simple interrupt
2679 * (wich determines the processor states), and do the main
2683 if (!smp_started || !invltlb_ok || cold || panicstr)
2686 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2688 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2689 checkstate_probed_cpus = 0;
2691 selected_apic_ipi(map,
2692 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2695 while (checkstate_probed_cpus != map) {
2699 #ifdef BETTER_CLOCK_DIAGNOSTIC
2700 printf("forward_hardclock: checkstate %x\n",
2701 checkstate_probed_cpus);
2708 * Step 2: walk through other processors processes, update virtual
2709 * timer and profiling timer. If stathz == 0, also update ticks and
2714 for (id = 0; id < mp_ncpus; id++) {
2715 if (id == PCPU_GET(cpuid))
2717 if (((1 << id) & checkstate_probed_cpus) == 0)
2719 p = checkstate_curproc[id];
2721 pstats = p->p_stats;
2722 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2723 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2724 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2725 psignal(p, SIGVTALRM);
2728 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2729 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2730 psignal(p, SIGPROF);
2735 forwarded_statclock( id, pscnt, &map);
2739 checkstate_need_ast |= map;
2740 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2742 while ((checkstate_need_ast & map) != 0) {
2746 #ifdef BETTER_CLOCK_DIAGNOSTIC
2747 printf("forward_hardclock: dropped ast 0x%x\n",
2748 checkstate_need_ast & map);
2756 #endif /* BETTER_CLOCK */
2759 forward_signal(struct proc *p)
2765 /* Kludge. We don't yet have separate locks for the interrupts
2766 * and the kernel. This means that we cannot let the other processors
2767 * handle complex interrupts while inhibiting them from entering
2768 * the kernel in a non-interrupt context.
2770 * What we can do, without changing the locking mechanisms yet,
2771 * is letting the other processors handle a very simple interrupt
2772 * (wich determines the processor states), and do the main
2776 if (!smp_started || !invltlb_ok || cold || panicstr)
2778 if (!forward_signal_enabled)
2781 if (p->p_stat != SRUN)
2787 checkstate_need_ast |= map;
2788 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2790 while ((checkstate_need_ast & map) != 0) {
2795 printf("forward_signal: dropped ast 0x%x\n",
2796 checkstate_need_ast & map);
2801 if (id == p->p_oncpu)
2807 forward_roundrobin(void)
2812 if (!smp_started || !invltlb_ok || cold || panicstr)
2814 if (!forward_roundrobin_enabled)
2816 resched_cpus |= PCPU_GET(other_cpus);
2817 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2819 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2821 (void) all_but_self_ipi(XCPUAST_OFFSET);
2824 while ((checkstate_need_ast & map) != 0) {
2829 printf("forward_roundrobin: dropped ast 0x%x\n",
2830 checkstate_need_ast & map);
2838 #ifdef APIC_INTR_REORDER
2840 * Maintain mapping from softintr vector to isr bit in local apic.
2843 set_lapic_isrloc(int intr, int vector)
2845 if (intr < 0 || intr > 32)
2846 panic("set_apic_isrloc: bad intr argument: %d",intr);
2847 if (vector < ICU_OFFSET || vector > 255)
2848 panic("set_apic_isrloc: bad vector argument: %d",vector);
2849 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2850 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2855 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2856 * (if specified), rendezvous, execute the action function (if specified),
2857 * rendezvous again, execute the teardown function (if specified), and then
2860 * Note that the supplied external functions _must_ be reentrant and aware
2861 * that they are running in parallel and in an unknown lock context.
2863 static void (*smp_rv_setup_func)(void *arg);
2864 static void (*smp_rv_action_func)(void *arg);
2865 static void (*smp_rv_teardown_func)(void *arg);
2866 static void *smp_rv_func_arg;
2867 static volatile int smp_rv_waiters[2];
2870 smp_rendezvous_action(void)
2872 /* setup function */
2873 if (smp_rv_setup_func != NULL)
2874 smp_rv_setup_func(smp_rv_func_arg);
2875 /* spin on entry rendezvous */
2876 atomic_add_int(&smp_rv_waiters[0], 1);
2877 while (smp_rv_waiters[0] < mp_ncpus)
2879 /* action function */
2880 if (smp_rv_action_func != NULL)
2881 smp_rv_action_func(smp_rv_func_arg);
2882 /* spin on exit rendezvous */
2883 atomic_add_int(&smp_rv_waiters[1], 1);
2884 while (smp_rv_waiters[1] < mp_ncpus)
2886 /* teardown function */
2887 if (smp_rv_teardown_func != NULL)
2888 smp_rv_teardown_func(smp_rv_func_arg);
2892 smp_rendezvous(void (* setup_func)(void *),
2893 void (* action_func)(void *),
2894 void (* teardown_func)(void *),
2899 /* obtain rendezvous lock */
2900 s_lock(&smp_rv_lock); /* XXX sleep here? NOWAIT flag? */
2902 /* set static function pointers */
2903 smp_rv_setup_func = setup_func;
2904 smp_rv_action_func = action_func;
2905 smp_rv_teardown_func = teardown_func;
2906 smp_rv_func_arg = arg;
2907 smp_rv_waiters[0] = 0;
2908 smp_rv_waiters[1] = 0;
2910 /* disable interrupts on this CPU, save interrupt status */
2911 efl = read_eflags();
2912 write_eflags(efl & ~PSL_I);
2914 /* signal other processors, which will enter the IPI with interrupts off */
2915 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2917 /* call executor function */
2918 smp_rendezvous_action();
2920 /* restore interrupt flag */
2924 s_unlock(&smp_rv_lock);
2928 release_aps(void *dummy __unused)
2930 s_unlock(&ap_boot_lock);
2933 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);