2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <machine/smptests.h>
36 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
42 #include <sys/malloc.h>
43 #include <sys/memrange.h>
44 #include <sys/mutex.h>
45 #include <sys/dkstat.h>
46 #include <sys/cons.h> /* cngetc() */
49 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
54 #include <vm/vm_map.h>
60 #include <machine/smp.h>
61 #include <machine/apic.h>
62 #include <machine/atomic.h>
63 #include <machine/cpufunc.h>
64 #include <machine/ipl.h>
65 #include <machine/mpapic.h>
66 #include <machine/psl.h>
67 #include <machine/segments.h>
68 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
69 #include <machine/tss.h>
70 #include <machine/specialreg.h>
71 #include <machine/globaldata.h>
74 #include <machine/md_var.h> /* setidt() */
75 #include <i386/isa/icu.h> /* IPIs */
76 #include <i386/isa/intr_machdep.h> /* IPIs */
79 #if defined(TEST_DEFAULT_CONFIG)
80 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
82 #define MPFPS_MPFB1 mpfps->mpfb1
83 #endif /* TEST_DEFAULT_CONFIG */
85 #define WARMBOOT_TARGET 0
86 #define WARMBOOT_OFF (KERNBASE + 0x0467)
87 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define BIOS_BASE (0xe8000)
91 #define BIOS_SIZE (0x18000)
93 #define BIOS_BASE (0xf0000)
94 #define BIOS_SIZE (0x10000)
96 #define BIOS_COUNT (BIOS_SIZE/4)
98 #define CMOS_REG (0x70)
99 #define CMOS_DATA (0x71)
100 #define BIOS_RESET (0x0f)
101 #define BIOS_WARM (0x0a)
103 #define PROCENTRY_FLAG_EN 0x01
104 #define PROCENTRY_FLAG_BP 0x02
105 #define IOAPICENTRY_FLAG_EN 0x01
108 /* MP Floating Pointer Structure */
109 typedef struct MPFPS {
122 /* MP Configuration Table Header */
123 typedef struct MPCTH {
125 u_short base_table_length;
129 u_char product_id[12];
130 void *oem_table_pointer;
131 u_short oem_table_size;
134 u_short extended_table_length;
135 u_char extended_table_checksum;
140 typedef struct PROCENTRY {
145 u_long cpu_signature;
146 u_long feature_flags;
151 typedef struct BUSENTRY {
157 typedef struct IOAPICENTRY {
163 } *io_apic_entry_ptr;
165 typedef struct INTENTRY {
175 /* descriptions of MP basetable entries */
176 typedef struct BASETABLE_ENTRY {
183 * this code MUST be enabled here and in mpboot.s.
184 * it follows the very early stages of AP boot by placing values in CMOS ram.
185 * it NORMALLY will never be needed and thus the primitive method for enabling.
190 #if defined(CHECK_POINTS) && !defined(PC98)
191 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
192 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
194 #define CHECK_INIT(D); \
195 CHECK_WRITE(0x34, (D)); \
196 CHECK_WRITE(0x35, (D)); \
197 CHECK_WRITE(0x36, (D)); \
198 CHECK_WRITE(0x37, (D)); \
199 CHECK_WRITE(0x38, (D)); \
200 CHECK_WRITE(0x39, (D));
202 #define CHECK_PRINT(S); \
203 printf("%s: %d, %d, %d, %d, %d, %d\n", \
212 #else /* CHECK_POINTS */
214 #define CHECK_INIT(D)
215 #define CHECK_PRINT(S)
217 #endif /* CHECK_POINTS */
220 * Values to send to the POST hardware.
222 #define MP_BOOTADDRESS_POST 0x10
223 #define MP_PROBE_POST 0x11
224 #define MPTABLE_PASS1_POST 0x12
226 #define MP_START_POST 0x13
227 #define MP_ENABLE_POST 0x14
228 #define MPTABLE_PASS2_POST 0x15
230 #define START_ALL_APS_POST 0x16
231 #define INSTALL_AP_TRAMP_POST 0x17
232 #define START_AP_POST 0x18
234 #define MP_ANNOUNCE_POST 0x19
236 /* used to hold the AP's until we are ready to release them */
237 struct mtx ap_boot_mtx;
239 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
240 int current_postcode;
242 /** XXX FIXME: what system files declare these??? */
243 extern struct region_descriptor r_gdt, r_idt;
245 int bsp_apic_ready = 0; /* flags useability of BSP apic */
246 int mp_ncpus; /* # of CPUs, including BSP */
247 int mp_naps; /* # of Applications processors */
248 int mp_nbusses; /* # of busses */
249 int mp_napics; /* # of IO APICs */
250 int boot_cpu_id; /* designated BSP */
251 vm_offset_t cpu_apic_address;
252 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
255 u_int32_t cpu_apic_versions[MAXCPU];
256 u_int32_t *io_apic_versions;
258 #ifdef APIC_INTR_REORDER
260 volatile int *location;
262 } apic_isrbit_location[32];
265 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
268 * APIC ID logical/physical mapping structures.
269 * We oversize these to simplify boot-time config.
271 int cpu_num_to_apic_id[NAPICID];
272 int io_num_to_apic_id[NAPICID];
273 int apic_id_to_logical[NAPICID];
276 /* Bitmap of all available CPUs */
279 /* AP uses this during bootstrap. Do not staticize. */
283 /* Hotwire a 0->4MB V==P mapping */
284 extern pt_entry_t *KPTphys;
286 /* SMP page table page */
287 extern pt_entry_t *SMPpt;
289 struct pcb stoppcbs[MAXCPU];
291 int smp_started; /* has the system started? */
292 int smp_active = 0; /* are the APs allowed to run? */
293 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
295 /* XXX maybe should be hw.ncpu */
296 static int smp_cpus = 1; /* how many cpu's running */
297 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
299 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
300 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
302 /* Enable forwarding of a signal to a process running on a different CPU */
303 static int forward_signal_enabled = 1;
304 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
305 &forward_signal_enabled, 0, "");
307 /* Enable forwarding of roundrobin to all other cpus */
308 static int forward_roundrobin_enabled = 1;
309 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
310 &forward_roundrobin_enabled, 0, "");
314 * Local data and functions.
317 /* Set to 1 once we're ready to let the APs out of the pen. */
318 static volatile int aps_ready = 0;
320 static int mp_capable;
321 static u_int boot_address;
322 static u_int base_memory;
324 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
325 static mpfps_t mpfps;
326 static int search_for_sig(u_int32_t target, int count);
327 static void mp_enable(u_int boot_addr);
329 static void mptable_pass1(void);
330 static int mptable_pass2(void);
331 static void default_mp_table(int type);
332 static void fix_mp_table(void);
333 static void setup_apic_irq_mapping(void);
334 static void init_locks(void);
335 static int start_all_aps(u_int boot_addr);
336 static void install_ap_tramp(u_int boot_addr);
337 static int start_ap(int logicalCpu, u_int boot_addr);
339 static int apic_int_is_bus_type(int intr, int bus_type);
340 static void release_aps(void *dummy);
343 * initialize all the SMP locks
346 /* critical region around IO APIC, apic_imen */
349 /* lock region used by kernel profiling */
350 struct mtx mcount_mtx;
353 /* locks com (tty) data/hardware accesses: a FASTINTR() */
355 #endif /* USE_COMLOCK */
357 /* lock around the MP rendezvous */
358 static struct mtx smp_rv_mtx;
364 * XXX The mcount mutex probably needs to be statically initialized,
365 * since it will be used even in the function calls that get us to this
368 mtx_init(&mcount_mtx, "mcount", MTX_DEF);
370 mtx_init(&smp_rv_mtx, "smp rendezvous", MTX_SPIN);
373 mtx_init(&com_mtx, "com", MTX_SPIN);
374 #endif /* USE_COMLOCK */
376 mtx_init(&ap_boot_mtx, "ap boot", MTX_SPIN);
380 * Calculate usable address in base memory for AP trampoline code.
383 mp_bootaddress(u_int basemem)
385 POSTCODE(MP_BOOTADDRESS_POST);
387 base_memory = basemem * 1024; /* convert to bytes */
389 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
390 if ((base_memory - boot_address) < bootMP_size)
391 boot_address -= 4096; /* not enough, lower by 4k */
398 * Look for an Intel MP spec table (ie, SMP capable hardware).
407 POSTCODE(MP_PROBE_POST);
409 /* see if EBDA exists */
410 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
411 /* search first 1K of EBDA */
412 target = (u_int32_t) (segment << 4);
413 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
416 /* last 1K of base memory, effective 'top of base' passed in */
417 target = (u_int32_t) (base_memory - 0x400);
418 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
422 /* search the BIOS */
423 target = (u_int32_t) BIOS_BASE;
424 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
433 /* calculate needed resources */
437 /* flag fact that we are running multiple processors */
444 * Initialize the SMP hardware and the APIC and start up the AP's.
449 POSTCODE(MP_START_POST);
451 /* look for MP capable motherboard */
453 mp_enable(boot_address);
455 panic("MP hardware not found!");
460 * Print various information about the SMP system hardware and setup.
467 POSTCODE(MP_ANNOUNCE_POST);
469 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
470 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
471 printf(", version: 0x%08x", cpu_apic_versions[0]);
472 printf(", at 0x%08x\n", cpu_apic_address);
473 for (x = 1; x <= mp_naps; ++x) {
474 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
475 printf(", version: 0x%08x", cpu_apic_versions[x]);
476 printf(", at 0x%08x\n", cpu_apic_address);
480 for (x = 0; x < mp_napics; ++x) {
481 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
482 printf(", version: 0x%08x", io_apic_versions[x]);
483 printf(", at 0x%08x\n", io_apic_address[x]);
486 printf(" Warning: APIC I/O disabled\n");
491 * AP cpu's call this to sync up protected mode.
497 int x, myid = bootAP;
499 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
500 gdt_segs[GPROC0_SEL].ssd_base =
501 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
502 SMP_prvspace[myid].globaldata.gd_prvspace =
503 &SMP_prvspace[myid].globaldata;
505 for (x = 0; x < NGDT; x++) {
506 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
509 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
510 r_gdt.rd_base = (int) &gdt[myid * NGDT];
511 lgdt(&r_gdt); /* does magic intra-segment return */
516 PCPU_SET(currentldt, _default_ldt);
518 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
519 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
520 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
521 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
522 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
523 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
524 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
533 * Final configuration of the BSP's local APIC:
534 * - disable 'pic mode'.
535 * - disable 'virtual wire mode'.
539 bsp_apic_configure(void)
544 /* leave 'pic mode' if necessary */
546 outb(0x22, 0x70); /* select IMCR */
547 byte = inb(0x23); /* current contents */
548 byte |= 0x01; /* mask external INTR */
549 outb(0x23, byte); /* disconnect 8259s/NMI */
552 /* mask lint0 (the 8259 'virtual wire' connection) */
553 temp = lapic.lvt_lint0;
554 temp |= APIC_LVT_M; /* set the mask */
555 lapic.lvt_lint0 = temp;
557 /* setup lint1 to handle NMI */
558 temp = lapic.lvt_lint1;
559 temp &= ~APIC_LVT_M; /* clear the mask */
560 lapic.lvt_lint1 = temp;
563 apic_dump("bsp_apic_configure()");
568 /*******************************************************************
569 * local functions and data
573 * start the SMP system
576 mp_enable(u_int boot_addr)
584 POSTCODE(MP_ENABLE_POST);
586 /* turn on 4MB of V == P addressing so we can get to MP table */
587 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
590 /* examine the MP table for needed info, uses physical addresses */
596 /* can't process default configs till the CPU APIC is pmapped */
600 /* post scan cleanup */
602 setup_apic_irq_mapping();
606 /* fill the LOGICAL io_apic_versions table */
607 for (apic = 0; apic < mp_napics; ++apic) {
608 ux = io_apic_read(apic, IOAPIC_VER);
609 io_apic_versions[apic] = ux;
610 io_apic_set_id(apic, IO_TO_ID(apic));
613 /* program each IO APIC in the system */
614 for (apic = 0; apic < mp_napics; ++apic)
615 if (io_apic_setup(apic) < 0)
616 panic("IO APIC setup failure");
618 /* install a 'Spurious INTerrupt' vector */
619 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
620 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
622 /* install an inter-CPU IPI for TLB invalidation */
623 setidt(XINVLTLB_OFFSET, Xinvltlb,
624 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
626 /* install an inter-CPU IPI for reading processor state */
627 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
628 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
630 /* install an inter-CPU IPI for all-CPU rendezvous */
631 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
632 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
634 /* install an inter-CPU IPI for forcing an additional software trap */
635 setidt(XCPUAST_OFFSET, Xcpuast,
636 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
638 /* install an inter-CPU IPI for CPU stop/restart */
639 setidt(XCPUSTOP_OFFSET, Xcpustop,
640 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
642 #if defined(TEST_TEST1)
643 /* install a "fake hardware INTerrupt" vector */
644 setidt(XTEST1_OFFSET, Xtest1,
645 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
646 #endif /** TEST_TEST1 */
650 /* initialize all SMP locks */
653 /* start each Application Processor */
654 start_all_aps(boot_addr);
659 * look for the MP spec signature
662 /* string defined by the Intel MP Spec as identifying the MP table */
663 #define MP_SIG 0x5f504d5f /* _MP_ */
664 #define NEXT(X) ((X) += 4)
666 search_for_sig(u_int32_t target, int count)
669 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
671 for (x = 0; x < count; NEXT(x))
672 if (addr[x] == MP_SIG)
673 /* make array index a byte index */
674 return (target + (x * sizeof(u_int32_t)));
680 static basetable_entry basetable_entry_types[] =
682 {0, 20, "Processor"},
689 typedef struct BUSDATA {
691 enum busTypes bus_type;
694 typedef struct INTDATA {
704 typedef struct BUSTYPENAME {
709 static bus_type_name bus_type_table[] =
715 {UNKNOWN_BUSTYPE, "---"},
718 {UNKNOWN_BUSTYPE, "---"},
719 {UNKNOWN_BUSTYPE, "---"},
720 {UNKNOWN_BUSTYPE, "---"},
721 {UNKNOWN_BUSTYPE, "---"},
722 {UNKNOWN_BUSTYPE, "---"},
724 {UNKNOWN_BUSTYPE, "---"},
725 {UNKNOWN_BUSTYPE, "---"},
726 {UNKNOWN_BUSTYPE, "---"},
727 {UNKNOWN_BUSTYPE, "---"},
729 {UNKNOWN_BUSTYPE, "---"}
731 /* from MP spec v1.4, table 5-1 */
732 static int default_data[7][5] =
734 /* nbus, id0, type0, id1, type1 */
735 {1, 0, ISA, 255, 255},
736 {1, 0, EISA, 255, 255},
737 {1, 0, EISA, 255, 255},
738 {1, 0, MCA, 255, 255},
740 {2, 0, EISA, 1, PCI},
746 static bus_datum *bus_data;
748 /* the IO INT data, one entry per possible APIC INTerrupt */
749 static io_int *io_apic_ints;
753 static int processor_entry __P((proc_entry_ptr entry, int cpu));
754 static int bus_entry __P((bus_entry_ptr entry, int bus));
755 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
756 static int int_entry __P((int_entry_ptr entry, int intr));
757 static int lookup_bus_type __P((char *name));
761 * 1st pass on motherboard's Intel MP specification table.
767 * cpu_apic_address (common to all CPUs)
784 POSTCODE(MPTABLE_PASS1_POST);
786 /* clear various tables */
787 for (x = 0; x < NAPICID; ++x) {
788 io_apic_address[x] = ~0; /* IO APIC address table */
791 /* init everything to empty */
797 /* check for use of 'default' configuration */
798 if (MPFPS_MPFB1 != 0) {
799 /* use default addresses */
800 cpu_apic_address = DEFAULT_APIC_BASE;
801 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
803 /* fill in with defaults */
804 mp_naps = 2; /* includes BSP */
805 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
812 if ((cth = mpfps->pap) == 0)
813 panic("MP Configuration Table Header MISSING!");
815 cpu_apic_address = (vm_offset_t) cth->apic_address;
817 /* walk the table, recording info of interest */
818 totalSize = cth->base_table_length - sizeof(struct MPCTH);
819 position = (u_char *) cth + sizeof(struct MPCTH);
820 count = cth->entry_count;
823 switch (type = *(u_char *) position) {
824 case 0: /* processor_entry */
825 if (((proc_entry_ptr)position)->cpu_flags
829 case 1: /* bus_entry */
832 case 2: /* io_apic_entry */
833 if (((io_apic_entry_ptr)position)->apic_flags
834 & IOAPICENTRY_FLAG_EN)
835 io_apic_address[mp_napics++] =
836 (vm_offset_t)((io_apic_entry_ptr)
837 position)->apic_address;
839 case 3: /* int_entry */
842 case 4: /* int_entry */
845 panic("mpfps Base Table HOSED!");
849 totalSize -= basetable_entry_types[type].length;
850 (u_char*)position += basetable_entry_types[type].length;
854 /* qualify the numbers */
855 if (mp_naps > MAXCPU) {
856 printf("Warning: only using %d of %d available CPUs!\n",
863 * This is also used as a counter while starting the APs.
867 --mp_naps; /* subtract the BSP */
872 * 2nd pass on motherboard's Intel MP specification table.
876 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
877 * CPU_TO_ID(N), logical CPU to APIC ID table
878 * IO_TO_ID(N), logical IO to APIC ID table
891 int apic, bus, cpu, intr;
895 POSTCODE(MPTABLE_PASS2_POST);
897 pgeflag = 0; /* XXX - Not used under SMP yet. */
899 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
901 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
903 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
905 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
908 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
910 for (i = 0; i < mp_napics; i++) {
911 for (j = 0; j < mp_napics; j++) {
912 /* same page frame as a previous IO apic? */
913 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
914 (io_apic_address[i] & PG_FRAME)) {
915 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
916 + (NPTEPG-2-j) * PAGE_SIZE
917 + (io_apic_address[i] & PAGE_MASK));
920 /* use this slot if available */
921 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
922 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
923 pgeflag | (io_apic_address[i] & PG_FRAME));
924 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
925 + (NPTEPG-2-j) * PAGE_SIZE
926 + (io_apic_address[i] & PAGE_MASK));
932 /* clear various tables */
933 for (x = 0; x < NAPICID; ++x) {
934 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
935 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
936 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
939 /* clear bus data table */
940 for (x = 0; x < mp_nbusses; ++x)
941 bus_data[x].bus_id = 0xff;
943 /* clear IO APIC INT table */
944 for (x = 0; x < (nintrs + 1); ++x) {
945 io_apic_ints[x].int_type = 0xff;
946 io_apic_ints[x].int_vector = 0xff;
949 /* setup the cpu/apic mapping arrays */
952 /* record whether PIC or virtual-wire mode */
953 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
955 /* check for use of 'default' configuration */
956 if (MPFPS_MPFB1 != 0)
957 return MPFPS_MPFB1; /* return default configuration type */
959 if ((cth = mpfps->pap) == 0)
960 panic("MP Configuration Table Header MISSING!");
962 /* walk the table, recording info of interest */
963 totalSize = cth->base_table_length - sizeof(struct MPCTH);
964 position = (u_char *) cth + sizeof(struct MPCTH);
965 count = cth->entry_count;
966 apic = bus = intr = 0;
967 cpu = 1; /* pre-count the BSP */
970 switch (type = *(u_char *) position) {
972 if (processor_entry(position, cpu))
976 if (bus_entry(position, bus))
980 if (io_apic_entry(position, apic))
984 if (int_entry(position, intr))
988 /* int_entry(position); */
991 panic("mpfps Base Table HOSED!");
995 totalSize -= basetable_entry_types[type].length;
996 (u_char *) position += basetable_entry_types[type].length;
999 if (boot_cpu_id == -1)
1000 panic("NO BSP found!");
1002 /* report fact that its NOT a default configuration */
1008 assign_apic_irq(int apic, int intpin, int irq)
1012 if (int_to_apicintpin[irq].ioapic != -1)
1013 panic("assign_apic_irq: inconsistent table");
1015 int_to_apicintpin[irq].ioapic = apic;
1016 int_to_apicintpin[irq].int_pin = intpin;
1017 int_to_apicintpin[irq].apic_address = ioapic[apic];
1018 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1020 for (x = 0; x < nintrs; x++) {
1021 if ((io_apic_ints[x].int_type == 0 ||
1022 io_apic_ints[x].int_type == 3) &&
1023 io_apic_ints[x].int_vector == 0xff &&
1024 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1025 io_apic_ints[x].dst_apic_int == intpin)
1026 io_apic_ints[x].int_vector = irq;
1031 revoke_apic_irq(int irq)
1037 if (int_to_apicintpin[irq].ioapic == -1)
1038 panic("assign_apic_irq: inconsistent table");
1040 oldapic = int_to_apicintpin[irq].ioapic;
1041 oldintpin = int_to_apicintpin[irq].int_pin;
1043 int_to_apicintpin[irq].ioapic = -1;
1044 int_to_apicintpin[irq].int_pin = 0;
1045 int_to_apicintpin[irq].apic_address = NULL;
1046 int_to_apicintpin[irq].redirindex = 0;
1048 for (x = 0; x < nintrs; x++) {
1049 if ((io_apic_ints[x].int_type == 0 ||
1050 io_apic_ints[x].int_type == 3) &&
1051 io_apic_ints[x].int_vector == 0xff &&
1052 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1053 io_apic_ints[x].dst_apic_int == oldintpin)
1054 io_apic_ints[x].int_vector = 0xff;
1060 allocate_apic_irq(int intr)
1066 if (io_apic_ints[intr].int_vector != 0xff)
1067 return; /* Interrupt handler already assigned */
1069 if (io_apic_ints[intr].int_type != 0 &&
1070 (io_apic_ints[intr].int_type != 3 ||
1071 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1072 io_apic_ints[intr].dst_apic_int == 0)))
1073 return; /* Not INT or ExtInt on != (0, 0) */
1076 while (irq < APIC_INTMAPSIZE &&
1077 int_to_apicintpin[irq].ioapic != -1)
1080 if (irq >= APIC_INTMAPSIZE)
1081 return; /* No free interrupt handlers */
1083 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1084 intpin = io_apic_ints[intr].dst_apic_int;
1086 assign_apic_irq(apic, intpin, irq);
1087 io_apic_setup_intpin(apic, intpin);
1092 swap_apic_id(int apic, int oldid, int newid)
1099 return; /* Nothing to do */
1101 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1102 apic, oldid, newid);
1104 /* Swap physical APIC IDs in interrupt entries */
1105 for (x = 0; x < nintrs; x++) {
1106 if (io_apic_ints[x].dst_apic_id == oldid)
1107 io_apic_ints[x].dst_apic_id = newid;
1108 else if (io_apic_ints[x].dst_apic_id == newid)
1109 io_apic_ints[x].dst_apic_id = oldid;
1112 /* Swap physical APIC IDs in IO_TO_ID mappings */
1113 for (oapic = 0; oapic < mp_napics; oapic++)
1114 if (IO_TO_ID(oapic) == newid)
1117 if (oapic < mp_napics) {
1118 printf("Changing APIC ID for IO APIC #%d from "
1119 "%d to %d in MP table\n",
1120 oapic, newid, oldid);
1121 IO_TO_ID(oapic) = oldid;
1123 IO_TO_ID(apic) = newid;
1128 fix_id_to_io_mapping(void)
1132 for (x = 0; x < NAPICID; x++)
1135 for (x = 0; x <= mp_naps; x++)
1136 if (CPU_TO_ID(x) < NAPICID)
1137 ID_TO_IO(CPU_TO_ID(x)) = x;
1139 for (x = 0; x < mp_napics; x++)
1140 if (IO_TO_ID(x) < NAPICID)
1141 ID_TO_IO(IO_TO_ID(x)) = x;
1146 first_free_apic_id(void)
1150 for (freeid = 0; freeid < NAPICID; freeid++) {
1151 for (x = 0; x <= mp_naps; x++)
1152 if (CPU_TO_ID(x) == freeid)
1156 for (x = 0; x < mp_napics; x++)
1157 if (IO_TO_ID(x) == freeid)
1168 io_apic_id_acceptable(int apic, int id)
1170 int cpu; /* Logical CPU number */
1171 int oapic; /* Logical IO APIC number for other IO APIC */
1174 return 0; /* Out of range */
1176 for (cpu = 0; cpu <= mp_naps; cpu++)
1177 if (CPU_TO_ID(cpu) == id)
1178 return 0; /* Conflict with CPU */
1180 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1181 if (IO_TO_ID(oapic) == id)
1182 return 0; /* Conflict with other APIC */
1184 return 1; /* ID is acceptable for IO APIC */
1189 * parse an Intel MP specification table
1196 int bus_0 = 0; /* Stop GCC warning */
1197 int bus_pci = 0; /* Stop GCC warning */
1199 int apic; /* IO APIC unit number */
1200 int freeid; /* Free physical APIC ID */
1201 int physid; /* Current physical IO APIC ID */
1204 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1205 * did it wrong. The MP spec says that when more than 1 PCI bus
1206 * exists the BIOS must begin with bus entries for the PCI bus and use
1207 * actual PCI bus numbering. This implies that when only 1 PCI bus
1208 * exists the BIOS can choose to ignore this ordering, and indeed many
1209 * MP motherboards do ignore it. This causes a problem when the PCI
1210 * sub-system makes requests of the MP sub-system based on PCI bus
1211 * numbers. So here we look for the situation and renumber the
1212 * busses and associated INTs in an effort to "make it right".
1215 /* find bus 0, PCI bus, count the number of PCI busses */
1216 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1217 if (bus_data[x].bus_id == 0) {
1220 if (bus_data[x].bus_type == PCI) {
1226 * bus_0 == slot of bus with ID of 0
1227 * bus_pci == slot of last PCI bus encountered
1230 /* check the 1 PCI bus case for sanity */
1231 /* if it is number 0 all is well */
1232 if (num_pci_bus == 1 &&
1233 bus_data[bus_pci].bus_id != 0) {
1235 /* mis-numbered, swap with whichever bus uses slot 0 */
1237 /* swap the bus entry types */
1238 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1239 bus_data[bus_0].bus_type = PCI;
1241 /* swap each relavant INTerrupt entry */
1242 id = bus_data[bus_pci].bus_id;
1243 for (x = 0; x < nintrs; ++x) {
1244 if (io_apic_ints[x].src_bus_id == id) {
1245 io_apic_ints[x].src_bus_id = 0;
1247 else if (io_apic_ints[x].src_bus_id == 0) {
1248 io_apic_ints[x].src_bus_id = id;
1253 /* Assign IO APIC IDs.
1255 * First try the existing ID. If a conflict is detected, try
1256 * the ID in the MP table. If a conflict is still detected, find
1259 * We cannot use the ID_TO_IO table before all conflicts has been
1260 * resolved and the table has been corrected.
1262 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1264 /* First try to use the value set by the BIOS */
1265 physid = io_apic_get_id(apic);
1266 if (io_apic_id_acceptable(apic, physid)) {
1267 if (IO_TO_ID(apic) != physid)
1268 swap_apic_id(apic, IO_TO_ID(apic), physid);
1272 /* Then check if the value in the MP table is acceptable */
1273 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1276 /* Last resort, find a free APIC ID and use it */
1277 freeid = first_free_apic_id();
1278 if (freeid >= NAPICID)
1279 panic("No free physical APIC IDs found");
1281 if (io_apic_id_acceptable(apic, freeid)) {
1282 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1285 panic("Free physical APIC ID not usable");
1287 fix_id_to_io_mapping();
1289 /* detect and fix broken Compaq MP table */
1290 if (apic_int_type(0, 0) == -1) {
1291 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1292 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1293 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1294 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1295 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1296 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1302 /* Assign low level interrupt handlers */
1304 setup_apic_irq_mapping(void)
1310 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1311 int_to_apicintpin[x].ioapic = -1;
1312 int_to_apicintpin[x].int_pin = 0;
1313 int_to_apicintpin[x].apic_address = NULL;
1314 int_to_apicintpin[x].redirindex = 0;
1317 /* First assign ISA/EISA interrupts */
1318 for (x = 0; x < nintrs; x++) {
1319 int_vector = io_apic_ints[x].src_bus_irq;
1320 if (int_vector < APIC_INTMAPSIZE &&
1321 io_apic_ints[x].int_vector == 0xff &&
1322 int_to_apicintpin[int_vector].ioapic == -1 &&
1323 (apic_int_is_bus_type(x, ISA) ||
1324 apic_int_is_bus_type(x, EISA)) &&
1325 io_apic_ints[x].int_type == 0) {
1326 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1327 io_apic_ints[x].dst_apic_int,
1332 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1333 for (x = 0; x < nintrs; x++) {
1334 if (io_apic_ints[x].dst_apic_int == 0 &&
1335 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1336 io_apic_ints[x].int_vector == 0xff &&
1337 int_to_apicintpin[0].ioapic == -1 &&
1338 io_apic_ints[x].int_type == 3) {
1339 assign_apic_irq(0, 0, 0);
1343 /* PCI interrupt assignment is deferred */
1348 processor_entry(proc_entry_ptr entry, int cpu)
1350 /* check for usability */
1351 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1354 if(entry->apic_id >= NAPICID)
1355 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1356 /* check for BSP flag */
1357 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1358 boot_cpu_id = entry->apic_id;
1359 CPU_TO_ID(0) = entry->apic_id;
1360 ID_TO_CPU(entry->apic_id) = 0;
1361 return 0; /* its already been counted */
1364 /* add another AP to list, if less than max number of CPUs */
1365 else if (cpu < MAXCPU) {
1366 CPU_TO_ID(cpu) = entry->apic_id;
1367 ID_TO_CPU(entry->apic_id) = cpu;
1376 bus_entry(bus_entry_ptr entry, int bus)
1381 /* encode the name into an index */
1382 for (x = 0; x < 6; ++x) {
1383 if ((c = entry->bus_type[x]) == ' ')
1389 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1390 panic("unknown bus type: '%s'", name);
1392 bus_data[bus].bus_id = entry->bus_id;
1393 bus_data[bus].bus_type = x;
1400 io_apic_entry(io_apic_entry_ptr entry, int apic)
1402 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1405 IO_TO_ID(apic) = entry->apic_id;
1406 if (entry->apic_id < NAPICID)
1407 ID_TO_IO(entry->apic_id) = apic;
1414 lookup_bus_type(char *name)
1418 for (x = 0; x < MAX_BUSTYPE; ++x)
1419 if (strcmp(bus_type_table[x].name, name) == 0)
1420 return bus_type_table[x].type;
1422 return UNKNOWN_BUSTYPE;
1427 int_entry(int_entry_ptr entry, int intr)
1431 io_apic_ints[intr].int_type = entry->int_type;
1432 io_apic_ints[intr].int_flags = entry->int_flags;
1433 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1434 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1435 if (entry->dst_apic_id == 255) {
1436 /* This signal goes to all IO APICS. Select an IO APIC
1437 with sufficient number of interrupt pins */
1438 for (apic = 0; apic < mp_napics; apic++)
1439 if (((io_apic_read(apic, IOAPIC_VER) &
1440 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1441 entry->dst_apic_int)
1443 if (apic < mp_napics)
1444 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1446 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1448 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1449 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1456 apic_int_is_bus_type(int intr, int bus_type)
1460 for (bus = 0; bus < mp_nbusses; ++bus)
1461 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1462 && ((int) bus_data[bus].bus_type == bus_type))
1470 * Given a traditional ISA INT mask, return an APIC mask.
1473 isa_apic_mask(u_int isa_mask)
1478 #if defined(SKIP_IRQ15_REDIRECT)
1479 if (isa_mask == (1 << 15)) {
1480 printf("skipping ISA IRQ15 redirect\n");
1483 #endif /* SKIP_IRQ15_REDIRECT */
1485 isa_irq = ffs(isa_mask); /* find its bit position */
1486 if (isa_irq == 0) /* doesn't exist */
1488 --isa_irq; /* make it zero based */
1490 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1494 return (1 << apic_pin); /* convert pin# to a mask */
1499 * Determine which APIC pin an ISA/EISA INT is attached to.
1501 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1502 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1503 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1504 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1506 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1508 isa_apic_irq(int isa_irq)
1512 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1513 if (INTTYPE(intr) == 0) { /* standard INT */
1514 if (SRCBUSIRQ(intr) == isa_irq) {
1515 if (apic_int_is_bus_type(intr, ISA) ||
1516 apic_int_is_bus_type(intr, EISA)) {
1517 if (INTIRQ(intr) == 0xff)
1518 return -1; /* unassigned */
1519 return INTIRQ(intr); /* found */
1524 return -1; /* NOT found */
1529 * Determine which APIC pin a PCI INT is attached to.
1531 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1532 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1533 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1535 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1539 --pciInt; /* zero based */
1541 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1542 if ((INTTYPE(intr) == 0) /* standard INT */
1543 && (SRCBUSID(intr) == pciBus)
1544 && (SRCBUSDEVICE(intr) == pciDevice)
1545 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1546 if (apic_int_is_bus_type(intr, PCI)) {
1547 if (INTIRQ(intr) == 0xff)
1548 allocate_apic_irq(intr);
1549 if (INTIRQ(intr) == 0xff)
1550 return -1; /* unassigned */
1551 return INTIRQ(intr); /* exact match */
1554 return -1; /* NOT found */
1558 next_apic_irq(int irq)
1565 for (intr = 0; intr < nintrs; intr++) {
1566 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1568 bus = SRCBUSID(intr);
1569 bustype = apic_bus_type(bus);
1570 if (bustype != ISA &&
1576 if (intr >= nintrs) {
1579 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1580 if (INTTYPE(ointr) != 0)
1582 if (bus != SRCBUSID(ointr))
1584 if (bustype == PCI) {
1585 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1587 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1590 if (bustype == ISA || bustype == EISA) {
1591 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1594 if (INTPIN(intr) == INTPIN(ointr))
1598 if (ointr >= nintrs) {
1601 return INTIRQ(ointr);
1615 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1618 * Exactly what this means is unclear at this point. It is a solution
1619 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1620 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1621 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1625 undirect_isa_irq(int rirq)
1629 printf("Freeing redirected ISA irq %d.\n", rirq);
1630 /** FIXME: tickle the MB redirector chip */
1634 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1641 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1644 undirect_pci_irq(int rirq)
1648 printf("Freeing redirected PCI irq %d.\n", rirq);
1650 /** FIXME: tickle the MB redirector chip */
1654 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1662 * given a bus ID, return:
1663 * the bus type if found
1667 apic_bus_type(int id)
1671 for (x = 0; x < mp_nbusses; ++x)
1672 if (bus_data[x].bus_id == id)
1673 return bus_data[x].bus_type;
1680 * given a LOGICAL APIC# and pin#, return:
1681 * the associated src bus ID if found
1685 apic_src_bus_id(int apic, int pin)
1689 /* search each of the possible INTerrupt sources */
1690 for (x = 0; x < nintrs; ++x)
1691 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1692 (pin == io_apic_ints[x].dst_apic_int))
1693 return (io_apic_ints[x].src_bus_id);
1695 return -1; /* NOT found */
1700 * given a LOGICAL APIC# and pin#, return:
1701 * the associated src bus IRQ if found
1705 apic_src_bus_irq(int apic, int pin)
1709 for (x = 0; x < nintrs; x++)
1710 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1711 (pin == io_apic_ints[x].dst_apic_int))
1712 return (io_apic_ints[x].src_bus_irq);
1714 return -1; /* NOT found */
1719 * given a LOGICAL APIC# and pin#, return:
1720 * the associated INTerrupt type if found
1724 apic_int_type(int apic, int pin)
1728 /* search each of the possible INTerrupt sources */
1729 for (x = 0; x < nintrs; ++x)
1730 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1731 (pin == io_apic_ints[x].dst_apic_int))
1732 return (io_apic_ints[x].int_type);
1734 return -1; /* NOT found */
1738 apic_irq(int apic, int pin)
1743 for (x = 0; x < nintrs; ++x)
1744 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1745 (pin == io_apic_ints[x].dst_apic_int)) {
1746 res = io_apic_ints[x].int_vector;
1749 if (apic != int_to_apicintpin[res].ioapic)
1750 panic("apic_irq: inconsistent table");
1751 if (pin != int_to_apicintpin[res].int_pin)
1752 panic("apic_irq inconsistent table (2)");
1760 * given a LOGICAL APIC# and pin#, return:
1761 * the associated trigger mode if found
1765 apic_trigger(int apic, int pin)
1769 /* search each of the possible INTerrupt sources */
1770 for (x = 0; x < nintrs; ++x)
1771 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1772 (pin == io_apic_ints[x].dst_apic_int))
1773 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1775 return -1; /* NOT found */
1780 * given a LOGICAL APIC# and pin#, return:
1781 * the associated 'active' level if found
1785 apic_polarity(int apic, int pin)
1789 /* search each of the possible INTerrupt sources */
1790 for (x = 0; x < nintrs; ++x)
1791 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1792 (pin == io_apic_ints[x].dst_apic_int))
1793 return (io_apic_ints[x].int_flags & 0x03);
1795 return -1; /* NOT found */
1800 * set data according to MP defaults
1801 * FIXME: probably not complete yet...
1804 default_mp_table(int type)
1807 #if defined(APIC_IO)
1810 #endif /* APIC_IO */
1813 printf(" MP default config type: %d\n", type);
1816 printf(" bus: ISA, APIC: 82489DX\n");
1819 printf(" bus: EISA, APIC: 82489DX\n");
1822 printf(" bus: EISA, APIC: 82489DX\n");
1825 printf(" bus: MCA, APIC: 82489DX\n");
1828 printf(" bus: ISA+PCI, APIC: Integrated\n");
1831 printf(" bus: EISA+PCI, APIC: Integrated\n");
1834 printf(" bus: MCA+PCI, APIC: Integrated\n");
1837 printf(" future type\n");
1843 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1844 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1847 CPU_TO_ID(0) = boot_cpu_id;
1848 ID_TO_CPU(boot_cpu_id) = 0;
1850 /* one and only AP */
1851 CPU_TO_ID(1) = ap_cpu_id;
1852 ID_TO_CPU(ap_cpu_id) = 1;
1854 #if defined(APIC_IO)
1855 /* one and only IO APIC */
1856 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1859 * sanity check, refer to MP spec section 3.6.6, last paragraph
1860 * necessary as some hardware isn't properly setting up the IO APIC
1862 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1863 if (io_apic_id != 2) {
1865 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1866 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1867 io_apic_set_id(0, 2);
1870 IO_TO_ID(0) = io_apic_id;
1871 ID_TO_IO(io_apic_id) = 0;
1872 #endif /* APIC_IO */
1874 /* fill out bus entries */
1883 bus_data[0].bus_id = default_data[type - 1][1];
1884 bus_data[0].bus_type = default_data[type - 1][2];
1885 bus_data[1].bus_id = default_data[type - 1][3];
1886 bus_data[1].bus_type = default_data[type - 1][4];
1889 /* case 4: case 7: MCA NOT supported */
1890 default: /* illegal/reserved */
1891 panic("BAD default MP config: %d", type);
1895 #if defined(APIC_IO)
1896 /* general cases from MP v1.4, table 5-2 */
1897 for (pin = 0; pin < 16; ++pin) {
1898 io_apic_ints[pin].int_type = 0;
1899 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1900 io_apic_ints[pin].src_bus_id = 0;
1901 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1902 io_apic_ints[pin].dst_apic_id = io_apic_id;
1903 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1906 /* special cases from MP v1.4, table 5-2 */
1908 io_apic_ints[2].int_type = 0xff; /* N/C */
1909 io_apic_ints[13].int_type = 0xff; /* N/C */
1910 #if !defined(APIC_MIXED_MODE)
1912 panic("sorry, can't support type 2 default yet");
1913 #endif /* APIC_MIXED_MODE */
1916 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1919 io_apic_ints[0].int_type = 0xff; /* N/C */
1921 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1922 #endif /* APIC_IO */
1927 * start each AP in our list
1930 start_all_aps(u_int boot_addr)
1933 u_char mpbiosreason;
1934 u_long mpbioswarmvec;
1935 struct globaldata *gd;
1939 POSTCODE(START_ALL_APS_POST);
1941 /* initialize BSP's local APIC */
1945 /* install the AP 1st level boot code */
1946 install_ap_tramp(boot_addr);
1949 /* save the current value of the warm-start vector */
1950 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1952 outb(CMOS_REG, BIOS_RESET);
1953 mpbiosreason = inb(CMOS_DATA);
1956 /* record BSP in CPU map */
1959 /* set up temporary P==V mapping for AP boot */
1960 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1961 kptbase = (uintptr_t)(void *)KPTphys;
1962 for (x = 0; x < NKPT; x++)
1963 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1964 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1968 for (x = 1; x <= mp_naps; ++x) {
1970 /* This is a bit verbose, it will go away soon. */
1972 /* first page of AP's private space */
1973 pg = x * i386_btop(sizeof(struct privatespace));
1975 /* allocate a new private data page */
1976 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1978 /* wire it into the private page table page */
1979 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1981 /* allocate and set up an idle stack data page */
1982 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1983 for (i = 0; i < UPAGES; i++)
1984 SMPpt[pg + 1 + i] = (pt_entry_t)
1985 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1987 /* prime data page for it to use */
1988 SLIST_INSERT_HEAD(&cpuhead, gd, gd_allcpu);
1991 /* setup a vector to our boot code */
1992 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1993 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1995 outb(CMOS_REG, BIOS_RESET);
1996 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1999 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
2002 /* attempt to start the Application Processor */
2003 CHECK_INIT(99); /* setup checkpoints */
2004 if (!start_ap(x, boot_addr)) {
2005 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2006 CHECK_PRINT("trace"); /* show checkpoints */
2007 /* better panic as the AP may be running loose */
2008 printf("panic y/n? [y] ");
2009 if (cngetc() != 'n')
2012 CHECK_PRINT("trace"); /* show checkpoints */
2014 /* record its version info */
2015 cpu_apic_versions[x] = cpu_apic_versions[0];
2017 all_cpus |= (1 << x); /* record AP in CPU map */
2020 /* build our map of 'other' CPUs */
2021 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2023 /* fill in our (BSP) APIC version */
2024 cpu_apic_versions[0] = lapic.version;
2026 /* restore the warmstart vector */
2027 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2029 outb(CMOS_REG, BIOS_RESET);
2030 outb(CMOS_DATA, mpbiosreason);
2034 * Set up the idle context for the BSP. Similar to above except
2035 * that some was done by locore, some by pmap.c and some is implicit
2036 * because the BSP is cpu#0 and the page is initially zero, and also
2037 * because we can refer to variables by name on the BSP..
2040 /* Allocate and setup BSP idle stack */
2041 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2042 for (i = 0; i < UPAGES; i++)
2043 SMPpt[1 + i] = (pt_entry_t)
2044 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2046 for (x = 0; x < NKPT; x++)
2050 /* number of APs actually started */
2051 return mp_ncpus - 1;
2056 * load the 1st level AP boot code into base memory.
2059 /* targets for relocation */
2060 extern void bigJump(void);
2061 extern void bootCodeSeg(void);
2062 extern void bootDataSeg(void);
2063 extern void MPentry(void);
2064 extern u_int MP_GDT;
2065 extern u_int mp_gdtbase;
2068 install_ap_tramp(u_int boot_addr)
2071 int size = *(int *) ((u_long) & bootMP_size);
2072 u_char *src = (u_char *) ((u_long) bootMP);
2073 u_char *dst = (u_char *) boot_addr + KERNBASE;
2074 u_int boot_base = (u_int) bootMP;
2079 POSTCODE(INSTALL_AP_TRAMP_POST);
2081 for (x = 0; x < size; ++x)
2085 * modify addresses in code we just moved to basemem. unfortunately we
2086 * need fairly detailed info about mpboot.s for this to work. changes
2087 * to mpboot.s might require changes here.
2090 /* boot code is located in KERNEL space */
2091 dst = (u_char *) boot_addr + KERNBASE;
2093 /* modify the lgdt arg */
2094 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2095 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2097 /* modify the ljmp target for MPentry() */
2098 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2099 *dst32 = ((u_int) MPentry - KERNBASE);
2101 /* modify the target for boot code segment */
2102 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2103 dst8 = (u_int8_t *) (dst16 + 1);
2104 *dst16 = (u_int) boot_addr & 0xffff;
2105 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2107 /* modify the target for boot data segment */
2108 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2109 dst8 = (u_int8_t *) (dst16 + 1);
2110 *dst16 = (u_int) boot_addr & 0xffff;
2111 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2116 * this function starts the AP (application processor) identified
2117 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2118 * to accomplish this. This is necessary because of the nuances
2119 * of the different hardware we might encounter. It ain't pretty,
2120 * but it seems to work.
2123 start_ap(int logical_cpu, u_int boot_addr)
2128 u_long icr_lo, icr_hi;
2130 POSTCODE(START_AP_POST);
2132 /* get the PHYSICAL APIC ID# */
2133 physical_cpu = CPU_TO_ID(logical_cpu);
2135 /* calculate the vector */
2136 vector = (boot_addr >> 12) & 0xff;
2138 /* used as a watchpoint to signal AP startup */
2142 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2143 * and running the target CPU. OR this INIT IPI might be latched (P5
2144 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2148 /* setup the address for the target AP */
2149 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2150 icr_hi |= (physical_cpu << 24);
2151 lapic.icr_hi = icr_hi;
2153 /* do an INIT IPI: assert RESET */
2154 icr_lo = lapic.icr_lo & 0xfff00000;
2155 lapic.icr_lo = icr_lo | 0x0000c500;
2157 /* wait for pending status end */
2158 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2161 /* do an INIT IPI: deassert RESET */
2162 lapic.icr_lo = icr_lo | 0x00008500;
2164 /* wait for pending status end */
2165 u_sleep(10000); /* wait ~10mS */
2166 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2170 * next we do a STARTUP IPI: the previous INIT IPI might still be
2171 * latched, (P5 bug) this 1st STARTUP would then terminate
2172 * immediately, and the previously started INIT IPI would continue. OR
2173 * the previous INIT IPI has already run. and this STARTUP IPI will
2174 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2178 /* do a STARTUP IPI */
2179 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2180 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2182 u_sleep(200); /* wait ~200uS */
2185 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2186 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2187 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2188 * recognized after hardware RESET or INIT IPI.
2191 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2192 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2194 u_sleep(200); /* wait ~200uS */
2196 /* wait for it to start */
2197 set_apic_timer(5000000);/* == 5 seconds */
2198 while (read_apic_timer())
2199 if (mp_ncpus > cpus)
2200 return 1; /* return SUCCESS */
2202 return 0; /* return FAILURE */
2206 * Flush the TLB on all other CPU's
2208 * XXX: Needs to handshake and wait for completion before proceding.
2213 #if defined(APIC_IO)
2214 if (smp_started && invltlb_ok)
2215 ipi_all_but_self(IPI_INVLTLB);
2216 #endif /* APIC_IO */
2222 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2224 /* send a message to the other CPUs */
2234 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2237 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2239 /* send a message to the other CPUs */
2245 * This is called once the rest of the system is up and running and we're
2246 * ready to let the AP's out of the pen.
2253 /* spin until all the AP's are ready */
2258 * Set curproc to our per-cpu idleproc so that mutexes have
2259 * something unique to lock with.
2261 PCPU_SET(curproc, PCPU_GET(idleproc));
2262 PCPU_SET(spinlocks, NULL);
2264 /* lock against other AP's that are waking up */
2265 mtx_lock_spin(&ap_boot_mtx);
2267 /* BSP may have changed PTD while we're waiting for the lock */
2272 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2276 /* Build our map of 'other' CPUs. */
2277 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2279 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2281 /* set up CPU registers and state */
2284 /* set up FPU state on the AP */
2285 npxinit(__INITIAL_NPXCW__);
2287 /* A quick check from sanity claus */
2288 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2289 if (PCPU_GET(cpuid) != apic_id) {
2290 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2291 printf("SMP: apic_id = %d\n", apic_id);
2292 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2293 panic("cpuid mismatch! boom!!");
2296 /* Init local apic for irq's */
2299 /* Set memory range attributes for this CPU to match the BSP */
2300 mem_range_AP_init();
2303 * Activate smp_invltlb, although strictly speaking, this isn't
2304 * quite correct yet. We should have a bitfield for cpus willing
2305 * to accept TLB flush IPI's or something and sync them.
2307 if (smp_cpus == mp_ncpus) {
2309 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2310 smp_active = 1; /* historic */
2313 /* let other AP's wake up now */
2314 mtx_unlock_spin(&ap_boot_mtx);
2316 /* wait until all the AP's are up */
2317 while (smp_started == 0)
2320 microuptime(PCPU_PTR(switchtime));
2321 PCPU_SET(switchticks, ticks);
2323 /* ok, now grab sched_lock and enter the scheduler */
2325 mtx_lock_spin(&sched_lock);
2326 cpu_throw(); /* doesn't return */
2328 panic("scheduler returned us to ap_init");
2331 #define CHECKSTATE_USER 0
2332 #define CHECKSTATE_SYS 1
2333 #define CHECKSTATE_INTR 2
2335 /* Do not staticize. Used from apic_vector.s */
2336 struct proc* checkstate_curproc[MAXCPU];
2337 int checkstate_cpustate[MAXCPU];
2338 u_long checkstate_pc[MAXCPU];
2340 #define PC_TO_INDEX(pc, prof) \
2341 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2342 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2345 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2351 pc = checkstate_pc[id];
2352 prof = &p->p_stats->p_prof;
2353 if (pc >= prof->pr_off &&
2354 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2355 mtx_assert(&sched_lock, MA_OWNED);
2356 if ((p->p_sflag & PS_OWEUPC) == 0) {
2359 p->p_sflag |= PS_OWEUPC;
2361 *astmap |= (1 << id);
2366 forwarded_statclock(int id, int pscnt, int *astmap)
2368 struct pstats *pstats;
2375 register struct gmonparam *g;
2379 mtx_assert(&sched_lock, MA_OWNED);
2380 p = checkstate_curproc[id];
2381 cpustate = checkstate_cpustate[id];
2385 cpustate = CHECKSTATE_INTR;
2386 else if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2387 cpustate = CHECKSTATE_SYS;
2390 case CHECKSTATE_USER:
2391 if (p->p_sflag & PS_PROFIL)
2392 addupc_intr_forwarded(p, id, astmap);
2396 if (p->p_nice > NZERO)
2401 case CHECKSTATE_SYS:
2404 * Kernel statistics are just like addupc_intr, only easier.
2407 if (g->state == GMON_PROF_ON) {
2408 i = checkstate_pc[id] - g->lowpc;
2409 if (i < g->textsize) {
2410 i /= HISTFRACTION * sizeof(*g->kcount);
2419 if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2424 case CHECKSTATE_INTR:
2428 * Kernel statistics are just like addupc_intr, only easier.
2431 if (g->state == GMON_PROF_ON) {
2432 i = checkstate_pc[id] - g->lowpc;
2433 if (i < g->textsize) {
2434 i /= HISTFRACTION * sizeof(*g->kcount);
2441 KASSERT(p != NULL, ("NULL process in interrupt state"));
2448 /* Update resource usage integrals and maximums. */
2449 if ((pstats = p->p_stats) != NULL &&
2450 (ru = &pstats->p_ru) != NULL &&
2451 (vm = p->p_vmspace) != NULL) {
2452 ru->ru_ixrss += pgtok(vm->vm_tsize);
2453 ru->ru_idrss += pgtok(vm->vm_dsize);
2454 ru->ru_isrss += pgtok(vm->vm_ssize);
2455 rss = pgtok(vmspace_resident_count(vm));
2456 if (ru->ru_maxrss < rss)
2457 ru->ru_maxrss = rss;
2462 forward_statclock(int pscnt)
2468 /* Kludge. We don't yet have separate locks for the interrupts
2469 * and the kernel. This means that we cannot let the other processors
2470 * handle complex interrupts while inhibiting them from entering
2471 * the kernel in a non-interrupt context.
2473 * What we can do, without changing the locking mechanisms yet,
2474 * is letting the other processors handle a very simple interrupt
2475 * (wich determines the processor states), and do the main
2479 CTR1(KTR_SMP, "forward_statclock(%d)", pscnt);
2481 if (!smp_started || !invltlb_ok || cold || panicstr)
2484 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2486 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2487 checkstate_probed_cpus = 0;
2489 ipi_selected(map, IPI_CHECKSTATE);
2492 while (checkstate_probed_cpus != map) {
2497 printf("forward_statclock: checkstate %x\n",
2498 checkstate_probed_cpus);
2505 * Step 2: walk through other processors processes, update ticks and
2510 for (id = 0; id < mp_ncpus; id++) {
2511 if (id == PCPU_GET(cpuid))
2513 if (((1 << id) & checkstate_probed_cpus) == 0)
2515 forwarded_statclock(id, pscnt, &map);
2518 checkstate_need_ast |= map;
2519 ipi_selected(map, IPI_AST);
2521 while ((checkstate_need_ast & map) != 0) {
2526 printf("forward_statclock: dropped ast 0x%x\n",
2527 checkstate_need_ast & map);
2536 forward_hardclock(int pscnt)
2541 struct pstats *pstats;
2544 /* Kludge. We don't yet have separate locks for the interrupts
2545 * and the kernel. This means that we cannot let the other processors
2546 * handle complex interrupts while inhibiting them from entering
2547 * the kernel in a non-interrupt context.
2549 * What we can do, without changing the locking mechanisms yet,
2550 * is letting the other processors handle a very simple interrupt
2551 * (wich determines the processor states), and do the main
2555 CTR1(KTR_SMP, "forward_hardclock(%d)", pscnt);
2557 if (!smp_started || !invltlb_ok || cold || panicstr)
2560 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2562 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2563 checkstate_probed_cpus = 0;
2565 ipi_selected(map, IPI_CHECKSTATE);
2568 while (checkstate_probed_cpus != map) {
2573 printf("forward_hardclock: checkstate %x\n",
2574 checkstate_probed_cpus);
2581 * Step 2: walk through other processors processes, update virtual
2582 * timer and profiling timer. If stathz == 0, also update ticks and
2587 for (id = 0; id < mp_ncpus; id++) {
2588 if (id == PCPU_GET(cpuid))
2590 if (((1 << id) & checkstate_probed_cpus) == 0)
2592 p = checkstate_curproc[id];
2594 pstats = p->p_stats;
2595 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2596 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2597 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2598 p->p_sflag |= PS_ALRMPEND;
2601 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2602 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2603 p->p_sflag |= PS_PROFPEND;
2608 forwarded_statclock( id, pscnt, &map);
2612 checkstate_need_ast |= map;
2613 ipi_selected(map, IPI_AST);
2615 while ((checkstate_need_ast & map) != 0) {
2620 printf("forward_hardclock: dropped ast 0x%x\n",
2621 checkstate_need_ast & map);
2630 forward_signal(struct proc *p)
2636 /* Kludge. We don't yet have separate locks for the interrupts
2637 * and the kernel. This means that we cannot let the other processors
2638 * handle complex interrupts while inhibiting them from entering
2639 * the kernel in a non-interrupt context.
2641 * What we can do, without changing the locking mechanisms yet,
2642 * is letting the other processors handle a very simple interrupt
2643 * (wich determines the processor states), and do the main
2647 CTR1(KTR_SMP, "forward_signal(%p)", p);
2649 if (!smp_started || !invltlb_ok || cold || panicstr)
2651 if (!forward_signal_enabled)
2653 mtx_lock_spin(&sched_lock);
2655 if (p->p_stat != SRUN) {
2656 mtx_unlock_spin(&sched_lock);
2660 mtx_unlock_spin(&sched_lock);
2664 checkstate_need_ast |= map;
2665 ipi_selected(map, IPI_AST);
2667 while ((checkstate_need_ast & map) != 0) {
2672 printf("forward_signal: dropped ast 0x%x\n",
2673 checkstate_need_ast & map);
2678 mtx_lock_spin(&sched_lock);
2679 if (id == p->p_oncpu) {
2680 mtx_unlock_spin(&sched_lock);
2687 forward_roundrobin(void)
2692 CTR0(KTR_SMP, "forward_roundrobin()");
2694 if (!smp_started || !invltlb_ok || cold || panicstr)
2696 if (!forward_roundrobin_enabled)
2698 resched_cpus |= PCPU_GET(other_cpus);
2699 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2701 ipi_selected(map, IPI_AST);
2703 ipi_all_but_self(IPI_AST);
2706 while ((checkstate_need_ast & map) != 0) {
2711 printf("forward_roundrobin: dropped ast 0x%x\n",
2712 checkstate_need_ast & map);
2720 * When called the executing CPU will send an IPI to all other CPUs
2721 * requesting that they halt execution.
2723 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2725 * - Signals all CPUs in map to stop.
2726 * - Waits for each to stop.
2733 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2734 * from executing at same time.
2737 stop_cpus(u_int map)
2744 /* send the Xcpustop IPI to all CPUs in map */
2745 ipi_selected(map, IPI_STOP);
2747 while (count++ < 100000 && (stopped_cpus & map) != map)
2751 if ((stopped_cpus & map) != map)
2752 printf("Warning: CPUs 0x%x did not stop!\n",
2753 (~(stopped_cpus & map)) & map);
2761 * Called by a CPU to restart stopped CPUs.
2763 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2765 * - Signals all CPUs in map to restart.
2766 * - Waits for each to restart.
2774 restart_cpus(u_int map)
2781 started_cpus = map; /* signal other cpus to restart */
2783 /* wait for each to clear its bit */
2784 while (count++ < 100000 && (stopped_cpus & map) != 0)
2788 if ((stopped_cpus & map) != 0)
2789 printf("Warning: CPUs 0x%x did not restart!\n",
2790 (~(stopped_cpus & map)) & map);
2797 #ifdef APIC_INTR_REORDER
2799 * Maintain mapping from softintr vector to isr bit in local apic.
2802 set_lapic_isrloc(int intr, int vector)
2804 if (intr < 0 || intr > 32)
2805 panic("set_apic_isrloc: bad intr argument: %d",intr);
2806 if (vector < ICU_OFFSET || vector > 255)
2807 panic("set_apic_isrloc: bad vector argument: %d",vector);
2808 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2809 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2814 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2815 * (if specified), rendezvous, execute the action function (if specified),
2816 * rendezvous again, execute the teardown function (if specified), and then
2819 * Note that the supplied external functions _must_ be reentrant and aware
2820 * that they are running in parallel and in an unknown lock context.
2822 static void (*smp_rv_setup_func)(void *arg);
2823 static void (*smp_rv_action_func)(void *arg);
2824 static void (*smp_rv_teardown_func)(void *arg);
2825 static void *smp_rv_func_arg;
2826 static volatile int smp_rv_waiters[2];
2829 smp_rendezvous_action(void)
2831 /* setup function */
2832 if (smp_rv_setup_func != NULL)
2833 smp_rv_setup_func(smp_rv_func_arg);
2834 /* spin on entry rendezvous */
2835 atomic_add_int(&smp_rv_waiters[0], 1);
2836 while (smp_rv_waiters[0] < mp_ncpus)
2838 /* action function */
2839 if (smp_rv_action_func != NULL)
2840 smp_rv_action_func(smp_rv_func_arg);
2841 /* spin on exit rendezvous */
2842 atomic_add_int(&smp_rv_waiters[1], 1);
2843 while (smp_rv_waiters[1] < mp_ncpus)
2845 /* teardown function */
2846 if (smp_rv_teardown_func != NULL)
2847 smp_rv_teardown_func(smp_rv_func_arg);
2851 smp_rendezvous(void (* setup_func)(void *),
2852 void (* action_func)(void *),
2853 void (* teardown_func)(void *),
2857 /* obtain rendezvous lock */
2858 mtx_lock_spin(&smp_rv_mtx);
2860 /* set static function pointers */
2861 smp_rv_setup_func = setup_func;
2862 smp_rv_action_func = action_func;
2863 smp_rv_teardown_func = teardown_func;
2864 smp_rv_func_arg = arg;
2865 smp_rv_waiters[0] = 0;
2866 smp_rv_waiters[1] = 0;
2869 * signal other processors, which will enter the IPI with interrupts off
2871 ipi_all_but_self(IPI_RENDEZVOUS);
2873 /* call executor function */
2874 smp_rendezvous_action();
2877 mtx_unlock_spin(&smp_rv_mtx);
2881 * send an IPI to a set of cpus.
2884 ipi_selected(u_int32_t cpus, u_int ipi)
2887 CTR2(KTR_SMP, __func__ ": cpus: %x ipi: %x", cpus, ipi);
2888 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED);
2892 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
2898 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi);
2899 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED);
2903 * send an IPI to all CPUs EXCEPT myself
2906 ipi_all_but_self(u_int ipi)
2909 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi);
2910 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED);
2914 * send an IPI to myself
2920 CTR1(KTR_SMP, __func__ ": ipi: %x", ipi);
2921 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED);
2925 release_aps(void *dummy __unused)
2927 atomic_store_rel_int(&aps_ready, 1);
2930 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);