2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include "opt_user_ldt.h"
32 #include <machine/smptests.h>
37 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
45 #include <sys/mutex.h>
47 #include <sys/dkstat.h>
49 #include <sys/cons.h> /* cngetc() */
52 #include <vm/vm_param.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_extern.h>
58 #include <vm/vm_map.h>
65 #include <machine/smp.h>
66 #include <machine/apic.h>
67 #include <machine/atomic.h>
68 #include <machine/cpufunc.h>
69 #include <machine/mpapic.h>
70 #include <machine/psl.h>
71 #include <machine/segments.h>
72 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
73 #include <machine/tss.h>
74 #include <machine/specialreg.h>
75 #include <machine/globaldata.h>
78 #include <machine/md_var.h> /* setidt() */
79 #include <i386/isa/icu.h> /* IPIs */
80 #include <i386/isa/intr_machdep.h> /* IPIs */
83 #if defined(TEST_DEFAULT_CONFIG)
84 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
86 #define MPFPS_MPFB1 mpfps->mpfb1
87 #endif /* TEST_DEFAULT_CONFIG */
89 #define WARMBOOT_TARGET 0
90 #define WARMBOOT_OFF (KERNBASE + 0x0467)
91 #define WARMBOOT_SEG (KERNBASE + 0x0469)
94 #define BIOS_BASE (0xe8000)
95 #define BIOS_SIZE (0x18000)
97 #define BIOS_BASE (0xf0000)
98 #define BIOS_SIZE (0x10000)
100 #define BIOS_COUNT (BIOS_SIZE/4)
102 #define CMOS_REG (0x70)
103 #define CMOS_DATA (0x71)
104 #define BIOS_RESET (0x0f)
105 #define BIOS_WARM (0x0a)
107 #define PROCENTRY_FLAG_EN 0x01
108 #define PROCENTRY_FLAG_BP 0x02
109 #define IOAPICENTRY_FLAG_EN 0x01
112 /* MP Floating Pointer Structure */
113 typedef struct MPFPS {
126 /* MP Configuration Table Header */
127 typedef struct MPCTH {
129 u_short base_table_length;
133 u_char product_id[12];
134 void *oem_table_pointer;
135 u_short oem_table_size;
138 u_short extended_table_length;
139 u_char extended_table_checksum;
144 typedef struct PROCENTRY {
149 u_long cpu_signature;
150 u_long feature_flags;
155 typedef struct BUSENTRY {
161 typedef struct IOAPICENTRY {
167 } *io_apic_entry_ptr;
169 typedef struct INTENTRY {
179 /* descriptions of MP basetable entries */
180 typedef struct BASETABLE_ENTRY {
187 * this code MUST be enabled here and in mpboot.s.
188 * it follows the very early stages of AP boot by placing values in CMOS ram.
189 * it NORMALLY will never be needed and thus the primitive method for enabling.
194 #if defined(CHECK_POINTS) && !defined(PC98)
195 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
196 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
198 #define CHECK_INIT(D); \
199 CHECK_WRITE(0x34, (D)); \
200 CHECK_WRITE(0x35, (D)); \
201 CHECK_WRITE(0x36, (D)); \
202 CHECK_WRITE(0x37, (D)); \
203 CHECK_WRITE(0x38, (D)); \
204 CHECK_WRITE(0x39, (D));
206 #define CHECK_PRINT(S); \
207 printf("%s: %d, %d, %d, %d, %d, %d\n", \
216 #else /* CHECK_POINTS */
218 #define CHECK_INIT(D)
219 #define CHECK_PRINT(S)
221 #endif /* CHECK_POINTS */
224 * Values to send to the POST hardware.
226 #define MP_BOOTADDRESS_POST 0x10
227 #define MP_PROBE_POST 0x11
228 #define MPTABLE_PASS1_POST 0x12
230 #define MP_START_POST 0x13
231 #define MP_ENABLE_POST 0x14
232 #define MPTABLE_PASS2_POST 0x15
234 #define START_ALL_APS_POST 0x16
235 #define INSTALL_AP_TRAMP_POST 0x17
236 #define START_AP_POST 0x18
238 #define MP_ANNOUNCE_POST 0x19
240 /* used to hold the AP's until we are ready to release them */
241 struct mtx ap_boot_mtx;
243 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
244 int current_postcode;
246 /** XXX FIXME: what system files declare these??? */
247 extern struct region_descriptor r_gdt, r_idt;
249 int bsp_apic_ready = 0; /* flags useability of BSP apic */
250 int mp_ncpus; /* # of CPUs, including BSP */
251 int mp_naps; /* # of Applications processors */
252 int mp_nbusses; /* # of busses */
253 int mp_napics; /* # of IO APICs */
254 int boot_cpu_id; /* designated BSP */
255 vm_offset_t cpu_apic_address;
256 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
259 u_int32_t cpu_apic_versions[MAXCPU];
260 u_int32_t *io_apic_versions;
262 #ifdef APIC_INTR_REORDER
264 volatile int *location;
266 } apic_isrbit_location[32];
269 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
272 * APIC ID logical/physical mapping structures.
273 * We oversize these to simplify boot-time config.
275 int cpu_num_to_apic_id[NAPICID];
276 int io_num_to_apic_id[NAPICID];
277 int apic_id_to_logical[NAPICID];
280 /* Bitmap of all available CPUs */
283 /* AP uses this during bootstrap. Do not staticize. */
287 /* Hotwire a 0->4MB V==P mapping */
288 extern pt_entry_t *KPTphys;
290 /* SMP page table page */
291 extern pt_entry_t *SMPpt;
293 struct pcb stoppcbs[MAXCPU];
295 int smp_started; /* has the system started? */
296 int smp_active = 0; /* are the APs allowed to run? */
297 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
299 /* XXX maybe should be hw.ncpu */
300 static int smp_cpus = 1; /* how many cpu's running */
301 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
303 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
304 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
306 /* Enable forwarding of a signal to a process running on a different CPU */
307 static int forward_signal_enabled = 1;
308 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
309 &forward_signal_enabled, 0, "");
311 /* Enable forwarding of roundrobin to all other cpus */
312 static int forward_roundrobin_enabled = 1;
313 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
314 &forward_roundrobin_enabled, 0, "");
318 * Local data and functions.
321 /* Set to 1 once we're ready to let the APs out of the pen. */
322 static volatile int aps_ready = 0;
324 static int mp_capable;
325 static u_int boot_address;
326 static u_int base_memory;
328 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
329 static mpfps_t mpfps;
330 static int search_for_sig(u_int32_t target, int count);
331 static void mp_enable(u_int boot_addr);
333 static void mptable_pass1(void);
334 static int mptable_pass2(void);
335 static void default_mp_table(int type);
336 static void fix_mp_table(void);
337 static void setup_apic_irq_mapping(void);
338 static void init_locks(void);
339 static int start_all_aps(u_int boot_addr);
340 static void install_ap_tramp(u_int boot_addr);
341 static int start_ap(int logicalCpu, u_int boot_addr);
343 static int apic_int_is_bus_type(int intr, int bus_type);
344 static void release_aps(void *dummy);
347 * initialize all the SMP locks
350 /* critical region around IO APIC, apic_imen */
353 /* lock region used by kernel profiling */
354 struct mtx mcount_mtx;
357 /* locks com (tty) data/hardware accesses: a FASTINTR() */
359 #endif /* USE_COMLOCK */
361 /* lock around the MP rendezvous */
362 static struct mtx smp_rv_mtx;
364 /* only 1 CPU can panic at a time :) */
365 struct mtx panic_mtx;
371 * XXX The mcount mutex probably needs to be statically initialized,
372 * since it will be used even in the function calls that get us to this
375 mtx_init(&mcount_mtx, "mcount", MTX_DEF);
377 mtx_init(&smp_rv_mtx, "smp rendezvous", MTX_SPIN);
378 mtx_init(&panic_mtx, "panic", MTX_DEF);
381 mtx_init(&com_mtx, "com", MTX_SPIN);
382 #endif /* USE_COMLOCK */
384 mtx_init(&ap_boot_mtx, "ap boot", MTX_SPIN);
388 * Calculate usable address in base memory for AP trampoline code.
391 mp_bootaddress(u_int basemem)
393 POSTCODE(MP_BOOTADDRESS_POST);
395 base_memory = basemem * 1024; /* convert to bytes */
397 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
398 if ((base_memory - boot_address) < bootMP_size)
399 boot_address -= 4096; /* not enough, lower by 4k */
406 * Look for an Intel MP spec table (ie, SMP capable hardware).
415 POSTCODE(MP_PROBE_POST);
417 /* see if EBDA exists */
418 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
419 /* search first 1K of EBDA */
420 target = (u_int32_t) (segment << 4);
421 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
424 /* last 1K of base memory, effective 'top of base' passed in */
425 target = (u_int32_t) (base_memory - 0x400);
426 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
430 /* search the BIOS */
431 target = (u_int32_t) BIOS_BASE;
432 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
441 /* calculate needed resources */
445 /* flag fact that we are running multiple processors */
452 * Initialize the SMP hardware and the APIC and start up the AP's.
457 POSTCODE(MP_START_POST);
459 /* look for MP capable motherboard */
461 mp_enable(boot_address);
463 panic("MP hardware not found!");
468 * Print various information about the SMP system hardware and setup.
475 POSTCODE(MP_ANNOUNCE_POST);
477 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
478 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
479 printf(", version: 0x%08x", cpu_apic_versions[0]);
480 printf(", at 0x%08x\n", cpu_apic_address);
481 for (x = 1; x <= mp_naps; ++x) {
482 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
483 printf(", version: 0x%08x", cpu_apic_versions[x]);
484 printf(", at 0x%08x\n", cpu_apic_address);
488 for (x = 0; x < mp_napics; ++x) {
489 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
490 printf(", version: 0x%08x", io_apic_versions[x]);
491 printf(", at 0x%08x\n", io_apic_address[x]);
494 printf(" Warning: APIC I/O disabled\n");
499 * AP cpu's call this to sync up protected mode.
505 int x, myid = bootAP;
507 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
508 gdt_segs[GPROC0_SEL].ssd_base =
509 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
510 SMP_prvspace[myid].globaldata.gd_prvspace =
511 &SMP_prvspace[myid].globaldata;
513 for (x = 0; x < NGDT; x++) {
514 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
517 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
518 r_gdt.rd_base = (int) &gdt[myid * NGDT];
519 lgdt(&r_gdt); /* does magic intra-segment return */
525 PCPU_SET(currentldt, _default_ldt);
528 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
529 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
530 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
531 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
532 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
533 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
534 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
543 * Final configuration of the BSP's local APIC:
544 * - disable 'pic mode'.
545 * - disable 'virtual wire mode'.
549 bsp_apic_configure(void)
554 /* leave 'pic mode' if necessary */
556 outb(0x22, 0x70); /* select IMCR */
557 byte = inb(0x23); /* current contents */
558 byte |= 0x01; /* mask external INTR */
559 outb(0x23, byte); /* disconnect 8259s/NMI */
562 /* mask lint0 (the 8259 'virtual wire' connection) */
563 temp = lapic.lvt_lint0;
564 temp |= APIC_LVT_M; /* set the mask */
565 lapic.lvt_lint0 = temp;
567 /* setup lint1 to handle NMI */
568 temp = lapic.lvt_lint1;
569 temp &= ~APIC_LVT_M; /* clear the mask */
570 lapic.lvt_lint1 = temp;
573 apic_dump("bsp_apic_configure()");
578 /*******************************************************************
579 * local functions and data
583 * start the SMP system
586 mp_enable(u_int boot_addr)
594 POSTCODE(MP_ENABLE_POST);
596 /* turn on 4MB of V == P addressing so we can get to MP table */
597 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
600 /* examine the MP table for needed info, uses physical addresses */
606 /* can't process default configs till the CPU APIC is pmapped */
610 /* post scan cleanup */
612 setup_apic_irq_mapping();
616 /* fill the LOGICAL io_apic_versions table */
617 for (apic = 0; apic < mp_napics; ++apic) {
618 ux = io_apic_read(apic, IOAPIC_VER);
619 io_apic_versions[apic] = ux;
620 io_apic_set_id(apic, IO_TO_ID(apic));
623 /* program each IO APIC in the system */
624 for (apic = 0; apic < mp_napics; ++apic)
625 if (io_apic_setup(apic) < 0)
626 panic("IO APIC setup failure");
628 /* install a 'Spurious INTerrupt' vector */
629 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
630 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
632 /* install an inter-CPU IPI for TLB invalidation */
633 setidt(XINVLTLB_OFFSET, Xinvltlb,
634 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
637 /* install an inter-CPU IPI for reading processor state */
638 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
639 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
642 /* install an inter-CPU IPI for all-CPU rendezvous */
643 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
644 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
646 /* install an inter-CPU IPI for forcing an additional software trap */
647 setidt(XCPUAST_OFFSET, Xcpuast,
648 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
650 /* install an inter-CPU IPI for CPU stop/restart */
651 setidt(XCPUSTOP_OFFSET, Xcpustop,
652 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
654 #if defined(TEST_TEST1)
655 /* install a "fake hardware INTerrupt" vector */
656 setidt(XTEST1_OFFSET, Xtest1,
657 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
658 #endif /** TEST_TEST1 */
662 /* initialize all SMP locks */
665 /* start each Application Processor */
666 start_all_aps(boot_addr);
671 * look for the MP spec signature
674 /* string defined by the Intel MP Spec as identifying the MP table */
675 #define MP_SIG 0x5f504d5f /* _MP_ */
676 #define NEXT(X) ((X) += 4)
678 search_for_sig(u_int32_t target, int count)
681 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
683 for (x = 0; x < count; NEXT(x))
684 if (addr[x] == MP_SIG)
685 /* make array index a byte index */
686 return (target + (x * sizeof(u_int32_t)));
692 static basetable_entry basetable_entry_types[] =
694 {0, 20, "Processor"},
701 typedef struct BUSDATA {
703 enum busTypes bus_type;
706 typedef struct INTDATA {
716 typedef struct BUSTYPENAME {
721 static bus_type_name bus_type_table[] =
727 {UNKNOWN_BUSTYPE, "---"},
730 {UNKNOWN_BUSTYPE, "---"},
731 {UNKNOWN_BUSTYPE, "---"},
732 {UNKNOWN_BUSTYPE, "---"},
733 {UNKNOWN_BUSTYPE, "---"},
734 {UNKNOWN_BUSTYPE, "---"},
736 {UNKNOWN_BUSTYPE, "---"},
737 {UNKNOWN_BUSTYPE, "---"},
738 {UNKNOWN_BUSTYPE, "---"},
739 {UNKNOWN_BUSTYPE, "---"},
741 {UNKNOWN_BUSTYPE, "---"}
743 /* from MP spec v1.4, table 5-1 */
744 static int default_data[7][5] =
746 /* nbus, id0, type0, id1, type1 */
747 {1, 0, ISA, 255, 255},
748 {1, 0, EISA, 255, 255},
749 {1, 0, EISA, 255, 255},
750 {1, 0, MCA, 255, 255},
752 {2, 0, EISA, 1, PCI},
758 static bus_datum *bus_data;
760 /* the IO INT data, one entry per possible APIC INTerrupt */
761 static io_int *io_apic_ints;
765 static int processor_entry __P((proc_entry_ptr entry, int cpu));
766 static int bus_entry __P((bus_entry_ptr entry, int bus));
767 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
768 static int int_entry __P((int_entry_ptr entry, int intr));
769 static int lookup_bus_type __P((char *name));
773 * 1st pass on motherboard's Intel MP specification table.
779 * cpu_apic_address (common to all CPUs)
796 POSTCODE(MPTABLE_PASS1_POST);
798 /* clear various tables */
799 for (x = 0; x < NAPICID; ++x) {
800 io_apic_address[x] = ~0; /* IO APIC address table */
803 /* init everything to empty */
809 /* check for use of 'default' configuration */
810 if (MPFPS_MPFB1 != 0) {
811 /* use default addresses */
812 cpu_apic_address = DEFAULT_APIC_BASE;
813 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
815 /* fill in with defaults */
816 mp_naps = 2; /* includes BSP */
817 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
824 if ((cth = mpfps->pap) == 0)
825 panic("MP Configuration Table Header MISSING!");
827 cpu_apic_address = (vm_offset_t) cth->apic_address;
829 /* walk the table, recording info of interest */
830 totalSize = cth->base_table_length - sizeof(struct MPCTH);
831 position = (u_char *) cth + sizeof(struct MPCTH);
832 count = cth->entry_count;
835 switch (type = *(u_char *) position) {
836 case 0: /* processor_entry */
837 if (((proc_entry_ptr)position)->cpu_flags
841 case 1: /* bus_entry */
844 case 2: /* io_apic_entry */
845 if (((io_apic_entry_ptr)position)->apic_flags
846 & IOAPICENTRY_FLAG_EN)
847 io_apic_address[mp_napics++] =
848 (vm_offset_t)((io_apic_entry_ptr)
849 position)->apic_address;
851 case 3: /* int_entry */
854 case 4: /* int_entry */
857 panic("mpfps Base Table HOSED!");
861 totalSize -= basetable_entry_types[type].length;
862 (u_char*)position += basetable_entry_types[type].length;
866 /* qualify the numbers */
867 if (mp_naps > MAXCPU) {
868 printf("Warning: only using %d of %d available CPUs!\n",
875 * This is also used as a counter while starting the APs.
879 --mp_naps; /* subtract the BSP */
884 * 2nd pass on motherboard's Intel MP specification table.
888 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
889 * CPU_TO_ID(N), logical CPU to APIC ID table
890 * IO_TO_ID(N), logical IO to APIC ID table
903 int apic, bus, cpu, intr;
907 POSTCODE(MPTABLE_PASS2_POST);
909 pgeflag = 0; /* XXX - Not used under SMP yet. */
911 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
913 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
915 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
917 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
920 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
922 for (i = 0; i < mp_napics; i++) {
923 for (j = 0; j < mp_napics; j++) {
924 /* same page frame as a previous IO apic? */
925 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
926 (io_apic_address[i] & PG_FRAME)) {
927 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
928 + (NPTEPG-2-j) * PAGE_SIZE
929 + (io_apic_address[i] & PAGE_MASK));
932 /* use this slot if available */
933 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
934 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
935 pgeflag | (io_apic_address[i] & PG_FRAME));
936 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
937 + (NPTEPG-2-j) * PAGE_SIZE
938 + (io_apic_address[i] & PAGE_MASK));
944 /* clear various tables */
945 for (x = 0; x < NAPICID; ++x) {
946 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
947 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
948 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
951 /* clear bus data table */
952 for (x = 0; x < mp_nbusses; ++x)
953 bus_data[x].bus_id = 0xff;
955 /* clear IO APIC INT table */
956 for (x = 0; x < (nintrs + 1); ++x) {
957 io_apic_ints[x].int_type = 0xff;
958 io_apic_ints[x].int_vector = 0xff;
961 /* setup the cpu/apic mapping arrays */
964 /* record whether PIC or virtual-wire mode */
965 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
967 /* check for use of 'default' configuration */
968 if (MPFPS_MPFB1 != 0)
969 return MPFPS_MPFB1; /* return default configuration type */
971 if ((cth = mpfps->pap) == 0)
972 panic("MP Configuration Table Header MISSING!");
974 /* walk the table, recording info of interest */
975 totalSize = cth->base_table_length - sizeof(struct MPCTH);
976 position = (u_char *) cth + sizeof(struct MPCTH);
977 count = cth->entry_count;
978 apic = bus = intr = 0;
979 cpu = 1; /* pre-count the BSP */
982 switch (type = *(u_char *) position) {
984 if (processor_entry(position, cpu))
988 if (bus_entry(position, bus))
992 if (io_apic_entry(position, apic))
996 if (int_entry(position, intr))
1000 /* int_entry(position); */
1003 panic("mpfps Base Table HOSED!");
1007 totalSize -= basetable_entry_types[type].length;
1008 (u_char *) position += basetable_entry_types[type].length;
1011 if (boot_cpu_id == -1)
1012 panic("NO BSP found!");
1014 /* report fact that its NOT a default configuration */
1020 assign_apic_irq(int apic, int intpin, int irq)
1024 if (int_to_apicintpin[irq].ioapic != -1)
1025 panic("assign_apic_irq: inconsistent table");
1027 int_to_apicintpin[irq].ioapic = apic;
1028 int_to_apicintpin[irq].int_pin = intpin;
1029 int_to_apicintpin[irq].apic_address = ioapic[apic];
1030 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1032 for (x = 0; x < nintrs; x++) {
1033 if ((io_apic_ints[x].int_type == 0 ||
1034 io_apic_ints[x].int_type == 3) &&
1035 io_apic_ints[x].int_vector == 0xff &&
1036 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1037 io_apic_ints[x].dst_apic_int == intpin)
1038 io_apic_ints[x].int_vector = irq;
1043 revoke_apic_irq(int irq)
1049 if (int_to_apicintpin[irq].ioapic == -1)
1050 panic("assign_apic_irq: inconsistent table");
1052 oldapic = int_to_apicintpin[irq].ioapic;
1053 oldintpin = int_to_apicintpin[irq].int_pin;
1055 int_to_apicintpin[irq].ioapic = -1;
1056 int_to_apicintpin[irq].int_pin = 0;
1057 int_to_apicintpin[irq].apic_address = NULL;
1058 int_to_apicintpin[irq].redirindex = 0;
1060 for (x = 0; x < nintrs; x++) {
1061 if ((io_apic_ints[x].int_type == 0 ||
1062 io_apic_ints[x].int_type == 3) &&
1063 io_apic_ints[x].int_vector == 0xff &&
1064 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1065 io_apic_ints[x].dst_apic_int == oldintpin)
1066 io_apic_ints[x].int_vector = 0xff;
1072 allocate_apic_irq(int intr)
1078 if (io_apic_ints[intr].int_vector != 0xff)
1079 return; /* Interrupt handler already assigned */
1081 if (io_apic_ints[intr].int_type != 0 &&
1082 (io_apic_ints[intr].int_type != 3 ||
1083 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1084 io_apic_ints[intr].dst_apic_int == 0)))
1085 return; /* Not INT or ExtInt on != (0, 0) */
1088 while (irq < APIC_INTMAPSIZE &&
1089 int_to_apicintpin[irq].ioapic != -1)
1092 if (irq >= APIC_INTMAPSIZE)
1093 return; /* No free interrupt handlers */
1095 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1096 intpin = io_apic_ints[intr].dst_apic_int;
1098 assign_apic_irq(apic, intpin, irq);
1099 io_apic_setup_intpin(apic, intpin);
1104 swap_apic_id(int apic, int oldid, int newid)
1111 return; /* Nothing to do */
1113 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1114 apic, oldid, newid);
1116 /* Swap physical APIC IDs in interrupt entries */
1117 for (x = 0; x < nintrs; x++) {
1118 if (io_apic_ints[x].dst_apic_id == oldid)
1119 io_apic_ints[x].dst_apic_id = newid;
1120 else if (io_apic_ints[x].dst_apic_id == newid)
1121 io_apic_ints[x].dst_apic_id = oldid;
1124 /* Swap physical APIC IDs in IO_TO_ID mappings */
1125 for (oapic = 0; oapic < mp_napics; oapic++)
1126 if (IO_TO_ID(oapic) == newid)
1129 if (oapic < mp_napics) {
1130 printf("Changing APIC ID for IO APIC #%d from "
1131 "%d to %d in MP table\n",
1132 oapic, newid, oldid);
1133 IO_TO_ID(oapic) = oldid;
1135 IO_TO_ID(apic) = newid;
1140 fix_id_to_io_mapping(void)
1144 for (x = 0; x < NAPICID; x++)
1147 for (x = 0; x <= mp_naps; x++)
1148 if (CPU_TO_ID(x) < NAPICID)
1149 ID_TO_IO(CPU_TO_ID(x)) = x;
1151 for (x = 0; x < mp_napics; x++)
1152 if (IO_TO_ID(x) < NAPICID)
1153 ID_TO_IO(IO_TO_ID(x)) = x;
1158 first_free_apic_id(void)
1162 for (freeid = 0; freeid < NAPICID; freeid++) {
1163 for (x = 0; x <= mp_naps; x++)
1164 if (CPU_TO_ID(x) == freeid)
1168 for (x = 0; x < mp_napics; x++)
1169 if (IO_TO_ID(x) == freeid)
1180 io_apic_id_acceptable(int apic, int id)
1182 int cpu; /* Logical CPU number */
1183 int oapic; /* Logical IO APIC number for other IO APIC */
1186 return 0; /* Out of range */
1188 for (cpu = 0; cpu <= mp_naps; cpu++)
1189 if (CPU_TO_ID(cpu) == id)
1190 return 0; /* Conflict with CPU */
1192 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1193 if (IO_TO_ID(oapic) == id)
1194 return 0; /* Conflict with other APIC */
1196 return 1; /* ID is acceptable for IO APIC */
1201 * parse an Intel MP specification table
1208 int bus_0 = 0; /* Stop GCC warning */
1209 int bus_pci = 0; /* Stop GCC warning */
1211 int apic; /* IO APIC unit number */
1212 int freeid; /* Free physical APIC ID */
1213 int physid; /* Current physical IO APIC ID */
1216 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1217 * did it wrong. The MP spec says that when more than 1 PCI bus
1218 * exists the BIOS must begin with bus entries for the PCI bus and use
1219 * actual PCI bus numbering. This implies that when only 1 PCI bus
1220 * exists the BIOS can choose to ignore this ordering, and indeed many
1221 * MP motherboards do ignore it. This causes a problem when the PCI
1222 * sub-system makes requests of the MP sub-system based on PCI bus
1223 * numbers. So here we look for the situation and renumber the
1224 * busses and associated INTs in an effort to "make it right".
1227 /* find bus 0, PCI bus, count the number of PCI busses */
1228 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1229 if (bus_data[x].bus_id == 0) {
1232 if (bus_data[x].bus_type == PCI) {
1238 * bus_0 == slot of bus with ID of 0
1239 * bus_pci == slot of last PCI bus encountered
1242 /* check the 1 PCI bus case for sanity */
1243 /* if it is number 0 all is well */
1244 if (num_pci_bus == 1 &&
1245 bus_data[bus_pci].bus_id != 0) {
1247 /* mis-numbered, swap with whichever bus uses slot 0 */
1249 /* swap the bus entry types */
1250 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1251 bus_data[bus_0].bus_type = PCI;
1253 /* swap each relavant INTerrupt entry */
1254 id = bus_data[bus_pci].bus_id;
1255 for (x = 0; x < nintrs; ++x) {
1256 if (io_apic_ints[x].src_bus_id == id) {
1257 io_apic_ints[x].src_bus_id = 0;
1259 else if (io_apic_ints[x].src_bus_id == 0) {
1260 io_apic_ints[x].src_bus_id = id;
1265 /* Assign IO APIC IDs.
1267 * First try the existing ID. If a conflict is detected, try
1268 * the ID in the MP table. If a conflict is still detected, find
1271 * We cannot use the ID_TO_IO table before all conflicts has been
1272 * resolved and the table has been corrected.
1274 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1276 /* First try to use the value set by the BIOS */
1277 physid = io_apic_get_id(apic);
1278 if (io_apic_id_acceptable(apic, physid)) {
1279 if (IO_TO_ID(apic) != physid)
1280 swap_apic_id(apic, IO_TO_ID(apic), physid);
1284 /* Then check if the value in the MP table is acceptable */
1285 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1288 /* Last resort, find a free APIC ID and use it */
1289 freeid = first_free_apic_id();
1290 if (freeid >= NAPICID)
1291 panic("No free physical APIC IDs found");
1293 if (io_apic_id_acceptable(apic, freeid)) {
1294 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1297 panic("Free physical APIC ID not usable");
1299 fix_id_to_io_mapping();
1301 /* detect and fix broken Compaq MP table */
1302 if (apic_int_type(0, 0) == -1) {
1303 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1304 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1305 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1306 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1307 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1308 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1314 /* Assign low level interrupt handlers */
1316 setup_apic_irq_mapping(void)
1322 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1323 int_to_apicintpin[x].ioapic = -1;
1324 int_to_apicintpin[x].int_pin = 0;
1325 int_to_apicintpin[x].apic_address = NULL;
1326 int_to_apicintpin[x].redirindex = 0;
1329 /* First assign ISA/EISA interrupts */
1330 for (x = 0; x < nintrs; x++) {
1331 int_vector = io_apic_ints[x].src_bus_irq;
1332 if (int_vector < APIC_INTMAPSIZE &&
1333 io_apic_ints[x].int_vector == 0xff &&
1334 int_to_apicintpin[int_vector].ioapic == -1 &&
1335 (apic_int_is_bus_type(x, ISA) ||
1336 apic_int_is_bus_type(x, EISA)) &&
1337 io_apic_ints[x].int_type == 0) {
1338 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1339 io_apic_ints[x].dst_apic_int,
1344 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1345 for (x = 0; x < nintrs; x++) {
1346 if (io_apic_ints[x].dst_apic_int == 0 &&
1347 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1348 io_apic_ints[x].int_vector == 0xff &&
1349 int_to_apicintpin[0].ioapic == -1 &&
1350 io_apic_ints[x].int_type == 3) {
1351 assign_apic_irq(0, 0, 0);
1355 /* PCI interrupt assignment is deferred */
1360 processor_entry(proc_entry_ptr entry, int cpu)
1362 /* check for usability */
1363 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1366 if(entry->apic_id >= NAPICID)
1367 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1368 /* check for BSP flag */
1369 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1370 boot_cpu_id = entry->apic_id;
1371 CPU_TO_ID(0) = entry->apic_id;
1372 ID_TO_CPU(entry->apic_id) = 0;
1373 return 0; /* its already been counted */
1376 /* add another AP to list, if less than max number of CPUs */
1377 else if (cpu < MAXCPU) {
1378 CPU_TO_ID(cpu) = entry->apic_id;
1379 ID_TO_CPU(entry->apic_id) = cpu;
1388 bus_entry(bus_entry_ptr entry, int bus)
1393 /* encode the name into an index */
1394 for (x = 0; x < 6; ++x) {
1395 if ((c = entry->bus_type[x]) == ' ')
1401 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1402 panic("unknown bus type: '%s'", name);
1404 bus_data[bus].bus_id = entry->bus_id;
1405 bus_data[bus].bus_type = x;
1412 io_apic_entry(io_apic_entry_ptr entry, int apic)
1414 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1417 IO_TO_ID(apic) = entry->apic_id;
1418 if (entry->apic_id < NAPICID)
1419 ID_TO_IO(entry->apic_id) = apic;
1426 lookup_bus_type(char *name)
1430 for (x = 0; x < MAX_BUSTYPE; ++x)
1431 if (strcmp(bus_type_table[x].name, name) == 0)
1432 return bus_type_table[x].type;
1434 return UNKNOWN_BUSTYPE;
1439 int_entry(int_entry_ptr entry, int intr)
1443 io_apic_ints[intr].int_type = entry->int_type;
1444 io_apic_ints[intr].int_flags = entry->int_flags;
1445 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1446 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1447 if (entry->dst_apic_id == 255) {
1448 /* This signal goes to all IO APICS. Select an IO APIC
1449 with sufficient number of interrupt pins */
1450 for (apic = 0; apic < mp_napics; apic++)
1451 if (((io_apic_read(apic, IOAPIC_VER) &
1452 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1453 entry->dst_apic_int)
1455 if (apic < mp_napics)
1456 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1458 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1460 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1461 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1468 apic_int_is_bus_type(int intr, int bus_type)
1472 for (bus = 0; bus < mp_nbusses; ++bus)
1473 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1474 && ((int) bus_data[bus].bus_type == bus_type))
1482 * Given a traditional ISA INT mask, return an APIC mask.
1485 isa_apic_mask(u_int isa_mask)
1490 #if defined(SKIP_IRQ15_REDIRECT)
1491 if (isa_mask == (1 << 15)) {
1492 printf("skipping ISA IRQ15 redirect\n");
1495 #endif /* SKIP_IRQ15_REDIRECT */
1497 isa_irq = ffs(isa_mask); /* find its bit position */
1498 if (isa_irq == 0) /* doesn't exist */
1500 --isa_irq; /* make it zero based */
1502 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1506 return (1 << apic_pin); /* convert pin# to a mask */
1511 * Determine which APIC pin an ISA/EISA INT is attached to.
1513 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1514 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1515 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1516 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1518 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1520 isa_apic_irq(int isa_irq)
1524 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1525 if (INTTYPE(intr) == 0) { /* standard INT */
1526 if (SRCBUSIRQ(intr) == isa_irq) {
1527 if (apic_int_is_bus_type(intr, ISA) ||
1528 apic_int_is_bus_type(intr, EISA)) {
1529 if (INTIRQ(intr) == 0xff)
1530 return -1; /* unassigned */
1531 return INTIRQ(intr); /* found */
1536 return -1; /* NOT found */
1541 * Determine which APIC pin a PCI INT is attached to.
1543 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1544 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1545 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1547 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1551 --pciInt; /* zero based */
1553 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1554 if ((INTTYPE(intr) == 0) /* standard INT */
1555 && (SRCBUSID(intr) == pciBus)
1556 && (SRCBUSDEVICE(intr) == pciDevice)
1557 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1558 if (apic_int_is_bus_type(intr, PCI)) {
1559 if (INTIRQ(intr) == 0xff)
1560 allocate_apic_irq(intr);
1561 if (INTIRQ(intr) == 0xff)
1562 return -1; /* unassigned */
1563 return INTIRQ(intr); /* exact match */
1566 return -1; /* NOT found */
1570 next_apic_irq(int irq)
1577 for (intr = 0; intr < nintrs; intr++) {
1578 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1580 bus = SRCBUSID(intr);
1581 bustype = apic_bus_type(bus);
1582 if (bustype != ISA &&
1588 if (intr >= nintrs) {
1591 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1592 if (INTTYPE(ointr) != 0)
1594 if (bus != SRCBUSID(ointr))
1596 if (bustype == PCI) {
1597 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1599 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1602 if (bustype == ISA || bustype == EISA) {
1603 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1606 if (INTPIN(intr) == INTPIN(ointr))
1610 if (ointr >= nintrs) {
1613 return INTIRQ(ointr);
1627 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1630 * Exactly what this means is unclear at this point. It is a solution
1631 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1632 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1633 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1637 undirect_isa_irq(int rirq)
1641 printf("Freeing redirected ISA irq %d.\n", rirq);
1642 /** FIXME: tickle the MB redirector chip */
1646 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1653 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1656 undirect_pci_irq(int rirq)
1660 printf("Freeing redirected PCI irq %d.\n", rirq);
1662 /** FIXME: tickle the MB redirector chip */
1666 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1674 * given a bus ID, return:
1675 * the bus type if found
1679 apic_bus_type(int id)
1683 for (x = 0; x < mp_nbusses; ++x)
1684 if (bus_data[x].bus_id == id)
1685 return bus_data[x].bus_type;
1692 * given a LOGICAL APIC# and pin#, return:
1693 * the associated src bus ID if found
1697 apic_src_bus_id(int apic, int pin)
1701 /* search each of the possible INTerrupt sources */
1702 for (x = 0; x < nintrs; ++x)
1703 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1704 (pin == io_apic_ints[x].dst_apic_int))
1705 return (io_apic_ints[x].src_bus_id);
1707 return -1; /* NOT found */
1712 * given a LOGICAL APIC# and pin#, return:
1713 * the associated src bus IRQ if found
1717 apic_src_bus_irq(int apic, int pin)
1721 for (x = 0; x < nintrs; x++)
1722 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1723 (pin == io_apic_ints[x].dst_apic_int))
1724 return (io_apic_ints[x].src_bus_irq);
1726 return -1; /* NOT found */
1731 * given a LOGICAL APIC# and pin#, return:
1732 * the associated INTerrupt type if found
1736 apic_int_type(int apic, int pin)
1740 /* search each of the possible INTerrupt sources */
1741 for (x = 0; x < nintrs; ++x)
1742 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1743 (pin == io_apic_ints[x].dst_apic_int))
1744 return (io_apic_ints[x].int_type);
1746 return -1; /* NOT found */
1750 apic_irq(int apic, int pin)
1755 for (x = 0; x < nintrs; ++x)
1756 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1757 (pin == io_apic_ints[x].dst_apic_int)) {
1758 res = io_apic_ints[x].int_vector;
1761 if (apic != int_to_apicintpin[res].ioapic)
1762 panic("apic_irq: inconsistent table");
1763 if (pin != int_to_apicintpin[res].int_pin)
1764 panic("apic_irq inconsistent table (2)");
1772 * given a LOGICAL APIC# and pin#, return:
1773 * the associated trigger mode if found
1777 apic_trigger(int apic, int pin)
1781 /* search each of the possible INTerrupt sources */
1782 for (x = 0; x < nintrs; ++x)
1783 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1784 (pin == io_apic_ints[x].dst_apic_int))
1785 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1787 return -1; /* NOT found */
1792 * given a LOGICAL APIC# and pin#, return:
1793 * the associated 'active' level if found
1797 apic_polarity(int apic, int pin)
1801 /* search each of the possible INTerrupt sources */
1802 for (x = 0; x < nintrs; ++x)
1803 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1804 (pin == io_apic_ints[x].dst_apic_int))
1805 return (io_apic_ints[x].int_flags & 0x03);
1807 return -1; /* NOT found */
1812 * set data according to MP defaults
1813 * FIXME: probably not complete yet...
1816 default_mp_table(int type)
1819 #if defined(APIC_IO)
1822 #endif /* APIC_IO */
1825 printf(" MP default config type: %d\n", type);
1828 printf(" bus: ISA, APIC: 82489DX\n");
1831 printf(" bus: EISA, APIC: 82489DX\n");
1834 printf(" bus: EISA, APIC: 82489DX\n");
1837 printf(" bus: MCA, APIC: 82489DX\n");
1840 printf(" bus: ISA+PCI, APIC: Integrated\n");
1843 printf(" bus: EISA+PCI, APIC: Integrated\n");
1846 printf(" bus: MCA+PCI, APIC: Integrated\n");
1849 printf(" future type\n");
1855 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1856 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1859 CPU_TO_ID(0) = boot_cpu_id;
1860 ID_TO_CPU(boot_cpu_id) = 0;
1862 /* one and only AP */
1863 CPU_TO_ID(1) = ap_cpu_id;
1864 ID_TO_CPU(ap_cpu_id) = 1;
1866 #if defined(APIC_IO)
1867 /* one and only IO APIC */
1868 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1871 * sanity check, refer to MP spec section 3.6.6, last paragraph
1872 * necessary as some hardware isn't properly setting up the IO APIC
1874 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1875 if (io_apic_id != 2) {
1877 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1878 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1879 io_apic_set_id(0, 2);
1882 IO_TO_ID(0) = io_apic_id;
1883 ID_TO_IO(io_apic_id) = 0;
1884 #endif /* APIC_IO */
1886 /* fill out bus entries */
1895 bus_data[0].bus_id = default_data[type - 1][1];
1896 bus_data[0].bus_type = default_data[type - 1][2];
1897 bus_data[1].bus_id = default_data[type - 1][3];
1898 bus_data[1].bus_type = default_data[type - 1][4];
1901 /* case 4: case 7: MCA NOT supported */
1902 default: /* illegal/reserved */
1903 panic("BAD default MP config: %d", type);
1907 #if defined(APIC_IO)
1908 /* general cases from MP v1.4, table 5-2 */
1909 for (pin = 0; pin < 16; ++pin) {
1910 io_apic_ints[pin].int_type = 0;
1911 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1912 io_apic_ints[pin].src_bus_id = 0;
1913 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1914 io_apic_ints[pin].dst_apic_id = io_apic_id;
1915 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1918 /* special cases from MP v1.4, table 5-2 */
1920 io_apic_ints[2].int_type = 0xff; /* N/C */
1921 io_apic_ints[13].int_type = 0xff; /* N/C */
1922 #if !defined(APIC_MIXED_MODE)
1924 panic("sorry, can't support type 2 default yet");
1925 #endif /* APIC_MIXED_MODE */
1928 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1931 io_apic_ints[0].int_type = 0xff; /* N/C */
1933 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1934 #endif /* APIC_IO */
1939 * start each AP in our list
1942 start_all_aps(u_int boot_addr)
1945 u_char mpbiosreason;
1946 u_long mpbioswarmvec;
1947 struct globaldata *gd;
1950 POSTCODE(START_ALL_APS_POST);
1952 /* initialize BSP's local APIC */
1956 /* install the AP 1st level boot code */
1957 install_ap_tramp(boot_addr);
1960 /* save the current value of the warm-start vector */
1961 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1963 outb(CMOS_REG, BIOS_RESET);
1964 mpbiosreason = inb(CMOS_DATA);
1967 /* record BSP in CPU map */
1970 /* set up 0 -> 4MB P==V mapping for AP boot */
1971 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
1975 for (x = 1; x <= mp_naps; ++x) {
1977 /* This is a bit verbose, it will go away soon. */
1979 /* first page of AP's private space */
1980 pg = x * i386_btop(sizeof(struct privatespace));
1982 /* allocate a new private data page */
1983 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1985 /* wire it into the private page table page */
1986 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1988 /* allocate and set up an idle stack data page */
1989 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1990 for (i = 0; i < UPAGES; i++)
1991 SMPpt[pg + 1 + i] = (pt_entry_t)
1992 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1994 /* prime data page for it to use */
1995 SLIST_INSERT_HEAD(&cpuhead, gd, gd_allcpu);
1997 gd->gd_cpu_lockid = x << 24;
1999 /* setup a vector to our boot code */
2000 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2001 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2003 outb(CMOS_REG, BIOS_RESET);
2004 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2007 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
2010 /* attempt to start the Application Processor */
2011 CHECK_INIT(99); /* setup checkpoints */
2012 if (!start_ap(x, boot_addr)) {
2013 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2014 CHECK_PRINT("trace"); /* show checkpoints */
2015 /* better panic as the AP may be running loose */
2016 printf("panic y/n? [y] ");
2017 if (cngetc() != 'n')
2020 CHECK_PRINT("trace"); /* show checkpoints */
2022 /* record its version info */
2023 cpu_apic_versions[x] = cpu_apic_versions[0];
2025 all_cpus |= (1 << x); /* record AP in CPU map */
2028 /* build our map of 'other' CPUs */
2029 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2031 /* fill in our (BSP) APIC version */
2032 cpu_apic_versions[0] = lapic.version;
2034 /* restore the warmstart vector */
2035 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2037 outb(CMOS_REG, BIOS_RESET);
2038 outb(CMOS_DATA, mpbiosreason);
2042 * Set up the idle context for the BSP. Similar to above except
2043 * that some was done by locore, some by pmap.c and some is implicit
2044 * because the BSP is cpu#0 and the page is initially zero, and also
2045 * because we can refer to variables by name on the BSP..
2048 /* Allocate and setup BSP idle stack */
2049 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2050 for (i = 0; i < UPAGES; i++)
2051 SMPpt[1 + i] = (pt_entry_t)
2052 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2057 /* number of APs actually started */
2058 return mp_ncpus - 1;
2063 * load the 1st level AP boot code into base memory.
2066 /* targets for relocation */
2067 extern void bigJump(void);
2068 extern void bootCodeSeg(void);
2069 extern void bootDataSeg(void);
2070 extern void MPentry(void);
2071 extern u_int MP_GDT;
2072 extern u_int mp_gdtbase;
2075 install_ap_tramp(u_int boot_addr)
2078 int size = *(int *) ((u_long) & bootMP_size);
2079 u_char *src = (u_char *) ((u_long) bootMP);
2080 u_char *dst = (u_char *) boot_addr + KERNBASE;
2081 u_int boot_base = (u_int) bootMP;
2086 POSTCODE(INSTALL_AP_TRAMP_POST);
2088 for (x = 0; x < size; ++x)
2092 * modify addresses in code we just moved to basemem. unfortunately we
2093 * need fairly detailed info about mpboot.s for this to work. changes
2094 * to mpboot.s might require changes here.
2097 /* boot code is located in KERNEL space */
2098 dst = (u_char *) boot_addr + KERNBASE;
2100 /* modify the lgdt arg */
2101 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2102 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2104 /* modify the ljmp target for MPentry() */
2105 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2106 *dst32 = ((u_int) MPentry - KERNBASE);
2108 /* modify the target for boot code segment */
2109 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2110 dst8 = (u_int8_t *) (dst16 + 1);
2111 *dst16 = (u_int) boot_addr & 0xffff;
2112 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2114 /* modify the target for boot data segment */
2115 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2116 dst8 = (u_int8_t *) (dst16 + 1);
2117 *dst16 = (u_int) boot_addr & 0xffff;
2118 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2123 * this function starts the AP (application processor) identified
2124 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2125 * to accomplish this. This is necessary because of the nuances
2126 * of the different hardware we might encounter. It ain't pretty,
2127 * but it seems to work.
2130 start_ap(int logical_cpu, u_int boot_addr)
2135 u_long icr_lo, icr_hi;
2137 POSTCODE(START_AP_POST);
2139 /* get the PHYSICAL APIC ID# */
2140 physical_cpu = CPU_TO_ID(logical_cpu);
2142 /* calculate the vector */
2143 vector = (boot_addr >> 12) & 0xff;
2145 /* used as a watchpoint to signal AP startup */
2149 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2150 * and running the target CPU. OR this INIT IPI might be latched (P5
2151 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2155 /* setup the address for the target AP */
2156 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2157 icr_hi |= (physical_cpu << 24);
2158 lapic.icr_hi = icr_hi;
2160 /* do an INIT IPI: assert RESET */
2161 icr_lo = lapic.icr_lo & 0xfff00000;
2162 lapic.icr_lo = icr_lo | 0x0000c500;
2164 /* wait for pending status end */
2165 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2168 /* do an INIT IPI: deassert RESET */
2169 lapic.icr_lo = icr_lo | 0x00008500;
2171 /* wait for pending status end */
2172 u_sleep(10000); /* wait ~10mS */
2173 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2177 * next we do a STARTUP IPI: the previous INIT IPI might still be
2178 * latched, (P5 bug) this 1st STARTUP would then terminate
2179 * immediately, and the previously started INIT IPI would continue. OR
2180 * the previous INIT IPI has already run. and this STARTUP IPI will
2181 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2185 /* do a STARTUP IPI */
2186 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2187 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2189 u_sleep(200); /* wait ~200uS */
2192 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2193 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2194 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2195 * recognized after hardware RESET or INIT IPI.
2198 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2199 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2201 u_sleep(200); /* wait ~200uS */
2203 /* wait for it to start */
2204 set_apic_timer(5000000);/* == 5 seconds */
2205 while (read_apic_timer())
2206 if (mp_ncpus > cpus)
2207 return 1; /* return SUCCESS */
2209 return 0; /* return FAILURE */
2213 * Flush the TLB on all other CPU's
2215 * XXX: Needs to handshake and wait for completion before proceding.
2220 #if defined(APIC_IO)
2221 if (smp_started && invltlb_ok)
2222 all_but_self_ipi(XINVLTLB_OFFSET);
2223 #endif /* APIC_IO */
2229 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2231 /* send a message to the other CPUs */
2241 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2244 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2246 /* send a message to the other CPUs */
2252 * This is called once the rest of the system is up and running and we're
2253 * ready to let the AP's out of the pen.
2260 /* spin until all the AP's are ready */
2265 * Set curproc to our per-cpu idleproc so that mutexes have
2266 * something unique to lock with.
2268 PCPU_SET(curproc, PCPU_GET(idleproc));
2270 /* lock against other AP's that are waking up */
2271 mtx_enter(&ap_boot_mtx, MTX_SPIN);
2273 /* BSP may have changed PTD while we're waiting for the lock */
2278 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2282 /* Build our map of 'other' CPUs. */
2283 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2285 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2287 /* set up CPU registers and state */
2290 /* set up FPU state on the AP */
2291 npxinit(__INITIAL_NPXCW__);
2293 /* A quick check from sanity claus */
2294 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2295 if (PCPU_GET(cpuid) != apic_id) {
2296 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2297 printf("SMP: apic_id = %d\n", apic_id);
2298 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2299 panic("cpuid mismatch! boom!!");
2302 /* Init local apic for irq's */
2305 /* Set memory range attributes for this CPU to match the BSP */
2306 mem_range_AP_init();
2309 * Activate smp_invltlb, although strictly speaking, this isn't
2310 * quite correct yet. We should have a bitfield for cpus willing
2311 * to accept TLB flush IPI's or something and sync them.
2313 if (smp_cpus == mp_ncpus) {
2315 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2316 smp_active = 1; /* historic */
2319 /* let other AP's wake up now */
2320 mtx_exit(&ap_boot_mtx, MTX_SPIN);
2322 /* wait until all the AP's are up */
2323 while (smp_started == 0)
2326 microuptime(PCPU_PTR(switchtime));
2327 PCPU_SET(switchticks, ticks);
2329 /* ok, now grab sched_lock and enter the scheduler */
2331 mtx_enter(&sched_lock, MTX_SPIN);
2332 cpu_throw(); /* doesn't return */
2334 panic("scheduler returned us to ap_init");
2339 #define CHECKSTATE_USER 0
2340 #define CHECKSTATE_SYS 1
2341 #define CHECKSTATE_INTR 2
2343 /* Do not staticize. Used from apic_vector.s */
2344 struct proc* checkstate_curproc[MAXCPU];
2345 int checkstate_cpustate[MAXCPU];
2346 u_long checkstate_pc[MAXCPU];
2348 #define PC_TO_INDEX(pc, prof) \
2349 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2350 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2353 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2359 pc = checkstate_pc[id];
2360 prof = &p->p_stats->p_prof;
2361 if (pc >= prof->pr_off &&
2362 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2363 mtx_assert(&sched_lock, MA_OWNED);
2364 if ((p->p_sflag & PS_OWEUPC) == 0) {
2367 p->p_sflag |= PS_OWEUPC;
2369 *astmap |= (1 << id);
2374 forwarded_statclock(int id, int pscnt, int *astmap)
2376 struct pstats *pstats;
2383 register struct gmonparam *g;
2387 mtx_assert(&sched_lock, MA_OWNED);
2388 p = checkstate_curproc[id];
2389 cpustate = checkstate_cpustate[id];
2393 cpustate = CHECKSTATE_INTR;
2394 else if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2395 cpustate = CHECKSTATE_SYS;
2398 case CHECKSTATE_USER:
2399 if (p->p_sflag & PS_PROFIL)
2400 addupc_intr_forwarded(p, id, astmap);
2404 if (p->p_nice > NZERO)
2409 case CHECKSTATE_SYS:
2412 * Kernel statistics are just like addupc_intr, only easier.
2415 if (g->state == GMON_PROF_ON) {
2416 i = checkstate_pc[id] - g->lowpc;
2417 if (i < g->textsize) {
2418 i /= HISTFRACTION * sizeof(*g->kcount);
2427 if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2432 case CHECKSTATE_INTR:
2436 * Kernel statistics are just like addupc_intr, only easier.
2439 if (g->state == GMON_PROF_ON) {
2440 i = checkstate_pc[id] - g->lowpc;
2441 if (i < g->textsize) {
2442 i /= HISTFRACTION * sizeof(*g->kcount);
2449 KASSERT(p != NULL, ("NULL process in interrupt state"));
2456 /* Update resource usage integrals and maximums. */
2457 if ((pstats = p->p_stats) != NULL &&
2458 (ru = &pstats->p_ru) != NULL &&
2459 (vm = p->p_vmspace) != NULL) {
2460 ru->ru_ixrss += pgtok(vm->vm_tsize);
2461 ru->ru_idrss += pgtok(vm->vm_dsize);
2462 ru->ru_isrss += pgtok(vm->vm_ssize);
2463 rss = pgtok(vmspace_resident_count(vm));
2464 if (ru->ru_maxrss < rss)
2465 ru->ru_maxrss = rss;
2470 forward_statclock(int pscnt)
2476 /* Kludge. We don't yet have separate locks for the interrupts
2477 * and the kernel. This means that we cannot let the other processors
2478 * handle complex interrupts while inhibiting them from entering
2479 * the kernel in a non-interrupt context.
2481 * What we can do, without changing the locking mechanisms yet,
2482 * is letting the other processors handle a very simple interrupt
2483 * (wich determines the processor states), and do the main
2487 CTR1(KTR_SMP, "forward_statclock(%d)", pscnt);
2489 if (!smp_started || !invltlb_ok || cold || panicstr)
2492 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2494 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2495 checkstate_probed_cpus = 0;
2497 selected_apic_ipi(map,
2498 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2501 while (checkstate_probed_cpus != map) {
2505 #ifdef BETTER_CLOCK_DIAGNOSTIC
2506 printf("forward_statclock: checkstate %x\n",
2507 checkstate_probed_cpus);
2514 * Step 2: walk through other processors processes, update ticks and
2519 for (id = 0; id < mp_ncpus; id++) {
2520 if (id == PCPU_GET(cpuid))
2522 if (((1 << id) & checkstate_probed_cpus) == 0)
2524 forwarded_statclock(id, pscnt, &map);
2527 checkstate_need_ast |= map;
2528 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2530 while ((checkstate_need_ast & map) != 0) {
2534 #ifdef BETTER_CLOCK_DIAGNOSTIC
2535 printf("forward_statclock: dropped ast 0x%x\n",
2536 checkstate_need_ast & map);
2545 forward_hardclock(int pscnt)
2550 struct pstats *pstats;
2553 /* Kludge. We don't yet have separate locks for the interrupts
2554 * and the kernel. This means that we cannot let the other processors
2555 * handle complex interrupts while inhibiting them from entering
2556 * the kernel in a non-interrupt context.
2558 * What we can do, without changing the locking mechanisms yet,
2559 * is letting the other processors handle a very simple interrupt
2560 * (wich determines the processor states), and do the main
2564 CTR1(KTR_SMP, "forward_hardclock(%d)", pscnt);
2566 if (!smp_started || !invltlb_ok || cold || panicstr)
2569 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2571 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2572 checkstate_probed_cpus = 0;
2574 selected_apic_ipi(map,
2575 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2578 while (checkstate_probed_cpus != map) {
2582 #ifdef BETTER_CLOCK_DIAGNOSTIC
2583 printf("forward_hardclock: checkstate %x\n",
2584 checkstate_probed_cpus);
2591 * Step 2: walk through other processors processes, update virtual
2592 * timer and profiling timer. If stathz == 0, also update ticks and
2597 for (id = 0; id < mp_ncpus; id++) {
2598 if (id == PCPU_GET(cpuid))
2600 if (((1 << id) & checkstate_probed_cpus) == 0)
2602 p = checkstate_curproc[id];
2604 pstats = p->p_stats;
2605 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2606 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2607 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2608 p->p_sflag |= PS_ALRMPEND;
2611 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2612 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2613 p->p_sflag |= PS_PROFPEND;
2618 forwarded_statclock( id, pscnt, &map);
2622 checkstate_need_ast |= map;
2623 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2625 while ((checkstate_need_ast & map) != 0) {
2629 #ifdef BETTER_CLOCK_DIAGNOSTIC
2630 printf("forward_hardclock: dropped ast 0x%x\n",
2631 checkstate_need_ast & map);
2639 #endif /* BETTER_CLOCK */
2642 forward_signal(struct proc *p)
2648 /* Kludge. We don't yet have separate locks for the interrupts
2649 * and the kernel. This means that we cannot let the other processors
2650 * handle complex interrupts while inhibiting them from entering
2651 * the kernel in a non-interrupt context.
2653 * What we can do, without changing the locking mechanisms yet,
2654 * is letting the other processors handle a very simple interrupt
2655 * (wich determines the processor states), and do the main
2659 CTR1(KTR_SMP, "forward_signal(%p)", p);
2661 if (!smp_started || !invltlb_ok || cold || panicstr)
2663 if (!forward_signal_enabled)
2665 mtx_enter(&sched_lock, MTX_SPIN);
2667 if (p->p_stat != SRUN) {
2668 mtx_exit(&sched_lock, MTX_SPIN);
2672 mtx_exit(&sched_lock, MTX_SPIN);
2676 checkstate_need_ast |= map;
2677 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2679 while ((checkstate_need_ast & map) != 0) {
2684 printf("forward_signal: dropped ast 0x%x\n",
2685 checkstate_need_ast & map);
2690 mtx_enter(&sched_lock, MTX_SPIN);
2691 if (id == p->p_oncpu) {
2692 mtx_exit(&sched_lock, MTX_SPIN);
2699 forward_roundrobin(void)
2704 CTR0(KTR_SMP, "forward_roundrobin()");
2706 if (!smp_started || !invltlb_ok || cold || panicstr)
2708 if (!forward_roundrobin_enabled)
2710 resched_cpus |= PCPU_GET(other_cpus);
2711 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2713 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2715 (void) all_but_self_ipi(XCPUAST_OFFSET);
2718 while ((checkstate_need_ast & map) != 0) {
2723 printf("forward_roundrobin: dropped ast 0x%x\n",
2724 checkstate_need_ast & map);
2732 * When called the executing CPU will send an IPI to all other CPUs
2733 * requesting that they halt execution.
2735 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2737 * - Signals all CPUs in map to stop.
2738 * - Waits for each to stop.
2745 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2746 * from executing at same time.
2749 stop_cpus(u_int map)
2756 /* send the Xcpustop IPI to all CPUs in map */
2757 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2759 while (count++ < 100000 && (stopped_cpus & map) != map)
2763 if ((stopped_cpus & map) != map)
2764 printf("Warning: CPUs 0x%x did not stop!\n",
2765 (~(stopped_cpus & map)) & map);
2773 * Called by a CPU to restart stopped CPUs.
2775 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2777 * - Signals all CPUs in map to restart.
2778 * - Waits for each to restart.
2786 restart_cpus(u_int map)
2793 started_cpus = map; /* signal other cpus to restart */
2795 /* wait for each to clear its bit */
2796 while (count++ < 100000 && (stopped_cpus & map) != 0)
2800 if ((stopped_cpus & map) != 0)
2801 printf("Warning: CPUs 0x%x did not restart!\n",
2802 (~(stopped_cpus & map)) & map);
2809 #ifdef APIC_INTR_REORDER
2811 * Maintain mapping from softintr vector to isr bit in local apic.
2814 set_lapic_isrloc(int intr, int vector)
2816 if (intr < 0 || intr > 32)
2817 panic("set_apic_isrloc: bad intr argument: %d",intr);
2818 if (vector < ICU_OFFSET || vector > 255)
2819 panic("set_apic_isrloc: bad vector argument: %d",vector);
2820 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2821 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2826 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2827 * (if specified), rendezvous, execute the action function (if specified),
2828 * rendezvous again, execute the teardown function (if specified), and then
2831 * Note that the supplied external functions _must_ be reentrant and aware
2832 * that they are running in parallel and in an unknown lock context.
2834 static void (*smp_rv_setup_func)(void *arg);
2835 static void (*smp_rv_action_func)(void *arg);
2836 static void (*smp_rv_teardown_func)(void *arg);
2837 static void *smp_rv_func_arg;
2838 static volatile int smp_rv_waiters[2];
2841 smp_rendezvous_action(void)
2843 /* setup function */
2844 if (smp_rv_setup_func != NULL)
2845 smp_rv_setup_func(smp_rv_func_arg);
2846 /* spin on entry rendezvous */
2847 atomic_add_int(&smp_rv_waiters[0], 1);
2848 while (smp_rv_waiters[0] < mp_ncpus)
2850 /* action function */
2851 if (smp_rv_action_func != NULL)
2852 smp_rv_action_func(smp_rv_func_arg);
2853 /* spin on exit rendezvous */
2854 atomic_add_int(&smp_rv_waiters[1], 1);
2855 while (smp_rv_waiters[1] < mp_ncpus)
2857 /* teardown function */
2858 if (smp_rv_teardown_func != NULL)
2859 smp_rv_teardown_func(smp_rv_func_arg);
2863 smp_rendezvous(void (* setup_func)(void *),
2864 void (* action_func)(void *),
2865 void (* teardown_func)(void *),
2869 /* obtain rendezvous lock */
2870 mtx_enter(&smp_rv_mtx, MTX_SPIN);
2872 /* set static function pointers */
2873 smp_rv_setup_func = setup_func;
2874 smp_rv_action_func = action_func;
2875 smp_rv_teardown_func = teardown_func;
2876 smp_rv_func_arg = arg;
2877 smp_rv_waiters[0] = 0;
2878 smp_rv_waiters[1] = 0;
2881 * signal other processors, which will enter the IPI with interrupts off
2883 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2885 /* call executor function */
2886 smp_rendezvous_action();
2889 mtx_exit(&smp_rv_mtx, MTX_SPIN);
2893 release_aps(void *dummy __unused)
2895 atomic_store_rel_int(&aps_ready, 1);
2898 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);