2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <machine/smptests.h>
36 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
42 #include <sys/malloc.h>
43 #include <sys/memrange.h>
44 #include <sys/mutex.h>
46 #include <sys/dkstat.h>
48 #include <sys/cons.h> /* cngetc() */
51 #include <vm/vm_param.h>
53 #include <vm/vm_kern.h>
54 #include <vm/vm_extern.h>
57 #include <vm/vm_map.h>
64 #include <machine/smp.h>
65 #include <machine/apic.h>
66 #include <machine/atomic.h>
67 #include <machine/cpufunc.h>
68 #include <machine/mpapic.h>
69 #include <machine/psl.h>
70 #include <machine/segments.h>
71 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
72 #include <machine/tss.h>
73 #include <machine/specialreg.h>
74 #include <machine/globaldata.h>
77 #include <machine/md_var.h> /* setidt() */
78 #include <i386/isa/icu.h> /* IPIs */
79 #include <i386/isa/intr_machdep.h> /* IPIs */
82 #if defined(TEST_DEFAULT_CONFIG)
83 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
85 #define MPFPS_MPFB1 mpfps->mpfb1
86 #endif /* TEST_DEFAULT_CONFIG */
88 #define WARMBOOT_TARGET 0
89 #define WARMBOOT_OFF (KERNBASE + 0x0467)
90 #define WARMBOOT_SEG (KERNBASE + 0x0469)
93 #define BIOS_BASE (0xe8000)
94 #define BIOS_SIZE (0x18000)
96 #define BIOS_BASE (0xf0000)
97 #define BIOS_SIZE (0x10000)
99 #define BIOS_COUNT (BIOS_SIZE/4)
101 #define CMOS_REG (0x70)
102 #define CMOS_DATA (0x71)
103 #define BIOS_RESET (0x0f)
104 #define BIOS_WARM (0x0a)
106 #define PROCENTRY_FLAG_EN 0x01
107 #define PROCENTRY_FLAG_BP 0x02
108 #define IOAPICENTRY_FLAG_EN 0x01
111 /* MP Floating Pointer Structure */
112 typedef struct MPFPS {
125 /* MP Configuration Table Header */
126 typedef struct MPCTH {
128 u_short base_table_length;
132 u_char product_id[12];
133 void *oem_table_pointer;
134 u_short oem_table_size;
137 u_short extended_table_length;
138 u_char extended_table_checksum;
143 typedef struct PROCENTRY {
148 u_long cpu_signature;
149 u_long feature_flags;
154 typedef struct BUSENTRY {
160 typedef struct IOAPICENTRY {
166 } *io_apic_entry_ptr;
168 typedef struct INTENTRY {
178 /* descriptions of MP basetable entries */
179 typedef struct BASETABLE_ENTRY {
186 * this code MUST be enabled here and in mpboot.s.
187 * it follows the very early stages of AP boot by placing values in CMOS ram.
188 * it NORMALLY will never be needed and thus the primitive method for enabling.
193 #if defined(CHECK_POINTS) && !defined(PC98)
194 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
195 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
197 #define CHECK_INIT(D); \
198 CHECK_WRITE(0x34, (D)); \
199 CHECK_WRITE(0x35, (D)); \
200 CHECK_WRITE(0x36, (D)); \
201 CHECK_WRITE(0x37, (D)); \
202 CHECK_WRITE(0x38, (D)); \
203 CHECK_WRITE(0x39, (D));
205 #define CHECK_PRINT(S); \
206 printf("%s: %d, %d, %d, %d, %d, %d\n", \
215 #else /* CHECK_POINTS */
217 #define CHECK_INIT(D)
218 #define CHECK_PRINT(S)
220 #endif /* CHECK_POINTS */
223 * Values to send to the POST hardware.
225 #define MP_BOOTADDRESS_POST 0x10
226 #define MP_PROBE_POST 0x11
227 #define MPTABLE_PASS1_POST 0x12
229 #define MP_START_POST 0x13
230 #define MP_ENABLE_POST 0x14
231 #define MPTABLE_PASS2_POST 0x15
233 #define START_ALL_APS_POST 0x16
234 #define INSTALL_AP_TRAMP_POST 0x17
235 #define START_AP_POST 0x18
237 #define MP_ANNOUNCE_POST 0x19
239 /* used to hold the AP's until we are ready to release them */
240 struct mtx ap_boot_mtx;
242 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
243 int current_postcode;
245 /** XXX FIXME: what system files declare these??? */
246 extern struct region_descriptor r_gdt, r_idt;
248 int bsp_apic_ready = 0; /* flags useability of BSP apic */
249 int mp_ncpus; /* # of CPUs, including BSP */
250 int mp_naps; /* # of Applications processors */
251 int mp_nbusses; /* # of busses */
252 int mp_napics; /* # of IO APICs */
253 int boot_cpu_id; /* designated BSP */
254 vm_offset_t cpu_apic_address;
255 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
258 u_int32_t cpu_apic_versions[MAXCPU];
259 u_int32_t *io_apic_versions;
261 #ifdef APIC_INTR_REORDER
263 volatile int *location;
265 } apic_isrbit_location[32];
268 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
271 * APIC ID logical/physical mapping structures.
272 * We oversize these to simplify boot-time config.
274 int cpu_num_to_apic_id[NAPICID];
275 int io_num_to_apic_id[NAPICID];
276 int apic_id_to_logical[NAPICID];
279 /* Bitmap of all available CPUs */
282 /* AP uses this during bootstrap. Do not staticize. */
286 /* Hotwire a 0->4MB V==P mapping */
287 extern pt_entry_t *KPTphys;
289 /* SMP page table page */
290 extern pt_entry_t *SMPpt;
292 struct pcb stoppcbs[MAXCPU];
294 int smp_started; /* has the system started? */
295 int smp_active = 0; /* are the APs allowed to run? */
296 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
298 /* XXX maybe should be hw.ncpu */
299 static int smp_cpus = 1; /* how many cpu's running */
300 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
302 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
303 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
305 /* Enable forwarding of a signal to a process running on a different CPU */
306 static int forward_signal_enabled = 1;
307 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
308 &forward_signal_enabled, 0, "");
310 /* Enable forwarding of roundrobin to all other cpus */
311 static int forward_roundrobin_enabled = 1;
312 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
313 &forward_roundrobin_enabled, 0, "");
317 * Local data and functions.
320 /* Set to 1 once we're ready to let the APs out of the pen. */
321 static volatile int aps_ready = 0;
323 static int mp_capable;
324 static u_int boot_address;
325 static u_int base_memory;
327 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
328 static mpfps_t mpfps;
329 static int search_for_sig(u_int32_t target, int count);
330 static void mp_enable(u_int boot_addr);
332 static void mptable_pass1(void);
333 static int mptable_pass2(void);
334 static void default_mp_table(int type);
335 static void fix_mp_table(void);
336 static void setup_apic_irq_mapping(void);
337 static void init_locks(void);
338 static int start_all_aps(u_int boot_addr);
339 static void install_ap_tramp(u_int boot_addr);
340 static int start_ap(int logicalCpu, u_int boot_addr);
342 static int apic_int_is_bus_type(int intr, int bus_type);
343 static void release_aps(void *dummy);
346 * initialize all the SMP locks
349 /* critical region around IO APIC, apic_imen */
352 /* lock region used by kernel profiling */
353 struct mtx mcount_mtx;
356 /* locks com (tty) data/hardware accesses: a FASTINTR() */
358 #endif /* USE_COMLOCK */
360 /* lock around the MP rendezvous */
361 static struct mtx smp_rv_mtx;
363 /* only 1 CPU can panic at a time :) */
364 struct mtx panic_mtx;
370 * XXX The mcount mutex probably needs to be statically initialized,
371 * since it will be used even in the function calls that get us to this
374 mtx_init(&mcount_mtx, "mcount", MTX_DEF);
376 mtx_init(&smp_rv_mtx, "smp rendezvous", MTX_SPIN);
377 mtx_init(&panic_mtx, "panic", MTX_DEF);
380 mtx_init(&com_mtx, "com", MTX_SPIN);
381 #endif /* USE_COMLOCK */
383 mtx_init(&ap_boot_mtx, "ap boot", MTX_SPIN);
387 * Calculate usable address in base memory for AP trampoline code.
390 mp_bootaddress(u_int basemem)
392 POSTCODE(MP_BOOTADDRESS_POST);
394 base_memory = basemem * 1024; /* convert to bytes */
396 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
397 if ((base_memory - boot_address) < bootMP_size)
398 boot_address -= 4096; /* not enough, lower by 4k */
405 * Look for an Intel MP spec table (ie, SMP capable hardware).
414 POSTCODE(MP_PROBE_POST);
416 /* see if EBDA exists */
417 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
418 /* search first 1K of EBDA */
419 target = (u_int32_t) (segment << 4);
420 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
423 /* last 1K of base memory, effective 'top of base' passed in */
424 target = (u_int32_t) (base_memory - 0x400);
425 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
429 /* search the BIOS */
430 target = (u_int32_t) BIOS_BASE;
431 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
440 /* calculate needed resources */
444 /* flag fact that we are running multiple processors */
451 * Initialize the SMP hardware and the APIC and start up the AP's.
456 POSTCODE(MP_START_POST);
458 /* look for MP capable motherboard */
460 mp_enable(boot_address);
462 panic("MP hardware not found!");
467 * Print various information about the SMP system hardware and setup.
474 POSTCODE(MP_ANNOUNCE_POST);
476 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
477 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
478 printf(", version: 0x%08x", cpu_apic_versions[0]);
479 printf(", at 0x%08x\n", cpu_apic_address);
480 for (x = 1; x <= mp_naps; ++x) {
481 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
482 printf(", version: 0x%08x", cpu_apic_versions[x]);
483 printf(", at 0x%08x\n", cpu_apic_address);
487 for (x = 0; x < mp_napics; ++x) {
488 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
489 printf(", version: 0x%08x", io_apic_versions[x]);
490 printf(", at 0x%08x\n", io_apic_address[x]);
493 printf(" Warning: APIC I/O disabled\n");
498 * AP cpu's call this to sync up protected mode.
504 int x, myid = bootAP;
506 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
507 gdt_segs[GPROC0_SEL].ssd_base =
508 (int) &SMP_prvspace[myid].globaldata.gd_common_tss;
509 SMP_prvspace[myid].globaldata.gd_prvspace =
510 &SMP_prvspace[myid].globaldata;
512 for (x = 0; x < NGDT; x++) {
513 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
516 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
517 r_gdt.rd_base = (int) &gdt[myid * NGDT];
518 lgdt(&r_gdt); /* does magic intra-segment return */
523 PCPU_SET(currentldt, _default_ldt);
525 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
526 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
527 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
528 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
529 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
530 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
531 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
540 * Final configuration of the BSP's local APIC:
541 * - disable 'pic mode'.
542 * - disable 'virtual wire mode'.
546 bsp_apic_configure(void)
551 /* leave 'pic mode' if necessary */
553 outb(0x22, 0x70); /* select IMCR */
554 byte = inb(0x23); /* current contents */
555 byte |= 0x01; /* mask external INTR */
556 outb(0x23, byte); /* disconnect 8259s/NMI */
559 /* mask lint0 (the 8259 'virtual wire' connection) */
560 temp = lapic.lvt_lint0;
561 temp |= APIC_LVT_M; /* set the mask */
562 lapic.lvt_lint0 = temp;
564 /* setup lint1 to handle NMI */
565 temp = lapic.lvt_lint1;
566 temp &= ~APIC_LVT_M; /* clear the mask */
567 lapic.lvt_lint1 = temp;
570 apic_dump("bsp_apic_configure()");
575 /*******************************************************************
576 * local functions and data
580 * start the SMP system
583 mp_enable(u_int boot_addr)
591 POSTCODE(MP_ENABLE_POST);
593 /* turn on 4MB of V == P addressing so we can get to MP table */
594 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
597 /* examine the MP table for needed info, uses physical addresses */
603 /* can't process default configs till the CPU APIC is pmapped */
607 /* post scan cleanup */
609 setup_apic_irq_mapping();
613 /* fill the LOGICAL io_apic_versions table */
614 for (apic = 0; apic < mp_napics; ++apic) {
615 ux = io_apic_read(apic, IOAPIC_VER);
616 io_apic_versions[apic] = ux;
617 io_apic_set_id(apic, IO_TO_ID(apic));
620 /* program each IO APIC in the system */
621 for (apic = 0; apic < mp_napics; ++apic)
622 if (io_apic_setup(apic) < 0)
623 panic("IO APIC setup failure");
625 /* install a 'Spurious INTerrupt' vector */
626 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
627 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
629 /* install an inter-CPU IPI for TLB invalidation */
630 setidt(XINVLTLB_OFFSET, Xinvltlb,
631 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
634 /* install an inter-CPU IPI for reading processor state */
635 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
636 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
639 /* install an inter-CPU IPI for all-CPU rendezvous */
640 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
641 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
643 /* install an inter-CPU IPI for forcing an additional software trap */
644 setidt(XCPUAST_OFFSET, Xcpuast,
645 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
647 /* install an inter-CPU IPI for CPU stop/restart */
648 setidt(XCPUSTOP_OFFSET, Xcpustop,
649 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
651 #if defined(TEST_TEST1)
652 /* install a "fake hardware INTerrupt" vector */
653 setidt(XTEST1_OFFSET, Xtest1,
654 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
655 #endif /** TEST_TEST1 */
659 /* initialize all SMP locks */
662 /* start each Application Processor */
663 start_all_aps(boot_addr);
668 * look for the MP spec signature
671 /* string defined by the Intel MP Spec as identifying the MP table */
672 #define MP_SIG 0x5f504d5f /* _MP_ */
673 #define NEXT(X) ((X) += 4)
675 search_for_sig(u_int32_t target, int count)
678 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
680 for (x = 0; x < count; NEXT(x))
681 if (addr[x] == MP_SIG)
682 /* make array index a byte index */
683 return (target + (x * sizeof(u_int32_t)));
689 static basetable_entry basetable_entry_types[] =
691 {0, 20, "Processor"},
698 typedef struct BUSDATA {
700 enum busTypes bus_type;
703 typedef struct INTDATA {
713 typedef struct BUSTYPENAME {
718 static bus_type_name bus_type_table[] =
724 {UNKNOWN_BUSTYPE, "---"},
727 {UNKNOWN_BUSTYPE, "---"},
728 {UNKNOWN_BUSTYPE, "---"},
729 {UNKNOWN_BUSTYPE, "---"},
730 {UNKNOWN_BUSTYPE, "---"},
731 {UNKNOWN_BUSTYPE, "---"},
733 {UNKNOWN_BUSTYPE, "---"},
734 {UNKNOWN_BUSTYPE, "---"},
735 {UNKNOWN_BUSTYPE, "---"},
736 {UNKNOWN_BUSTYPE, "---"},
738 {UNKNOWN_BUSTYPE, "---"}
740 /* from MP spec v1.4, table 5-1 */
741 static int default_data[7][5] =
743 /* nbus, id0, type0, id1, type1 */
744 {1, 0, ISA, 255, 255},
745 {1, 0, EISA, 255, 255},
746 {1, 0, EISA, 255, 255},
747 {1, 0, MCA, 255, 255},
749 {2, 0, EISA, 1, PCI},
755 static bus_datum *bus_data;
757 /* the IO INT data, one entry per possible APIC INTerrupt */
758 static io_int *io_apic_ints;
762 static int processor_entry __P((proc_entry_ptr entry, int cpu));
763 static int bus_entry __P((bus_entry_ptr entry, int bus));
764 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic));
765 static int int_entry __P((int_entry_ptr entry, int intr));
766 static int lookup_bus_type __P((char *name));
770 * 1st pass on motherboard's Intel MP specification table.
776 * cpu_apic_address (common to all CPUs)
793 POSTCODE(MPTABLE_PASS1_POST);
795 /* clear various tables */
796 for (x = 0; x < NAPICID; ++x) {
797 io_apic_address[x] = ~0; /* IO APIC address table */
800 /* init everything to empty */
806 /* check for use of 'default' configuration */
807 if (MPFPS_MPFB1 != 0) {
808 /* use default addresses */
809 cpu_apic_address = DEFAULT_APIC_BASE;
810 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
812 /* fill in with defaults */
813 mp_naps = 2; /* includes BSP */
814 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
821 if ((cth = mpfps->pap) == 0)
822 panic("MP Configuration Table Header MISSING!");
824 cpu_apic_address = (vm_offset_t) cth->apic_address;
826 /* walk the table, recording info of interest */
827 totalSize = cth->base_table_length - sizeof(struct MPCTH);
828 position = (u_char *) cth + sizeof(struct MPCTH);
829 count = cth->entry_count;
832 switch (type = *(u_char *) position) {
833 case 0: /* processor_entry */
834 if (((proc_entry_ptr)position)->cpu_flags
838 case 1: /* bus_entry */
841 case 2: /* io_apic_entry */
842 if (((io_apic_entry_ptr)position)->apic_flags
843 & IOAPICENTRY_FLAG_EN)
844 io_apic_address[mp_napics++] =
845 (vm_offset_t)((io_apic_entry_ptr)
846 position)->apic_address;
848 case 3: /* int_entry */
851 case 4: /* int_entry */
854 panic("mpfps Base Table HOSED!");
858 totalSize -= basetable_entry_types[type].length;
859 (u_char*)position += basetable_entry_types[type].length;
863 /* qualify the numbers */
864 if (mp_naps > MAXCPU) {
865 printf("Warning: only using %d of %d available CPUs!\n",
872 * This is also used as a counter while starting the APs.
876 --mp_naps; /* subtract the BSP */
881 * 2nd pass on motherboard's Intel MP specification table.
885 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
886 * CPU_TO_ID(N), logical CPU to APIC ID table
887 * IO_TO_ID(N), logical IO to APIC ID table
900 int apic, bus, cpu, intr;
904 POSTCODE(MPTABLE_PASS2_POST);
906 pgeflag = 0; /* XXX - Not used under SMP yet. */
908 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
910 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
912 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
914 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
917 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
919 for (i = 0; i < mp_napics; i++) {
920 for (j = 0; j < mp_napics; j++) {
921 /* same page frame as a previous IO apic? */
922 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
923 (io_apic_address[i] & PG_FRAME)) {
924 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
925 + (NPTEPG-2-j) * PAGE_SIZE
926 + (io_apic_address[i] & PAGE_MASK));
929 /* use this slot if available */
930 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
931 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
932 pgeflag | (io_apic_address[i] & PG_FRAME));
933 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
934 + (NPTEPG-2-j) * PAGE_SIZE
935 + (io_apic_address[i] & PAGE_MASK));
941 /* clear various tables */
942 for (x = 0; x < NAPICID; ++x) {
943 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
944 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
945 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
948 /* clear bus data table */
949 for (x = 0; x < mp_nbusses; ++x)
950 bus_data[x].bus_id = 0xff;
952 /* clear IO APIC INT table */
953 for (x = 0; x < (nintrs + 1); ++x) {
954 io_apic_ints[x].int_type = 0xff;
955 io_apic_ints[x].int_vector = 0xff;
958 /* setup the cpu/apic mapping arrays */
961 /* record whether PIC or virtual-wire mode */
962 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
964 /* check for use of 'default' configuration */
965 if (MPFPS_MPFB1 != 0)
966 return MPFPS_MPFB1; /* return default configuration type */
968 if ((cth = mpfps->pap) == 0)
969 panic("MP Configuration Table Header MISSING!");
971 /* walk the table, recording info of interest */
972 totalSize = cth->base_table_length - sizeof(struct MPCTH);
973 position = (u_char *) cth + sizeof(struct MPCTH);
974 count = cth->entry_count;
975 apic = bus = intr = 0;
976 cpu = 1; /* pre-count the BSP */
979 switch (type = *(u_char *) position) {
981 if (processor_entry(position, cpu))
985 if (bus_entry(position, bus))
989 if (io_apic_entry(position, apic))
993 if (int_entry(position, intr))
997 /* int_entry(position); */
1000 panic("mpfps Base Table HOSED!");
1004 totalSize -= basetable_entry_types[type].length;
1005 (u_char *) position += basetable_entry_types[type].length;
1008 if (boot_cpu_id == -1)
1009 panic("NO BSP found!");
1011 /* report fact that its NOT a default configuration */
1017 assign_apic_irq(int apic, int intpin, int irq)
1021 if (int_to_apicintpin[irq].ioapic != -1)
1022 panic("assign_apic_irq: inconsistent table");
1024 int_to_apicintpin[irq].ioapic = apic;
1025 int_to_apicintpin[irq].int_pin = intpin;
1026 int_to_apicintpin[irq].apic_address = ioapic[apic];
1027 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1029 for (x = 0; x < nintrs; x++) {
1030 if ((io_apic_ints[x].int_type == 0 ||
1031 io_apic_ints[x].int_type == 3) &&
1032 io_apic_ints[x].int_vector == 0xff &&
1033 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1034 io_apic_ints[x].dst_apic_int == intpin)
1035 io_apic_ints[x].int_vector = irq;
1040 revoke_apic_irq(int irq)
1046 if (int_to_apicintpin[irq].ioapic == -1)
1047 panic("assign_apic_irq: inconsistent table");
1049 oldapic = int_to_apicintpin[irq].ioapic;
1050 oldintpin = int_to_apicintpin[irq].int_pin;
1052 int_to_apicintpin[irq].ioapic = -1;
1053 int_to_apicintpin[irq].int_pin = 0;
1054 int_to_apicintpin[irq].apic_address = NULL;
1055 int_to_apicintpin[irq].redirindex = 0;
1057 for (x = 0; x < nintrs; x++) {
1058 if ((io_apic_ints[x].int_type == 0 ||
1059 io_apic_ints[x].int_type == 3) &&
1060 io_apic_ints[x].int_vector == 0xff &&
1061 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1062 io_apic_ints[x].dst_apic_int == oldintpin)
1063 io_apic_ints[x].int_vector = 0xff;
1069 allocate_apic_irq(int intr)
1075 if (io_apic_ints[intr].int_vector != 0xff)
1076 return; /* Interrupt handler already assigned */
1078 if (io_apic_ints[intr].int_type != 0 &&
1079 (io_apic_ints[intr].int_type != 3 ||
1080 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1081 io_apic_ints[intr].dst_apic_int == 0)))
1082 return; /* Not INT or ExtInt on != (0, 0) */
1085 while (irq < APIC_INTMAPSIZE &&
1086 int_to_apicintpin[irq].ioapic != -1)
1089 if (irq >= APIC_INTMAPSIZE)
1090 return; /* No free interrupt handlers */
1092 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1093 intpin = io_apic_ints[intr].dst_apic_int;
1095 assign_apic_irq(apic, intpin, irq);
1096 io_apic_setup_intpin(apic, intpin);
1101 swap_apic_id(int apic, int oldid, int newid)
1108 return; /* Nothing to do */
1110 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1111 apic, oldid, newid);
1113 /* Swap physical APIC IDs in interrupt entries */
1114 for (x = 0; x < nintrs; x++) {
1115 if (io_apic_ints[x].dst_apic_id == oldid)
1116 io_apic_ints[x].dst_apic_id = newid;
1117 else if (io_apic_ints[x].dst_apic_id == newid)
1118 io_apic_ints[x].dst_apic_id = oldid;
1121 /* Swap physical APIC IDs in IO_TO_ID mappings */
1122 for (oapic = 0; oapic < mp_napics; oapic++)
1123 if (IO_TO_ID(oapic) == newid)
1126 if (oapic < mp_napics) {
1127 printf("Changing APIC ID for IO APIC #%d from "
1128 "%d to %d in MP table\n",
1129 oapic, newid, oldid);
1130 IO_TO_ID(oapic) = oldid;
1132 IO_TO_ID(apic) = newid;
1137 fix_id_to_io_mapping(void)
1141 for (x = 0; x < NAPICID; x++)
1144 for (x = 0; x <= mp_naps; x++)
1145 if (CPU_TO_ID(x) < NAPICID)
1146 ID_TO_IO(CPU_TO_ID(x)) = x;
1148 for (x = 0; x < mp_napics; x++)
1149 if (IO_TO_ID(x) < NAPICID)
1150 ID_TO_IO(IO_TO_ID(x)) = x;
1155 first_free_apic_id(void)
1159 for (freeid = 0; freeid < NAPICID; freeid++) {
1160 for (x = 0; x <= mp_naps; x++)
1161 if (CPU_TO_ID(x) == freeid)
1165 for (x = 0; x < mp_napics; x++)
1166 if (IO_TO_ID(x) == freeid)
1177 io_apic_id_acceptable(int apic, int id)
1179 int cpu; /* Logical CPU number */
1180 int oapic; /* Logical IO APIC number for other IO APIC */
1183 return 0; /* Out of range */
1185 for (cpu = 0; cpu <= mp_naps; cpu++)
1186 if (CPU_TO_ID(cpu) == id)
1187 return 0; /* Conflict with CPU */
1189 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1190 if (IO_TO_ID(oapic) == id)
1191 return 0; /* Conflict with other APIC */
1193 return 1; /* ID is acceptable for IO APIC */
1198 * parse an Intel MP specification table
1205 int bus_0 = 0; /* Stop GCC warning */
1206 int bus_pci = 0; /* Stop GCC warning */
1208 int apic; /* IO APIC unit number */
1209 int freeid; /* Free physical APIC ID */
1210 int physid; /* Current physical IO APIC ID */
1213 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1214 * did it wrong. The MP spec says that when more than 1 PCI bus
1215 * exists the BIOS must begin with bus entries for the PCI bus and use
1216 * actual PCI bus numbering. This implies that when only 1 PCI bus
1217 * exists the BIOS can choose to ignore this ordering, and indeed many
1218 * MP motherboards do ignore it. This causes a problem when the PCI
1219 * sub-system makes requests of the MP sub-system based on PCI bus
1220 * numbers. So here we look for the situation and renumber the
1221 * busses and associated INTs in an effort to "make it right".
1224 /* find bus 0, PCI bus, count the number of PCI busses */
1225 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1226 if (bus_data[x].bus_id == 0) {
1229 if (bus_data[x].bus_type == PCI) {
1235 * bus_0 == slot of bus with ID of 0
1236 * bus_pci == slot of last PCI bus encountered
1239 /* check the 1 PCI bus case for sanity */
1240 /* if it is number 0 all is well */
1241 if (num_pci_bus == 1 &&
1242 bus_data[bus_pci].bus_id != 0) {
1244 /* mis-numbered, swap with whichever bus uses slot 0 */
1246 /* swap the bus entry types */
1247 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1248 bus_data[bus_0].bus_type = PCI;
1250 /* swap each relavant INTerrupt entry */
1251 id = bus_data[bus_pci].bus_id;
1252 for (x = 0; x < nintrs; ++x) {
1253 if (io_apic_ints[x].src_bus_id == id) {
1254 io_apic_ints[x].src_bus_id = 0;
1256 else if (io_apic_ints[x].src_bus_id == 0) {
1257 io_apic_ints[x].src_bus_id = id;
1262 /* Assign IO APIC IDs.
1264 * First try the existing ID. If a conflict is detected, try
1265 * the ID in the MP table. If a conflict is still detected, find
1268 * We cannot use the ID_TO_IO table before all conflicts has been
1269 * resolved and the table has been corrected.
1271 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1273 /* First try to use the value set by the BIOS */
1274 physid = io_apic_get_id(apic);
1275 if (io_apic_id_acceptable(apic, physid)) {
1276 if (IO_TO_ID(apic) != physid)
1277 swap_apic_id(apic, IO_TO_ID(apic), physid);
1281 /* Then check if the value in the MP table is acceptable */
1282 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1285 /* Last resort, find a free APIC ID and use it */
1286 freeid = first_free_apic_id();
1287 if (freeid >= NAPICID)
1288 panic("No free physical APIC IDs found");
1290 if (io_apic_id_acceptable(apic, freeid)) {
1291 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1294 panic("Free physical APIC ID not usable");
1296 fix_id_to_io_mapping();
1298 /* detect and fix broken Compaq MP table */
1299 if (apic_int_type(0, 0) == -1) {
1300 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1301 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1302 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1303 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1304 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1305 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1311 /* Assign low level interrupt handlers */
1313 setup_apic_irq_mapping(void)
1319 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1320 int_to_apicintpin[x].ioapic = -1;
1321 int_to_apicintpin[x].int_pin = 0;
1322 int_to_apicintpin[x].apic_address = NULL;
1323 int_to_apicintpin[x].redirindex = 0;
1326 /* First assign ISA/EISA interrupts */
1327 for (x = 0; x < nintrs; x++) {
1328 int_vector = io_apic_ints[x].src_bus_irq;
1329 if (int_vector < APIC_INTMAPSIZE &&
1330 io_apic_ints[x].int_vector == 0xff &&
1331 int_to_apicintpin[int_vector].ioapic == -1 &&
1332 (apic_int_is_bus_type(x, ISA) ||
1333 apic_int_is_bus_type(x, EISA)) &&
1334 io_apic_ints[x].int_type == 0) {
1335 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1336 io_apic_ints[x].dst_apic_int,
1341 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1342 for (x = 0; x < nintrs; x++) {
1343 if (io_apic_ints[x].dst_apic_int == 0 &&
1344 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1345 io_apic_ints[x].int_vector == 0xff &&
1346 int_to_apicintpin[0].ioapic == -1 &&
1347 io_apic_ints[x].int_type == 3) {
1348 assign_apic_irq(0, 0, 0);
1352 /* PCI interrupt assignment is deferred */
1357 processor_entry(proc_entry_ptr entry, int cpu)
1359 /* check for usability */
1360 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1363 if(entry->apic_id >= NAPICID)
1364 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1365 /* check for BSP flag */
1366 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1367 boot_cpu_id = entry->apic_id;
1368 CPU_TO_ID(0) = entry->apic_id;
1369 ID_TO_CPU(entry->apic_id) = 0;
1370 return 0; /* its already been counted */
1373 /* add another AP to list, if less than max number of CPUs */
1374 else if (cpu < MAXCPU) {
1375 CPU_TO_ID(cpu) = entry->apic_id;
1376 ID_TO_CPU(entry->apic_id) = cpu;
1385 bus_entry(bus_entry_ptr entry, int bus)
1390 /* encode the name into an index */
1391 for (x = 0; x < 6; ++x) {
1392 if ((c = entry->bus_type[x]) == ' ')
1398 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1399 panic("unknown bus type: '%s'", name);
1401 bus_data[bus].bus_id = entry->bus_id;
1402 bus_data[bus].bus_type = x;
1409 io_apic_entry(io_apic_entry_ptr entry, int apic)
1411 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1414 IO_TO_ID(apic) = entry->apic_id;
1415 if (entry->apic_id < NAPICID)
1416 ID_TO_IO(entry->apic_id) = apic;
1423 lookup_bus_type(char *name)
1427 for (x = 0; x < MAX_BUSTYPE; ++x)
1428 if (strcmp(bus_type_table[x].name, name) == 0)
1429 return bus_type_table[x].type;
1431 return UNKNOWN_BUSTYPE;
1436 int_entry(int_entry_ptr entry, int intr)
1440 io_apic_ints[intr].int_type = entry->int_type;
1441 io_apic_ints[intr].int_flags = entry->int_flags;
1442 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1443 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1444 if (entry->dst_apic_id == 255) {
1445 /* This signal goes to all IO APICS. Select an IO APIC
1446 with sufficient number of interrupt pins */
1447 for (apic = 0; apic < mp_napics; apic++)
1448 if (((io_apic_read(apic, IOAPIC_VER) &
1449 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1450 entry->dst_apic_int)
1452 if (apic < mp_napics)
1453 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1455 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1457 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1458 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1465 apic_int_is_bus_type(int intr, int bus_type)
1469 for (bus = 0; bus < mp_nbusses; ++bus)
1470 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1471 && ((int) bus_data[bus].bus_type == bus_type))
1479 * Given a traditional ISA INT mask, return an APIC mask.
1482 isa_apic_mask(u_int isa_mask)
1487 #if defined(SKIP_IRQ15_REDIRECT)
1488 if (isa_mask == (1 << 15)) {
1489 printf("skipping ISA IRQ15 redirect\n");
1492 #endif /* SKIP_IRQ15_REDIRECT */
1494 isa_irq = ffs(isa_mask); /* find its bit position */
1495 if (isa_irq == 0) /* doesn't exist */
1497 --isa_irq; /* make it zero based */
1499 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1503 return (1 << apic_pin); /* convert pin# to a mask */
1508 * Determine which APIC pin an ISA/EISA INT is attached to.
1510 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1511 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1512 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1513 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1515 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1517 isa_apic_irq(int isa_irq)
1521 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1522 if (INTTYPE(intr) == 0) { /* standard INT */
1523 if (SRCBUSIRQ(intr) == isa_irq) {
1524 if (apic_int_is_bus_type(intr, ISA) ||
1525 apic_int_is_bus_type(intr, EISA)) {
1526 if (INTIRQ(intr) == 0xff)
1527 return -1; /* unassigned */
1528 return INTIRQ(intr); /* found */
1533 return -1; /* NOT found */
1538 * Determine which APIC pin a PCI INT is attached to.
1540 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1541 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1542 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1544 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1548 --pciInt; /* zero based */
1550 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1551 if ((INTTYPE(intr) == 0) /* standard INT */
1552 && (SRCBUSID(intr) == pciBus)
1553 && (SRCBUSDEVICE(intr) == pciDevice)
1554 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1555 if (apic_int_is_bus_type(intr, PCI)) {
1556 if (INTIRQ(intr) == 0xff)
1557 allocate_apic_irq(intr);
1558 if (INTIRQ(intr) == 0xff)
1559 return -1; /* unassigned */
1560 return INTIRQ(intr); /* exact match */
1563 return -1; /* NOT found */
1567 next_apic_irq(int irq)
1574 for (intr = 0; intr < nintrs; intr++) {
1575 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1577 bus = SRCBUSID(intr);
1578 bustype = apic_bus_type(bus);
1579 if (bustype != ISA &&
1585 if (intr >= nintrs) {
1588 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1589 if (INTTYPE(ointr) != 0)
1591 if (bus != SRCBUSID(ointr))
1593 if (bustype == PCI) {
1594 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1596 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1599 if (bustype == ISA || bustype == EISA) {
1600 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1603 if (INTPIN(intr) == INTPIN(ointr))
1607 if (ointr >= nintrs) {
1610 return INTIRQ(ointr);
1624 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1627 * Exactly what this means is unclear at this point. It is a solution
1628 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1629 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1630 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1634 undirect_isa_irq(int rirq)
1638 printf("Freeing redirected ISA irq %d.\n", rirq);
1639 /** FIXME: tickle the MB redirector chip */
1643 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1650 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1653 undirect_pci_irq(int rirq)
1657 printf("Freeing redirected PCI irq %d.\n", rirq);
1659 /** FIXME: tickle the MB redirector chip */
1663 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1671 * given a bus ID, return:
1672 * the bus type if found
1676 apic_bus_type(int id)
1680 for (x = 0; x < mp_nbusses; ++x)
1681 if (bus_data[x].bus_id == id)
1682 return bus_data[x].bus_type;
1689 * given a LOGICAL APIC# and pin#, return:
1690 * the associated src bus ID if found
1694 apic_src_bus_id(int apic, int pin)
1698 /* search each of the possible INTerrupt sources */
1699 for (x = 0; x < nintrs; ++x)
1700 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1701 (pin == io_apic_ints[x].dst_apic_int))
1702 return (io_apic_ints[x].src_bus_id);
1704 return -1; /* NOT found */
1709 * given a LOGICAL APIC# and pin#, return:
1710 * the associated src bus IRQ if found
1714 apic_src_bus_irq(int apic, int pin)
1718 for (x = 0; x < nintrs; x++)
1719 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1720 (pin == io_apic_ints[x].dst_apic_int))
1721 return (io_apic_ints[x].src_bus_irq);
1723 return -1; /* NOT found */
1728 * given a LOGICAL APIC# and pin#, return:
1729 * the associated INTerrupt type if found
1733 apic_int_type(int apic, int pin)
1737 /* search each of the possible INTerrupt sources */
1738 for (x = 0; x < nintrs; ++x)
1739 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1740 (pin == io_apic_ints[x].dst_apic_int))
1741 return (io_apic_ints[x].int_type);
1743 return -1; /* NOT found */
1747 apic_irq(int apic, int pin)
1752 for (x = 0; x < nintrs; ++x)
1753 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1754 (pin == io_apic_ints[x].dst_apic_int)) {
1755 res = io_apic_ints[x].int_vector;
1758 if (apic != int_to_apicintpin[res].ioapic)
1759 panic("apic_irq: inconsistent table");
1760 if (pin != int_to_apicintpin[res].int_pin)
1761 panic("apic_irq inconsistent table (2)");
1769 * given a LOGICAL APIC# and pin#, return:
1770 * the associated trigger mode if found
1774 apic_trigger(int apic, int pin)
1778 /* search each of the possible INTerrupt sources */
1779 for (x = 0; x < nintrs; ++x)
1780 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1781 (pin == io_apic_ints[x].dst_apic_int))
1782 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1784 return -1; /* NOT found */
1789 * given a LOGICAL APIC# and pin#, return:
1790 * the associated 'active' level if found
1794 apic_polarity(int apic, int pin)
1798 /* search each of the possible INTerrupt sources */
1799 for (x = 0; x < nintrs; ++x)
1800 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1801 (pin == io_apic_ints[x].dst_apic_int))
1802 return (io_apic_ints[x].int_flags & 0x03);
1804 return -1; /* NOT found */
1809 * set data according to MP defaults
1810 * FIXME: probably not complete yet...
1813 default_mp_table(int type)
1816 #if defined(APIC_IO)
1819 #endif /* APIC_IO */
1822 printf(" MP default config type: %d\n", type);
1825 printf(" bus: ISA, APIC: 82489DX\n");
1828 printf(" bus: EISA, APIC: 82489DX\n");
1831 printf(" bus: EISA, APIC: 82489DX\n");
1834 printf(" bus: MCA, APIC: 82489DX\n");
1837 printf(" bus: ISA+PCI, APIC: Integrated\n");
1840 printf(" bus: EISA+PCI, APIC: Integrated\n");
1843 printf(" bus: MCA+PCI, APIC: Integrated\n");
1846 printf(" future type\n");
1852 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1853 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1856 CPU_TO_ID(0) = boot_cpu_id;
1857 ID_TO_CPU(boot_cpu_id) = 0;
1859 /* one and only AP */
1860 CPU_TO_ID(1) = ap_cpu_id;
1861 ID_TO_CPU(ap_cpu_id) = 1;
1863 #if defined(APIC_IO)
1864 /* one and only IO APIC */
1865 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1868 * sanity check, refer to MP spec section 3.6.6, last paragraph
1869 * necessary as some hardware isn't properly setting up the IO APIC
1871 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1872 if (io_apic_id != 2) {
1874 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1875 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1876 io_apic_set_id(0, 2);
1879 IO_TO_ID(0) = io_apic_id;
1880 ID_TO_IO(io_apic_id) = 0;
1881 #endif /* APIC_IO */
1883 /* fill out bus entries */
1892 bus_data[0].bus_id = default_data[type - 1][1];
1893 bus_data[0].bus_type = default_data[type - 1][2];
1894 bus_data[1].bus_id = default_data[type - 1][3];
1895 bus_data[1].bus_type = default_data[type - 1][4];
1898 /* case 4: case 7: MCA NOT supported */
1899 default: /* illegal/reserved */
1900 panic("BAD default MP config: %d", type);
1904 #if defined(APIC_IO)
1905 /* general cases from MP v1.4, table 5-2 */
1906 for (pin = 0; pin < 16; ++pin) {
1907 io_apic_ints[pin].int_type = 0;
1908 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1909 io_apic_ints[pin].src_bus_id = 0;
1910 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1911 io_apic_ints[pin].dst_apic_id = io_apic_id;
1912 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1915 /* special cases from MP v1.4, table 5-2 */
1917 io_apic_ints[2].int_type = 0xff; /* N/C */
1918 io_apic_ints[13].int_type = 0xff; /* N/C */
1919 #if !defined(APIC_MIXED_MODE)
1921 panic("sorry, can't support type 2 default yet");
1922 #endif /* APIC_MIXED_MODE */
1925 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1928 io_apic_ints[0].int_type = 0xff; /* N/C */
1930 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1931 #endif /* APIC_IO */
1936 * start each AP in our list
1939 start_all_aps(u_int boot_addr)
1942 u_char mpbiosreason;
1943 u_long mpbioswarmvec;
1944 struct globaldata *gd;
1948 POSTCODE(START_ALL_APS_POST);
1950 /* initialize BSP's local APIC */
1954 /* install the AP 1st level boot code */
1955 install_ap_tramp(boot_addr);
1958 /* save the current value of the warm-start vector */
1959 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1961 outb(CMOS_REG, BIOS_RESET);
1962 mpbiosreason = inb(CMOS_DATA);
1965 /* record BSP in CPU map */
1968 /* set up temporary P==V mapping for AP boot */
1969 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1970 kptbase = (uintptr_t)(void *)KPTphys;
1971 for (x = 0; x < NKPT; x++)
1972 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1973 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1977 for (x = 1; x <= mp_naps; ++x) {
1979 /* This is a bit verbose, it will go away soon. */
1981 /* first page of AP's private space */
1982 pg = x * i386_btop(sizeof(struct privatespace));
1984 /* allocate a new private data page */
1985 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1987 /* wire it into the private page table page */
1988 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd));
1990 /* allocate and set up an idle stack data page */
1991 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1992 for (i = 0; i < UPAGES; i++)
1993 SMPpt[pg + 1 + i] = (pt_entry_t)
1994 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
1996 /* prime data page for it to use */
1997 SLIST_INSERT_HEAD(&cpuhead, gd, gd_allcpu);
2000 /* setup a vector to our boot code */
2001 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2002 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2004 outb(CMOS_REG, BIOS_RESET);
2005 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2008 bootSTK = &SMP_prvspace[x].idlestack[UPAGES*PAGE_SIZE];
2011 /* attempt to start the Application Processor */
2012 CHECK_INIT(99); /* setup checkpoints */
2013 if (!start_ap(x, boot_addr)) {
2014 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2015 CHECK_PRINT("trace"); /* show checkpoints */
2016 /* better panic as the AP may be running loose */
2017 printf("panic y/n? [y] ");
2018 if (cngetc() != 'n')
2021 CHECK_PRINT("trace"); /* show checkpoints */
2023 /* record its version info */
2024 cpu_apic_versions[x] = cpu_apic_versions[0];
2026 all_cpus |= (1 << x); /* record AP in CPU map */
2029 /* build our map of 'other' CPUs */
2030 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2032 /* fill in our (BSP) APIC version */
2033 cpu_apic_versions[0] = lapic.version;
2035 /* restore the warmstart vector */
2036 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2038 outb(CMOS_REG, BIOS_RESET);
2039 outb(CMOS_DATA, mpbiosreason);
2043 * Set up the idle context for the BSP. Similar to above except
2044 * that some was done by locore, some by pmap.c and some is implicit
2045 * because the BSP is cpu#0 and the page is initially zero, and also
2046 * because we can refer to variables by name on the BSP..
2049 /* Allocate and setup BSP idle stack */
2050 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE);
2051 for (i = 0; i < UPAGES; i++)
2052 SMPpt[1 + i] = (pt_entry_t)
2053 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2055 for (x = 0; x < NKPT; x++)
2059 /* number of APs actually started */
2060 return mp_ncpus - 1;
2065 * load the 1st level AP boot code into base memory.
2068 /* targets for relocation */
2069 extern void bigJump(void);
2070 extern void bootCodeSeg(void);
2071 extern void bootDataSeg(void);
2072 extern void MPentry(void);
2073 extern u_int MP_GDT;
2074 extern u_int mp_gdtbase;
2077 install_ap_tramp(u_int boot_addr)
2080 int size = *(int *) ((u_long) & bootMP_size);
2081 u_char *src = (u_char *) ((u_long) bootMP);
2082 u_char *dst = (u_char *) boot_addr + KERNBASE;
2083 u_int boot_base = (u_int) bootMP;
2088 POSTCODE(INSTALL_AP_TRAMP_POST);
2090 for (x = 0; x < size; ++x)
2094 * modify addresses in code we just moved to basemem. unfortunately we
2095 * need fairly detailed info about mpboot.s for this to work. changes
2096 * to mpboot.s might require changes here.
2099 /* boot code is located in KERNEL space */
2100 dst = (u_char *) boot_addr + KERNBASE;
2102 /* modify the lgdt arg */
2103 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2104 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2106 /* modify the ljmp target for MPentry() */
2107 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2108 *dst32 = ((u_int) MPentry - KERNBASE);
2110 /* modify the target for boot code segment */
2111 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2112 dst8 = (u_int8_t *) (dst16 + 1);
2113 *dst16 = (u_int) boot_addr & 0xffff;
2114 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2116 /* modify the target for boot data segment */
2117 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2118 dst8 = (u_int8_t *) (dst16 + 1);
2119 *dst16 = (u_int) boot_addr & 0xffff;
2120 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2125 * this function starts the AP (application processor) identified
2126 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2127 * to accomplish this. This is necessary because of the nuances
2128 * of the different hardware we might encounter. It ain't pretty,
2129 * but it seems to work.
2132 start_ap(int logical_cpu, u_int boot_addr)
2137 u_long icr_lo, icr_hi;
2139 POSTCODE(START_AP_POST);
2141 /* get the PHYSICAL APIC ID# */
2142 physical_cpu = CPU_TO_ID(logical_cpu);
2144 /* calculate the vector */
2145 vector = (boot_addr >> 12) & 0xff;
2147 /* used as a watchpoint to signal AP startup */
2151 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2152 * and running the target CPU. OR this INIT IPI might be latched (P5
2153 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2157 /* setup the address for the target AP */
2158 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2159 icr_hi |= (physical_cpu << 24);
2160 lapic.icr_hi = icr_hi;
2162 /* do an INIT IPI: assert RESET */
2163 icr_lo = lapic.icr_lo & 0xfff00000;
2164 lapic.icr_lo = icr_lo | 0x0000c500;
2166 /* wait for pending status end */
2167 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2170 /* do an INIT IPI: deassert RESET */
2171 lapic.icr_lo = icr_lo | 0x00008500;
2173 /* wait for pending status end */
2174 u_sleep(10000); /* wait ~10mS */
2175 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2179 * next we do a STARTUP IPI: the previous INIT IPI might still be
2180 * latched, (P5 bug) this 1st STARTUP would then terminate
2181 * immediately, and the previously started INIT IPI would continue. OR
2182 * the previous INIT IPI has already run. and this STARTUP IPI will
2183 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2187 /* do a STARTUP IPI */
2188 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2189 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2191 u_sleep(200); /* wait ~200uS */
2194 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2195 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2196 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2197 * recognized after hardware RESET or INIT IPI.
2200 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2201 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2203 u_sleep(200); /* wait ~200uS */
2205 /* wait for it to start */
2206 set_apic_timer(5000000);/* == 5 seconds */
2207 while (read_apic_timer())
2208 if (mp_ncpus > cpus)
2209 return 1; /* return SUCCESS */
2211 return 0; /* return FAILURE */
2215 * Flush the TLB on all other CPU's
2217 * XXX: Needs to handshake and wait for completion before proceding.
2222 #if defined(APIC_IO)
2223 if (smp_started && invltlb_ok)
2224 all_but_self_ipi(XINVLTLB_OFFSET);
2225 #endif /* APIC_IO */
2231 __asm __volatile("invlpg (%0)"::"r"(addr):"memory");
2233 /* send a message to the other CPUs */
2243 * This should be implemented as load_cr3(rcr3()) when load_cr3() is
2246 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
2248 /* send a message to the other CPUs */
2254 * This is called once the rest of the system is up and running and we're
2255 * ready to let the AP's out of the pen.
2262 /* spin until all the AP's are ready */
2267 * Set curproc to our per-cpu idleproc so that mutexes have
2268 * something unique to lock with.
2270 PCPU_SET(curproc, PCPU_GET(idleproc));
2271 PCPU_SET(spinlocks, NULL);
2273 /* lock against other AP's that are waking up */
2274 mtx_lock_spin(&ap_boot_mtx);
2276 /* BSP may have changed PTD while we're waiting for the lock */
2281 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2285 /* Build our map of 'other' CPUs. */
2286 PCPU_SET(other_cpus, all_cpus & ~(1 << PCPU_GET(cpuid)));
2288 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2290 /* set up CPU registers and state */
2293 /* set up FPU state on the AP */
2294 npxinit(__INITIAL_NPXCW__);
2296 /* A quick check from sanity claus */
2297 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2298 if (PCPU_GET(cpuid) != apic_id) {
2299 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2300 printf("SMP: apic_id = %d\n", apic_id);
2301 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2302 panic("cpuid mismatch! boom!!");
2305 /* Init local apic for irq's */
2308 /* Set memory range attributes for this CPU to match the BSP */
2309 mem_range_AP_init();
2312 * Activate smp_invltlb, although strictly speaking, this isn't
2313 * quite correct yet. We should have a bitfield for cpus willing
2314 * to accept TLB flush IPI's or something and sync them.
2316 if (smp_cpus == mp_ncpus) {
2318 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2319 smp_active = 1; /* historic */
2322 /* let other AP's wake up now */
2323 mtx_unlock_spin(&ap_boot_mtx);
2325 /* wait until all the AP's are up */
2326 while (smp_started == 0)
2329 microuptime(PCPU_PTR(switchtime));
2330 PCPU_SET(switchticks, ticks);
2332 /* ok, now grab sched_lock and enter the scheduler */
2334 mtx_lock_spin(&sched_lock);
2335 cpu_throw(); /* doesn't return */
2337 panic("scheduler returned us to ap_init");
2342 #define CHECKSTATE_USER 0
2343 #define CHECKSTATE_SYS 1
2344 #define CHECKSTATE_INTR 2
2346 /* Do not staticize. Used from apic_vector.s */
2347 struct proc* checkstate_curproc[MAXCPU];
2348 int checkstate_cpustate[MAXCPU];
2349 u_long checkstate_pc[MAXCPU];
2351 #define PC_TO_INDEX(pc, prof) \
2352 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2353 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2356 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2362 pc = checkstate_pc[id];
2363 prof = &p->p_stats->p_prof;
2364 if (pc >= prof->pr_off &&
2365 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2366 mtx_assert(&sched_lock, MA_OWNED);
2367 if ((p->p_sflag & PS_OWEUPC) == 0) {
2370 p->p_sflag |= PS_OWEUPC;
2372 *astmap |= (1 << id);
2377 forwarded_statclock(int id, int pscnt, int *astmap)
2379 struct pstats *pstats;
2386 register struct gmonparam *g;
2390 mtx_assert(&sched_lock, MA_OWNED);
2391 p = checkstate_curproc[id];
2392 cpustate = checkstate_cpustate[id];
2396 cpustate = CHECKSTATE_INTR;
2397 else if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2398 cpustate = CHECKSTATE_SYS;
2401 case CHECKSTATE_USER:
2402 if (p->p_sflag & PS_PROFIL)
2403 addupc_intr_forwarded(p, id, astmap);
2407 if (p->p_nice > NZERO)
2412 case CHECKSTATE_SYS:
2415 * Kernel statistics are just like addupc_intr, only easier.
2418 if (g->state == GMON_PROF_ON) {
2419 i = checkstate_pc[id] - g->lowpc;
2420 if (i < g->textsize) {
2421 i /= HISTFRACTION * sizeof(*g->kcount);
2430 if (p == SMP_prvspace[id].globaldata.gd_idleproc)
2435 case CHECKSTATE_INTR:
2439 * Kernel statistics are just like addupc_intr, only easier.
2442 if (g->state == GMON_PROF_ON) {
2443 i = checkstate_pc[id] - g->lowpc;
2444 if (i < g->textsize) {
2445 i /= HISTFRACTION * sizeof(*g->kcount);
2452 KASSERT(p != NULL, ("NULL process in interrupt state"));
2459 /* Update resource usage integrals and maximums. */
2460 if ((pstats = p->p_stats) != NULL &&
2461 (ru = &pstats->p_ru) != NULL &&
2462 (vm = p->p_vmspace) != NULL) {
2463 ru->ru_ixrss += pgtok(vm->vm_tsize);
2464 ru->ru_idrss += pgtok(vm->vm_dsize);
2465 ru->ru_isrss += pgtok(vm->vm_ssize);
2466 rss = pgtok(vmspace_resident_count(vm));
2467 if (ru->ru_maxrss < rss)
2468 ru->ru_maxrss = rss;
2473 forward_statclock(int pscnt)
2479 /* Kludge. We don't yet have separate locks for the interrupts
2480 * and the kernel. This means that we cannot let the other processors
2481 * handle complex interrupts while inhibiting them from entering
2482 * the kernel in a non-interrupt context.
2484 * What we can do, without changing the locking mechanisms yet,
2485 * is letting the other processors handle a very simple interrupt
2486 * (wich determines the processor states), and do the main
2490 CTR1(KTR_SMP, "forward_statclock(%d)", pscnt);
2492 if (!smp_started || !invltlb_ok || cold || panicstr)
2495 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2497 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2498 checkstate_probed_cpus = 0;
2500 selected_apic_ipi(map,
2501 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2504 while (checkstate_probed_cpus != map) {
2508 #ifdef BETTER_CLOCK_DIAGNOSTIC
2509 printf("forward_statclock: checkstate %x\n",
2510 checkstate_probed_cpus);
2517 * Step 2: walk through other processors processes, update ticks and
2522 for (id = 0; id < mp_ncpus; id++) {
2523 if (id == PCPU_GET(cpuid))
2525 if (((1 << id) & checkstate_probed_cpus) == 0)
2527 forwarded_statclock(id, pscnt, &map);
2530 checkstate_need_ast |= map;
2531 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2533 while ((checkstate_need_ast & map) != 0) {
2537 #ifdef BETTER_CLOCK_DIAGNOSTIC
2538 printf("forward_statclock: dropped ast 0x%x\n",
2539 checkstate_need_ast & map);
2548 forward_hardclock(int pscnt)
2553 struct pstats *pstats;
2556 /* Kludge. We don't yet have separate locks for the interrupts
2557 * and the kernel. This means that we cannot let the other processors
2558 * handle complex interrupts while inhibiting them from entering
2559 * the kernel in a non-interrupt context.
2561 * What we can do, without changing the locking mechanisms yet,
2562 * is letting the other processors handle a very simple interrupt
2563 * (wich determines the processor states), and do the main
2567 CTR1(KTR_SMP, "forward_hardclock(%d)", pscnt);
2569 if (!smp_started || !invltlb_ok || cold || panicstr)
2572 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2574 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2575 checkstate_probed_cpus = 0;
2577 selected_apic_ipi(map,
2578 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2581 while (checkstate_probed_cpus != map) {
2585 #ifdef BETTER_CLOCK_DIAGNOSTIC
2586 printf("forward_hardclock: checkstate %x\n",
2587 checkstate_probed_cpus);
2594 * Step 2: walk through other processors processes, update virtual
2595 * timer and profiling timer. If stathz == 0, also update ticks and
2600 for (id = 0; id < mp_ncpus; id++) {
2601 if (id == PCPU_GET(cpuid))
2603 if (((1 << id) & checkstate_probed_cpus) == 0)
2605 p = checkstate_curproc[id];
2607 pstats = p->p_stats;
2608 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2609 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2610 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2611 p->p_sflag |= PS_ALRMPEND;
2614 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2615 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2616 p->p_sflag |= PS_PROFPEND;
2621 forwarded_statclock( id, pscnt, &map);
2625 checkstate_need_ast |= map;
2626 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2628 while ((checkstate_need_ast & map) != 0) {
2632 #ifdef BETTER_CLOCK_DIAGNOSTIC
2633 printf("forward_hardclock: dropped ast 0x%x\n",
2634 checkstate_need_ast & map);
2642 #endif /* BETTER_CLOCK */
2645 forward_signal(struct proc *p)
2651 /* Kludge. We don't yet have separate locks for the interrupts
2652 * and the kernel. This means that we cannot let the other processors
2653 * handle complex interrupts while inhibiting them from entering
2654 * the kernel in a non-interrupt context.
2656 * What we can do, without changing the locking mechanisms yet,
2657 * is letting the other processors handle a very simple interrupt
2658 * (wich determines the processor states), and do the main
2662 CTR1(KTR_SMP, "forward_signal(%p)", p);
2664 if (!smp_started || !invltlb_ok || cold || panicstr)
2666 if (!forward_signal_enabled)
2668 mtx_lock_spin(&sched_lock);
2670 if (p->p_stat != SRUN) {
2671 mtx_unlock_spin(&sched_lock);
2675 mtx_unlock_spin(&sched_lock);
2679 checkstate_need_ast |= map;
2680 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2682 while ((checkstate_need_ast & map) != 0) {
2687 printf("forward_signal: dropped ast 0x%x\n",
2688 checkstate_need_ast & map);
2693 mtx_lock_spin(&sched_lock);
2694 if (id == p->p_oncpu) {
2695 mtx_unlock_spin(&sched_lock);
2702 forward_roundrobin(void)
2707 CTR0(KTR_SMP, "forward_roundrobin()");
2709 if (!smp_started || !invltlb_ok || cold || panicstr)
2711 if (!forward_roundrobin_enabled)
2713 resched_cpus |= PCPU_GET(other_cpus);
2714 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2716 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED);
2718 (void) all_but_self_ipi(XCPUAST_OFFSET);
2721 while ((checkstate_need_ast & map) != 0) {
2726 printf("forward_roundrobin: dropped ast 0x%x\n",
2727 checkstate_need_ast & map);
2735 * When called the executing CPU will send an IPI to all other CPUs
2736 * requesting that they halt execution.
2738 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2740 * - Signals all CPUs in map to stop.
2741 * - Waits for each to stop.
2748 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2749 * from executing at same time.
2752 stop_cpus(u_int map)
2759 /* send the Xcpustop IPI to all CPUs in map */
2760 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2762 while (count++ < 100000 && (stopped_cpus & map) != map)
2766 if ((stopped_cpus & map) != map)
2767 printf("Warning: CPUs 0x%x did not stop!\n",
2768 (~(stopped_cpus & map)) & map);
2776 * Called by a CPU to restart stopped CPUs.
2778 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2780 * - Signals all CPUs in map to restart.
2781 * - Waits for each to restart.
2789 restart_cpus(u_int map)
2796 started_cpus = map; /* signal other cpus to restart */
2798 /* wait for each to clear its bit */
2799 while (count++ < 100000 && (stopped_cpus & map) != 0)
2803 if ((stopped_cpus & map) != 0)
2804 printf("Warning: CPUs 0x%x did not restart!\n",
2805 (~(stopped_cpus & map)) & map);
2812 #ifdef APIC_INTR_REORDER
2814 * Maintain mapping from softintr vector to isr bit in local apic.
2817 set_lapic_isrloc(int intr, int vector)
2819 if (intr < 0 || intr > 32)
2820 panic("set_apic_isrloc: bad intr argument: %d",intr);
2821 if (vector < ICU_OFFSET || vector > 255)
2822 panic("set_apic_isrloc: bad vector argument: %d",vector);
2823 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2824 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2829 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2830 * (if specified), rendezvous, execute the action function (if specified),
2831 * rendezvous again, execute the teardown function (if specified), and then
2834 * Note that the supplied external functions _must_ be reentrant and aware
2835 * that they are running in parallel and in an unknown lock context.
2837 static void (*smp_rv_setup_func)(void *arg);
2838 static void (*smp_rv_action_func)(void *arg);
2839 static void (*smp_rv_teardown_func)(void *arg);
2840 static void *smp_rv_func_arg;
2841 static volatile int smp_rv_waiters[2];
2844 smp_rendezvous_action(void)
2846 /* setup function */
2847 if (smp_rv_setup_func != NULL)
2848 smp_rv_setup_func(smp_rv_func_arg);
2849 /* spin on entry rendezvous */
2850 atomic_add_int(&smp_rv_waiters[0], 1);
2851 while (smp_rv_waiters[0] < mp_ncpus)
2853 /* action function */
2854 if (smp_rv_action_func != NULL)
2855 smp_rv_action_func(smp_rv_func_arg);
2856 /* spin on exit rendezvous */
2857 atomic_add_int(&smp_rv_waiters[1], 1);
2858 while (smp_rv_waiters[1] < mp_ncpus)
2860 /* teardown function */
2861 if (smp_rv_teardown_func != NULL)
2862 smp_rv_teardown_func(smp_rv_func_arg);
2866 smp_rendezvous(void (* setup_func)(void *),
2867 void (* action_func)(void *),
2868 void (* teardown_func)(void *),
2872 /* obtain rendezvous lock */
2873 mtx_lock_spin(&smp_rv_mtx);
2875 /* set static function pointers */
2876 smp_rv_setup_func = setup_func;
2877 smp_rv_action_func = action_func;
2878 smp_rv_teardown_func = teardown_func;
2879 smp_rv_func_arg = arg;
2880 smp_rv_waiters[0] = 0;
2881 smp_rv_waiters[1] = 0;
2884 * signal other processors, which will enter the IPI with interrupts off
2886 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2888 /* call executor function */
2889 smp_rendezvous_action();
2892 mtx_unlock_spin(&smp_rv_mtx);
2896 release_aps(void *dummy __unused)
2898 atomic_store_rel_int(&aps_ready, 1);
2901 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);