2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
326 #define pa_index(pa) ({ \
327 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
328 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
345 #define NPV_LIST_LOCKS MAXCPU
347 #define PHYS_TO_PV_LIST_LOCK(pa) \
348 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
351 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
352 struct rwlock **_lockp = (lockp); \
353 struct rwlock *_new_lock; \
355 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
356 if (_new_lock != *_lockp) { \
357 if (*_lockp != NULL) \
358 rw_wunlock(*_lockp); \
359 *_lockp = _new_lock; \
364 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
365 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
367 #define RELEASE_PV_LIST_LOCK(lockp) do { \
368 struct rwlock **_lockp = (lockp); \
370 if (*_lockp != NULL) { \
371 rw_wunlock(*_lockp); \
376 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
377 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
379 struct pmap kernel_pmap_store;
381 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
382 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
385 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
386 "Number of kernel page table pages allocated on bootup");
389 vm_paddr_t dmaplimit;
390 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
393 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
394 "VM/pmap parameters");
396 static int pg_ps_enabled = 1;
397 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
398 &pg_ps_enabled, 0, "Are large page mappings enabled?");
400 #define PAT_INDEX_SIZE 8
401 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
403 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
404 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
405 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
406 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
408 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
409 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
410 static int ndmpdpphys; /* number of DMPDPphys pages */
412 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
415 * pmap_mapdev support pre initialization (i.e. console)
417 #define PMAP_PREINIT_MAPPING_COUNT 8
418 static struct pmap_preinit_mapping {
423 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
424 static int pmap_initialized;
427 * Data for the pv entry allocation mechanism.
428 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
432 pc_to_domain(struct pv_chunk *pc)
435 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
439 pc_to_domain(struct pv_chunk *pc __unused)
446 struct pv_chunks_list {
448 TAILQ_HEAD(pch, pv_chunk) pvc_list;
450 } __aligned(CACHE_LINE_SIZE);
452 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
455 struct pmap_large_md_page {
456 struct rwlock pv_lock;
457 struct md_page pv_page;
460 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
461 #define pv_dummy pv_dummy_large.pv_page
462 __read_mostly static struct pmap_large_md_page *pv_table;
463 __read_mostly vm_paddr_t pmap_last_pa;
465 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
466 static u_long pv_invl_gen[NPV_LIST_LOCKS];
467 static struct md_page *pv_table;
468 static struct md_page pv_dummy;
472 * All those kernel PT submaps that BSD is so fond of
474 pt_entry_t *CMAP1 = NULL;
476 static vm_offset_t qframe = 0;
477 static struct mtx qframe_mtx;
479 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
481 static vmem_t *large_vmem;
482 static u_int lm_ents;
483 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
484 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
486 int pmap_pcid_enabled = 1;
487 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
488 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
489 int invpcid_works = 0;
490 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
491 "Is the invpcid instruction available ?");
493 int __read_frequently pti = 0;
494 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
496 "Page Table Isolation enabled");
497 static vm_object_t pti_obj;
498 static pml4_entry_t *pti_pml4;
499 static vm_pindex_t pti_pg_idx;
500 static bool pti_finalized;
502 struct pmap_pkru_range {
503 struct rs_el pkru_rs_el;
508 static uma_zone_t pmap_pkru_ranges_zone;
509 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
510 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
511 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
512 static void *pkru_dup_range(void *ctx, void *data);
513 static void pkru_free_range(void *ctx, void *node);
514 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
515 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
516 static void pmap_pkru_deassign_all(pmap_t pmap);
519 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
526 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
528 return (sysctl_handle_64(oidp, &res, 0, req));
530 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
531 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
532 "Count of saved TLB context on switch");
534 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
535 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
536 static struct mtx invl_gen_mtx;
537 /* Fake lock object to satisfy turnstiles interface. */
538 static struct lock_object invl_gen_ts = {
541 static struct pmap_invl_gen pmap_invl_gen_head = {
545 static u_long pmap_invl_gen = 1;
546 static int pmap_invl_waiters;
547 static struct callout pmap_invl_callout;
548 static bool pmap_invl_callout_inited;
550 #define PMAP_ASSERT_NOT_IN_DI() \
551 KASSERT(pmap_not_in_di(), ("DI already started"))
558 if ((cpu_feature2 & CPUID2_CX16) == 0)
561 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
566 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
570 locked = pmap_di_locked();
571 return (sysctl_handle_int(oidp, &locked, 0, req));
573 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
574 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
575 "Locked delayed invalidation");
577 static bool pmap_not_in_di_l(void);
578 static bool pmap_not_in_di_u(void);
579 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
582 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
586 pmap_not_in_di_l(void)
588 struct pmap_invl_gen *invl_gen;
590 invl_gen = &curthread->td_md.md_invl_gen;
591 return (invl_gen->gen == 0);
595 pmap_thread_init_invl_gen_l(struct thread *td)
597 struct pmap_invl_gen *invl_gen;
599 invl_gen = &td->td_md.md_invl_gen;
604 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
606 struct turnstile *ts;
608 ts = turnstile_trywait(&invl_gen_ts);
609 if (*m_gen > atomic_load_long(invl_gen))
610 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
612 turnstile_cancel(ts);
616 pmap_delayed_invl_finish_unblock(u_long new_gen)
618 struct turnstile *ts;
620 turnstile_chain_lock(&invl_gen_ts);
621 ts = turnstile_lookup(&invl_gen_ts);
623 pmap_invl_gen = new_gen;
625 turnstile_broadcast(ts, TS_SHARED_QUEUE);
626 turnstile_unpend(ts);
628 turnstile_chain_unlock(&invl_gen_ts);
632 * Start a new Delayed Invalidation (DI) block of code, executed by
633 * the current thread. Within a DI block, the current thread may
634 * destroy both the page table and PV list entries for a mapping and
635 * then release the corresponding PV list lock before ensuring that
636 * the mapping is flushed from the TLBs of any processors with the
640 pmap_delayed_invl_start_l(void)
642 struct pmap_invl_gen *invl_gen;
645 invl_gen = &curthread->td_md.md_invl_gen;
646 PMAP_ASSERT_NOT_IN_DI();
647 mtx_lock(&invl_gen_mtx);
648 if (LIST_EMPTY(&pmap_invl_gen_tracker))
649 currgen = pmap_invl_gen;
651 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
652 invl_gen->gen = currgen + 1;
653 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
654 mtx_unlock(&invl_gen_mtx);
658 * Finish the DI block, previously started by the current thread. All
659 * required TLB flushes for the pages marked by
660 * pmap_delayed_invl_page() must be finished before this function is
663 * This function works by bumping the global DI generation number to
664 * the generation number of the current thread's DI, unless there is a
665 * pending DI that started earlier. In the latter case, bumping the
666 * global DI generation number would incorrectly signal that the
667 * earlier DI had finished. Instead, this function bumps the earlier
668 * DI's generation number to match the generation number of the
669 * current thread's DI.
672 pmap_delayed_invl_finish_l(void)
674 struct pmap_invl_gen *invl_gen, *next;
676 invl_gen = &curthread->td_md.md_invl_gen;
677 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
678 mtx_lock(&invl_gen_mtx);
679 next = LIST_NEXT(invl_gen, link);
681 pmap_delayed_invl_finish_unblock(invl_gen->gen);
683 next->gen = invl_gen->gen;
684 LIST_REMOVE(invl_gen, link);
685 mtx_unlock(&invl_gen_mtx);
690 pmap_not_in_di_u(void)
692 struct pmap_invl_gen *invl_gen;
694 invl_gen = &curthread->td_md.md_invl_gen;
695 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
699 pmap_thread_init_invl_gen_u(struct thread *td)
701 struct pmap_invl_gen *invl_gen;
703 invl_gen = &td->td_md.md_invl_gen;
705 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
709 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
711 uint64_t new_high, new_low, old_high, old_low;
714 old_low = new_low = 0;
715 old_high = new_high = (uintptr_t)0;
717 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
718 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
719 : "b"(new_low), "c" (new_high)
722 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
725 out->next = (void *)old_high;
728 out->next = (void *)new_high;
734 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
735 struct pmap_invl_gen *new_val)
737 uint64_t new_high, new_low, old_high, old_low;
740 new_low = new_val->gen;
741 new_high = (uintptr_t)new_val->next;
742 old_low = old_val->gen;
743 old_high = (uintptr_t)old_val->next;
745 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
746 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
747 : "b"(new_low), "c" (new_high)
753 static long invl_start_restart;
754 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
755 &invl_start_restart, 0,
757 static long invl_finish_restart;
758 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
759 &invl_finish_restart, 0,
761 static int invl_max_qlen;
762 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
767 #define di_delay locks_delay
770 pmap_delayed_invl_start_u(void)
772 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
774 struct lock_delay_arg lda;
782 invl_gen = &td->td_md.md_invl_gen;
783 PMAP_ASSERT_NOT_IN_DI();
784 lock_delay_arg_init(&lda, &di_delay);
785 invl_gen->saved_pri = 0;
786 pri = td->td_base_pri;
789 pri = td->td_base_pri;
791 invl_gen->saved_pri = pri;
798 for (p = &pmap_invl_gen_head;; p = prev.next) {
800 prevl = (uintptr_t)atomic_load_ptr(&p->next);
801 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
802 PV_STAT(atomic_add_long(&invl_start_restart, 1));
808 prev.next = (void *)prevl;
811 if ((ii = invl_max_qlen) < i)
812 atomic_cmpset_int(&invl_max_qlen, ii, i);
815 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
816 PV_STAT(atomic_add_long(&invl_start_restart, 1));
821 new_prev.gen = prev.gen;
822 new_prev.next = invl_gen;
823 invl_gen->gen = prev.gen + 1;
825 /* Formal fence between store to invl->gen and updating *p. */
826 atomic_thread_fence_rel();
829 * After inserting an invl_gen element with invalid bit set,
830 * this thread blocks any other thread trying to enter the
831 * delayed invalidation block. Do not allow to remove us from
832 * the CPU, because it causes starvation for other threads.
837 * ABA for *p is not possible there, since p->gen can only
838 * increase. So if the *p thread finished its di, then
839 * started a new one and got inserted into the list at the
840 * same place, its gen will appear greater than the previously
843 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
845 PV_STAT(atomic_add_long(&invl_start_restart, 1));
851 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
852 * invl_gen->next, allowing other threads to iterate past us.
853 * pmap_di_store_invl() provides fence between the generation
854 * write and the update of next.
856 invl_gen->next = NULL;
861 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
862 struct pmap_invl_gen *p)
864 struct pmap_invl_gen prev, new_prev;
868 * Load invl_gen->gen after setting invl_gen->next
869 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
870 * generations to propagate to our invl_gen->gen. Lock prefix
871 * in atomic_set_ptr() worked as seq_cst fence.
873 mygen = atomic_load_long(&invl_gen->gen);
875 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
878 KASSERT(prev.gen < mygen,
879 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
880 new_prev.gen = mygen;
881 new_prev.next = (void *)((uintptr_t)invl_gen->next &
882 ~PMAP_INVL_GEN_NEXT_INVALID);
884 /* Formal fence between load of prev and storing update to it. */
885 atomic_thread_fence_rel();
887 return (pmap_di_store_invl(p, &prev, &new_prev));
891 pmap_delayed_invl_finish_u(void)
893 struct pmap_invl_gen *invl_gen, *p;
895 struct lock_delay_arg lda;
899 invl_gen = &td->td_md.md_invl_gen;
900 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
901 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
902 ("missed invl_start: INVALID"));
903 lock_delay_arg_init(&lda, &di_delay);
906 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
907 prevl = (uintptr_t)atomic_load_ptr(&p->next);
908 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
909 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
913 if ((void *)prevl == invl_gen)
918 * It is legitimate to not find ourself on the list if a
919 * thread before us finished its DI and started it again.
921 if (__predict_false(p == NULL)) {
922 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
928 atomic_set_ptr((uintptr_t *)&invl_gen->next,
929 PMAP_INVL_GEN_NEXT_INVALID);
930 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
931 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
932 PMAP_INVL_GEN_NEXT_INVALID);
934 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
939 if (atomic_load_int(&pmap_invl_waiters) > 0)
940 pmap_delayed_invl_finish_unblock(0);
941 if (invl_gen->saved_pri != 0) {
943 sched_prio(td, invl_gen->saved_pri);
949 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
951 struct pmap_invl_gen *p, *pn;
956 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
958 nextl = (uintptr_t)atomic_load_ptr(&p->next);
959 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
960 td = first ? NULL : __containerof(p, struct thread,
962 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
963 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
964 td != NULL ? td->td_tid : -1);
970 static long invl_wait;
971 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
972 "Number of times DI invalidation blocked pmap_remove_all/write");
973 static long invl_wait_slow;
974 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
975 "Number of slow invalidation waits for lockless DI");
980 pmap_delayed_invl_genp(vm_page_t m)
985 pa = VM_PAGE_TO_PHYS(m);
986 if (__predict_false((pa) > pmap_last_pa))
987 gen = &pv_dummy_large.pv_invl_gen;
989 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
995 pmap_delayed_invl_genp(vm_page_t m)
998 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1003 pmap_delayed_invl_callout_func(void *arg __unused)
1006 if (atomic_load_int(&pmap_invl_waiters) == 0)
1008 pmap_delayed_invl_finish_unblock(0);
1012 pmap_delayed_invl_callout_init(void *arg __unused)
1015 if (pmap_di_locked())
1017 callout_init(&pmap_invl_callout, 1);
1018 pmap_invl_callout_inited = true;
1020 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1021 pmap_delayed_invl_callout_init, NULL);
1024 * Ensure that all currently executing DI blocks, that need to flush
1025 * TLB for the given page m, actually flushed the TLB at the time the
1026 * function returned. If the page m has an empty PV list and we call
1027 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1028 * valid mapping for the page m in either its page table or TLB.
1030 * This function works by blocking until the global DI generation
1031 * number catches up with the generation number associated with the
1032 * given page m and its PV list. Since this function's callers
1033 * typically own an object lock and sometimes own a page lock, it
1034 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1038 pmap_delayed_invl_wait_l(vm_page_t m)
1042 bool accounted = false;
1045 m_gen = pmap_delayed_invl_genp(m);
1046 while (*m_gen > pmap_invl_gen) {
1049 atomic_add_long(&invl_wait, 1);
1053 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1058 pmap_delayed_invl_wait_u(vm_page_t m)
1061 struct lock_delay_arg lda;
1065 m_gen = pmap_delayed_invl_genp(m);
1066 lock_delay_arg_init(&lda, &di_delay);
1067 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1068 if (fast || !pmap_invl_callout_inited) {
1069 PV_STAT(atomic_add_long(&invl_wait, 1));
1074 * The page's invalidation generation number
1075 * is still below the current thread's number.
1076 * Prepare to block so that we do not waste
1077 * CPU cycles or worse, suffer livelock.
1079 * Since it is impossible to block without
1080 * racing with pmap_delayed_invl_finish_u(),
1081 * prepare for the race by incrementing
1082 * pmap_invl_waiters and arming a 1-tick
1083 * callout which will unblock us if we lose
1086 atomic_add_int(&pmap_invl_waiters, 1);
1089 * Re-check the current thread's invalidation
1090 * generation after incrementing
1091 * pmap_invl_waiters, so that there is no race
1092 * with pmap_delayed_invl_finish_u() setting
1093 * the page generation and checking
1094 * pmap_invl_waiters. The only race allowed
1095 * is for a missed unblock, which is handled
1099 atomic_load_long(&pmap_invl_gen_head.gen)) {
1100 callout_reset(&pmap_invl_callout, 1,
1101 pmap_delayed_invl_callout_func, NULL);
1102 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1103 pmap_delayed_invl_wait_block(m_gen,
1104 &pmap_invl_gen_head.gen);
1106 atomic_add_int(&pmap_invl_waiters, -1);
1111 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1114 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1115 pmap_thread_init_invl_gen_u);
1118 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1121 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1122 pmap_delayed_invl_start_u);
1125 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1128 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1129 pmap_delayed_invl_finish_u);
1132 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1135 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1136 pmap_delayed_invl_wait_u);
1140 * Mark the page m's PV list as participating in the current thread's
1141 * DI block. Any threads concurrently using m's PV list to remove or
1142 * restrict all mappings to m will wait for the current thread's DI
1143 * block to complete before proceeding.
1145 * The function works by setting the DI generation number for m's PV
1146 * list to at least the DI generation number of the current thread.
1147 * This forces a caller of pmap_delayed_invl_wait() to block until
1148 * current thread calls pmap_delayed_invl_finish().
1151 pmap_delayed_invl_page(vm_page_t m)
1155 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1156 gen = curthread->td_md.md_invl_gen.gen;
1159 m_gen = pmap_delayed_invl_genp(m);
1167 static caddr_t crashdumpmap;
1170 * Internal flags for pmap_enter()'s helper functions.
1172 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1173 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1176 * Internal flags for pmap_mapdev_internal() and
1177 * pmap_change_props_locked().
1179 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1180 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1181 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1183 TAILQ_HEAD(pv_chunklist, pv_chunk);
1185 static void free_pv_chunk(struct pv_chunk *pc);
1186 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1187 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1188 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1189 static int popcnt_pc_map_pq(uint64_t *map);
1190 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1191 static void reserve_pv_entries(pmap_t pmap, int needed,
1192 struct rwlock **lockp);
1193 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1194 struct rwlock **lockp);
1195 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1196 u_int flags, struct rwlock **lockp);
1197 #if VM_NRESERVLEVEL > 0
1198 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1199 struct rwlock **lockp);
1201 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1202 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1205 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1206 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1207 vm_prot_t prot, int mode, int flags);
1208 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1209 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1210 vm_offset_t va, struct rwlock **lockp);
1211 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1213 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1214 vm_prot_t prot, struct rwlock **lockp);
1215 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1216 u_int flags, vm_page_t m, struct rwlock **lockp);
1217 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1218 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1219 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1220 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1221 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1223 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1225 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1227 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1228 static vm_page_t pmap_large_map_getptp_unlocked(void);
1229 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1230 #if VM_NRESERVLEVEL > 0
1231 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1232 struct rwlock **lockp);
1234 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1236 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1237 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1239 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1240 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1241 static void pmap_pti_wire_pte(void *pte);
1242 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1243 struct spglist *free, struct rwlock **lockp);
1244 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1245 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1246 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1247 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1248 struct spglist *free);
1249 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1250 pd_entry_t *pde, struct spglist *free,
1251 struct rwlock **lockp);
1252 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1253 vm_page_t m, struct rwlock **lockp);
1254 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1256 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1258 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1259 struct rwlock **lockp);
1260 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1261 struct rwlock **lockp);
1262 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1263 struct rwlock **lockp);
1265 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1266 struct spglist *free);
1267 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1269 /********************/
1270 /* Inline functions */
1271 /********************/
1273 /* Return a non-clipped PD index for a given VA */
1274 static __inline vm_pindex_t
1275 pmap_pde_pindex(vm_offset_t va)
1277 return (va >> PDRSHIFT);
1281 /* Return a pointer to the PML4 slot that corresponds to a VA */
1282 static __inline pml4_entry_t *
1283 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1286 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1289 /* Return a pointer to the PDP slot that corresponds to a VA */
1290 static __inline pdp_entry_t *
1291 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1295 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1296 return (&pdpe[pmap_pdpe_index(va)]);
1299 /* Return a pointer to the PDP slot that corresponds to a VA */
1300 static __inline pdp_entry_t *
1301 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1303 pml4_entry_t *pml4e;
1306 PG_V = pmap_valid_bit(pmap);
1307 pml4e = pmap_pml4e(pmap, va);
1308 if ((*pml4e & PG_V) == 0)
1310 return (pmap_pml4e_to_pdpe(pml4e, va));
1313 /* Return a pointer to the PD slot that corresponds to a VA */
1314 static __inline pd_entry_t *
1315 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1319 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1320 return (&pde[pmap_pde_index(va)]);
1323 /* Return a pointer to the PD slot that corresponds to a VA */
1324 static __inline pd_entry_t *
1325 pmap_pde(pmap_t pmap, vm_offset_t va)
1330 PG_V = pmap_valid_bit(pmap);
1331 pdpe = pmap_pdpe(pmap, va);
1332 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1334 return (pmap_pdpe_to_pde(pdpe, va));
1337 /* Return a pointer to the PT slot that corresponds to a VA */
1338 static __inline pt_entry_t *
1339 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1343 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1344 return (&pte[pmap_pte_index(va)]);
1347 /* Return a pointer to the PT slot that corresponds to a VA */
1348 static __inline pt_entry_t *
1349 pmap_pte(pmap_t pmap, vm_offset_t va)
1354 PG_V = pmap_valid_bit(pmap);
1355 pde = pmap_pde(pmap, va);
1356 if (pde == NULL || (*pde & PG_V) == 0)
1358 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1359 return ((pt_entry_t *)pde);
1360 return (pmap_pde_to_pte(pde, va));
1363 static __inline void
1364 pmap_resident_count_inc(pmap_t pmap, int count)
1367 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1368 pmap->pm_stats.resident_count += count;
1371 static __inline void
1372 pmap_resident_count_dec(pmap_t pmap, int count)
1375 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1376 KASSERT(pmap->pm_stats.resident_count >= count,
1377 ("pmap %p resident count underflow %ld %d", pmap,
1378 pmap->pm_stats.resident_count, count));
1379 pmap->pm_stats.resident_count -= count;
1382 PMAP_INLINE pt_entry_t *
1383 vtopte(vm_offset_t va)
1385 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1387 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1389 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1392 static __inline pd_entry_t *
1393 vtopde(vm_offset_t va)
1395 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1397 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1399 return (PDmap + ((va >> PDRSHIFT) & mask));
1403 allocpages(vm_paddr_t *firstaddr, int n)
1408 bzero((void *)ret, n * PAGE_SIZE);
1409 *firstaddr += n * PAGE_SIZE;
1413 CTASSERT(powerof2(NDMPML4E));
1415 /* number of kernel PDP slots */
1416 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1419 nkpt_init(vm_paddr_t addr)
1426 pt_pages = howmany(addr, 1 << PDRSHIFT);
1427 pt_pages += NKPDPE(pt_pages);
1430 * Add some slop beyond the bare minimum required for bootstrapping
1433 * This is quite important when allocating KVA for kernel modules.
1434 * The modules are required to be linked in the negative 2GB of
1435 * the address space. If we run out of KVA in this region then
1436 * pmap_growkernel() will need to allocate page table pages to map
1437 * the entire 512GB of KVA space which is an unnecessary tax on
1440 * Secondly, device memory mapped as part of setting up the low-
1441 * level console(s) is taken from KVA, starting at virtual_avail.
1442 * This is because cninit() is called after pmap_bootstrap() but
1443 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1446 pt_pages += 32; /* 64MB additional slop. */
1452 * Returns the proper write/execute permission for a physical page that is
1453 * part of the initial boot allocations.
1455 * If the page has kernel text, it is marked as read-only. If the page has
1456 * kernel read-only data, it is marked as read-only/not-executable. If the
1457 * page has only read-write data, it is marked as read-write/not-executable.
1458 * If the page is below/above the kernel range, it is marked as read-write.
1460 * This function operates on 2M pages, since we map the kernel space that
1463 static inline pt_entry_t
1464 bootaddr_rwx(vm_paddr_t pa)
1468 * The kernel is loaded at a 2MB-aligned address, and memory below that
1469 * need not be executable. The .bss section is padded to a 2MB
1470 * boundary, so memory following the kernel need not be executable
1471 * either. Preloaded kernel modules have their mapping permissions
1472 * fixed up by the linker.
1474 if (pa < trunc_2mpage(btext - KERNBASE) ||
1475 pa >= trunc_2mpage(_end - KERNBASE))
1476 return (X86_PG_RW | pg_nx);
1479 * The linker should ensure that the read-only and read-write
1480 * portions don't share the same 2M page, so this shouldn't
1481 * impact read-only data. However, in any case, any page with
1482 * read-write data needs to be read-write.
1484 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1485 return (X86_PG_RW | pg_nx);
1488 * Mark any 2M page containing kernel text as read-only. Mark
1489 * other pages with read-only data as read-only and not executable.
1490 * (It is likely a small portion of the read-only data section will
1491 * be marked as read-only, but executable. This should be acceptable
1492 * since the read-only protection will keep the data from changing.)
1493 * Note that fixups to the .text section will still work until we
1496 if (pa < round_2mpage(etext - KERNBASE))
1502 create_pagetables(vm_paddr_t *firstaddr)
1504 int i, j, ndm1g, nkpdpe, nkdmpde;
1508 uint64_t DMPDkernphys;
1510 /* Allocate page table pages for the direct map */
1511 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1512 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1514 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1515 if (ndmpdpphys > NDMPML4E) {
1517 * Each NDMPML4E allows 512 GB, so limit to that,
1518 * and then readjust ndmpdp and ndmpdpphys.
1520 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1521 Maxmem = atop(NDMPML4E * NBPML4);
1522 ndmpdpphys = NDMPML4E;
1523 ndmpdp = NDMPML4E * NPDEPG;
1525 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1527 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1529 * Calculate the number of 1G pages that will fully fit in
1532 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1535 * Allocate 2M pages for the kernel. These will be used in
1536 * place of the first one or more 1G pages from ndm1g.
1538 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1539 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1542 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1543 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1545 /* Allocate pages */
1546 KPML4phys = allocpages(firstaddr, 1);
1547 KPDPphys = allocpages(firstaddr, NKPML4E);
1550 * Allocate the initial number of kernel page table pages required to
1551 * bootstrap. We defer this until after all memory-size dependent
1552 * allocations are done (e.g. direct map), so that we don't have to
1553 * build in too much slop in our estimate.
1555 * Note that when NKPML4E > 1, we have an empty page underneath
1556 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1557 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1559 nkpt_init(*firstaddr);
1560 nkpdpe = NKPDPE(nkpt);
1562 KPTphys = allocpages(firstaddr, nkpt);
1563 KPDphys = allocpages(firstaddr, nkpdpe);
1566 * Connect the zero-filled PT pages to their PD entries. This
1567 * implicitly maps the PT pages at their correct locations within
1570 pd_p = (pd_entry_t *)KPDphys;
1571 for (i = 0; i < nkpt; i++)
1572 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1575 * Map from physical address zero to the end of loader preallocated
1576 * memory using 2MB pages. This replaces some of the PD entries
1579 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1580 /* Preset PG_M and PG_A because demotion expects it. */
1581 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1582 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1585 * Because we map the physical blocks in 2M pages, adjust firstaddr
1586 * to record the physical blocks we've actually mapped into kernel
1587 * virtual address space.
1589 if (*firstaddr < round_2mpage(KERNend))
1590 *firstaddr = round_2mpage(KERNend);
1592 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1593 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1594 for (i = 0; i < nkpdpe; i++)
1595 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1598 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1599 * the end of physical memory is not aligned to a 1GB page boundary,
1600 * then the residual physical memory is mapped with 2MB pages. Later,
1601 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1602 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1603 * that are partially used.
1605 pd_p = (pd_entry_t *)DMPDphys;
1606 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1607 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1608 /* Preset PG_M and PG_A because demotion expects it. */
1609 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1610 X86_PG_M | X86_PG_A | pg_nx;
1612 pdp_p = (pdp_entry_t *)DMPDPphys;
1613 for (i = 0; i < ndm1g; i++) {
1614 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1615 /* Preset PG_M and PG_A because demotion expects it. */
1616 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1617 X86_PG_M | X86_PG_A | pg_nx;
1619 for (j = 0; i < ndmpdp; i++, j++) {
1620 pdp_p[i] = DMPDphys + ptoa(j);
1621 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1625 * Instead of using a 1G page for the memory containing the kernel,
1626 * use 2M pages with read-only and no-execute permissions. (If using 1G
1627 * pages, this will partially overwrite the PDPEs above.)
1630 pd_p = (pd_entry_t *)DMPDkernphys;
1631 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1632 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1633 X86_PG_M | X86_PG_A | pg_nx |
1634 bootaddr_rwx(i << PDRSHIFT);
1635 for (i = 0; i < nkdmpde; i++)
1636 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1640 /* And recursively map PML4 to itself in order to get PTmap */
1641 p4_p = (pml4_entry_t *)KPML4phys;
1642 p4_p[PML4PML4I] = KPML4phys;
1643 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1645 /* Connect the Direct Map slot(s) up to the PML4. */
1646 for (i = 0; i < ndmpdpphys; i++) {
1647 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1648 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1651 /* Connect the KVA slots up to the PML4 */
1652 for (i = 0; i < NKPML4E; i++) {
1653 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1654 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1659 * Bootstrap the system enough to run with virtual memory.
1661 * On amd64 this is called after mapping has already been enabled
1662 * and just syncs the pmap module with what has already been done.
1663 * [We can't call it easily with mapping off since the kernel is not
1664 * mapped with PA == VA, hence we would have to relocate every address
1665 * from the linked base (virtual) address "KERNBASE" to the actual
1666 * (physical) address starting relative to 0]
1669 pmap_bootstrap(vm_paddr_t *firstaddr)
1672 pt_entry_t *pte, *pcpu_pte;
1673 struct region_descriptor r_gdt;
1674 uint64_t cr4, pcpu_phys;
1678 KERNend = *firstaddr;
1679 res = atop(KERNend - (vm_paddr_t)kernphys);
1685 * Create an initial set of page tables to run the kernel in.
1687 create_pagetables(firstaddr);
1689 pcpu_phys = allocpages(firstaddr, MAXCPU);
1692 * Add a physical memory segment (vm_phys_seg) corresponding to the
1693 * preallocated kernel page table pages so that vm_page structures
1694 * representing these pages will be created. The vm_page structures
1695 * are required for promotion of the corresponding kernel virtual
1696 * addresses to superpage mappings.
1698 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1701 * Account for the virtual addresses mapped by create_pagetables().
1703 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1704 virtual_end = VM_MAX_KERNEL_ADDRESS;
1707 * Enable PG_G global pages, then switch to the kernel page
1708 * table from the bootstrap page table. After the switch, it
1709 * is possible to enable SMEP and SMAP since PG_U bits are
1715 load_cr3(KPML4phys);
1716 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1718 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1723 * Initialize the kernel pmap (which is statically allocated).
1724 * Count bootstrap data as being resident in case any of this data is
1725 * later unmapped (using pmap_remove()) and freed.
1727 PMAP_LOCK_INIT(kernel_pmap);
1728 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1729 kernel_pmap->pm_cr3 = KPML4phys;
1730 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1731 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1732 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1733 kernel_pmap->pm_stats.resident_count = res;
1734 kernel_pmap->pm_flags = pmap_flags;
1737 * Initialize the TLB invalidations generation number lock.
1739 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1742 * Reserve some special page table entries/VA space for temporary
1745 #define SYSMAP(c, p, v, n) \
1746 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1752 * Crashdump maps. The first page is reused as CMAP1 for the
1755 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1756 CADDR1 = crashdumpmap;
1758 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1761 for (i = 0; i < MAXCPU; i++) {
1762 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1763 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1767 * Re-initialize PCPU area for BSP after switching.
1768 * Make hardware use gdt and common_tss from the new PCPU.
1770 STAILQ_INIT(&cpuhead);
1771 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1772 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1773 amd64_bsp_pcpu_init1(&__pcpu[0]);
1774 amd64_bsp_ist_init(&__pcpu[0]);
1775 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1777 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1778 sizeof(struct user_segment_descriptor));
1779 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1780 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1781 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1782 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1783 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1785 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1786 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1787 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1788 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1791 * Initialize the PAT MSR.
1792 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1793 * side-effect, invalidates stale PG_G TLB entries that might
1794 * have been created in our pre-boot environment.
1798 /* Initialize TLB Context Id. */
1799 if (pmap_pcid_enabled) {
1800 for (i = 0; i < MAXCPU; i++) {
1801 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1802 kernel_pmap->pm_pcids[i].pm_gen = 1;
1806 * PMAP_PCID_KERN + 1 is used for initialization of
1807 * proc0 pmap. The pmap' pcid state might be used by
1808 * EFIRT entry before first context switch, so it
1809 * needs to be valid.
1811 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1812 PCPU_SET(pcid_gen, 1);
1815 * pcpu area for APs is zeroed during AP startup.
1816 * pc_pcid_next and pc_pcid_gen are initialized by AP
1817 * during pcpu setup.
1819 load_cr4(rcr4() | CR4_PCIDE);
1824 * Setup the PAT MSR.
1833 /* Bail if this CPU doesn't implement PAT. */
1834 if ((cpu_feature & CPUID_PAT) == 0)
1837 /* Set default PAT index table. */
1838 for (i = 0; i < PAT_INDEX_SIZE; i++)
1840 pat_index[PAT_WRITE_BACK] = 0;
1841 pat_index[PAT_WRITE_THROUGH] = 1;
1842 pat_index[PAT_UNCACHEABLE] = 3;
1843 pat_index[PAT_WRITE_COMBINING] = 6;
1844 pat_index[PAT_WRITE_PROTECTED] = 5;
1845 pat_index[PAT_UNCACHED] = 2;
1848 * Initialize default PAT entries.
1849 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1850 * Program 5 and 6 as WP and WC.
1852 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1853 * mapping for a 2M page uses a PAT value with the bit 3 set due
1854 * to its overload with PG_PS.
1856 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1857 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1858 PAT_VALUE(2, PAT_UNCACHED) |
1859 PAT_VALUE(3, PAT_UNCACHEABLE) |
1860 PAT_VALUE(4, PAT_WRITE_BACK) |
1861 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1862 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1863 PAT_VALUE(7, PAT_UNCACHEABLE);
1867 load_cr4(cr4 & ~CR4_PGE);
1869 /* Disable caches (CD = 1, NW = 0). */
1871 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1873 /* Flushes caches and TLBs. */
1877 /* Update PAT and index table. */
1878 wrmsr(MSR_PAT, pat_msr);
1880 /* Flush caches and TLBs again. */
1884 /* Restore caches and PGE. */
1890 * Initialize a vm_page's machine-dependent fields.
1893 pmap_page_init(vm_page_t m)
1896 TAILQ_INIT(&m->md.pv_list);
1897 m->md.pat_mode = PAT_WRITE_BACK;
1900 static int pmap_allow_2m_x_ept;
1901 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1902 &pmap_allow_2m_x_ept, 0,
1903 "Allow executable superpage mappings in EPT");
1906 pmap_allow_2m_x_ept_recalculate(void)
1909 * SKL002, SKL012S. Since the EPT format is only used by
1910 * Intel CPUs, the vendor check is merely a formality.
1912 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1913 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1914 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1915 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1916 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1917 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1918 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1919 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1920 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1921 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1922 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1923 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1924 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1925 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1926 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1927 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1928 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1929 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1930 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1931 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1932 CPUID_TO_MODEL(cpu_id) == 0x85))))
1933 pmap_allow_2m_x_ept = 1;
1934 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1938 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1941 return (pmap->pm_type != PT_EPT || !executable ||
1942 !pmap_allow_2m_x_ept);
1947 pmap_init_pv_table(void)
1949 struct pmap_large_md_page *pvd;
1951 long start, end, highest, pv_npg;
1952 int domain, i, j, pages;
1955 * We strongly depend on the size being a power of two, so the assert
1956 * is overzealous. However, should the struct be resized to a
1957 * different power of two, the code below needs to be revisited.
1959 CTASSERT((sizeof(*pvd) == 64));
1962 * Calculate the size of the array.
1964 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
1965 pv_npg = howmany(pmap_last_pa, NBPDR);
1966 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
1968 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1969 if (pv_table == NULL)
1970 panic("%s: kva_alloc failed\n", __func__);
1973 * Iterate physical segments to allocate space for respective pages.
1977 for (i = 0; i < vm_phys_nsegs; i++) {
1978 end = vm_phys_segs[i].end / NBPDR;
1979 domain = vm_phys_segs[i].domain;
1984 start = highest + 1;
1985 pvd = &pv_table[start];
1987 pages = end - start + 1;
1988 s = round_page(pages * sizeof(*pvd));
1989 highest = start + (s / sizeof(*pvd)) - 1;
1991 for (j = 0; j < s; j += PAGE_SIZE) {
1992 vm_page_t m = vm_page_alloc_domain(NULL, 0,
1993 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
1995 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
1996 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
1999 for (j = 0; j < s / sizeof(*pvd); j++) {
2000 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2001 TAILQ_INIT(&pvd->pv_page.pv_list);
2002 pvd->pv_page.pv_gen = 0;
2003 pvd->pv_page.pat_mode = 0;
2004 pvd->pv_invl_gen = 0;
2008 pvd = &pv_dummy_large;
2009 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2010 TAILQ_INIT(&pvd->pv_page.pv_list);
2011 pvd->pv_page.pv_gen = 0;
2012 pvd->pv_page.pat_mode = 0;
2013 pvd->pv_invl_gen = 0;
2017 pmap_init_pv_table(void)
2023 * Initialize the pool of pv list locks.
2025 for (i = 0; i < NPV_LIST_LOCKS; i++)
2026 rw_init(&pv_list_locks[i], "pmap pv list");
2029 * Calculate the size of the pv head table for superpages.
2031 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2034 * Allocate memory for the pv head table for superpages.
2036 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2038 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2039 for (i = 0; i < pv_npg; i++)
2040 TAILQ_INIT(&pv_table[i].pv_list);
2041 TAILQ_INIT(&pv_dummy.pv_list);
2046 * Initialize the pmap module.
2047 * Called by vm_init, to initialize any structures that the pmap
2048 * system needs to map virtual memory.
2053 struct pmap_preinit_mapping *ppim;
2055 int error, i, ret, skz63;
2057 /* L1TF, reserve page @0 unconditionally */
2058 vm_page_blacklist_add(0, bootverbose);
2060 /* Detect bare-metal Skylake Server and Skylake-X. */
2061 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2062 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2064 * Skylake-X errata SKZ63. Processor May Hang When
2065 * Executing Code In an HLE Transaction Region between
2066 * 40000000H and 403FFFFFH.
2068 * Mark the pages in the range as preallocated. It
2069 * seems to be impossible to distinguish between
2070 * Skylake Server and Skylake X.
2073 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2076 printf("SKZ63: skipping 4M RAM starting "
2077 "at physical 1G\n");
2078 for (i = 0; i < atop(0x400000); i++) {
2079 ret = vm_page_blacklist_add(0x40000000 +
2081 if (!ret && bootverbose)
2082 printf("page at %#lx already used\n",
2083 0x40000000 + ptoa(i));
2089 pmap_allow_2m_x_ept_recalculate();
2092 * Initialize the vm page array entries for the kernel pmap's
2095 PMAP_LOCK(kernel_pmap);
2096 for (i = 0; i < nkpt; i++) {
2097 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2098 KASSERT(mpte >= vm_page_array &&
2099 mpte < &vm_page_array[vm_page_array_size],
2100 ("pmap_init: page table page is out of range"));
2101 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2102 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2103 mpte->ref_count = 1;
2106 * Collect the page table pages that were replaced by a 2MB
2107 * page in create_pagetables(). They are zero filled.
2109 if (i << PDRSHIFT < KERNend &&
2110 pmap_insert_pt_page(kernel_pmap, mpte, false))
2111 panic("pmap_init: pmap_insert_pt_page failed");
2113 PMAP_UNLOCK(kernel_pmap);
2117 * If the kernel is running on a virtual machine, then it must assume
2118 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2119 * be prepared for the hypervisor changing the vendor and family that
2120 * are reported by CPUID. Consequently, the workaround for AMD Family
2121 * 10h Erratum 383 is enabled if the processor's feature set does not
2122 * include at least one feature that is only supported by older Intel
2123 * or newer AMD processors.
2125 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2126 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2127 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2129 workaround_erratum383 = 1;
2132 * Are large page mappings enabled?
2134 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2135 if (pg_ps_enabled) {
2136 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2137 ("pmap_init: can't assign to pagesizes[1]"));
2138 pagesizes[1] = NBPDR;
2142 * Initialize pv chunk lists.
2144 for (i = 0; i < PMAP_MEMDOM; i++) {
2145 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2146 TAILQ_INIT(&pv_chunks[i].pvc_list);
2148 pmap_init_pv_table();
2150 pmap_initialized = 1;
2151 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2152 ppim = pmap_preinit_mapping + i;
2155 /* Make the direct map consistent */
2156 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2157 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2158 ppim->sz, ppim->mode);
2162 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2163 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2166 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2167 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2168 (vmem_addr_t *)&qframe);
2170 panic("qframe allocation failed");
2173 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2174 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2175 lm_ents = LMEPML4I - LMSPML4I + 1;
2177 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2178 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2180 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2181 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2182 if (large_vmem == NULL) {
2183 printf("pmap: cannot create large map\n");
2186 for (i = 0; i < lm_ents; i++) {
2187 m = pmap_large_map_getptp_unlocked();
2188 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
2189 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2195 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2196 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2197 "Maximum number of PML4 entries for use by large map (tunable). "
2198 "Each entry corresponds to 512GB of address space.");
2200 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2201 "2MB page mapping counters");
2203 static u_long pmap_pde_demotions;
2204 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2205 &pmap_pde_demotions, 0, "2MB page demotions");
2207 static u_long pmap_pde_mappings;
2208 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2209 &pmap_pde_mappings, 0, "2MB page mappings");
2211 static u_long pmap_pde_p_failures;
2212 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2213 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2215 static u_long pmap_pde_promotions;
2216 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2217 &pmap_pde_promotions, 0, "2MB page promotions");
2219 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2220 "1GB page mapping counters");
2222 static u_long pmap_pdpe_demotions;
2223 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2224 &pmap_pdpe_demotions, 0, "1GB page demotions");
2226 /***************************************************
2227 * Low level helper routines.....
2228 ***************************************************/
2231 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2233 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2235 switch (pmap->pm_type) {
2238 /* Verify that both PAT bits are not set at the same time */
2239 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2240 ("Invalid PAT bits in entry %#lx", entry));
2242 /* Swap the PAT bits if one of them is set */
2243 if ((entry & x86_pat_bits) != 0)
2244 entry ^= x86_pat_bits;
2248 * Nothing to do - the memory attributes are represented
2249 * the same way for regular pages and superpages.
2253 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2260 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2263 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2264 pat_index[(int)mode] >= 0);
2268 * Determine the appropriate bits to set in a PTE or PDE for a specified
2272 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2274 int cache_bits, pat_flag, pat_idx;
2276 if (!pmap_is_valid_memattr(pmap, mode))
2277 panic("Unknown caching mode %d\n", mode);
2279 switch (pmap->pm_type) {
2282 /* The PAT bit is different for PTE's and PDE's. */
2283 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2285 /* Map the caching mode to a PAT index. */
2286 pat_idx = pat_index[mode];
2288 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2291 cache_bits |= pat_flag;
2293 cache_bits |= PG_NC_PCD;
2295 cache_bits |= PG_NC_PWT;
2299 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2303 panic("unsupported pmap type %d", pmap->pm_type);
2306 return (cache_bits);
2310 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2314 switch (pmap->pm_type) {
2317 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2320 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2323 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2330 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2332 int pat_flag, pat_idx;
2335 switch (pmap->pm_type) {
2338 /* The PAT bit is different for PTE's and PDE's. */
2339 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2341 if ((pte & pat_flag) != 0)
2343 if ((pte & PG_NC_PCD) != 0)
2345 if ((pte & PG_NC_PWT) != 0)
2349 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2350 panic("EPT PTE %#lx has no PAT memory type", pte);
2351 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2355 /* See pmap_init_pat(). */
2365 pmap_ps_enabled(pmap_t pmap)
2368 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2372 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2375 switch (pmap->pm_type) {
2382 * This is a little bogus since the generation number is
2383 * supposed to be bumped up when a region of the address
2384 * space is invalidated in the page tables.
2386 * In this case the old PDE entry is valid but yet we want
2387 * to make sure that any mappings using the old entry are
2388 * invalidated in the TLB.
2390 * The reason this works as expected is because we rendezvous
2391 * "all" host cpus and force any vcpu context to exit as a
2394 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2397 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2399 pde_store(pde, newpde);
2403 * After changing the page size for the specified virtual address in the page
2404 * table, flush the corresponding entries from the processor's TLB. Only the
2405 * calling processor's TLB is affected.
2407 * The calling thread must be pinned to a processor.
2410 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2414 if (pmap_type_guest(pmap))
2417 KASSERT(pmap->pm_type == PT_X86,
2418 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2420 PG_G = pmap_global_bit(pmap);
2422 if ((newpde & PG_PS) == 0)
2423 /* Demotion: flush a specific 2MB page mapping. */
2425 else if ((newpde & PG_G) == 0)
2427 * Promotion: flush every 4KB page mapping from the TLB
2428 * because there are too many to flush individually.
2433 * Promotion: flush every 4KB page mapping from the TLB,
2434 * including any global (PG_G) mappings.
2442 * For SMP, these functions have to use the IPI mechanism for coherence.
2444 * N.B.: Before calling any of the following TLB invalidation functions,
2445 * the calling processor must ensure that all stores updating a non-
2446 * kernel page table are globally performed. Otherwise, another
2447 * processor could cache an old, pre-update entry without being
2448 * invalidated. This can happen one of two ways: (1) The pmap becomes
2449 * active on another processor after its pm_active field is checked by
2450 * one of the following functions but before a store updating the page
2451 * table is globally performed. (2) The pmap becomes active on another
2452 * processor before its pm_active field is checked but due to
2453 * speculative loads one of the following functions stills reads the
2454 * pmap as inactive on the other processor.
2456 * The kernel page table is exempt because its pm_active field is
2457 * immutable. The kernel page table is always active on every
2462 * Interrupt the cpus that are executing in the guest context.
2463 * This will force the vcpu to exit and the cached EPT mappings
2464 * will be invalidated by the host before the next vmresume.
2466 static __inline void
2467 pmap_invalidate_ept(pmap_t pmap)
2472 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2473 ("pmap_invalidate_ept: absurd pm_active"));
2476 * The TLB mappings associated with a vcpu context are not
2477 * flushed each time a different vcpu is chosen to execute.
2479 * This is in contrast with a process's vtop mappings that
2480 * are flushed from the TLB on each context switch.
2482 * Therefore we need to do more than just a TLB shootdown on
2483 * the active cpus in 'pmap->pm_active'. To do this we keep
2484 * track of the number of invalidations performed on this pmap.
2486 * Each vcpu keeps a cache of this counter and compares it
2487 * just before a vmresume. If the counter is out-of-date an
2488 * invept will be done to flush stale mappings from the TLB.
2490 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2493 * Force the vcpu to exit and trap back into the hypervisor.
2495 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2496 ipi_selected(pmap->pm_active, ipinum);
2501 pmap_invalidate_cpu_mask(pmap_t pmap)
2504 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2508 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2509 const bool invpcid_works1)
2511 struct invpcid_descr d;
2512 uint64_t kcr3, ucr3;
2516 cpuid = PCPU_GET(cpuid);
2517 if (pmap == PCPU_GET(curpmap)) {
2518 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2520 * Because pm_pcid is recalculated on a
2521 * context switch, we must disable switching.
2522 * Otherwise, we might use a stale value
2526 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2527 if (invpcid_works1) {
2528 d.pcid = pcid | PMAP_PCID_USER_PT;
2531 invpcid(&d, INVPCID_ADDR);
2533 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2534 ucr3 = pmap->pm_ucr3 | pcid |
2535 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2536 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2541 pmap->pm_pcids[cpuid].pm_gen = 0;
2545 pmap->pm_pcids[i].pm_gen = 0;
2549 * The fence is between stores to pm_gen and the read of the
2550 * pm_active mask. We need to ensure that it is impossible
2551 * for us to miss the bit update in pm_active and
2552 * simultaneously observe a non-zero pm_gen in
2553 * pmap_activate_sw(), otherwise TLB update is missed.
2554 * Without the fence, IA32 allows such an outcome. Note that
2555 * pm_active is updated by a locked operation, which provides
2556 * the reciprocal fence.
2558 atomic_thread_fence_seq_cst();
2562 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2565 pmap_invalidate_page_pcid(pmap, va, true);
2569 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2572 pmap_invalidate_page_pcid(pmap, va, false);
2576 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2580 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2583 if (pmap_pcid_enabled)
2584 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2585 pmap_invalidate_page_pcid_noinvpcid);
2586 return (pmap_invalidate_page_nopcid);
2590 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2593 if (pmap_type_guest(pmap)) {
2594 pmap_invalidate_ept(pmap);
2598 KASSERT(pmap->pm_type == PT_X86,
2599 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2602 if (pmap == kernel_pmap) {
2605 if (pmap == PCPU_GET(curpmap))
2607 pmap_invalidate_page_mode(pmap, va);
2609 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2613 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2614 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2617 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2618 const bool invpcid_works1)
2620 struct invpcid_descr d;
2621 uint64_t kcr3, ucr3;
2625 cpuid = PCPU_GET(cpuid);
2626 if (pmap == PCPU_GET(curpmap)) {
2627 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2629 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2630 if (invpcid_works1) {
2631 d.pcid = pcid | PMAP_PCID_USER_PT;
2634 for (; d.addr < eva; d.addr += PAGE_SIZE)
2635 invpcid(&d, INVPCID_ADDR);
2637 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2638 ucr3 = pmap->pm_ucr3 | pcid |
2639 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2640 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2645 pmap->pm_pcids[cpuid].pm_gen = 0;
2649 pmap->pm_pcids[i].pm_gen = 0;
2651 /* See the comment in pmap_invalidate_page_pcid(). */
2652 atomic_thread_fence_seq_cst();
2656 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2660 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2664 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2668 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2672 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2676 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2680 if (pmap_pcid_enabled)
2681 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2682 pmap_invalidate_range_pcid_noinvpcid);
2683 return (pmap_invalidate_range_nopcid);
2687 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2691 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2692 pmap_invalidate_all(pmap);
2696 if (pmap_type_guest(pmap)) {
2697 pmap_invalidate_ept(pmap);
2701 KASSERT(pmap->pm_type == PT_X86,
2702 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2705 if (pmap == kernel_pmap) {
2706 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2709 if (pmap == PCPU_GET(curpmap)) {
2710 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2713 pmap_invalidate_range_mode(pmap, sva, eva);
2715 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2720 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2722 struct invpcid_descr d;
2723 uint64_t kcr3, ucr3;
2727 if (pmap == kernel_pmap) {
2728 if (invpcid_works1) {
2729 bzero(&d, sizeof(d));
2730 invpcid(&d, INVPCID_CTXGLOB);
2735 cpuid = PCPU_GET(cpuid);
2736 if (pmap == PCPU_GET(curpmap)) {
2738 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2739 if (invpcid_works1) {
2743 invpcid(&d, INVPCID_CTX);
2744 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2745 d.pcid |= PMAP_PCID_USER_PT;
2746 invpcid(&d, INVPCID_CTX);
2749 kcr3 = pmap->pm_cr3 | pcid;
2750 ucr3 = pmap->pm_ucr3;
2751 if (ucr3 != PMAP_NO_CR3) {
2752 ucr3 |= pcid | PMAP_PCID_USER_PT;
2753 pmap_pti_pcid_invalidate(ucr3, kcr3);
2760 pmap->pm_pcids[cpuid].pm_gen = 0;
2763 pmap->pm_pcids[i].pm_gen = 0;
2766 /* See the comment in pmap_invalidate_page_pcid(). */
2767 atomic_thread_fence_seq_cst();
2771 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2774 pmap_invalidate_all_pcid(pmap, true);
2778 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2781 pmap_invalidate_all_pcid(pmap, false);
2785 pmap_invalidate_all_nopcid(pmap_t pmap)
2788 if (pmap == kernel_pmap)
2790 else if (pmap == PCPU_GET(curpmap))
2794 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2797 if (pmap_pcid_enabled)
2798 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2799 pmap_invalidate_all_pcid_noinvpcid);
2800 return (pmap_invalidate_all_nopcid);
2804 pmap_invalidate_all(pmap_t pmap)
2807 if (pmap_type_guest(pmap)) {
2808 pmap_invalidate_ept(pmap);
2812 KASSERT(pmap->pm_type == PT_X86,
2813 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2816 pmap_invalidate_all_mode(pmap);
2817 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2822 pmap_invalidate_cache(void)
2832 cpuset_t invalidate; /* processors that invalidate their TLB */
2837 u_int store; /* processor that updates the PDE */
2841 pmap_update_pde_action(void *arg)
2843 struct pde_action *act = arg;
2845 if (act->store == PCPU_GET(cpuid))
2846 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2850 pmap_update_pde_teardown(void *arg)
2852 struct pde_action *act = arg;
2854 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2855 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2859 * Change the page size for the specified virtual address in a way that
2860 * prevents any possibility of the TLB ever having two entries that map the
2861 * same virtual address using different page sizes. This is the recommended
2862 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2863 * machine check exception for a TLB state that is improperly diagnosed as a
2867 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2869 struct pde_action act;
2870 cpuset_t active, other_cpus;
2874 cpuid = PCPU_GET(cpuid);
2875 other_cpus = all_cpus;
2876 CPU_CLR(cpuid, &other_cpus);
2877 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2880 active = pmap->pm_active;
2882 if (CPU_OVERLAP(&active, &other_cpus)) {
2884 act.invalidate = active;
2888 act.newpde = newpde;
2889 CPU_SET(cpuid, &active);
2890 smp_rendezvous_cpus(active,
2891 smp_no_rendezvous_barrier, pmap_update_pde_action,
2892 pmap_update_pde_teardown, &act);
2894 pmap_update_pde_store(pmap, pde, newpde);
2895 if (CPU_ISSET(cpuid, &active))
2896 pmap_update_pde_invalidate(pmap, va, newpde);
2902 * Normal, non-SMP, invalidation functions.
2905 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2907 struct invpcid_descr d;
2908 uint64_t kcr3, ucr3;
2911 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2915 KASSERT(pmap->pm_type == PT_X86,
2916 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2918 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2920 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2921 pmap->pm_ucr3 != PMAP_NO_CR3) {
2923 pcid = pmap->pm_pcids[0].pm_pcid;
2924 if (invpcid_works) {
2925 d.pcid = pcid | PMAP_PCID_USER_PT;
2928 invpcid(&d, INVPCID_ADDR);
2930 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2931 ucr3 = pmap->pm_ucr3 | pcid |
2932 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2933 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2937 } else if (pmap_pcid_enabled)
2938 pmap->pm_pcids[0].pm_gen = 0;
2942 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2944 struct invpcid_descr d;
2946 uint64_t kcr3, ucr3;
2948 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2952 KASSERT(pmap->pm_type == PT_X86,
2953 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2955 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2956 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2958 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2959 pmap->pm_ucr3 != PMAP_NO_CR3) {
2961 if (invpcid_works) {
2962 d.pcid = pmap->pm_pcids[0].pm_pcid |
2966 for (; d.addr < eva; d.addr += PAGE_SIZE)
2967 invpcid(&d, INVPCID_ADDR);
2969 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2970 pm_pcid | CR3_PCID_SAVE;
2971 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2972 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2973 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2977 } else if (pmap_pcid_enabled) {
2978 pmap->pm_pcids[0].pm_gen = 0;
2983 pmap_invalidate_all(pmap_t pmap)
2985 struct invpcid_descr d;
2986 uint64_t kcr3, ucr3;
2988 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2992 KASSERT(pmap->pm_type == PT_X86,
2993 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2995 if (pmap == kernel_pmap) {
2996 if (pmap_pcid_enabled && invpcid_works) {
2997 bzero(&d, sizeof(d));
2998 invpcid(&d, INVPCID_CTXGLOB);
3002 } else if (pmap == PCPU_GET(curpmap)) {
3003 if (pmap_pcid_enabled) {
3005 if (invpcid_works) {
3006 d.pcid = pmap->pm_pcids[0].pm_pcid;
3009 invpcid(&d, INVPCID_CTX);
3010 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3011 d.pcid |= PMAP_PCID_USER_PT;
3012 invpcid(&d, INVPCID_CTX);
3015 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3016 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3017 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3018 0].pm_pcid | PMAP_PCID_USER_PT;
3019 pmap_pti_pcid_invalidate(ucr3, kcr3);
3027 } else if (pmap_pcid_enabled) {
3028 pmap->pm_pcids[0].pm_gen = 0;
3033 pmap_invalidate_cache(void)
3040 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3043 pmap_update_pde_store(pmap, pde, newpde);
3044 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3045 pmap_update_pde_invalidate(pmap, va, newpde);
3047 pmap->pm_pcids[0].pm_gen = 0;
3052 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3056 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3057 * by a promotion that did not invalidate the 512 4KB page mappings
3058 * that might exist in the TLB. Consequently, at this point, the TLB
3059 * may hold both 4KB and 2MB page mappings for the address range [va,
3060 * va + NBPDR). Therefore, the entire range must be invalidated here.
3061 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3062 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3063 * single INVLPG suffices to invalidate the 2MB page mapping from the
3066 if ((pde & PG_PROMOTED) != 0)
3067 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3069 pmap_invalidate_page(pmap, va);
3072 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3073 (vm_offset_t sva, vm_offset_t eva))
3076 if ((cpu_feature & CPUID_SS) != 0)
3077 return (pmap_invalidate_cache_range_selfsnoop);
3078 if ((cpu_feature & CPUID_CLFSH) != 0)
3079 return (pmap_force_invalidate_cache_range);
3080 return (pmap_invalidate_cache_range_all);
3083 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3086 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3089 KASSERT((sva & PAGE_MASK) == 0,
3090 ("pmap_invalidate_cache_range: sva not page-aligned"));
3091 KASSERT((eva & PAGE_MASK) == 0,
3092 ("pmap_invalidate_cache_range: eva not page-aligned"));
3096 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3099 pmap_invalidate_cache_range_check_align(sva, eva);
3103 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3106 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3109 * XXX: Some CPUs fault, hang, or trash the local APIC
3110 * registers if we use CLFLUSH on the local APIC range. The
3111 * local APIC is always uncached, so we don't need to flush
3112 * for that range anyway.
3114 if (pmap_kextract(sva) == lapic_paddr)
3117 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3119 * Do per-cache line flush. Use a locked
3120 * instruction to insure that previous stores are
3121 * included in the write-back. The processor
3122 * propagates flush to other processors in the cache
3125 atomic_thread_fence_seq_cst();
3126 for (; sva < eva; sva += cpu_clflush_line_size)
3128 atomic_thread_fence_seq_cst();
3131 * Writes are ordered by CLFLUSH on Intel CPUs.
3133 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3135 for (; sva < eva; sva += cpu_clflush_line_size)
3137 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3143 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3146 pmap_invalidate_cache_range_check_align(sva, eva);
3147 pmap_invalidate_cache();
3151 * Remove the specified set of pages from the data and instruction caches.
3153 * In contrast to pmap_invalidate_cache_range(), this function does not
3154 * rely on the CPU's self-snoop feature, because it is intended for use
3155 * when moving pages into a different cache domain.
3158 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3160 vm_offset_t daddr, eva;
3164 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3165 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3166 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3167 pmap_invalidate_cache();
3170 atomic_thread_fence_seq_cst();
3171 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3173 for (i = 0; i < count; i++) {
3174 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3175 eva = daddr + PAGE_SIZE;
3176 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3184 atomic_thread_fence_seq_cst();
3185 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3191 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3194 pmap_invalidate_cache_range_check_align(sva, eva);
3196 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3197 pmap_force_invalidate_cache_range(sva, eva);
3201 /* See comment in pmap_force_invalidate_cache_range(). */
3202 if (pmap_kextract(sva) == lapic_paddr)
3205 atomic_thread_fence_seq_cst();
3206 for (; sva < eva; sva += cpu_clflush_line_size)
3208 atomic_thread_fence_seq_cst();
3212 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3216 int error, pte_bits;
3218 KASSERT((spa & PAGE_MASK) == 0,
3219 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3220 KASSERT((epa & PAGE_MASK) == 0,
3221 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3223 if (spa < dmaplimit) {
3224 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3226 if (dmaplimit >= epa)
3231 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3233 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3235 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3236 pte = vtopte(vaddr);
3237 for (; spa < epa; spa += PAGE_SIZE) {
3239 pte_store(pte, spa | pte_bits);
3241 /* XXXKIB atomic inside flush_cache_range are excessive */
3242 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3245 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3249 * Routine: pmap_extract
3251 * Extract the physical page address associated
3252 * with the given map/virtual_address pair.
3255 pmap_extract(pmap_t pmap, vm_offset_t va)
3259 pt_entry_t *pte, PG_V;
3263 PG_V = pmap_valid_bit(pmap);
3265 pdpe = pmap_pdpe(pmap, va);
3266 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3267 if ((*pdpe & PG_PS) != 0)
3268 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3270 pde = pmap_pdpe_to_pde(pdpe, va);
3271 if ((*pde & PG_V) != 0) {
3272 if ((*pde & PG_PS) != 0) {
3273 pa = (*pde & PG_PS_FRAME) |
3276 pte = pmap_pde_to_pte(pde, va);
3277 pa = (*pte & PG_FRAME) |
3288 * Routine: pmap_extract_and_hold
3290 * Atomically extract and hold the physical page
3291 * with the given pmap and virtual address pair
3292 * if that mapping permits the given protection.
3295 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3297 pd_entry_t pde, *pdep;
3298 pt_entry_t pte, PG_RW, PG_V;
3302 PG_RW = pmap_rw_bit(pmap);
3303 PG_V = pmap_valid_bit(pmap);
3306 pdep = pmap_pde(pmap, va);
3307 if (pdep != NULL && (pde = *pdep)) {
3309 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3310 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3313 pte = *pmap_pde_to_pte(pdep, va);
3314 if ((pte & PG_V) != 0 &&
3315 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3316 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3318 if (m != NULL && !vm_page_wire_mapped(m))
3326 pmap_kextract(vm_offset_t va)
3331 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3332 pa = DMAP_TO_PHYS(va);
3333 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3334 pa = pmap_large_map_kextract(va);
3338 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3341 * Beware of a concurrent promotion that changes the
3342 * PDE at this point! For example, vtopte() must not
3343 * be used to access the PTE because it would use the
3344 * new PDE. It is, however, safe to use the old PDE
3345 * because the page table page is preserved by the
3348 pa = *pmap_pde_to_pte(&pde, va);
3349 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3355 /***************************************************
3356 * Low level mapping routines.....
3357 ***************************************************/
3360 * Add a wired page to the kva.
3361 * Note: not SMP coherent.
3364 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3369 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3372 static __inline void
3373 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3379 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3380 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3384 * Remove a page from the kernel pagetables.
3385 * Note: not SMP coherent.
3388 pmap_kremove(vm_offset_t va)
3397 * Used to map a range of physical addresses into kernel
3398 * virtual address space.
3400 * The value passed in '*virt' is a suggested virtual address for
3401 * the mapping. Architectures which can support a direct-mapped
3402 * physical to virtual region can return the appropriate address
3403 * within that region, leaving '*virt' unchanged. Other
3404 * architectures should map the pages starting at '*virt' and
3405 * update '*virt' with the first usable address after the mapped
3409 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3411 return PHYS_TO_DMAP(start);
3416 * Add a list of wired pages to the kva
3417 * this routine is only used for temporary
3418 * kernel mappings that do not need to have
3419 * page modification or references recorded.
3420 * Note that old mappings are simply written
3421 * over. The page *must* be wired.
3422 * Note: SMP coherent. Uses a ranged shootdown IPI.
3425 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3427 pt_entry_t *endpte, oldpte, pa, *pte;
3433 endpte = pte + count;
3434 while (pte < endpte) {
3436 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3437 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3438 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3440 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3444 if (__predict_false((oldpte & X86_PG_V) != 0))
3445 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3450 * This routine tears out page mappings from the
3451 * kernel -- it is meant only for temporary mappings.
3452 * Note: SMP coherent. Uses a ranged shootdown IPI.
3455 pmap_qremove(vm_offset_t sva, int count)
3460 while (count-- > 0) {
3461 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3465 pmap_invalidate_range(kernel_pmap, sva, va);
3468 /***************************************************
3469 * Page table page management routines.....
3470 ***************************************************/
3472 * Schedule the specified unused page table page to be freed. Specifically,
3473 * add the page to the specified list of pages that will be released to the
3474 * physical memory manager after the TLB has been updated.
3476 static __inline void
3477 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3478 boolean_t set_PG_ZERO)
3482 m->flags |= PG_ZERO;
3484 m->flags &= ~PG_ZERO;
3485 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3489 * Inserts the specified page table page into the specified pmap's collection
3490 * of idle page table pages. Each of a pmap's page table pages is responsible
3491 * for mapping a distinct range of virtual addresses. The pmap's collection is
3492 * ordered by this virtual address range.
3494 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3497 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3500 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3501 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3502 return (vm_radix_insert(&pmap->pm_root, mpte));
3506 * Removes the page table page mapping the specified virtual address from the
3507 * specified pmap's collection of idle page table pages, and returns it.
3508 * Otherwise, returns NULL if there is no page table page corresponding to the
3509 * specified virtual address.
3511 static __inline vm_page_t
3512 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3515 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3516 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3520 * Decrements a page table page's reference count, which is used to record the
3521 * number of valid page table entries within the page. If the reference count
3522 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3523 * page table page was unmapped and FALSE otherwise.
3525 static inline boolean_t
3526 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3530 if (m->ref_count == 0) {
3531 _pmap_unwire_ptp(pmap, va, m, free);
3538 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3541 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3543 * unmap the page table page
3545 if (m->pindex >= NUPDE + NUPDPE) {
3548 pml4 = pmap_pml4e(pmap, va);
3550 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3551 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3554 } else if (m->pindex >= NUPDE) {
3557 pdp = pmap_pdpe(pmap, va);
3562 pd = pmap_pde(pmap, va);
3565 pmap_resident_count_dec(pmap, 1);
3566 if (m->pindex < NUPDE) {
3567 /* We just released a PT, unhold the matching PD */
3570 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3571 pmap_unwire_ptp(pmap, va, pdpg, free);
3572 } else if (m->pindex < NUPDE + NUPDPE) {
3573 /* We just released a PD, unhold the matching PDP */
3576 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3577 pmap_unwire_ptp(pmap, va, pdppg, free);
3581 * Put page on a list so that it is released after
3582 * *ALL* TLB shootdown is done
3584 pmap_add_delayed_free_list(m, free, TRUE);
3588 * After removing a page table entry, this routine is used to
3589 * conditionally free the page, and manage the reference count.
3592 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3593 struct spglist *free)
3597 if (va >= VM_MAXUSER_ADDRESS)
3599 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3600 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3601 return (pmap_unwire_ptp(pmap, va, mpte, free));
3605 * Release a page table page reference after a failed attempt to create a
3609 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3611 struct spglist free;
3614 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3616 * Although "va" was never mapped, paging-structure caches
3617 * could nonetheless have entries that refer to the freed
3618 * page table pages. Invalidate those entries.
3620 pmap_invalidate_page(pmap, va);
3621 vm_page_free_pages_toq(&free, true);
3626 pmap_pinit0(pmap_t pmap)
3632 PMAP_LOCK_INIT(pmap);
3633 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3634 pmap->pm_pml4u = NULL;
3635 pmap->pm_cr3 = KPML4phys;
3636 /* hack to keep pmap_pti_pcid_invalidate() alive */
3637 pmap->pm_ucr3 = PMAP_NO_CR3;
3638 pmap->pm_root.rt_root = 0;
3639 CPU_ZERO(&pmap->pm_active);
3640 TAILQ_INIT(&pmap->pm_pvchunk);
3641 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3642 pmap->pm_flags = pmap_flags;
3644 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3645 pmap->pm_pcids[i].pm_gen = 1;
3647 pmap_activate_boot(pmap);
3652 p->p_md.md_flags |= P_MD_KPTI;
3655 pmap_thread_init_invl_gen(td);
3657 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3658 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3659 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3665 pmap_pinit_pml4(vm_page_t pml4pg)
3667 pml4_entry_t *pm_pml4;
3670 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3672 /* Wire in kernel global address entries. */
3673 for (i = 0; i < NKPML4E; i++) {
3674 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3677 for (i = 0; i < ndmpdpphys; i++) {
3678 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3682 /* install self-referential address mapping entry(s) */
3683 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3684 X86_PG_A | X86_PG_M;
3686 /* install large map entries if configured */
3687 for (i = 0; i < lm_ents; i++)
3688 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3692 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3694 pml4_entry_t *pm_pml4;
3697 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3698 for (i = 0; i < NPML4EPG; i++)
3699 pm_pml4[i] = pti_pml4[i];
3703 * Initialize a preallocated and zeroed pmap structure,
3704 * such as one in a vmspace structure.
3707 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3709 vm_page_t pml4pg, pml4pgu;
3710 vm_paddr_t pml4phys;
3714 * allocate the page directory page
3716 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3717 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3719 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3720 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3722 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3723 pmap->pm_pcids[i].pm_gen = 0;
3725 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3726 pmap->pm_ucr3 = PMAP_NO_CR3;
3727 pmap->pm_pml4u = NULL;
3729 pmap->pm_type = pm_type;
3730 if ((pml4pg->flags & PG_ZERO) == 0)
3731 pagezero(pmap->pm_pml4);
3734 * Do not install the host kernel mappings in the nested page
3735 * tables. These mappings are meaningless in the guest physical
3737 * Install minimal kernel mappings in PTI case.
3739 if (pm_type == PT_X86) {
3740 pmap->pm_cr3 = pml4phys;
3741 pmap_pinit_pml4(pml4pg);
3742 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3743 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3744 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3745 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3746 VM_PAGE_TO_PHYS(pml4pgu));
3747 pmap_pinit_pml4_pti(pml4pgu);
3748 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3750 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3751 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3752 pkru_free_range, pmap, M_NOWAIT);
3756 pmap->pm_root.rt_root = 0;
3757 CPU_ZERO(&pmap->pm_active);
3758 TAILQ_INIT(&pmap->pm_pvchunk);
3759 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3760 pmap->pm_flags = flags;
3761 pmap->pm_eptgen = 0;
3767 pmap_pinit(pmap_t pmap)
3770 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3774 * This routine is called if the desired page table page does not exist.
3776 * If page table page allocation fails, this routine may sleep before
3777 * returning NULL. It sleeps only if a lock pointer was given.
3779 * Note: If a page allocation fails at page table level two or three,
3780 * one or two pages may be held during the wait, only to be released
3781 * afterwards. This conservative approach is easily argued to avoid
3785 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3787 vm_page_t m, pdppg, pdpg;
3788 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3790 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3792 PG_A = pmap_accessed_bit(pmap);
3793 PG_M = pmap_modified_bit(pmap);
3794 PG_V = pmap_valid_bit(pmap);
3795 PG_RW = pmap_rw_bit(pmap);
3798 * Allocate a page table page.
3800 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3801 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3802 if (lockp != NULL) {
3803 RELEASE_PV_LIST_LOCK(lockp);
3805 PMAP_ASSERT_NOT_IN_DI();
3811 * Indicate the need to retry. While waiting, the page table
3812 * page may have been allocated.
3816 if ((m->flags & PG_ZERO) == 0)
3820 * Map the pagetable page into the process address space, if
3821 * it isn't already there.
3824 if (ptepindex >= (NUPDE + NUPDPE)) {
3825 pml4_entry_t *pml4, *pml4u;
3826 vm_pindex_t pml4index;
3828 /* Wire up a new PDPE page */
3829 pml4index = ptepindex - (NUPDE + NUPDPE);
3830 pml4 = &pmap->pm_pml4[pml4index];
3831 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3832 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3834 * PTI: Make all user-space mappings in the
3835 * kernel-mode page table no-execute so that
3836 * we detect any programming errors that leave
3837 * the kernel-mode page table active on return
3840 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3843 pml4u = &pmap->pm_pml4u[pml4index];
3844 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3848 } else if (ptepindex >= NUPDE) {
3849 vm_pindex_t pml4index;
3850 vm_pindex_t pdpindex;
3854 /* Wire up a new PDE page */
3855 pdpindex = ptepindex - NUPDE;
3856 pml4index = pdpindex >> NPML4EPGSHIFT;
3858 pml4 = &pmap->pm_pml4[pml4index];
3859 if ((*pml4 & PG_V) == 0) {
3860 /* Have to allocate a new pdp, recurse */
3861 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3863 vm_page_unwire_noq(m);
3864 vm_page_free_zero(m);
3868 /* Add reference to pdp page */
3869 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3872 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3874 /* Now find the pdp page */
3875 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3876 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3879 vm_pindex_t pml4index;
3880 vm_pindex_t pdpindex;
3885 /* Wire up a new PTE page */
3886 pdpindex = ptepindex >> NPDPEPGSHIFT;
3887 pml4index = pdpindex >> NPML4EPGSHIFT;
3889 /* First, find the pdp and check that its valid. */
3890 pml4 = &pmap->pm_pml4[pml4index];
3891 if ((*pml4 & PG_V) == 0) {
3892 /* Have to allocate a new pd, recurse */
3893 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3895 vm_page_unwire_noq(m);
3896 vm_page_free_zero(m);
3899 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3900 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3902 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3903 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3904 if ((*pdp & PG_V) == 0) {
3905 /* Have to allocate a new pd, recurse */
3906 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3908 vm_page_unwire_noq(m);
3909 vm_page_free_zero(m);
3913 /* Add reference to the pd page */
3914 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3918 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3920 /* Now we know where the page directory page is */
3921 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3922 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3925 pmap_resident_count_inc(pmap, 1);
3931 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
3932 struct rwlock **lockp)
3934 pdp_entry_t *pdpe, PG_V;
3937 vm_pindex_t pdpindex;
3939 PG_V = pmap_valid_bit(pmap);
3942 pdpe = pmap_pdpe(pmap, va);
3943 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3944 pde = pmap_pdpe_to_pde(pdpe, va);
3945 if (va < VM_MAXUSER_ADDRESS) {
3946 /* Add a reference to the pd page. */
3947 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3951 } else if (va < VM_MAXUSER_ADDRESS) {
3952 /* Allocate a pd page. */
3953 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
3954 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3961 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3962 pde = &pde[pmap_pde_index(va)];
3964 panic("pmap_alloc_pde: missing page table page for va %#lx",
3971 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3973 vm_pindex_t ptepindex;
3974 pd_entry_t *pd, PG_V;
3977 PG_V = pmap_valid_bit(pmap);
3980 * Calculate pagetable page index
3982 ptepindex = pmap_pde_pindex(va);
3985 * Get the page directory entry
3987 pd = pmap_pde(pmap, va);
3990 * This supports switching from a 2MB page to a
3993 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3994 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3996 * Invalidation of the 2MB page mapping may have caused
3997 * the deallocation of the underlying PD page.
4004 * If the page table page is mapped, we just increment the
4005 * hold count, and activate it.
4007 if (pd != NULL && (*pd & PG_V) != 0) {
4008 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4012 * Here if the pte page isn't mapped, or if it has been
4015 m = _pmap_allocpte(pmap, ptepindex, lockp);
4016 if (m == NULL && lockp != NULL)
4023 /***************************************************
4024 * Pmap allocation/deallocation routines.
4025 ***************************************************/
4028 * Release any resources held by the given physical map.
4029 * Called when a pmap initialized by pmap_pinit is being released.
4030 * Should only be called if the map contains no valid mappings.
4033 pmap_release(pmap_t pmap)
4038 KASSERT(pmap->pm_stats.resident_count == 0,
4039 ("pmap_release: pmap resident count %ld != 0",
4040 pmap->pm_stats.resident_count));
4041 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4042 ("pmap_release: pmap has reserved page table page(s)"));
4043 KASSERT(CPU_EMPTY(&pmap->pm_active),
4044 ("releasing active pmap %p", pmap));
4046 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
4048 for (i = 0; i < NKPML4E; i++) /* KVA */
4049 pmap->pm_pml4[KPML4BASE + i] = 0;
4050 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4051 pmap->pm_pml4[DMPML4I + i] = 0;
4052 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
4053 for (i = 0; i < lm_ents; i++) /* Large Map */
4054 pmap->pm_pml4[LMSPML4I + i] = 0;
4056 vm_page_unwire_noq(m);
4057 vm_page_free_zero(m);
4059 if (pmap->pm_pml4u != NULL) {
4060 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
4061 vm_page_unwire_noq(m);
4064 if (pmap->pm_type == PT_X86 &&
4065 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4066 rangeset_fini(&pmap->pm_pkru);
4070 kvm_size(SYSCTL_HANDLER_ARGS)
4072 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4074 return sysctl_handle_long(oidp, &ksize, 0, req);
4076 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4077 0, 0, kvm_size, "LU",
4081 kvm_free(SYSCTL_HANDLER_ARGS)
4083 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4085 return sysctl_handle_long(oidp, &kfree, 0, req);
4087 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4088 0, 0, kvm_free, "LU",
4089 "Amount of KVM free");
4092 * Allocate physical memory for the vm_page array and map it into KVA,
4093 * attempting to back the vm_pages with domain-local memory.
4096 pmap_page_array_startup(long pages)
4099 pd_entry_t *pde, newpdir;
4100 vm_offset_t va, start, end;
4105 vm_page_array_size = pages;
4107 start = VM_MIN_KERNEL_ADDRESS;
4108 end = start + pages * sizeof(struct vm_page);
4109 for (va = start; va < end; va += NBPDR) {
4110 pfn = first_page + (va - start) / sizeof(struct vm_page);
4111 domain = _vm_phys_domain(ptoa(pfn));
4112 pdpe = pmap_pdpe(kernel_pmap, va);
4113 if ((*pdpe & X86_PG_V) == 0) {
4114 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4116 pagezero((void *)PHYS_TO_DMAP(pa));
4117 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4118 X86_PG_A | X86_PG_M);
4120 pde = pmap_pdpe_to_pde(pdpe, va);
4121 if ((*pde & X86_PG_V) != 0)
4122 panic("Unexpected pde");
4123 pa = vm_phys_early_alloc(domain, NBPDR);
4124 for (i = 0; i < NPDEPG; i++)
4125 dump_add_page(pa + i * PAGE_SIZE);
4126 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4127 X86_PG_M | PG_PS | pg_g | pg_nx);
4128 pde_store(pde, newpdir);
4130 vm_page_array = (vm_page_t)start;
4134 * grow the number of kernel page table entries, if needed
4137 pmap_growkernel(vm_offset_t addr)
4141 pd_entry_t *pde, newpdir;
4144 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4147 * Return if "addr" is within the range of kernel page table pages
4148 * that were preallocated during pmap bootstrap. Moreover, leave
4149 * "kernel_vm_end" and the kernel page table as they were.
4151 * The correctness of this action is based on the following
4152 * argument: vm_map_insert() allocates contiguous ranges of the
4153 * kernel virtual address space. It calls this function if a range
4154 * ends after "kernel_vm_end". If the kernel is mapped between
4155 * "kernel_vm_end" and "addr", then the range cannot begin at
4156 * "kernel_vm_end". In fact, its beginning address cannot be less
4157 * than the kernel. Thus, there is no immediate need to allocate
4158 * any new kernel page table pages between "kernel_vm_end" and
4161 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4164 addr = roundup2(addr, NBPDR);
4165 if (addr - 1 >= vm_map_max(kernel_map))
4166 addr = vm_map_max(kernel_map);
4167 while (kernel_vm_end < addr) {
4168 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4169 if ((*pdpe & X86_PG_V) == 0) {
4170 /* We need a new PDP entry */
4171 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4172 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4173 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4175 panic("pmap_growkernel: no memory to grow kernel");
4176 if ((nkpg->flags & PG_ZERO) == 0)
4177 pmap_zero_page(nkpg);
4178 paddr = VM_PAGE_TO_PHYS(nkpg);
4179 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4180 X86_PG_A | X86_PG_M);
4181 continue; /* try again */
4183 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4184 if ((*pde & X86_PG_V) != 0) {
4185 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4186 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4187 kernel_vm_end = vm_map_max(kernel_map);
4193 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4194 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4197 panic("pmap_growkernel: no memory to grow kernel");
4198 if ((nkpg->flags & PG_ZERO) == 0)
4199 pmap_zero_page(nkpg);
4200 paddr = VM_PAGE_TO_PHYS(nkpg);
4201 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4202 pde_store(pde, newpdir);
4204 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4205 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4206 kernel_vm_end = vm_map_max(kernel_map);
4213 /***************************************************
4214 * page management routines.
4215 ***************************************************/
4217 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4218 CTASSERT(_NPCM == 3);
4219 CTASSERT(_NPCPV == 168);
4221 static __inline struct pv_chunk *
4222 pv_to_chunk(pv_entry_t pv)
4225 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4228 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4230 #define PC_FREE0 0xfffffffffffffffful
4231 #define PC_FREE1 0xfffffffffffffffful
4232 #define PC_FREE2 0x000000fffffffffful
4234 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4237 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4239 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4240 "Current number of pv entry chunks");
4241 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4242 "Current number of pv entry chunks allocated");
4243 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4244 "Current number of pv entry chunks frees");
4245 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4246 "Number of times tried to get a chunk page but failed.");
4248 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4249 static int pv_entry_spare;
4251 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4252 "Current number of pv entry frees");
4253 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4254 "Current number of pv entry allocs");
4255 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4256 "Current number of pv entries");
4257 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4258 "Current number of spare pv entries");
4262 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4267 pmap_invalidate_all(pmap);
4268 if (pmap != locked_pmap)
4271 pmap_delayed_invl_finish();
4275 * We are in a serious low memory condition. Resort to
4276 * drastic measures to free some pages so we can allocate
4277 * another pv entry chunk.
4279 * Returns NULL if PV entries were reclaimed from the specified pmap.
4281 * We do not, however, unmap 2mpages because subsequent accesses will
4282 * allocate per-page pv entries until repromotion occurs, thereby
4283 * exacerbating the shortage of free pv entries.
4286 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4288 struct pv_chunks_list *pvc;
4289 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4290 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4291 struct md_page *pvh;
4293 pmap_t next_pmap, pmap;
4294 pt_entry_t *pte, tpte;
4295 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4299 struct spglist free;
4301 int bit, field, freed;
4302 bool start_di, restart;
4304 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4305 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4308 PG_G = PG_A = PG_M = PG_RW = 0;
4310 bzero(&pc_marker_b, sizeof(pc_marker_b));
4311 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4312 pc_marker = (struct pv_chunk *)&pc_marker_b;
4313 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4316 * A delayed invalidation block should already be active if
4317 * pmap_advise() or pmap_remove() called this function by way
4318 * of pmap_demote_pde_locked().
4320 start_di = pmap_not_in_di();
4322 pvc = &pv_chunks[domain];
4323 mtx_lock(&pvc->pvc_lock);
4324 pvc->active_reclaims++;
4325 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4326 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4327 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4328 SLIST_EMPTY(&free)) {
4329 next_pmap = pc->pc_pmap;
4330 if (next_pmap == NULL) {
4332 * The next chunk is a marker. However, it is
4333 * not our marker, so active_reclaims must be
4334 * > 1. Consequently, the next_chunk code
4335 * will not rotate the pv_chunks list.
4339 mtx_unlock(&pvc->pvc_lock);
4342 * A pv_chunk can only be removed from the pc_lru list
4343 * when both pc_chunks_mutex is owned and the
4344 * corresponding pmap is locked.
4346 if (pmap != next_pmap) {
4348 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4351 /* Avoid deadlock and lock recursion. */
4352 if (pmap > locked_pmap) {
4353 RELEASE_PV_LIST_LOCK(lockp);
4356 pmap_delayed_invl_start();
4357 mtx_lock(&pvc->pvc_lock);
4359 } else if (pmap != locked_pmap) {
4360 if (PMAP_TRYLOCK(pmap)) {
4362 pmap_delayed_invl_start();
4363 mtx_lock(&pvc->pvc_lock);
4366 pmap = NULL; /* pmap is not locked */
4367 mtx_lock(&pvc->pvc_lock);
4368 pc = TAILQ_NEXT(pc_marker, pc_lru);
4370 pc->pc_pmap != next_pmap)
4374 } else if (start_di)
4375 pmap_delayed_invl_start();
4376 PG_G = pmap_global_bit(pmap);
4377 PG_A = pmap_accessed_bit(pmap);
4378 PG_M = pmap_modified_bit(pmap);
4379 PG_RW = pmap_rw_bit(pmap);
4385 * Destroy every non-wired, 4 KB page mapping in the chunk.
4388 for (field = 0; field < _NPCM; field++) {
4389 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4390 inuse != 0; inuse &= ~(1UL << bit)) {
4392 pv = &pc->pc_pventry[field * 64 + bit];
4394 pde = pmap_pde(pmap, va);
4395 if ((*pde & PG_PS) != 0)
4397 pte = pmap_pde_to_pte(pde, va);
4398 if ((*pte & PG_W) != 0)
4400 tpte = pte_load_clear(pte);
4401 if ((tpte & PG_G) != 0)
4402 pmap_invalidate_page(pmap, va);
4403 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4404 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4406 if ((tpte & PG_A) != 0)
4407 vm_page_aflag_set(m, PGA_REFERENCED);
4408 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4409 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4411 if (TAILQ_EMPTY(&m->md.pv_list) &&
4412 (m->flags & PG_FICTITIOUS) == 0) {
4413 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4414 if (TAILQ_EMPTY(&pvh->pv_list)) {
4415 vm_page_aflag_clear(m,
4419 pmap_delayed_invl_page(m);
4420 pc->pc_map[field] |= 1UL << bit;
4421 pmap_unuse_pt(pmap, va, *pde, &free);
4426 mtx_lock(&pvc->pvc_lock);
4429 /* Every freed mapping is for a 4 KB page. */
4430 pmap_resident_count_dec(pmap, freed);
4431 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4432 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4433 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4434 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4435 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4436 pc->pc_map[2] == PC_FREE2) {
4437 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4438 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4439 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4440 /* Entire chunk is free; return it. */
4441 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4442 dump_drop_page(m_pc->phys_addr);
4443 mtx_lock(&pvc->pvc_lock);
4444 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4447 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4448 mtx_lock(&pvc->pvc_lock);
4449 /* One freed pv entry in locked_pmap is sufficient. */
4450 if (pmap == locked_pmap)
4453 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4454 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4455 if (pvc->active_reclaims == 1 && pmap != NULL) {
4457 * Rotate the pv chunks list so that we do not
4458 * scan the same pv chunks that could not be
4459 * freed (because they contained a wired
4460 * and/or superpage mapping) on every
4461 * invocation of reclaim_pv_chunk().
4463 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4464 MPASS(pc->pc_pmap != NULL);
4465 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4466 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4470 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4471 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4472 pvc->active_reclaims--;
4473 mtx_unlock(&pvc->pvc_lock);
4474 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4475 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4476 m_pc = SLIST_FIRST(&free);
4477 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4478 /* Recycle a freed page table page. */
4479 m_pc->ref_count = 1;
4481 vm_page_free_pages_toq(&free, true);
4486 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4491 domain = PCPU_GET(domain);
4492 for (i = 0; i < vm_ndomains; i++) {
4493 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4496 domain = (domain + 1) % vm_ndomains;
4503 * free the pv_entry back to the free list
4506 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4508 struct pv_chunk *pc;
4509 int idx, field, bit;
4511 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4512 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4513 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4514 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4515 pc = pv_to_chunk(pv);
4516 idx = pv - &pc->pc_pventry[0];
4519 pc->pc_map[field] |= 1ul << bit;
4520 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4521 pc->pc_map[2] != PC_FREE2) {
4522 /* 98% of the time, pc is already at the head of the list. */
4523 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4524 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4525 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4529 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4534 free_pv_chunk_dequeued(struct pv_chunk *pc)
4538 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4539 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4540 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4541 /* entire chunk is free, return it */
4542 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4543 dump_drop_page(m->phys_addr);
4544 vm_page_unwire_noq(m);
4549 free_pv_chunk(struct pv_chunk *pc)
4551 struct pv_chunks_list *pvc;
4553 pvc = &pv_chunks[pc_to_domain(pc)];
4554 mtx_lock(&pvc->pvc_lock);
4555 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4556 mtx_unlock(&pvc->pvc_lock);
4557 free_pv_chunk_dequeued(pc);
4561 free_pv_chunk_batch(struct pv_chunklist *batch)
4563 struct pv_chunks_list *pvc;
4564 struct pv_chunk *pc, *npc;
4567 for (i = 0; i < vm_ndomains; i++) {
4568 if (TAILQ_EMPTY(&batch[i]))
4570 pvc = &pv_chunks[i];
4571 mtx_lock(&pvc->pvc_lock);
4572 TAILQ_FOREACH(pc, &batch[i], pc_list) {
4573 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4575 mtx_unlock(&pvc->pvc_lock);
4578 for (i = 0; i < vm_ndomains; i++) {
4579 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
4580 free_pv_chunk_dequeued(pc);
4586 * Returns a new PV entry, allocating a new PV chunk from the system when
4587 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4588 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4591 * The given PV list lock may be released.
4594 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4596 struct pv_chunks_list *pvc;
4599 struct pv_chunk *pc;
4602 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4603 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4605 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4607 for (field = 0; field < _NPCM; field++) {
4608 if (pc->pc_map[field]) {
4609 bit = bsfq(pc->pc_map[field]);
4613 if (field < _NPCM) {
4614 pv = &pc->pc_pventry[field * 64 + bit];
4615 pc->pc_map[field] &= ~(1ul << bit);
4616 /* If this was the last item, move it to tail */
4617 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4618 pc->pc_map[2] == 0) {
4619 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4620 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4623 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4624 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4628 /* No free items, allocate another chunk */
4629 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4632 if (lockp == NULL) {
4633 PV_STAT(pc_chunk_tryfail++);
4636 m = reclaim_pv_chunk(pmap, lockp);
4640 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4641 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4642 dump_add_page(m->phys_addr);
4643 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4645 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4646 pc->pc_map[1] = PC_FREE1;
4647 pc->pc_map[2] = PC_FREE2;
4648 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
4649 mtx_lock(&pvc->pvc_lock);
4650 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4651 mtx_unlock(&pvc->pvc_lock);
4652 pv = &pc->pc_pventry[0];
4653 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4654 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4655 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4660 * Returns the number of one bits within the given PV chunk map.
4662 * The erratas for Intel processors state that "POPCNT Instruction May
4663 * Take Longer to Execute Than Expected". It is believed that the
4664 * issue is the spurious dependency on the destination register.
4665 * Provide a hint to the register rename logic that the destination
4666 * value is overwritten, by clearing it, as suggested in the
4667 * optimization manual. It should be cheap for unaffected processors
4670 * Reference numbers for erratas are
4671 * 4th Gen Core: HSD146
4672 * 5th Gen Core: BDM85
4673 * 6th Gen Core: SKL029
4676 popcnt_pc_map_pq(uint64_t *map)
4680 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4681 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4682 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4683 : "=&r" (result), "=&r" (tmp)
4684 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4689 * Ensure that the number of spare PV entries in the specified pmap meets or
4690 * exceeds the given count, "needed".
4692 * The given PV list lock may be released.
4695 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4697 struct pv_chunks_list *pvc;
4698 struct pch new_tail[PMAP_MEMDOM];
4699 struct pv_chunk *pc;
4704 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4705 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4708 * Newly allocated PV chunks must be stored in a private list until
4709 * the required number of PV chunks have been allocated. Otherwise,
4710 * reclaim_pv_chunk() could recycle one of these chunks. In
4711 * contrast, these chunks must be added to the pmap upon allocation.
4713 for (i = 0; i < PMAP_MEMDOM; i++)
4714 TAILQ_INIT(&new_tail[i]);
4717 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4719 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4720 bit_count((bitstr_t *)pc->pc_map, 0,
4721 sizeof(pc->pc_map) * NBBY, &free);
4724 free = popcnt_pc_map_pq(pc->pc_map);
4728 if (avail >= needed)
4731 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4732 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4735 m = reclaim_pv_chunk(pmap, lockp);
4740 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4741 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4742 dump_add_page(m->phys_addr);
4743 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4745 pc->pc_map[0] = PC_FREE0;
4746 pc->pc_map[1] = PC_FREE1;
4747 pc->pc_map[2] = PC_FREE2;
4748 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4749 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
4750 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4753 * The reclaim might have freed a chunk from the current pmap.
4754 * If that chunk contained available entries, we need to
4755 * re-count the number of available entries.
4760 for (i = 0; i < vm_ndomains; i++) {
4761 if (TAILQ_EMPTY(&new_tail[i]))
4763 pvc = &pv_chunks[i];
4764 mtx_lock(&pvc->pvc_lock);
4765 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
4766 mtx_unlock(&pvc->pvc_lock);
4771 * First find and then remove the pv entry for the specified pmap and virtual
4772 * address from the specified pv list. Returns the pv entry if found and NULL
4773 * otherwise. This operation can be performed on pv lists for either 4KB or
4774 * 2MB page mappings.
4776 static __inline pv_entry_t
4777 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4781 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4782 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4783 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4792 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4793 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4794 * entries for each of the 4KB page mappings.
4797 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4798 struct rwlock **lockp)
4800 struct md_page *pvh;
4801 struct pv_chunk *pc;
4803 vm_offset_t va_last;
4807 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4808 KASSERT((pa & PDRMASK) == 0,
4809 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4810 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4813 * Transfer the 2mpage's pv entry for this mapping to the first
4814 * page's pv list. Once this transfer begins, the pv list lock
4815 * must not be released until the last pv entry is reinstantiated.
4817 pvh = pa_to_pvh(pa);
4818 va = trunc_2mpage(va);
4819 pv = pmap_pvh_remove(pvh, pmap, va);
4820 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4821 m = PHYS_TO_VM_PAGE(pa);
4822 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4824 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4825 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4826 va_last = va + NBPDR - PAGE_SIZE;
4828 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4829 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4830 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4831 for (field = 0; field < _NPCM; field++) {
4832 while (pc->pc_map[field]) {
4833 bit = bsfq(pc->pc_map[field]);
4834 pc->pc_map[field] &= ~(1ul << bit);
4835 pv = &pc->pc_pventry[field * 64 + bit];
4839 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4840 ("pmap_pv_demote_pde: page %p is not managed", m));
4841 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4847 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4848 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4851 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4852 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4853 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4855 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4856 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4859 #if VM_NRESERVLEVEL > 0
4861 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4862 * replace the many pv entries for the 4KB page mappings by a single pv entry
4863 * for the 2MB page mapping.
4866 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4867 struct rwlock **lockp)
4869 struct md_page *pvh;
4871 vm_offset_t va_last;
4874 KASSERT((pa & PDRMASK) == 0,
4875 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4876 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4879 * Transfer the first page's pv entry for this mapping to the 2mpage's
4880 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4881 * a transfer avoids the possibility that get_pv_entry() calls
4882 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4883 * mappings that is being promoted.
4885 m = PHYS_TO_VM_PAGE(pa);
4886 va = trunc_2mpage(va);
4887 pv = pmap_pvh_remove(&m->md, pmap, va);
4888 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4889 pvh = pa_to_pvh(pa);
4890 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4892 /* Free the remaining NPTEPG - 1 pv entries. */
4893 va_last = va + NBPDR - PAGE_SIZE;
4897 pmap_pvh_free(&m->md, pmap, va);
4898 } while (va < va_last);
4900 #endif /* VM_NRESERVLEVEL > 0 */
4903 * First find and then destroy the pv entry for the specified pmap and virtual
4904 * address. This operation can be performed on pv lists for either 4KB or 2MB
4908 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4912 pv = pmap_pvh_remove(pvh, pmap, va);
4913 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4914 free_pv_entry(pmap, pv);
4918 * Conditionally create the PV entry for a 4KB page mapping if the required
4919 * memory can be allocated without resorting to reclamation.
4922 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4923 struct rwlock **lockp)
4927 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4928 /* Pass NULL instead of the lock pointer to disable reclamation. */
4929 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4931 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4932 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4940 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4941 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4942 * false if the PV entry cannot be allocated without resorting to reclamation.
4945 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4946 struct rwlock **lockp)
4948 struct md_page *pvh;
4952 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4953 /* Pass NULL instead of the lock pointer to disable reclamation. */
4954 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4955 NULL : lockp)) == NULL)
4958 pa = pde & PG_PS_FRAME;
4959 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4960 pvh = pa_to_pvh(pa);
4961 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4967 * Fills a page table page with mappings to consecutive physical pages.
4970 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4974 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4976 newpte += PAGE_SIZE;
4981 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4982 * mapping is invalidated.
4985 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4987 struct rwlock *lock;
4991 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4998 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5002 pt_entry_t *xpte, *ypte;
5004 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5005 xpte++, newpte += PAGE_SIZE) {
5006 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5007 printf("pmap_demote_pde: xpte %zd and newpte map "
5008 "different pages: found %#lx, expected %#lx\n",
5009 xpte - firstpte, *xpte, newpte);
5010 printf("page table dump\n");
5011 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5012 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5017 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5018 ("pmap_demote_pde: firstpte and newpte map different physical"
5025 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5026 pd_entry_t oldpde, struct rwlock **lockp)
5028 struct spglist free;
5032 sva = trunc_2mpage(va);
5033 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5034 if ((oldpde & pmap_global_bit(pmap)) == 0)
5035 pmap_invalidate_pde_page(pmap, sva, oldpde);
5036 vm_page_free_pages_toq(&free, true);
5037 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5042 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5043 struct rwlock **lockp)
5045 pd_entry_t newpde, oldpde;
5046 pt_entry_t *firstpte, newpte;
5047 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5053 PG_A = pmap_accessed_bit(pmap);
5054 PG_G = pmap_global_bit(pmap);
5055 PG_M = pmap_modified_bit(pmap);
5056 PG_RW = pmap_rw_bit(pmap);
5057 PG_V = pmap_valid_bit(pmap);
5058 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5059 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5061 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5062 in_kernel = va >= VM_MAXUSER_ADDRESS;
5064 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5065 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5068 * Invalidate the 2MB page mapping and return "failure" if the
5069 * mapping was never accessed.
5071 if ((oldpde & PG_A) == 0) {
5072 KASSERT((oldpde & PG_W) == 0,
5073 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5074 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5078 mpte = pmap_remove_pt_page(pmap, va);
5080 KASSERT((oldpde & PG_W) == 0,
5081 ("pmap_demote_pde: page table page for a wired mapping"
5085 * If the page table page is missing and the mapping
5086 * is for a kernel address, the mapping must belong to
5087 * the direct map. Page table pages are preallocated
5088 * for every other part of the kernel address space,
5089 * so the direct map region is the only part of the
5090 * kernel address space that must be handled here.
5092 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5093 va < DMAP_MAX_ADDRESS),
5094 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5097 * If the 2MB page mapping belongs to the direct map
5098 * region of the kernel's address space, then the page
5099 * allocation request specifies the highest possible
5100 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5101 * priority is normal.
5103 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5104 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5105 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5108 * If the allocation of the new page table page fails,
5109 * invalidate the 2MB page mapping and return "failure".
5112 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5117 mpte->ref_count = NPTEPG;
5118 pmap_resident_count_inc(pmap, 1);
5121 mptepa = VM_PAGE_TO_PHYS(mpte);
5122 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5123 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5124 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5125 ("pmap_demote_pde: oldpde is missing PG_M"));
5126 newpte = oldpde & ~PG_PS;
5127 newpte = pmap_swap_pat(pmap, newpte);
5130 * If the page table page is not leftover from an earlier promotion,
5133 if (mpte->valid == 0)
5134 pmap_fill_ptp(firstpte, newpte);
5136 pmap_demote_pde_check(firstpte, newpte);
5139 * If the mapping has changed attributes, update the page table
5142 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5143 pmap_fill_ptp(firstpte, newpte);
5146 * The spare PV entries must be reserved prior to demoting the
5147 * mapping, that is, prior to changing the PDE. Otherwise, the state
5148 * of the PDE and the PV lists will be inconsistent, which can result
5149 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5150 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5151 * PV entry for the 2MB page mapping that is being demoted.
5153 if ((oldpde & PG_MANAGED) != 0)
5154 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5157 * Demote the mapping. This pmap is locked. The old PDE has
5158 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5159 * set. Thus, there is no danger of a race with another
5160 * processor changing the setting of PG_A and/or PG_M between
5161 * the read above and the store below.
5163 if (workaround_erratum383)
5164 pmap_update_pde(pmap, va, pde, newpde);
5166 pde_store(pde, newpde);
5169 * Invalidate a stale recursive mapping of the page table page.
5172 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5175 * Demote the PV entry.
5177 if ((oldpde & PG_MANAGED) != 0)
5178 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5180 atomic_add_long(&pmap_pde_demotions, 1);
5181 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5187 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5190 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5196 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5197 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5198 mpte = pmap_remove_pt_page(pmap, va);
5200 panic("pmap_remove_kernel_pde: Missing pt page.");
5202 mptepa = VM_PAGE_TO_PHYS(mpte);
5203 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5206 * If this page table page was unmapped by a promotion, then it
5207 * contains valid mappings. Zero it to invalidate those mappings.
5209 if (mpte->valid != 0)
5210 pagezero((void *)PHYS_TO_DMAP(mptepa));
5213 * Demote the mapping.
5215 if (workaround_erratum383)
5216 pmap_update_pde(pmap, va, pde, newpde);
5218 pde_store(pde, newpde);
5221 * Invalidate a stale recursive mapping of the page table page.
5223 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5227 * pmap_remove_pde: do the things to unmap a superpage in a process
5230 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5231 struct spglist *free, struct rwlock **lockp)
5233 struct md_page *pvh;
5235 vm_offset_t eva, va;
5237 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5239 PG_G = pmap_global_bit(pmap);
5240 PG_A = pmap_accessed_bit(pmap);
5241 PG_M = pmap_modified_bit(pmap);
5242 PG_RW = pmap_rw_bit(pmap);
5244 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5245 KASSERT((sva & PDRMASK) == 0,
5246 ("pmap_remove_pde: sva is not 2mpage aligned"));
5247 oldpde = pte_load_clear(pdq);
5249 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5250 if ((oldpde & PG_G) != 0)
5251 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5252 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5253 if (oldpde & PG_MANAGED) {
5254 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5255 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5256 pmap_pvh_free(pvh, pmap, sva);
5258 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5259 va < eva; va += PAGE_SIZE, m++) {
5260 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5263 vm_page_aflag_set(m, PGA_REFERENCED);
5264 if (TAILQ_EMPTY(&m->md.pv_list) &&
5265 TAILQ_EMPTY(&pvh->pv_list))
5266 vm_page_aflag_clear(m, PGA_WRITEABLE);
5267 pmap_delayed_invl_page(m);
5270 if (pmap == kernel_pmap) {
5271 pmap_remove_kernel_pde(pmap, pdq, sva);
5273 mpte = pmap_remove_pt_page(pmap, sva);
5275 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5276 ("pmap_remove_pde: pte page not promoted"));
5277 pmap_resident_count_dec(pmap, 1);
5278 KASSERT(mpte->ref_count == NPTEPG,
5279 ("pmap_remove_pde: pte page ref count error"));
5280 mpte->ref_count = 0;
5281 pmap_add_delayed_free_list(mpte, free, FALSE);
5284 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5288 * pmap_remove_pte: do the things to unmap a page in a process
5291 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5292 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5294 struct md_page *pvh;
5295 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5298 PG_A = pmap_accessed_bit(pmap);
5299 PG_M = pmap_modified_bit(pmap);
5300 PG_RW = pmap_rw_bit(pmap);
5302 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5303 oldpte = pte_load_clear(ptq);
5305 pmap->pm_stats.wired_count -= 1;
5306 pmap_resident_count_dec(pmap, 1);
5307 if (oldpte & PG_MANAGED) {
5308 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5309 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5312 vm_page_aflag_set(m, PGA_REFERENCED);
5313 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5314 pmap_pvh_free(&m->md, pmap, va);
5315 if (TAILQ_EMPTY(&m->md.pv_list) &&
5316 (m->flags & PG_FICTITIOUS) == 0) {
5317 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5318 if (TAILQ_EMPTY(&pvh->pv_list))
5319 vm_page_aflag_clear(m, PGA_WRITEABLE);
5321 pmap_delayed_invl_page(m);
5323 return (pmap_unuse_pt(pmap, va, ptepde, free));
5327 * Remove a single page from a process address space
5330 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5331 struct spglist *free)
5333 struct rwlock *lock;
5334 pt_entry_t *pte, PG_V;
5336 PG_V = pmap_valid_bit(pmap);
5337 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5338 if ((*pde & PG_V) == 0)
5340 pte = pmap_pde_to_pte(pde, va);
5341 if ((*pte & PG_V) == 0)
5344 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5347 pmap_invalidate_page(pmap, va);
5351 * Removes the specified range of addresses from the page table page.
5354 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5355 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5357 pt_entry_t PG_G, *pte;
5361 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5362 PG_G = pmap_global_bit(pmap);
5365 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5369 pmap_invalidate_range(pmap, va, sva);
5374 if ((*pte & PG_G) == 0)
5378 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5384 pmap_invalidate_range(pmap, va, sva);
5389 * Remove the given range of addresses from the specified map.
5391 * It is assumed that the start and end are properly
5392 * rounded to the page size.
5395 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5397 struct rwlock *lock;
5398 vm_offset_t va_next;
5399 pml4_entry_t *pml4e;
5401 pd_entry_t ptpaddr, *pde;
5402 pt_entry_t PG_G, PG_V;
5403 struct spglist free;
5406 PG_G = pmap_global_bit(pmap);
5407 PG_V = pmap_valid_bit(pmap);
5410 * Perform an unsynchronized read. This is, however, safe.
5412 if (pmap->pm_stats.resident_count == 0)
5418 pmap_delayed_invl_start();
5420 pmap_pkru_on_remove(pmap, sva, eva);
5423 * special handling of removing one page. a very
5424 * common operation and easy to short circuit some
5427 if (sva + PAGE_SIZE == eva) {
5428 pde = pmap_pde(pmap, sva);
5429 if (pde && (*pde & PG_PS) == 0) {
5430 pmap_remove_page(pmap, sva, pde, &free);
5436 for (; sva < eva; sva = va_next) {
5438 if (pmap->pm_stats.resident_count == 0)
5441 pml4e = pmap_pml4e(pmap, sva);
5442 if ((*pml4e & PG_V) == 0) {
5443 va_next = (sva + NBPML4) & ~PML4MASK;
5449 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5450 if ((*pdpe & PG_V) == 0) {
5451 va_next = (sva + NBPDP) & ~PDPMASK;
5458 * Calculate index for next page table.
5460 va_next = (sva + NBPDR) & ~PDRMASK;
5464 pde = pmap_pdpe_to_pde(pdpe, sva);
5468 * Weed out invalid mappings.
5474 * Check for large page.
5476 if ((ptpaddr & PG_PS) != 0) {
5478 * Are we removing the entire large page? If not,
5479 * demote the mapping and fall through.
5481 if (sva + NBPDR == va_next && eva >= va_next) {
5483 * The TLB entry for a PG_G mapping is
5484 * invalidated by pmap_remove_pde().
5486 if ((ptpaddr & PG_G) == 0)
5488 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5490 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5492 /* The large page mapping was destroyed. */
5499 * Limit our scan to either the end of the va represented
5500 * by the current page table page, or to the end of the
5501 * range being removed.
5506 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5513 pmap_invalidate_all(pmap);
5515 pmap_delayed_invl_finish();
5516 vm_page_free_pages_toq(&free, true);
5520 * Routine: pmap_remove_all
5522 * Removes this physical page from
5523 * all physical maps in which it resides.
5524 * Reflects back modify bits to the pager.
5527 * Original versions of this routine were very
5528 * inefficient because they iteratively called
5529 * pmap_remove (slow...)
5533 pmap_remove_all(vm_page_t m)
5535 struct md_page *pvh;
5538 struct rwlock *lock;
5539 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5542 struct spglist free;
5543 int pvh_gen, md_gen;
5545 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5546 ("pmap_remove_all: page %p is not managed", m));
5548 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5549 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5550 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5553 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5555 if (!PMAP_TRYLOCK(pmap)) {
5556 pvh_gen = pvh->pv_gen;
5560 if (pvh_gen != pvh->pv_gen) {
5567 pde = pmap_pde(pmap, va);
5568 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5571 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5573 if (!PMAP_TRYLOCK(pmap)) {
5574 pvh_gen = pvh->pv_gen;
5575 md_gen = m->md.pv_gen;
5579 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5585 PG_A = pmap_accessed_bit(pmap);
5586 PG_M = pmap_modified_bit(pmap);
5587 PG_RW = pmap_rw_bit(pmap);
5588 pmap_resident_count_dec(pmap, 1);
5589 pde = pmap_pde(pmap, pv->pv_va);
5590 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5591 " a 2mpage in page %p's pv list", m));
5592 pte = pmap_pde_to_pte(pde, pv->pv_va);
5593 tpte = pte_load_clear(pte);
5595 pmap->pm_stats.wired_count--;
5597 vm_page_aflag_set(m, PGA_REFERENCED);
5600 * Update the vm_page_t clean and reference bits.
5602 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5604 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5605 pmap_invalidate_page(pmap, pv->pv_va);
5606 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5608 free_pv_entry(pmap, pv);
5611 vm_page_aflag_clear(m, PGA_WRITEABLE);
5613 pmap_delayed_invl_wait(m);
5614 vm_page_free_pages_toq(&free, true);
5618 * pmap_protect_pde: do the things to protect a 2mpage in a process
5621 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5623 pd_entry_t newpde, oldpde;
5625 boolean_t anychanged;
5626 pt_entry_t PG_G, PG_M, PG_RW;
5628 PG_G = pmap_global_bit(pmap);
5629 PG_M = pmap_modified_bit(pmap);
5630 PG_RW = pmap_rw_bit(pmap);
5632 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5633 KASSERT((sva & PDRMASK) == 0,
5634 ("pmap_protect_pde: sva is not 2mpage aligned"));
5637 oldpde = newpde = *pde;
5638 if ((prot & VM_PROT_WRITE) == 0) {
5639 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5640 (PG_MANAGED | PG_M | PG_RW)) {
5641 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5642 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5645 newpde &= ~(PG_RW | PG_M);
5647 if ((prot & VM_PROT_EXECUTE) == 0)
5649 if (newpde != oldpde) {
5651 * As an optimization to future operations on this PDE, clear
5652 * PG_PROMOTED. The impending invalidation will remove any
5653 * lingering 4KB page mappings from the TLB.
5655 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5657 if ((oldpde & PG_G) != 0)
5658 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5662 return (anychanged);
5666 * Set the physical protection on the
5667 * specified range of this map as requested.
5670 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5672 vm_offset_t va_next;
5673 pml4_entry_t *pml4e;
5675 pd_entry_t ptpaddr, *pde;
5676 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5677 boolean_t anychanged;
5679 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5680 if (prot == VM_PROT_NONE) {
5681 pmap_remove(pmap, sva, eva);
5685 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5686 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5689 PG_G = pmap_global_bit(pmap);
5690 PG_M = pmap_modified_bit(pmap);
5691 PG_V = pmap_valid_bit(pmap);
5692 PG_RW = pmap_rw_bit(pmap);
5696 * Although this function delays and batches the invalidation
5697 * of stale TLB entries, it does not need to call
5698 * pmap_delayed_invl_start() and
5699 * pmap_delayed_invl_finish(), because it does not
5700 * ordinarily destroy mappings. Stale TLB entries from
5701 * protection-only changes need only be invalidated before the
5702 * pmap lock is released, because protection-only changes do
5703 * not destroy PV entries. Even operations that iterate over
5704 * a physical page's PV list of mappings, like
5705 * pmap_remove_write(), acquire the pmap lock for each
5706 * mapping. Consequently, for protection-only changes, the
5707 * pmap lock suffices to synchronize both page table and TLB
5710 * This function only destroys a mapping if pmap_demote_pde()
5711 * fails. In that case, stale TLB entries are immediately
5716 for (; sva < eva; sva = va_next) {
5718 pml4e = pmap_pml4e(pmap, sva);
5719 if ((*pml4e & PG_V) == 0) {
5720 va_next = (sva + NBPML4) & ~PML4MASK;
5726 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5727 if ((*pdpe & PG_V) == 0) {
5728 va_next = (sva + NBPDP) & ~PDPMASK;
5734 va_next = (sva + NBPDR) & ~PDRMASK;
5738 pde = pmap_pdpe_to_pde(pdpe, sva);
5742 * Weed out invalid mappings.
5748 * Check for large page.
5750 if ((ptpaddr & PG_PS) != 0) {
5752 * Are we protecting the entire large page? If not,
5753 * demote the mapping and fall through.
5755 if (sva + NBPDR == va_next && eva >= va_next) {
5757 * The TLB entry for a PG_G mapping is
5758 * invalidated by pmap_protect_pde().
5760 if (pmap_protect_pde(pmap, pde, sva, prot))
5763 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5765 * The large page mapping was destroyed.
5774 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5776 pt_entry_t obits, pbits;
5780 obits = pbits = *pte;
5781 if ((pbits & PG_V) == 0)
5784 if ((prot & VM_PROT_WRITE) == 0) {
5785 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5786 (PG_MANAGED | PG_M | PG_RW)) {
5787 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5790 pbits &= ~(PG_RW | PG_M);
5792 if ((prot & VM_PROT_EXECUTE) == 0)
5795 if (pbits != obits) {
5796 if (!atomic_cmpset_long(pte, obits, pbits))
5799 pmap_invalidate_page(pmap, sva);
5806 pmap_invalidate_all(pmap);
5810 #if VM_NRESERVLEVEL > 0
5812 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5815 if (pmap->pm_type != PT_EPT)
5817 return ((pde & EPT_PG_EXECUTE) != 0);
5821 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5822 * single page table page (PTP) to a single 2MB page mapping. For promotion
5823 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5824 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5825 * identical characteristics.
5828 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5829 struct rwlock **lockp)
5832 pt_entry_t *firstpte, oldpte, pa, *pte;
5833 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5837 PG_A = pmap_accessed_bit(pmap);
5838 PG_G = pmap_global_bit(pmap);
5839 PG_M = pmap_modified_bit(pmap);
5840 PG_V = pmap_valid_bit(pmap);
5841 PG_RW = pmap_rw_bit(pmap);
5842 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5843 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5845 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5848 * Examine the first PTE in the specified PTP. Abort if this PTE is
5849 * either invalid, unused, or does not map the first 4KB physical page
5850 * within a 2MB page.
5852 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5855 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5856 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5858 atomic_add_long(&pmap_pde_p_failures, 1);
5859 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5860 " in pmap %p", va, pmap);
5863 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5865 * When PG_M is already clear, PG_RW can be cleared without
5866 * a TLB invalidation.
5868 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5874 * Examine each of the other PTEs in the specified PTP. Abort if this
5875 * PTE maps an unexpected 4KB physical page or does not have identical
5876 * characteristics to the first PTE.
5878 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5879 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5882 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5883 atomic_add_long(&pmap_pde_p_failures, 1);
5884 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5885 " in pmap %p", va, pmap);
5888 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5890 * When PG_M is already clear, PG_RW can be cleared
5891 * without a TLB invalidation.
5893 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5896 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5897 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5898 (va & ~PDRMASK), pmap);
5900 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5901 atomic_add_long(&pmap_pde_p_failures, 1);
5902 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5903 " in pmap %p", va, pmap);
5910 * Save the page table page in its current state until the PDE
5911 * mapping the superpage is demoted by pmap_demote_pde() or
5912 * destroyed by pmap_remove_pde().
5914 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5915 KASSERT(mpte >= vm_page_array &&
5916 mpte < &vm_page_array[vm_page_array_size],
5917 ("pmap_promote_pde: page table page is out of range"));
5918 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5919 ("pmap_promote_pde: page table page's pindex is wrong"));
5920 if (pmap_insert_pt_page(pmap, mpte, true)) {
5921 atomic_add_long(&pmap_pde_p_failures, 1);
5923 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5929 * Promote the pv entries.
5931 if ((newpde & PG_MANAGED) != 0)
5932 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5935 * Propagate the PAT index to its proper position.
5937 newpde = pmap_swap_pat(pmap, newpde);
5940 * Map the superpage.
5942 if (workaround_erratum383)
5943 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5945 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5947 atomic_add_long(&pmap_pde_promotions, 1);
5948 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5949 " in pmap %p", va, pmap);
5951 #endif /* VM_NRESERVLEVEL > 0 */
5954 * Insert the given physical page (p) at
5955 * the specified virtual address (v) in the
5956 * target physical map with the protection requested.
5958 * If specified, the page will be wired down, meaning
5959 * that the related pte can not be reclaimed.
5961 * NB: This is the only routine which MAY NOT lazy-evaluate
5962 * or lose information. That is, this routine must actually
5963 * insert this page into the given map NOW.
5965 * When destroying both a page table and PV entry, this function
5966 * performs the TLB invalidation before releasing the PV list
5967 * lock, so we do not need pmap_delayed_invl_page() calls here.
5970 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5971 u_int flags, int8_t psind)
5973 struct rwlock *lock;
5975 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5976 pt_entry_t newpte, origpte;
5983 PG_A = pmap_accessed_bit(pmap);
5984 PG_G = pmap_global_bit(pmap);
5985 PG_M = pmap_modified_bit(pmap);
5986 PG_V = pmap_valid_bit(pmap);
5987 PG_RW = pmap_rw_bit(pmap);
5989 va = trunc_page(va);
5990 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5991 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5992 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5994 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5995 va >= kmi.clean_eva,
5996 ("pmap_enter: managed mapping within the clean submap"));
5997 if ((m->oflags & VPO_UNMANAGED) == 0)
5998 VM_PAGE_OBJECT_BUSY_ASSERT(m);
5999 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6000 ("pmap_enter: flags %u has reserved bits set", flags));
6001 pa = VM_PAGE_TO_PHYS(m);
6002 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6003 if ((flags & VM_PROT_WRITE) != 0)
6005 if ((prot & VM_PROT_WRITE) != 0)
6007 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6008 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6009 if ((prot & VM_PROT_EXECUTE) == 0)
6011 if ((flags & PMAP_ENTER_WIRED) != 0)
6013 if (va < VM_MAXUSER_ADDRESS)
6015 if (pmap == kernel_pmap)
6017 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6020 * Set modified bit gratuitously for writeable mappings if
6021 * the page is unmanaged. We do not want to take a fault
6022 * to do the dirty bit accounting for these mappings.
6024 if ((m->oflags & VPO_UNMANAGED) != 0) {
6025 if ((newpte & PG_RW) != 0)
6028 newpte |= PG_MANAGED;
6033 /* Assert the required virtual and physical alignment. */
6034 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6035 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6036 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6042 * In the case that a page table page is not
6043 * resident, we are creating it here.
6046 pde = pmap_pde(pmap, va);
6047 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6048 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6049 pte = pmap_pde_to_pte(pde, va);
6050 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6051 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6054 } else if (va < VM_MAXUSER_ADDRESS) {
6056 * Here if the pte page isn't mapped, or if it has been
6059 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6060 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6061 nosleep ? NULL : &lock);
6062 if (mpte == NULL && nosleep) {
6063 rv = KERN_RESOURCE_SHORTAGE;
6068 panic("pmap_enter: invalid page directory va=%#lx", va);
6072 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6073 newpte |= pmap_pkru_get(pmap, va);
6076 * Is the specified virtual address already mapped?
6078 if ((origpte & PG_V) != 0) {
6080 * Wiring change, just update stats. We don't worry about
6081 * wiring PT pages as they remain resident as long as there
6082 * are valid mappings in them. Hence, if a user page is wired,
6083 * the PT page will be also.
6085 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6086 pmap->pm_stats.wired_count++;
6087 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6088 pmap->pm_stats.wired_count--;
6091 * Remove the extra PT page reference.
6095 KASSERT(mpte->ref_count > 0,
6096 ("pmap_enter: missing reference to page table page,"
6101 * Has the physical page changed?
6103 opa = origpte & PG_FRAME;
6106 * No, might be a protection or wiring change.
6108 if ((origpte & PG_MANAGED) != 0 &&
6109 (newpte & PG_RW) != 0)
6110 vm_page_aflag_set(m, PGA_WRITEABLE);
6111 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6117 * The physical page has changed. Temporarily invalidate
6118 * the mapping. This ensures that all threads sharing the
6119 * pmap keep a consistent view of the mapping, which is
6120 * necessary for the correct handling of COW faults. It
6121 * also permits reuse of the old mapping's PV entry,
6122 * avoiding an allocation.
6124 * For consistency, handle unmanaged mappings the same way.
6126 origpte = pte_load_clear(pte);
6127 KASSERT((origpte & PG_FRAME) == opa,
6128 ("pmap_enter: unexpected pa update for %#lx", va));
6129 if ((origpte & PG_MANAGED) != 0) {
6130 om = PHYS_TO_VM_PAGE(opa);
6133 * The pmap lock is sufficient to synchronize with
6134 * concurrent calls to pmap_page_test_mappings() and
6135 * pmap_ts_referenced().
6137 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6139 if ((origpte & PG_A) != 0) {
6140 pmap_invalidate_page(pmap, va);
6141 vm_page_aflag_set(om, PGA_REFERENCED);
6143 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6144 pv = pmap_pvh_remove(&om->md, pmap, va);
6146 ("pmap_enter: no PV entry for %#lx", va));
6147 if ((newpte & PG_MANAGED) == 0)
6148 free_pv_entry(pmap, pv);
6149 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6150 TAILQ_EMPTY(&om->md.pv_list) &&
6151 ((om->flags & PG_FICTITIOUS) != 0 ||
6152 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6153 vm_page_aflag_clear(om, PGA_WRITEABLE);
6156 * Since this mapping is unmanaged, assume that PG_A
6159 pmap_invalidate_page(pmap, va);
6164 * Increment the counters.
6166 if ((newpte & PG_W) != 0)
6167 pmap->pm_stats.wired_count++;
6168 pmap_resident_count_inc(pmap, 1);
6172 * Enter on the PV list if part of our managed memory.
6174 if ((newpte & PG_MANAGED) != 0) {
6176 pv = get_pv_entry(pmap, &lock);
6179 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6180 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6182 if ((newpte & PG_RW) != 0)
6183 vm_page_aflag_set(m, PGA_WRITEABLE);
6189 if ((origpte & PG_V) != 0) {
6191 origpte = pte_load_store(pte, newpte);
6192 KASSERT((origpte & PG_FRAME) == pa,
6193 ("pmap_enter: unexpected pa update for %#lx", va));
6194 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6196 if ((origpte & PG_MANAGED) != 0)
6200 * Although the PTE may still have PG_RW set, TLB
6201 * invalidation may nonetheless be required because
6202 * the PTE no longer has PG_M set.
6204 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6206 * This PTE change does not require TLB invalidation.
6210 if ((origpte & PG_A) != 0)
6211 pmap_invalidate_page(pmap, va);
6213 pte_store(pte, newpte);
6217 #if VM_NRESERVLEVEL > 0
6219 * If both the page table page and the reservation are fully
6220 * populated, then attempt promotion.
6222 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6223 pmap_ps_enabled(pmap) &&
6224 (m->flags & PG_FICTITIOUS) == 0 &&
6225 vm_reserv_level_iffullpop(m) == 0)
6226 pmap_promote_pde(pmap, pde, va, &lock);
6238 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6239 * if successful. Returns false if (1) a page table page cannot be allocated
6240 * without sleeping, (2) a mapping already exists at the specified virtual
6241 * address, or (3) a PV entry cannot be allocated without reclaiming another
6245 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6246 struct rwlock **lockp)
6251 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6252 PG_V = pmap_valid_bit(pmap);
6253 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6255 if ((m->oflags & VPO_UNMANAGED) == 0)
6256 newpde |= PG_MANAGED;
6257 if ((prot & VM_PROT_EXECUTE) == 0)
6259 if (va < VM_MAXUSER_ADDRESS)
6261 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6262 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6267 * Returns true if every page table entry in the specified page table page is
6271 pmap_every_pte_zero(vm_paddr_t pa)
6273 pt_entry_t *pt_end, *pte;
6275 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6276 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6277 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6285 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6286 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6287 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6288 * a mapping already exists at the specified virtual address. Returns
6289 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6290 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6291 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6293 * The parameter "m" is only used when creating a managed, writeable mapping.
6296 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6297 vm_page_t m, struct rwlock **lockp)
6299 struct spglist free;
6300 pd_entry_t oldpde, *pde;
6301 pt_entry_t PG_G, PG_RW, PG_V;
6304 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6305 ("pmap_enter_pde: cannot create wired user mapping"));
6306 PG_G = pmap_global_bit(pmap);
6307 PG_RW = pmap_rw_bit(pmap);
6308 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6309 ("pmap_enter_pde: newpde is missing PG_M"));
6310 PG_V = pmap_valid_bit(pmap);
6311 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6313 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6315 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6316 " in pmap %p", va, pmap);
6317 return (KERN_FAILURE);
6319 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6320 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6321 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6322 " in pmap %p", va, pmap);
6323 return (KERN_RESOURCE_SHORTAGE);
6327 * If pkru is not same for the whole pde range, return failure
6328 * and let vm_fault() cope. Check after pde allocation, since
6331 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6332 pmap_abort_ptp(pmap, va, pdpg);
6333 return (KERN_FAILURE);
6335 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6336 newpde &= ~X86_PG_PKU_MASK;
6337 newpde |= pmap_pkru_get(pmap, va);
6341 * If there are existing mappings, either abort or remove them.
6344 if ((oldpde & PG_V) != 0) {
6345 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6346 ("pmap_enter_pde: pdpg's reference count is too low"));
6347 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6348 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6349 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6352 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6353 " in pmap %p", va, pmap);
6354 return (KERN_FAILURE);
6356 /* Break the existing mapping(s). */
6358 if ((oldpde & PG_PS) != 0) {
6360 * The reference to the PD page that was acquired by
6361 * pmap_alloc_pde() ensures that it won't be freed.
6362 * However, if the PDE resulted from a promotion, then
6363 * a reserved PT page could be freed.
6365 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6366 if ((oldpde & PG_G) == 0)
6367 pmap_invalidate_pde_page(pmap, va, oldpde);
6369 pmap_delayed_invl_start();
6370 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6372 pmap_invalidate_all(pmap);
6373 pmap_delayed_invl_finish();
6375 if (va < VM_MAXUSER_ADDRESS) {
6376 vm_page_free_pages_toq(&free, true);
6377 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6380 KASSERT(SLIST_EMPTY(&free),
6381 ("pmap_enter_pde: freed kernel page table page"));
6384 * Both pmap_remove_pde() and pmap_remove_ptes() will
6385 * leave the kernel page table page zero filled.
6387 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6388 if (pmap_insert_pt_page(pmap, mt, false))
6389 panic("pmap_enter_pde: trie insert failed");
6393 if ((newpde & PG_MANAGED) != 0) {
6395 * Abort this mapping if its PV entry could not be created.
6397 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6399 pmap_abort_ptp(pmap, va, pdpg);
6400 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6401 " in pmap %p", va, pmap);
6402 return (KERN_RESOURCE_SHORTAGE);
6404 if ((newpde & PG_RW) != 0) {
6405 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6406 vm_page_aflag_set(mt, PGA_WRITEABLE);
6411 * Increment counters.
6413 if ((newpde & PG_W) != 0)
6414 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6415 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6418 * Map the superpage. (This is not a promoted mapping; there will not
6419 * be any lingering 4KB page mappings in the TLB.)
6421 pde_store(pde, newpde);
6423 atomic_add_long(&pmap_pde_mappings, 1);
6424 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
6426 return (KERN_SUCCESS);
6430 * Maps a sequence of resident pages belonging to the same object.
6431 * The sequence begins with the given page m_start. This page is
6432 * mapped at the given virtual address start. Each subsequent page is
6433 * mapped at a virtual address that is offset from start by the same
6434 * amount as the page is offset from m_start within the object. The
6435 * last page in the sequence is the page with the largest offset from
6436 * m_start that can be mapped at a virtual address less than the given
6437 * virtual address end. Not every virtual page between start and end
6438 * is mapped; only those for which a resident page exists with the
6439 * corresponding offset from m_start are mapped.
6442 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6443 vm_page_t m_start, vm_prot_t prot)
6445 struct rwlock *lock;
6448 vm_pindex_t diff, psize;
6450 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6452 psize = atop(end - start);
6457 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6458 va = start + ptoa(diff);
6459 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6460 m->psind == 1 && pmap_ps_enabled(pmap) &&
6461 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6462 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6463 m = &m[NBPDR / PAGE_SIZE - 1];
6465 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6467 m = TAILQ_NEXT(m, listq);
6475 * this code makes some *MAJOR* assumptions:
6476 * 1. Current pmap & pmap exists.
6479 * 4. No page table pages.
6480 * but is *MUCH* faster than pmap_enter...
6484 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6486 struct rwlock *lock;
6490 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6497 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6498 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6500 pt_entry_t newpte, *pte, PG_V;
6502 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6503 (m->oflags & VPO_UNMANAGED) != 0,
6504 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6505 PG_V = pmap_valid_bit(pmap);
6506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6509 * In the case that a page table page is not
6510 * resident, we are creating it here.
6512 if (va < VM_MAXUSER_ADDRESS) {
6513 vm_pindex_t ptepindex;
6517 * Calculate pagetable page index
6519 ptepindex = pmap_pde_pindex(va);
6520 if (mpte && (mpte->pindex == ptepindex)) {
6524 * Get the page directory entry
6526 ptepa = pmap_pde(pmap, va);
6529 * If the page table page is mapped, we just increment
6530 * the hold count, and activate it. Otherwise, we
6531 * attempt to allocate a page table page. If this
6532 * attempt fails, we don't retry. Instead, we give up.
6534 if (ptepa && (*ptepa & PG_V) != 0) {
6537 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6541 * Pass NULL instead of the PV list lock
6542 * pointer, because we don't intend to sleep.
6544 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6549 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6550 pte = &pte[pmap_pte_index(va)];
6562 * Enter on the PV list if part of our managed memory.
6564 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6565 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6567 pmap_abort_ptp(pmap, va, mpte);
6572 * Increment counters
6574 pmap_resident_count_inc(pmap, 1);
6576 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6577 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6578 if ((m->oflags & VPO_UNMANAGED) == 0)
6579 newpte |= PG_MANAGED;
6580 if ((prot & VM_PROT_EXECUTE) == 0)
6582 if (va < VM_MAXUSER_ADDRESS)
6583 newpte |= PG_U | pmap_pkru_get(pmap, va);
6584 pte_store(pte, newpte);
6589 * Make a temporary mapping for a physical address. This is only intended
6590 * to be used for panic dumps.
6593 pmap_kenter_temporary(vm_paddr_t pa, int i)
6597 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6598 pmap_kenter(va, pa);
6600 return ((void *)crashdumpmap);
6604 * This code maps large physical mmap regions into the
6605 * processor address space. Note that some shortcuts
6606 * are taken, but the code works.
6609 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6610 vm_pindex_t pindex, vm_size_t size)
6613 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6614 vm_paddr_t pa, ptepa;
6618 PG_A = pmap_accessed_bit(pmap);
6619 PG_M = pmap_modified_bit(pmap);
6620 PG_V = pmap_valid_bit(pmap);
6621 PG_RW = pmap_rw_bit(pmap);
6623 VM_OBJECT_ASSERT_WLOCKED(object);
6624 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6625 ("pmap_object_init_pt: non-device object"));
6626 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6627 if (!pmap_ps_enabled(pmap))
6629 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6631 p = vm_page_lookup(object, pindex);
6632 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6633 ("pmap_object_init_pt: invalid page %p", p));
6634 pat_mode = p->md.pat_mode;
6637 * Abort the mapping if the first page is not physically
6638 * aligned to a 2MB page boundary.
6640 ptepa = VM_PAGE_TO_PHYS(p);
6641 if (ptepa & (NBPDR - 1))
6645 * Skip the first page. Abort the mapping if the rest of
6646 * the pages are not physically contiguous or have differing
6647 * memory attributes.
6649 p = TAILQ_NEXT(p, listq);
6650 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6652 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6653 ("pmap_object_init_pt: invalid page %p", p));
6654 if (pa != VM_PAGE_TO_PHYS(p) ||
6655 pat_mode != p->md.pat_mode)
6657 p = TAILQ_NEXT(p, listq);
6661 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6662 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6663 * will not affect the termination of this loop.
6666 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6667 pa < ptepa + size; pa += NBPDR) {
6668 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
6671 * The creation of mappings below is only an
6672 * optimization. If a page directory page
6673 * cannot be allocated without blocking,
6674 * continue on to the next mapping rather than
6680 if ((*pde & PG_V) == 0) {
6681 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6682 PG_U | PG_RW | PG_V);
6683 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6684 atomic_add_long(&pmap_pde_mappings, 1);
6686 /* Continue on if the PDE is already valid. */
6688 KASSERT(pdpg->ref_count > 0,
6689 ("pmap_object_init_pt: missing reference "
6690 "to page directory page, va: 0x%lx", addr));
6699 * Clear the wired attribute from the mappings for the specified range of
6700 * addresses in the given pmap. Every valid mapping within that range
6701 * must have the wired attribute set. In contrast, invalid mappings
6702 * cannot have the wired attribute set, so they are ignored.
6704 * The wired attribute of the page table entry is not a hardware
6705 * feature, so there is no need to invalidate any TLB entries.
6706 * Since pmap_demote_pde() for the wired entry must never fail,
6707 * pmap_delayed_invl_start()/finish() calls around the
6708 * function are not needed.
6711 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6713 vm_offset_t va_next;
6714 pml4_entry_t *pml4e;
6717 pt_entry_t *pte, PG_V;
6719 PG_V = pmap_valid_bit(pmap);
6721 for (; sva < eva; sva = va_next) {
6722 pml4e = pmap_pml4e(pmap, sva);
6723 if ((*pml4e & PG_V) == 0) {
6724 va_next = (sva + NBPML4) & ~PML4MASK;
6729 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6730 if ((*pdpe & PG_V) == 0) {
6731 va_next = (sva + NBPDP) & ~PDPMASK;
6736 va_next = (sva + NBPDR) & ~PDRMASK;
6739 pde = pmap_pdpe_to_pde(pdpe, sva);
6740 if ((*pde & PG_V) == 0)
6742 if ((*pde & PG_PS) != 0) {
6743 if ((*pde & PG_W) == 0)
6744 panic("pmap_unwire: pde %#jx is missing PG_W",
6748 * Are we unwiring the entire large page? If not,
6749 * demote the mapping and fall through.
6751 if (sva + NBPDR == va_next && eva >= va_next) {
6752 atomic_clear_long(pde, PG_W);
6753 pmap->pm_stats.wired_count -= NBPDR /
6756 } else if (!pmap_demote_pde(pmap, pde, sva))
6757 panic("pmap_unwire: demotion failed");
6761 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6763 if ((*pte & PG_V) == 0)
6765 if ((*pte & PG_W) == 0)
6766 panic("pmap_unwire: pte %#jx is missing PG_W",
6770 * PG_W must be cleared atomically. Although the pmap
6771 * lock synchronizes access to PG_W, another processor
6772 * could be setting PG_M and/or PG_A concurrently.
6774 atomic_clear_long(pte, PG_W);
6775 pmap->pm_stats.wired_count--;
6782 * Copy the range specified by src_addr/len
6783 * from the source map to the range dst_addr/len
6784 * in the destination map.
6786 * This routine is only advisory and need not do anything.
6789 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6790 vm_offset_t src_addr)
6792 struct rwlock *lock;
6793 pml4_entry_t *pml4e;
6795 pd_entry_t *pde, srcptepaddr;
6796 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6797 vm_offset_t addr, end_addr, va_next;
6798 vm_page_t dst_pdpg, dstmpte, srcmpte;
6800 if (dst_addr != src_addr)
6803 if (dst_pmap->pm_type != src_pmap->pm_type)
6807 * EPT page table entries that require emulation of A/D bits are
6808 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6809 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6810 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6811 * implementations flag an EPT misconfiguration for exec-only
6812 * mappings we skip this function entirely for emulated pmaps.
6814 if (pmap_emulate_ad_bits(dst_pmap))
6817 end_addr = src_addr + len;
6819 if (dst_pmap < src_pmap) {
6820 PMAP_LOCK(dst_pmap);
6821 PMAP_LOCK(src_pmap);
6823 PMAP_LOCK(src_pmap);
6824 PMAP_LOCK(dst_pmap);
6827 PG_A = pmap_accessed_bit(dst_pmap);
6828 PG_M = pmap_modified_bit(dst_pmap);
6829 PG_V = pmap_valid_bit(dst_pmap);
6831 for (addr = src_addr; addr < end_addr; addr = va_next) {
6832 KASSERT(addr < UPT_MIN_ADDRESS,
6833 ("pmap_copy: invalid to pmap_copy page tables"));
6835 pml4e = pmap_pml4e(src_pmap, addr);
6836 if ((*pml4e & PG_V) == 0) {
6837 va_next = (addr + NBPML4) & ~PML4MASK;
6843 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6844 if ((*pdpe & PG_V) == 0) {
6845 va_next = (addr + NBPDP) & ~PDPMASK;
6851 va_next = (addr + NBPDR) & ~PDRMASK;
6855 pde = pmap_pdpe_to_pde(pdpe, addr);
6857 if (srcptepaddr == 0)
6860 if (srcptepaddr & PG_PS) {
6861 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6863 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
6866 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6867 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6868 PMAP_ENTER_NORECLAIM, &lock))) {
6869 *pde = srcptepaddr & ~PG_W;
6870 pmap_resident_count_inc(dst_pmap, NBPDR /
6872 atomic_add_long(&pmap_pde_mappings, 1);
6874 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
6878 srcptepaddr &= PG_FRAME;
6879 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6880 KASSERT(srcmpte->ref_count > 0,
6881 ("pmap_copy: source page table page is unused"));
6883 if (va_next > end_addr)
6886 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6887 src_pte = &src_pte[pmap_pte_index(addr)];
6889 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6893 * We only virtual copy managed pages.
6895 if ((ptetemp & PG_MANAGED) == 0)
6898 if (dstmpte != NULL) {
6899 KASSERT(dstmpte->pindex ==
6900 pmap_pde_pindex(addr),
6901 ("dstmpte pindex/addr mismatch"));
6902 dstmpte->ref_count++;
6903 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6906 dst_pte = (pt_entry_t *)
6907 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6908 dst_pte = &dst_pte[pmap_pte_index(addr)];
6909 if (*dst_pte == 0 &&
6910 pmap_try_insert_pv_entry(dst_pmap, addr,
6911 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6913 * Clear the wired, modified, and accessed
6914 * (referenced) bits during the copy.
6916 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6917 pmap_resident_count_inc(dst_pmap, 1);
6919 pmap_abort_ptp(dst_pmap, addr, dstmpte);
6922 /* Have we copied all of the valid mappings? */
6923 if (dstmpte->ref_count >= srcmpte->ref_count)
6930 PMAP_UNLOCK(src_pmap);
6931 PMAP_UNLOCK(dst_pmap);
6935 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6939 if (dst_pmap->pm_type != src_pmap->pm_type ||
6940 dst_pmap->pm_type != PT_X86 ||
6941 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6944 if (dst_pmap < src_pmap) {
6945 PMAP_LOCK(dst_pmap);
6946 PMAP_LOCK(src_pmap);
6948 PMAP_LOCK(src_pmap);
6949 PMAP_LOCK(dst_pmap);
6951 error = pmap_pkru_copy(dst_pmap, src_pmap);
6952 /* Clean up partial copy on failure due to no memory. */
6953 if (error == ENOMEM)
6954 pmap_pkru_deassign_all(dst_pmap);
6955 PMAP_UNLOCK(src_pmap);
6956 PMAP_UNLOCK(dst_pmap);
6957 if (error != ENOMEM)
6965 * Zero the specified hardware page.
6968 pmap_zero_page(vm_page_t m)
6970 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6972 pagezero((void *)va);
6976 * Zero an an area within a single hardware page. off and size must not
6977 * cover an area beyond a single hardware page.
6980 pmap_zero_page_area(vm_page_t m, int off, int size)
6982 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6984 if (off == 0 && size == PAGE_SIZE)
6985 pagezero((void *)va);
6987 bzero((char *)va + off, size);
6991 * Copy 1 specified hardware page to another.
6994 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6996 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6997 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6999 pagecopy((void *)src, (void *)dst);
7002 int unmapped_buf_allowed = 1;
7005 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7006 vm_offset_t b_offset, int xfersize)
7010 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7014 while (xfersize > 0) {
7015 a_pg_offset = a_offset & PAGE_MASK;
7016 pages[0] = ma[a_offset >> PAGE_SHIFT];
7017 b_pg_offset = b_offset & PAGE_MASK;
7018 pages[1] = mb[b_offset >> PAGE_SHIFT];
7019 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7020 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7021 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7022 a_cp = (char *)vaddr[0] + a_pg_offset;
7023 b_cp = (char *)vaddr[1] + b_pg_offset;
7024 bcopy(a_cp, b_cp, cnt);
7025 if (__predict_false(mapped))
7026 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7034 * Returns true if the pmap's pv is one of the first
7035 * 16 pvs linked to from this page. This count may
7036 * be changed upwards or downwards in the future; it
7037 * is only necessary that true be returned for a small
7038 * subset of pmaps for proper page aging.
7041 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7043 struct md_page *pvh;
7044 struct rwlock *lock;
7049 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7050 ("pmap_page_exists_quick: page %p is not managed", m));
7052 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7054 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7055 if (PV_PMAP(pv) == pmap) {
7063 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7064 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7065 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7066 if (PV_PMAP(pv) == pmap) {
7080 * pmap_page_wired_mappings:
7082 * Return the number of managed mappings to the given physical page
7086 pmap_page_wired_mappings(vm_page_t m)
7088 struct rwlock *lock;
7089 struct md_page *pvh;
7093 int count, md_gen, pvh_gen;
7095 if ((m->oflags & VPO_UNMANAGED) != 0)
7097 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7101 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7103 if (!PMAP_TRYLOCK(pmap)) {
7104 md_gen = m->md.pv_gen;
7108 if (md_gen != m->md.pv_gen) {
7113 pte = pmap_pte(pmap, pv->pv_va);
7114 if ((*pte & PG_W) != 0)
7118 if ((m->flags & PG_FICTITIOUS) == 0) {
7119 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7120 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7122 if (!PMAP_TRYLOCK(pmap)) {
7123 md_gen = m->md.pv_gen;
7124 pvh_gen = pvh->pv_gen;
7128 if (md_gen != m->md.pv_gen ||
7129 pvh_gen != pvh->pv_gen) {
7134 pte = pmap_pde(pmap, pv->pv_va);
7135 if ((*pte & PG_W) != 0)
7145 * Returns TRUE if the given page is mapped individually or as part of
7146 * a 2mpage. Otherwise, returns FALSE.
7149 pmap_page_is_mapped(vm_page_t m)
7151 struct rwlock *lock;
7154 if ((m->oflags & VPO_UNMANAGED) != 0)
7156 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7158 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7159 ((m->flags & PG_FICTITIOUS) == 0 &&
7160 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7166 * Destroy all managed, non-wired mappings in the given user-space
7167 * pmap. This pmap cannot be active on any processor besides the
7170 * This function cannot be applied to the kernel pmap. Moreover, it
7171 * is not intended for general use. It is only to be used during
7172 * process termination. Consequently, it can be implemented in ways
7173 * that make it faster than pmap_remove(). First, it can more quickly
7174 * destroy mappings by iterating over the pmap's collection of PV
7175 * entries, rather than searching the page table. Second, it doesn't
7176 * have to test and clear the page table entries atomically, because
7177 * no processor is currently accessing the user address space. In
7178 * particular, a page table entry's dirty bit won't change state once
7179 * this function starts.
7181 * Although this function destroys all of the pmap's managed,
7182 * non-wired mappings, it can delay and batch the invalidation of TLB
7183 * entries without calling pmap_delayed_invl_start() and
7184 * pmap_delayed_invl_finish(). Because the pmap is not active on
7185 * any other processor, none of these TLB entries will ever be used
7186 * before their eventual invalidation. Consequently, there is no need
7187 * for either pmap_remove_all() or pmap_remove_write() to wait for
7188 * that eventual TLB invalidation.
7191 pmap_remove_pages(pmap_t pmap)
7194 pt_entry_t *pte, tpte;
7195 pt_entry_t PG_M, PG_RW, PG_V;
7196 struct spglist free;
7197 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7198 vm_page_t m, mpte, mt;
7200 struct md_page *pvh;
7201 struct pv_chunk *pc, *npc;
7202 struct rwlock *lock;
7204 uint64_t inuse, bitmask;
7205 int allfree, field, freed, i, idx;
7206 boolean_t superpage;
7210 * Assert that the given pmap is only active on the current
7211 * CPU. Unfortunately, we cannot block another CPU from
7212 * activating the pmap while this function is executing.
7214 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7217 cpuset_t other_cpus;
7219 other_cpus = all_cpus;
7221 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7222 CPU_AND(&other_cpus, &pmap->pm_active);
7224 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7229 PG_M = pmap_modified_bit(pmap);
7230 PG_V = pmap_valid_bit(pmap);
7231 PG_RW = pmap_rw_bit(pmap);
7233 for (i = 0; i < PMAP_MEMDOM; i++)
7234 TAILQ_INIT(&free_chunks[i]);
7237 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7240 for (field = 0; field < _NPCM; field++) {
7241 inuse = ~pc->pc_map[field] & pc_freemask[field];
7242 while (inuse != 0) {
7244 bitmask = 1UL << bit;
7245 idx = field * 64 + bit;
7246 pv = &pc->pc_pventry[idx];
7249 pte = pmap_pdpe(pmap, pv->pv_va);
7251 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7253 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7256 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7258 pte = &pte[pmap_pte_index(pv->pv_va)];
7262 * Keep track whether 'tpte' is a
7263 * superpage explicitly instead of
7264 * relying on PG_PS being set.
7266 * This is because PG_PS is numerically
7267 * identical to PG_PTE_PAT and thus a
7268 * regular page could be mistaken for
7274 if ((tpte & PG_V) == 0) {
7275 panic("bad pte va %lx pte %lx",
7280 * We cannot remove wired pages from a process' mapping at this time
7288 pa = tpte & PG_PS_FRAME;
7290 pa = tpte & PG_FRAME;
7292 m = PHYS_TO_VM_PAGE(pa);
7293 KASSERT(m->phys_addr == pa,
7294 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7295 m, (uintmax_t)m->phys_addr,
7298 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7299 m < &vm_page_array[vm_page_array_size],
7300 ("pmap_remove_pages: bad tpte %#jx",
7306 * Update the vm_page_t clean/reference bits.
7308 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7310 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7316 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7319 pc->pc_map[field] |= bitmask;
7321 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7322 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7323 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7325 if (TAILQ_EMPTY(&pvh->pv_list)) {
7326 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7327 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7328 TAILQ_EMPTY(&mt->md.pv_list))
7329 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7331 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7333 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7334 ("pmap_remove_pages: pte page not promoted"));
7335 pmap_resident_count_dec(pmap, 1);
7336 KASSERT(mpte->ref_count == NPTEPG,
7337 ("pmap_remove_pages: pte page reference count error"));
7338 mpte->ref_count = 0;
7339 pmap_add_delayed_free_list(mpte, &free, FALSE);
7342 pmap_resident_count_dec(pmap, 1);
7343 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7345 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
7346 TAILQ_EMPTY(&m->md.pv_list) &&
7347 (m->flags & PG_FICTITIOUS) == 0) {
7348 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7349 if (TAILQ_EMPTY(&pvh->pv_list))
7350 vm_page_aflag_clear(m, PGA_WRITEABLE);
7353 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7357 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7358 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7359 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7361 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7362 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7367 pmap_invalidate_all(pmap);
7368 pmap_pkru_deassign_all(pmap);
7369 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7371 vm_page_free_pages_toq(&free, true);
7375 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7377 struct rwlock *lock;
7379 struct md_page *pvh;
7380 pt_entry_t *pte, mask;
7381 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7383 int md_gen, pvh_gen;
7387 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7390 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7392 if (!PMAP_TRYLOCK(pmap)) {
7393 md_gen = m->md.pv_gen;
7397 if (md_gen != m->md.pv_gen) {
7402 pte = pmap_pte(pmap, pv->pv_va);
7405 PG_M = pmap_modified_bit(pmap);
7406 PG_RW = pmap_rw_bit(pmap);
7407 mask |= PG_RW | PG_M;
7410 PG_A = pmap_accessed_bit(pmap);
7411 PG_V = pmap_valid_bit(pmap);
7412 mask |= PG_V | PG_A;
7414 rv = (*pte & mask) == mask;
7419 if ((m->flags & PG_FICTITIOUS) == 0) {
7420 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7421 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7423 if (!PMAP_TRYLOCK(pmap)) {
7424 md_gen = m->md.pv_gen;
7425 pvh_gen = pvh->pv_gen;
7429 if (md_gen != m->md.pv_gen ||
7430 pvh_gen != pvh->pv_gen) {
7435 pte = pmap_pde(pmap, pv->pv_va);
7438 PG_M = pmap_modified_bit(pmap);
7439 PG_RW = pmap_rw_bit(pmap);
7440 mask |= PG_RW | PG_M;
7443 PG_A = pmap_accessed_bit(pmap);
7444 PG_V = pmap_valid_bit(pmap);
7445 mask |= PG_V | PG_A;
7447 rv = (*pte & mask) == mask;
7461 * Return whether or not the specified physical page was modified
7462 * in any physical maps.
7465 pmap_is_modified(vm_page_t m)
7468 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7469 ("pmap_is_modified: page %p is not managed", m));
7472 * If the page is not busied then this check is racy.
7474 if (!pmap_page_is_write_mapped(m))
7476 return (pmap_page_test_mappings(m, FALSE, TRUE));
7480 * pmap_is_prefaultable:
7482 * Return whether or not the specified virtual address is eligible
7486 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7489 pt_entry_t *pte, PG_V;
7492 PG_V = pmap_valid_bit(pmap);
7495 pde = pmap_pde(pmap, addr);
7496 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7497 pte = pmap_pde_to_pte(pde, addr);
7498 rv = (*pte & PG_V) == 0;
7505 * pmap_is_referenced:
7507 * Return whether or not the specified physical page was referenced
7508 * in any physical maps.
7511 pmap_is_referenced(vm_page_t m)
7514 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7515 ("pmap_is_referenced: page %p is not managed", m));
7516 return (pmap_page_test_mappings(m, TRUE, FALSE));
7520 * Clear the write and modified bits in each of the given page's mappings.
7523 pmap_remove_write(vm_page_t m)
7525 struct md_page *pvh;
7527 struct rwlock *lock;
7528 pv_entry_t next_pv, pv;
7530 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7532 int pvh_gen, md_gen;
7534 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7535 ("pmap_remove_write: page %p is not managed", m));
7537 vm_page_assert_busied(m);
7538 if (!pmap_page_is_write_mapped(m))
7541 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7542 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7543 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7546 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7548 if (!PMAP_TRYLOCK(pmap)) {
7549 pvh_gen = pvh->pv_gen;
7553 if (pvh_gen != pvh->pv_gen) {
7559 PG_RW = pmap_rw_bit(pmap);
7561 pde = pmap_pde(pmap, va);
7562 if ((*pde & PG_RW) != 0)
7563 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7564 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7565 ("inconsistent pv lock %p %p for page %p",
7566 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7569 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7571 if (!PMAP_TRYLOCK(pmap)) {
7572 pvh_gen = pvh->pv_gen;
7573 md_gen = m->md.pv_gen;
7577 if (pvh_gen != pvh->pv_gen ||
7578 md_gen != m->md.pv_gen) {
7584 PG_M = pmap_modified_bit(pmap);
7585 PG_RW = pmap_rw_bit(pmap);
7586 pde = pmap_pde(pmap, pv->pv_va);
7587 KASSERT((*pde & PG_PS) == 0,
7588 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7590 pte = pmap_pde_to_pte(pde, pv->pv_va);
7593 if (oldpte & PG_RW) {
7594 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7597 if ((oldpte & PG_M) != 0)
7599 pmap_invalidate_page(pmap, pv->pv_va);
7604 vm_page_aflag_clear(m, PGA_WRITEABLE);
7605 pmap_delayed_invl_wait(m);
7608 static __inline boolean_t
7609 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7612 if (!pmap_emulate_ad_bits(pmap))
7615 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7618 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7619 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7620 * if the EPT_PG_WRITE bit is set.
7622 if ((pte & EPT_PG_WRITE) != 0)
7626 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7628 if ((pte & EPT_PG_EXECUTE) == 0 ||
7629 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7636 * pmap_ts_referenced:
7638 * Return a count of reference bits for a page, clearing those bits.
7639 * It is not necessary for every reference bit to be cleared, but it
7640 * is necessary that 0 only be returned when there are truly no
7641 * reference bits set.
7643 * As an optimization, update the page's dirty field if a modified bit is
7644 * found while counting reference bits. This opportunistic update can be
7645 * performed at low cost and can eliminate the need for some future calls
7646 * to pmap_is_modified(). However, since this function stops after
7647 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7648 * dirty pages. Those dirty pages will only be detected by a future call
7649 * to pmap_is_modified().
7651 * A DI block is not needed within this function, because
7652 * invalidations are performed before the PV list lock is
7656 pmap_ts_referenced(vm_page_t m)
7658 struct md_page *pvh;
7661 struct rwlock *lock;
7662 pd_entry_t oldpde, *pde;
7663 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7666 int cleared, md_gen, not_cleared, pvh_gen;
7667 struct spglist free;
7670 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7671 ("pmap_ts_referenced: page %p is not managed", m));
7674 pa = VM_PAGE_TO_PHYS(m);
7675 lock = PHYS_TO_PV_LIST_LOCK(pa);
7676 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7680 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7681 goto small_mappings;
7687 if (!PMAP_TRYLOCK(pmap)) {
7688 pvh_gen = pvh->pv_gen;
7692 if (pvh_gen != pvh->pv_gen) {
7697 PG_A = pmap_accessed_bit(pmap);
7698 PG_M = pmap_modified_bit(pmap);
7699 PG_RW = pmap_rw_bit(pmap);
7701 pde = pmap_pde(pmap, pv->pv_va);
7703 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7705 * Although "oldpde" is mapping a 2MB page, because
7706 * this function is called at a 4KB page granularity,
7707 * we only update the 4KB page under test.
7711 if ((oldpde & PG_A) != 0) {
7713 * Since this reference bit is shared by 512 4KB
7714 * pages, it should not be cleared every time it is
7715 * tested. Apply a simple "hash" function on the
7716 * physical page number, the virtual superpage number,
7717 * and the pmap address to select one 4KB page out of
7718 * the 512 on which testing the reference bit will
7719 * result in clearing that reference bit. This
7720 * function is designed to avoid the selection of the
7721 * same 4KB page for every 2MB page mapping.
7723 * On demotion, a mapping that hasn't been referenced
7724 * is simply destroyed. To avoid the possibility of a
7725 * subsequent page fault on a demoted wired mapping,
7726 * always leave its reference bit set. Moreover,
7727 * since the superpage is wired, the current state of
7728 * its reference bit won't affect page replacement.
7730 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7731 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7732 (oldpde & PG_W) == 0) {
7733 if (safe_to_clear_referenced(pmap, oldpde)) {
7734 atomic_clear_long(pde, PG_A);
7735 pmap_invalidate_page(pmap, pv->pv_va);
7737 } else if (pmap_demote_pde_locked(pmap, pde,
7738 pv->pv_va, &lock)) {
7740 * Remove the mapping to a single page
7741 * so that a subsequent access may
7742 * repromote. Since the underlying
7743 * page table page is fully populated,
7744 * this removal never frees a page
7748 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7750 pte = pmap_pde_to_pte(pde, va);
7751 pmap_remove_pte(pmap, pte, va, *pde,
7753 pmap_invalidate_page(pmap, va);
7759 * The superpage mapping was removed
7760 * entirely and therefore 'pv' is no
7768 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7769 ("inconsistent pv lock %p %p for page %p",
7770 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7775 /* Rotate the PV list if it has more than one entry. */
7776 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7777 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7778 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7781 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7783 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7785 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7792 if (!PMAP_TRYLOCK(pmap)) {
7793 pvh_gen = pvh->pv_gen;
7794 md_gen = m->md.pv_gen;
7798 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7803 PG_A = pmap_accessed_bit(pmap);
7804 PG_M = pmap_modified_bit(pmap);
7805 PG_RW = pmap_rw_bit(pmap);
7806 pde = pmap_pde(pmap, pv->pv_va);
7807 KASSERT((*pde & PG_PS) == 0,
7808 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7810 pte = pmap_pde_to_pte(pde, pv->pv_va);
7811 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7813 if ((*pte & PG_A) != 0) {
7814 if (safe_to_clear_referenced(pmap, *pte)) {
7815 atomic_clear_long(pte, PG_A);
7816 pmap_invalidate_page(pmap, pv->pv_va);
7818 } else if ((*pte & PG_W) == 0) {
7820 * Wired pages cannot be paged out so
7821 * doing accessed bit emulation for
7822 * them is wasted effort. We do the
7823 * hard work for unwired pages only.
7825 pmap_remove_pte(pmap, pte, pv->pv_va,
7826 *pde, &free, &lock);
7827 pmap_invalidate_page(pmap, pv->pv_va);
7832 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7833 ("inconsistent pv lock %p %p for page %p",
7834 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7839 /* Rotate the PV list if it has more than one entry. */
7840 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7841 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7842 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7845 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7846 not_cleared < PMAP_TS_REFERENCED_MAX);
7849 vm_page_free_pages_toq(&free, true);
7850 return (cleared + not_cleared);
7854 * Apply the given advice to the specified range of addresses within the
7855 * given pmap. Depending on the advice, clear the referenced and/or
7856 * modified flags in each mapping and set the mapped page's dirty field.
7859 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7861 struct rwlock *lock;
7862 pml4_entry_t *pml4e;
7864 pd_entry_t oldpde, *pde;
7865 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7866 vm_offset_t va, va_next;
7870 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7874 * A/D bit emulation requires an alternate code path when clearing
7875 * the modified and accessed bits below. Since this function is
7876 * advisory in nature we skip it entirely for pmaps that require
7877 * A/D bit emulation.
7879 if (pmap_emulate_ad_bits(pmap))
7882 PG_A = pmap_accessed_bit(pmap);
7883 PG_G = pmap_global_bit(pmap);
7884 PG_M = pmap_modified_bit(pmap);
7885 PG_V = pmap_valid_bit(pmap);
7886 PG_RW = pmap_rw_bit(pmap);
7888 pmap_delayed_invl_start();
7890 for (; sva < eva; sva = va_next) {
7891 pml4e = pmap_pml4e(pmap, sva);
7892 if ((*pml4e & PG_V) == 0) {
7893 va_next = (sva + NBPML4) & ~PML4MASK;
7898 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7899 if ((*pdpe & PG_V) == 0) {
7900 va_next = (sva + NBPDP) & ~PDPMASK;
7905 va_next = (sva + NBPDR) & ~PDRMASK;
7908 pde = pmap_pdpe_to_pde(pdpe, sva);
7910 if ((oldpde & PG_V) == 0)
7912 else if ((oldpde & PG_PS) != 0) {
7913 if ((oldpde & PG_MANAGED) == 0)
7916 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7921 * The large page mapping was destroyed.
7927 * Unless the page mappings are wired, remove the
7928 * mapping to a single page so that a subsequent
7929 * access may repromote. Choosing the last page
7930 * within the address range [sva, min(va_next, eva))
7931 * generally results in more repromotions. Since the
7932 * underlying page table page is fully populated, this
7933 * removal never frees a page table page.
7935 if ((oldpde & PG_W) == 0) {
7941 ("pmap_advise: no address gap"));
7942 pte = pmap_pde_to_pte(pde, va);
7943 KASSERT((*pte & PG_V) != 0,
7944 ("pmap_advise: invalid PTE"));
7945 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7955 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7957 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7959 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7960 if (advice == MADV_DONTNEED) {
7962 * Future calls to pmap_is_modified()
7963 * can be avoided by making the page
7966 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7969 atomic_clear_long(pte, PG_M | PG_A);
7970 } else if ((*pte & PG_A) != 0)
7971 atomic_clear_long(pte, PG_A);
7975 if ((*pte & PG_G) != 0) {
7982 if (va != va_next) {
7983 pmap_invalidate_range(pmap, va, sva);
7988 pmap_invalidate_range(pmap, va, sva);
7991 pmap_invalidate_all(pmap);
7993 pmap_delayed_invl_finish();
7997 * Clear the modify bits on the specified physical page.
8000 pmap_clear_modify(vm_page_t m)
8002 struct md_page *pvh;
8004 pv_entry_t next_pv, pv;
8005 pd_entry_t oldpde, *pde;
8006 pt_entry_t *pte, PG_M, PG_RW;
8007 struct rwlock *lock;
8009 int md_gen, pvh_gen;
8011 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8012 ("pmap_clear_modify: page %p is not managed", m));
8013 vm_page_assert_busied(m);
8015 if (!pmap_page_is_write_mapped(m))
8017 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8018 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8019 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8022 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8024 if (!PMAP_TRYLOCK(pmap)) {
8025 pvh_gen = pvh->pv_gen;
8029 if (pvh_gen != pvh->pv_gen) {
8034 PG_M = pmap_modified_bit(pmap);
8035 PG_RW = pmap_rw_bit(pmap);
8037 pde = pmap_pde(pmap, va);
8039 /* If oldpde has PG_RW set, then it also has PG_M set. */
8040 if ((oldpde & PG_RW) != 0 &&
8041 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8042 (oldpde & PG_W) == 0) {
8044 * Write protect the mapping to a single page so that
8045 * a subsequent write access may repromote.
8047 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8048 pte = pmap_pde_to_pte(pde, va);
8049 atomic_clear_long(pte, PG_M | PG_RW);
8051 pmap_invalidate_page(pmap, va);
8055 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8057 if (!PMAP_TRYLOCK(pmap)) {
8058 md_gen = m->md.pv_gen;
8059 pvh_gen = pvh->pv_gen;
8063 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8068 PG_M = pmap_modified_bit(pmap);
8069 PG_RW = pmap_rw_bit(pmap);
8070 pde = pmap_pde(pmap, pv->pv_va);
8071 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8072 " a 2mpage in page %p's pv list", m));
8073 pte = pmap_pde_to_pte(pde, pv->pv_va);
8074 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8075 atomic_clear_long(pte, PG_M);
8076 pmap_invalidate_page(pmap, pv->pv_va);
8084 * Miscellaneous support routines follow
8087 /* Adjust the properties for a leaf page table entry. */
8088 static __inline void
8089 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8093 opte = *(u_long *)pte;
8095 npte = opte & ~mask;
8097 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8102 * Map a set of physical memory pages into the kernel virtual
8103 * address space. Return a pointer to where it is mapped. This
8104 * routine is intended to be used for mapping device memory,
8108 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8110 struct pmap_preinit_mapping *ppim;
8111 vm_offset_t va, offset;
8115 offset = pa & PAGE_MASK;
8116 size = round_page(offset + size);
8117 pa = trunc_page(pa);
8119 if (!pmap_initialized) {
8121 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8122 ppim = pmap_preinit_mapping + i;
8123 if (ppim->va == 0) {
8127 ppim->va = virtual_avail;
8128 virtual_avail += size;
8134 panic("%s: too many preinit mappings", __func__);
8137 * If we have a preinit mapping, re-use it.
8139 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8140 ppim = pmap_preinit_mapping + i;
8141 if (ppim->pa == pa && ppim->sz == size &&
8142 (ppim->mode == mode ||
8143 (flags & MAPDEV_SETATTR) == 0))
8144 return ((void *)(ppim->va + offset));
8147 * If the specified range of physical addresses fits within
8148 * the direct map window, use the direct map.
8150 if (pa < dmaplimit && pa + size <= dmaplimit) {
8151 va = PHYS_TO_DMAP(pa);
8152 if ((flags & MAPDEV_SETATTR) != 0) {
8153 PMAP_LOCK(kernel_pmap);
8154 i = pmap_change_props_locked(va, size,
8155 PROT_NONE, mode, flags);
8156 PMAP_UNLOCK(kernel_pmap);
8160 return ((void *)(va + offset));
8162 va = kva_alloc(size);
8164 panic("%s: Couldn't allocate KVA", __func__);
8166 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8167 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8168 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8169 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8170 pmap_invalidate_cache_range(va, va + tmpsize);
8171 return ((void *)(va + offset));
8175 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8178 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8183 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8186 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8190 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8193 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8198 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8201 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8202 MAPDEV_FLUSHCACHE));
8206 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8208 struct pmap_preinit_mapping *ppim;
8212 /* If we gave a direct map region in pmap_mapdev, do nothing */
8213 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8215 offset = va & PAGE_MASK;
8216 size = round_page(offset + size);
8217 va = trunc_page(va);
8218 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8219 ppim = pmap_preinit_mapping + i;
8220 if (ppim->va == va && ppim->sz == size) {
8221 if (pmap_initialized)
8227 if (va + size == virtual_avail)
8232 if (pmap_initialized)
8237 * Tries to demote a 1GB page mapping.
8240 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8242 pdp_entry_t newpdpe, oldpdpe;
8243 pd_entry_t *firstpde, newpde, *pde;
8244 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8248 PG_A = pmap_accessed_bit(pmap);
8249 PG_M = pmap_modified_bit(pmap);
8250 PG_V = pmap_valid_bit(pmap);
8251 PG_RW = pmap_rw_bit(pmap);
8253 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8255 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8256 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8257 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8258 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8259 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8260 " in pmap %p", va, pmap);
8263 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8264 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8265 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8266 KASSERT((oldpdpe & PG_A) != 0,
8267 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8268 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8269 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8273 * Initialize the page directory page.
8275 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8281 * Demote the mapping.
8286 * Invalidate a stale recursive mapping of the page directory page.
8288 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8290 pmap_pdpe_demotions++;
8291 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8292 " in pmap %p", va, pmap);
8297 * Sets the memory attribute for the specified page.
8300 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8303 m->md.pat_mode = ma;
8306 * If "m" is a normal page, update its direct mapping. This update
8307 * can be relied upon to perform any cache operations that are
8308 * required for data coherence.
8310 if ((m->flags & PG_FICTITIOUS) == 0 &&
8311 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8313 panic("memory attribute change on the direct map failed");
8317 * Changes the specified virtual address range's memory type to that given by
8318 * the parameter "mode". The specified virtual address range must be
8319 * completely contained within either the direct map or the kernel map. If
8320 * the virtual address range is contained within the kernel map, then the
8321 * memory type for each of the corresponding ranges of the direct map is also
8322 * changed. (The corresponding ranges of the direct map are those ranges that
8323 * map the same physical pages as the specified virtual address range.) These
8324 * changes to the direct map are necessary because Intel describes the
8325 * behavior of their processors as "undefined" if two or more mappings to the
8326 * same physical page have different memory types.
8328 * Returns zero if the change completed successfully, and either EINVAL or
8329 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8330 * of the virtual address range was not mapped, and ENOMEM is returned if
8331 * there was insufficient memory available to complete the change. In the
8332 * latter case, the memory type may have been changed on some part of the
8333 * virtual address range or the direct map.
8336 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8340 PMAP_LOCK(kernel_pmap);
8341 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8343 PMAP_UNLOCK(kernel_pmap);
8348 * Changes the specified virtual address range's protections to those
8349 * specified by "prot". Like pmap_change_attr(), protections for aliases
8350 * in the direct map are updated as well. Protections on aliasing mappings may
8351 * be a subset of the requested protections; for example, mappings in the direct
8352 * map are never executable.
8355 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8359 /* Only supported within the kernel map. */
8360 if (va < VM_MIN_KERNEL_ADDRESS)
8363 PMAP_LOCK(kernel_pmap);
8364 error = pmap_change_props_locked(va, size, prot, -1,
8365 MAPDEV_ASSERTVALID);
8366 PMAP_UNLOCK(kernel_pmap);
8371 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8372 int mode, int flags)
8374 vm_offset_t base, offset, tmpva;
8375 vm_paddr_t pa_start, pa_end, pa_end1;
8377 pd_entry_t *pde, pde_bits, pde_mask;
8378 pt_entry_t *pte, pte_bits, pte_mask;
8382 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8383 base = trunc_page(va);
8384 offset = va & PAGE_MASK;
8385 size = round_page(offset + size);
8388 * Only supported on kernel virtual addresses, including the direct
8389 * map but excluding the recursive map.
8391 if (base < DMAP_MIN_ADDRESS)
8395 * Construct our flag sets and masks. "bits" is the subset of
8396 * "mask" that will be set in each modified PTE.
8398 * Mappings in the direct map are never allowed to be executable.
8400 pde_bits = pte_bits = 0;
8401 pde_mask = pte_mask = 0;
8403 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8404 pde_mask |= X86_PG_PDE_CACHE;
8405 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8406 pte_mask |= X86_PG_PTE_CACHE;
8408 if (prot != VM_PROT_NONE) {
8409 if ((prot & VM_PROT_WRITE) != 0) {
8410 pde_bits |= X86_PG_RW;
8411 pte_bits |= X86_PG_RW;
8413 if ((prot & VM_PROT_EXECUTE) == 0 ||
8414 va < VM_MIN_KERNEL_ADDRESS) {
8418 pde_mask |= X86_PG_RW | pg_nx;
8419 pte_mask |= X86_PG_RW | pg_nx;
8423 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8424 * into 4KB pages if required.
8426 for (tmpva = base; tmpva < base + size; ) {
8427 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8428 if (pdpe == NULL || *pdpe == 0) {
8429 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8430 ("%s: addr %#lx is not mapped", __func__, tmpva));
8433 if (*pdpe & PG_PS) {
8435 * If the current 1GB page already has the required
8436 * properties, then we need not demote this page. Just
8437 * increment tmpva to the next 1GB page frame.
8439 if ((*pdpe & pde_mask) == pde_bits) {
8440 tmpva = trunc_1gpage(tmpva) + NBPDP;
8445 * If the current offset aligns with a 1GB page frame
8446 * and there is at least 1GB left within the range, then
8447 * we need not break down this page into 2MB pages.
8449 if ((tmpva & PDPMASK) == 0 &&
8450 tmpva + PDPMASK < base + size) {
8454 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8457 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8459 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8460 ("%s: addr %#lx is not mapped", __func__, tmpva));
8465 * If the current 2MB page already has the required
8466 * properties, then we need not demote this page. Just
8467 * increment tmpva to the next 2MB page frame.
8469 if ((*pde & pde_mask) == pde_bits) {
8470 tmpva = trunc_2mpage(tmpva) + NBPDR;
8475 * If the current offset aligns with a 2MB page frame
8476 * and there is at least 2MB left within the range, then
8477 * we need not break down this page into 4KB pages.
8479 if ((tmpva & PDRMASK) == 0 &&
8480 tmpva + PDRMASK < base + size) {
8484 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8487 pte = pmap_pde_to_pte(pde, tmpva);
8489 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8490 ("%s: addr %#lx is not mapped", __func__, tmpva));
8498 * Ok, all the pages exist, so run through them updating their
8499 * properties if required.
8502 pa_start = pa_end = 0;
8503 for (tmpva = base; tmpva < base + size; ) {
8504 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8505 if (*pdpe & PG_PS) {
8506 if ((*pdpe & pde_mask) != pde_bits) {
8507 pmap_pte_props(pdpe, pde_bits, pde_mask);
8510 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8511 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8512 if (pa_start == pa_end) {
8513 /* Start physical address run. */
8514 pa_start = *pdpe & PG_PS_FRAME;
8515 pa_end = pa_start + NBPDP;
8516 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8519 /* Run ended, update direct map. */
8520 error = pmap_change_props_locked(
8521 PHYS_TO_DMAP(pa_start),
8522 pa_end - pa_start, prot, mode,
8526 /* Start physical address run. */
8527 pa_start = *pdpe & PG_PS_FRAME;
8528 pa_end = pa_start + NBPDP;
8531 tmpva = trunc_1gpage(tmpva) + NBPDP;
8534 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8536 if ((*pde & pde_mask) != pde_bits) {
8537 pmap_pte_props(pde, pde_bits, pde_mask);
8540 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8541 (*pde & PG_PS_FRAME) < dmaplimit) {
8542 if (pa_start == pa_end) {
8543 /* Start physical address run. */
8544 pa_start = *pde & PG_PS_FRAME;
8545 pa_end = pa_start + NBPDR;
8546 } else if (pa_end == (*pde & PG_PS_FRAME))
8549 /* Run ended, update direct map. */
8550 error = pmap_change_props_locked(
8551 PHYS_TO_DMAP(pa_start),
8552 pa_end - pa_start, prot, mode,
8556 /* Start physical address run. */
8557 pa_start = *pde & PG_PS_FRAME;
8558 pa_end = pa_start + NBPDR;
8561 tmpva = trunc_2mpage(tmpva) + NBPDR;
8563 pte = pmap_pde_to_pte(pde, tmpva);
8564 if ((*pte & pte_mask) != pte_bits) {
8565 pmap_pte_props(pte, pte_bits, pte_mask);
8568 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8569 (*pte & PG_FRAME) < dmaplimit) {
8570 if (pa_start == pa_end) {
8571 /* Start physical address run. */
8572 pa_start = *pte & PG_FRAME;
8573 pa_end = pa_start + PAGE_SIZE;
8574 } else if (pa_end == (*pte & PG_FRAME))
8575 pa_end += PAGE_SIZE;
8577 /* Run ended, update direct map. */
8578 error = pmap_change_props_locked(
8579 PHYS_TO_DMAP(pa_start),
8580 pa_end - pa_start, prot, mode,
8584 /* Start physical address run. */
8585 pa_start = *pte & PG_FRAME;
8586 pa_end = pa_start + PAGE_SIZE;
8592 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8593 pa_end1 = MIN(pa_end, dmaplimit);
8594 if (pa_start != pa_end1)
8595 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
8596 pa_end1 - pa_start, prot, mode, flags);
8600 * Flush CPU caches if required to make sure any data isn't cached that
8601 * shouldn't be, etc.
8604 pmap_invalidate_range(kernel_pmap, base, tmpva);
8605 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8606 pmap_invalidate_cache_range(base, tmpva);
8612 * Demotes any mapping within the direct map region that covers more than the
8613 * specified range of physical addresses. This range's size must be a power
8614 * of two and its starting address must be a multiple of its size. Since the
8615 * demotion does not change any attributes of the mapping, a TLB invalidation
8616 * is not mandatory. The caller may, however, request a TLB invalidation.
8619 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8628 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8629 KASSERT((base & (len - 1)) == 0,
8630 ("pmap_demote_DMAP: base is not a multiple of len"));
8631 if (len < NBPDP && base < dmaplimit) {
8632 va = PHYS_TO_DMAP(base);
8634 PMAP_LOCK(kernel_pmap);
8635 pdpe = pmap_pdpe(kernel_pmap, va);
8636 if ((*pdpe & X86_PG_V) == 0)
8637 panic("pmap_demote_DMAP: invalid PDPE");
8638 if ((*pdpe & PG_PS) != 0) {
8639 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8640 panic("pmap_demote_DMAP: PDPE failed");
8644 pde = pmap_pdpe_to_pde(pdpe, va);
8645 if ((*pde & X86_PG_V) == 0)
8646 panic("pmap_demote_DMAP: invalid PDE");
8647 if ((*pde & PG_PS) != 0) {
8648 if (!pmap_demote_pde(kernel_pmap, pde, va))
8649 panic("pmap_demote_DMAP: PDE failed");
8653 if (changed && invalidate)
8654 pmap_invalidate_page(kernel_pmap, va);
8655 PMAP_UNLOCK(kernel_pmap);
8660 * Perform the pmap work for mincore(2). If the page is not both referenced and
8661 * modified by this pmap, returns its physical address so that the caller can
8662 * find other mappings.
8665 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
8668 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8672 PG_A = pmap_accessed_bit(pmap);
8673 PG_M = pmap_modified_bit(pmap);
8674 PG_V = pmap_valid_bit(pmap);
8675 PG_RW = pmap_rw_bit(pmap);
8678 pdep = pmap_pde(pmap, addr);
8679 if (pdep != NULL && (*pdep & PG_V)) {
8680 if (*pdep & PG_PS) {
8682 /* Compute the physical address of the 4KB page. */
8683 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8685 val = MINCORE_SUPER;
8687 pte = *pmap_pde_to_pte(pdep, addr);
8688 pa = pte & PG_FRAME;
8696 if ((pte & PG_V) != 0) {
8697 val |= MINCORE_INCORE;
8698 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8699 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8700 if ((pte & PG_A) != 0)
8701 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8703 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8704 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8705 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8713 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8715 uint32_t gen, new_gen, pcid_next;
8717 CRITICAL_ASSERT(curthread);
8718 gen = PCPU_GET(pcid_gen);
8719 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8720 return (pti ? 0 : CR3_PCID_SAVE);
8721 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8722 return (CR3_PCID_SAVE);
8723 pcid_next = PCPU_GET(pcid_next);
8724 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8725 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8726 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8727 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8728 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8732 PCPU_SET(pcid_gen, new_gen);
8733 pcid_next = PMAP_PCID_KERN + 1;
8737 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8738 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8739 PCPU_SET(pcid_next, pcid_next + 1);
8744 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8748 cached = pmap_pcid_alloc(pmap, cpuid);
8749 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8750 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8751 pmap->pm_pcids[cpuid].pm_pcid));
8752 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8753 pmap == kernel_pmap,
8754 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8755 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8760 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8763 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8764 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
8768 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8770 struct invpcid_descr d;
8771 uint64_t cached, cr3, kcr3, ucr3;
8773 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8775 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8776 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8777 PCPU_SET(curpmap, pmap);
8778 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8779 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8782 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8784 * Explicitly invalidate translations cached from the
8785 * user page table. They are not automatically
8786 * flushed by reload of cr3 with the kernel page table
8789 * Note that the if() condition is resolved statically
8790 * by using the function argument instead of
8791 * runtime-evaluated invpcid_works value.
8793 if (invpcid_works1) {
8794 d.pcid = PMAP_PCID_USER_PT |
8795 pmap->pm_pcids[cpuid].pm_pcid;
8798 invpcid(&d, INVPCID_CTX);
8800 pmap_pti_pcid_invalidate(ucr3, kcr3);
8804 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8805 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8807 PCPU_INC(pm_save_cnt);
8811 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8814 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8815 pmap_activate_sw_pti_post(td, pmap);
8819 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8825 * If the INVPCID instruction is not available,
8826 * invltlb_pcid_handler() is used to handle an invalidate_all
8827 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8828 * sequence of operations has a window where %CR3 is loaded
8829 * with the new pmap's PML4 address, but the curpmap value has
8830 * not yet been updated. This causes the invltlb IPI handler,
8831 * which is called between the updates, to execute as a NOP,
8832 * which leaves stale TLB entries.
8834 * Note that the most typical use of pmap_activate_sw(), from
8835 * the context switch, is immune to this race, because
8836 * interrupts are disabled (while the thread lock is owned),
8837 * and the IPI happens after curpmap is updated. Protect
8838 * other callers in a similar way, by disabling interrupts
8839 * around the %cr3 register reload and curpmap assignment.
8841 rflags = intr_disable();
8842 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8843 intr_restore(rflags);
8844 pmap_activate_sw_pti_post(td, pmap);
8848 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8851 uint64_t cached, cr3;
8853 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8855 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8856 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8858 PCPU_SET(curpmap, pmap);
8860 PCPU_INC(pm_save_cnt);
8864 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8869 rflags = intr_disable();
8870 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8871 intr_restore(rflags);
8875 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8876 u_int cpuid __unused)
8879 load_cr3(pmap->pm_cr3);
8880 PCPU_SET(curpmap, pmap);
8884 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8885 u_int cpuid __unused)
8888 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8889 PCPU_SET(kcr3, pmap->pm_cr3);
8890 PCPU_SET(ucr3, pmap->pm_ucr3);
8891 pmap_activate_sw_pti_post(td, pmap);
8894 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8898 if (pmap_pcid_enabled && pti && invpcid_works)
8899 return (pmap_activate_sw_pcid_invpcid_pti);
8900 else if (pmap_pcid_enabled && pti && !invpcid_works)
8901 return (pmap_activate_sw_pcid_noinvpcid_pti);
8902 else if (pmap_pcid_enabled && !pti && invpcid_works)
8903 return (pmap_activate_sw_pcid_nopti);
8904 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8905 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8906 else if (!pmap_pcid_enabled && pti)
8907 return (pmap_activate_sw_nopcid_pti);
8908 else /* if (!pmap_pcid_enabled && !pti) */
8909 return (pmap_activate_sw_nopcid_nopti);
8913 pmap_activate_sw(struct thread *td)
8915 pmap_t oldpmap, pmap;
8918 oldpmap = PCPU_GET(curpmap);
8919 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8920 if (oldpmap == pmap) {
8921 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8925 cpuid = PCPU_GET(cpuid);
8927 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8929 CPU_SET(cpuid, &pmap->pm_active);
8931 pmap_activate_sw_mode(td, pmap, cpuid);
8933 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8935 CPU_CLR(cpuid, &oldpmap->pm_active);
8940 pmap_activate(struct thread *td)
8944 pmap_activate_sw(td);
8949 pmap_activate_boot(pmap_t pmap)
8955 * kernel_pmap must be never deactivated, and we ensure that
8956 * by never activating it at all.
8958 MPASS(pmap != kernel_pmap);
8960 cpuid = PCPU_GET(cpuid);
8962 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8964 CPU_SET(cpuid, &pmap->pm_active);
8966 PCPU_SET(curpmap, pmap);
8968 kcr3 = pmap->pm_cr3;
8969 if (pmap_pcid_enabled)
8970 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8974 PCPU_SET(kcr3, kcr3);
8975 PCPU_SET(ucr3, PMAP_NO_CR3);
8979 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8984 * Increase the starting virtual address of the given mapping if a
8985 * different alignment might result in more superpage mappings.
8988 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8989 vm_offset_t *addr, vm_size_t size)
8991 vm_offset_t superpage_offset;
8995 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8996 offset += ptoa(object->pg_color);
8997 superpage_offset = offset & PDRMASK;
8998 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8999 (*addr & PDRMASK) == superpage_offset)
9001 if ((*addr & PDRMASK) < superpage_offset)
9002 *addr = (*addr & ~PDRMASK) + superpage_offset;
9004 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9008 static unsigned long num_dirty_emulations;
9009 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9010 &num_dirty_emulations, 0, NULL);
9012 static unsigned long num_accessed_emulations;
9013 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9014 &num_accessed_emulations, 0, NULL);
9016 static unsigned long num_superpage_accessed_emulations;
9017 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9018 &num_superpage_accessed_emulations, 0, NULL);
9020 static unsigned long ad_emulation_superpage_promotions;
9021 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9022 &ad_emulation_superpage_promotions, 0, NULL);
9023 #endif /* INVARIANTS */
9026 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9029 struct rwlock *lock;
9030 #if VM_NRESERVLEVEL > 0
9034 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9036 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9037 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9039 if (!pmap_emulate_ad_bits(pmap))
9042 PG_A = pmap_accessed_bit(pmap);
9043 PG_M = pmap_modified_bit(pmap);
9044 PG_V = pmap_valid_bit(pmap);
9045 PG_RW = pmap_rw_bit(pmap);
9051 pde = pmap_pde(pmap, va);
9052 if (pde == NULL || (*pde & PG_V) == 0)
9055 if ((*pde & PG_PS) != 0) {
9056 if (ftype == VM_PROT_READ) {
9058 atomic_add_long(&num_superpage_accessed_emulations, 1);
9066 pte = pmap_pde_to_pte(pde, va);
9067 if ((*pte & PG_V) == 0)
9070 if (ftype == VM_PROT_WRITE) {
9071 if ((*pte & PG_RW) == 0)
9074 * Set the modified and accessed bits simultaneously.
9076 * Intel EPT PTEs that do software emulation of A/D bits map
9077 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9078 * An EPT misconfiguration is triggered if the PTE is writable
9079 * but not readable (WR=10). This is avoided by setting PG_A
9080 * and PG_M simultaneously.
9082 *pte |= PG_M | PG_A;
9087 #if VM_NRESERVLEVEL > 0
9088 /* try to promote the mapping */
9089 if (va < VM_MAXUSER_ADDRESS)
9090 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9094 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9096 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9097 pmap_ps_enabled(pmap) &&
9098 (m->flags & PG_FICTITIOUS) == 0 &&
9099 vm_reserv_level_iffullpop(m) == 0) {
9100 pmap_promote_pde(pmap, pde, va, &lock);
9102 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9108 if (ftype == VM_PROT_WRITE)
9109 atomic_add_long(&num_dirty_emulations, 1);
9111 atomic_add_long(&num_accessed_emulations, 1);
9113 rv = 0; /* success */
9122 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9127 pt_entry_t *pte, PG_V;
9131 PG_V = pmap_valid_bit(pmap);
9134 pml4 = pmap_pml4e(pmap, va);
9136 if ((*pml4 & PG_V) == 0)
9139 pdp = pmap_pml4e_to_pdpe(pml4, va);
9141 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9144 pde = pmap_pdpe_to_pde(pdp, va);
9146 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9149 pte = pmap_pde_to_pte(pde, va);
9158 * Get the kernel virtual address of a set of physical pages. If there are
9159 * physical addresses not covered by the DMAP perform a transient mapping
9160 * that will be removed when calling pmap_unmap_io_transient.
9162 * \param page The pages the caller wishes to obtain the virtual
9163 * address on the kernel memory map.
9164 * \param vaddr On return contains the kernel virtual memory address
9165 * of the pages passed in the page parameter.
9166 * \param count Number of pages passed in.
9167 * \param can_fault TRUE if the thread using the mapped pages can take
9168 * page faults, FALSE otherwise.
9170 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9171 * finished or FALSE otherwise.
9175 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9176 boolean_t can_fault)
9179 boolean_t needs_mapping;
9181 int cache_bits, error __unused, i;
9184 * Allocate any KVA space that we need, this is done in a separate
9185 * loop to prevent calling vmem_alloc while pinned.
9187 needs_mapping = FALSE;
9188 for (i = 0; i < count; i++) {
9189 paddr = VM_PAGE_TO_PHYS(page[i]);
9190 if (__predict_false(paddr >= dmaplimit)) {
9191 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9192 M_BESTFIT | M_WAITOK, &vaddr[i]);
9193 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9194 needs_mapping = TRUE;
9196 vaddr[i] = PHYS_TO_DMAP(paddr);
9200 /* Exit early if everything is covered by the DMAP */
9205 * NB: The sequence of updating a page table followed by accesses
9206 * to the corresponding pages used in the !DMAP case is subject to
9207 * the situation described in the "AMD64 Architecture Programmer's
9208 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9209 * Coherency Considerations". Therefore, issuing the INVLPG right
9210 * after modifying the PTE bits is crucial.
9214 for (i = 0; i < count; i++) {
9215 paddr = VM_PAGE_TO_PHYS(page[i]);
9216 if (paddr >= dmaplimit) {
9219 * Slow path, since we can get page faults
9220 * while mappings are active don't pin the
9221 * thread to the CPU and instead add a global
9222 * mapping visible to all CPUs.
9224 pmap_qenter(vaddr[i], &page[i], 1);
9226 pte = vtopte(vaddr[i]);
9227 cache_bits = pmap_cache_bits(kernel_pmap,
9228 page[i]->md.pat_mode, 0);
9229 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9236 return (needs_mapping);
9240 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9241 boolean_t can_fault)
9248 for (i = 0; i < count; i++) {
9249 paddr = VM_PAGE_TO_PHYS(page[i]);
9250 if (paddr >= dmaplimit) {
9252 pmap_qremove(vaddr[i], 1);
9253 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9259 pmap_quick_enter_page(vm_page_t m)
9263 paddr = VM_PAGE_TO_PHYS(m);
9264 if (paddr < dmaplimit)
9265 return (PHYS_TO_DMAP(paddr));
9266 mtx_lock_spin(&qframe_mtx);
9267 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9268 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9269 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9274 pmap_quick_remove_page(vm_offset_t addr)
9279 pte_store(vtopte(qframe), 0);
9281 mtx_unlock_spin(&qframe_mtx);
9285 * Pdp pages from the large map are managed differently from either
9286 * kernel or user page table pages. They are permanently allocated at
9287 * initialization time, and their reference count is permanently set to
9288 * zero. The pml4 entries pointing to those pages are copied into
9289 * each allocated pmap.
9291 * In contrast, pd and pt pages are managed like user page table
9292 * pages. They are dynamically allocated, and their reference count
9293 * represents the number of valid entries within the page.
9296 pmap_large_map_getptp_unlocked(void)
9300 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9302 if (m != NULL && (m->flags & PG_ZERO) == 0)
9308 pmap_large_map_getptp(void)
9312 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9313 m = pmap_large_map_getptp_unlocked();
9315 PMAP_UNLOCK(kernel_pmap);
9317 PMAP_LOCK(kernel_pmap);
9318 /* Callers retry. */
9323 static pdp_entry_t *
9324 pmap_large_map_pdpe(vm_offset_t va)
9326 vm_pindex_t pml4_idx;
9329 pml4_idx = pmap_pml4e_index(va);
9330 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9331 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9333 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9334 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
9335 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9336 "LMSPML4I %#jx lm_ents %d",
9337 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9338 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
9339 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9343 pmap_large_map_pde(vm_offset_t va)
9350 pdpe = pmap_large_map_pdpe(va);
9352 m = pmap_large_map_getptp();
9355 mphys = VM_PAGE_TO_PHYS(m);
9356 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9358 MPASS((*pdpe & X86_PG_PS) == 0);
9359 mphys = *pdpe & PG_FRAME;
9361 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9365 pmap_large_map_pte(vm_offset_t va)
9372 pde = pmap_large_map_pde(va);
9374 m = pmap_large_map_getptp();
9377 mphys = VM_PAGE_TO_PHYS(m);
9378 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9379 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9381 MPASS((*pde & X86_PG_PS) == 0);
9382 mphys = *pde & PG_FRAME;
9384 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9388 pmap_large_map_kextract(vm_offset_t va)
9390 pdp_entry_t *pdpe, pdp;
9391 pd_entry_t *pde, pd;
9392 pt_entry_t *pte, pt;
9394 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9395 ("not largemap range %#lx", (u_long)va));
9396 pdpe = pmap_large_map_pdpe(va);
9398 KASSERT((pdp & X86_PG_V) != 0,
9399 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9400 (u_long)pdpe, pdp));
9401 if ((pdp & X86_PG_PS) != 0) {
9402 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9403 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9404 (u_long)pdpe, pdp));
9405 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9407 pde = pmap_pdpe_to_pde(pdpe, va);
9409 KASSERT((pd & X86_PG_V) != 0,
9410 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9411 if ((pd & X86_PG_PS) != 0)
9412 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9413 pte = pmap_pde_to_pte(pde, va);
9415 KASSERT((pt & X86_PG_V) != 0,
9416 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9417 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9421 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9422 vmem_addr_t *vmem_res)
9426 * Large mappings are all but static. Consequently, there
9427 * is no point in waiting for an earlier allocation to be
9430 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9431 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9435 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9441 vm_offset_t va, inc;
9442 vmem_addr_t vmem_res;
9446 if (len == 0 || spa + len < spa)
9449 /* See if DMAP can serve. */
9450 if (spa + len <= dmaplimit) {
9451 va = PHYS_TO_DMAP(spa);
9453 return (pmap_change_attr(va, len, mattr));
9457 * No, allocate KVA. Fit the address with best possible
9458 * alignment for superpages. Fall back to worse align if
9462 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9463 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9464 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9466 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9468 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9471 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9476 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9477 * in the pagetable to minimize flushing. No need to
9478 * invalidate TLB, since we only update invalid entries.
9480 PMAP_LOCK(kernel_pmap);
9481 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9483 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9484 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9485 pdpe = pmap_large_map_pdpe(va);
9487 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9488 X86_PG_V | X86_PG_A | pg_nx |
9489 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9491 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9492 (va & PDRMASK) == 0) {
9493 pde = pmap_large_map_pde(va);
9495 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9496 X86_PG_V | X86_PG_A | pg_nx |
9497 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9498 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9502 pte = pmap_large_map_pte(va);
9504 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9505 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9507 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9512 PMAP_UNLOCK(kernel_pmap);
9515 *addr = (void *)vmem_res;
9520 pmap_large_unmap(void *svaa, vm_size_t len)
9522 vm_offset_t sva, va;
9524 pdp_entry_t *pdpe, pdp;
9525 pd_entry_t *pde, pd;
9528 struct spglist spgf;
9530 sva = (vm_offset_t)svaa;
9531 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9532 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9536 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9537 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9538 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9539 PMAP_LOCK(kernel_pmap);
9540 for (va = sva; va < sva + len; va += inc) {
9541 pdpe = pmap_large_map_pdpe(va);
9543 KASSERT((pdp & X86_PG_V) != 0,
9544 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9545 (u_long)pdpe, pdp));
9546 if ((pdp & X86_PG_PS) != 0) {
9547 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9548 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9549 (u_long)pdpe, pdp));
9550 KASSERT((va & PDPMASK) == 0,
9551 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9552 (u_long)pdpe, pdp));
9553 KASSERT(va + NBPDP <= sva + len,
9554 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9555 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9556 (u_long)pdpe, pdp, len));
9561 pde = pmap_pdpe_to_pde(pdpe, va);
9563 KASSERT((pd & X86_PG_V) != 0,
9564 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9566 if ((pd & X86_PG_PS) != 0) {
9567 KASSERT((va & PDRMASK) == 0,
9568 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9570 KASSERT(va + NBPDR <= sva + len,
9571 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9572 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9576 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9578 if (m->ref_count == 0) {
9580 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9584 pte = pmap_pde_to_pte(pde, va);
9585 KASSERT((*pte & X86_PG_V) != 0,
9586 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9587 (u_long)pte, *pte));
9590 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9592 if (m->ref_count == 0) {
9594 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9595 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9597 if (m->ref_count == 0) {
9599 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9603 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9604 PMAP_UNLOCK(kernel_pmap);
9605 vm_page_free_pages_toq(&spgf, false);
9606 vmem_free(large_vmem, sva, len);
9610 pmap_large_map_wb_fence_mfence(void)
9617 pmap_large_map_wb_fence_atomic(void)
9620 atomic_thread_fence_seq_cst();
9624 pmap_large_map_wb_fence_nop(void)
9628 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9631 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9632 return (pmap_large_map_wb_fence_mfence);
9633 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9634 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9635 return (pmap_large_map_wb_fence_atomic);
9637 /* clflush is strongly enough ordered */
9638 return (pmap_large_map_wb_fence_nop);
9642 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9645 for (; len > 0; len -= cpu_clflush_line_size,
9646 va += cpu_clflush_line_size)
9651 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9654 for (; len > 0; len -= cpu_clflush_line_size,
9655 va += cpu_clflush_line_size)
9660 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9663 for (; len > 0; len -= cpu_clflush_line_size,
9664 va += cpu_clflush_line_size)
9669 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9673 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9676 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9677 return (pmap_large_map_flush_range_clwb);
9678 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9679 return (pmap_large_map_flush_range_clflushopt);
9680 else if ((cpu_feature & CPUID_CLFSH) != 0)
9681 return (pmap_large_map_flush_range_clflush);
9683 return (pmap_large_map_flush_range_nop);
9687 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9689 volatile u_long *pe;
9695 for (va = sva; va < eva; va += inc) {
9697 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9698 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9700 if ((p & X86_PG_PS) != 0)
9704 pe = (volatile u_long *)pmap_large_map_pde(va);
9706 if ((p & X86_PG_PS) != 0)
9710 pe = (volatile u_long *)pmap_large_map_pte(va);
9716 if ((p & X86_PG_AVAIL1) != 0) {
9718 * Spin-wait for the end of a parallel
9725 * If we saw other write-back
9726 * occuring, we cannot rely on PG_M to
9727 * indicate state of the cache. The
9728 * PG_M bit is cleared before the
9729 * flush to avoid ignoring new writes,
9730 * and writes which are relevant for
9731 * us might happen after.
9737 if ((p & X86_PG_M) != 0 || seen_other) {
9738 if (!atomic_fcmpset_long(pe, &p,
9739 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9741 * If we saw PG_M without
9742 * PG_AVAIL1, and then on the
9743 * next attempt we do not
9744 * observe either PG_M or
9745 * PG_AVAIL1, the other
9746 * write-back started after us
9747 * and finished before us. We
9748 * can rely on it doing our
9752 pmap_large_map_flush_range(va, inc);
9753 atomic_clear_long(pe, X86_PG_AVAIL1);
9762 * Write-back cache lines for the given address range.
9764 * Must be called only on the range or sub-range returned from
9765 * pmap_large_map(). Must not be called on the coalesced ranges.
9767 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9768 * instructions support.
9771 pmap_large_map_wb(void *svap, vm_size_t len)
9773 vm_offset_t eva, sva;
9775 sva = (vm_offset_t)svap;
9777 pmap_large_map_wb_fence();
9778 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9779 pmap_large_map_flush_range(sva, len);
9781 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9782 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9783 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9784 pmap_large_map_wb_large(sva, eva);
9786 pmap_large_map_wb_fence();
9790 pmap_pti_alloc_page(void)
9794 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9795 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9796 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9801 pmap_pti_free_page(vm_page_t m)
9804 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
9805 if (!vm_page_unwire_noq(m))
9807 vm_page_free_zero(m);
9821 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9822 VM_OBJECT_WLOCK(pti_obj);
9823 pml4_pg = pmap_pti_alloc_page();
9824 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9825 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9826 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9827 pdpe = pmap_pti_pdpe(va);
9828 pmap_pti_wire_pte(pdpe);
9830 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9831 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9832 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9833 sizeof(struct gate_descriptor) * NIDT, false);
9835 /* Doublefault stack IST 1 */
9836 va = __pcpu[i].pc_common_tss.tss_ist1;
9837 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9838 /* NMI stack IST 2 */
9839 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
9840 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9841 /* MC# stack IST 3 */
9842 va = __pcpu[i].pc_common_tss.tss_ist3 +
9843 sizeof(struct nmi_pcpu);
9844 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9845 /* DB# stack IST 4 */
9846 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
9847 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9849 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9850 (vm_offset_t)etext, true);
9851 pti_finalized = true;
9852 VM_OBJECT_WUNLOCK(pti_obj);
9854 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9856 static pdp_entry_t *
9857 pmap_pti_pdpe(vm_offset_t va)
9859 pml4_entry_t *pml4e;
9862 vm_pindex_t pml4_idx;
9865 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9867 pml4_idx = pmap_pml4e_index(va);
9868 pml4e = &pti_pml4[pml4_idx];
9872 panic("pml4 alloc after finalization\n");
9873 m = pmap_pti_alloc_page();
9875 pmap_pti_free_page(m);
9876 mphys = *pml4e & ~PAGE_MASK;
9878 mphys = VM_PAGE_TO_PHYS(m);
9879 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9882 mphys = *pml4e & ~PAGE_MASK;
9884 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9889 pmap_pti_wire_pte(void *pte)
9893 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9894 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9899 pmap_pti_unwire_pde(void *pde, bool only_ref)
9903 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9904 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9905 MPASS(m->ref_count > 0);
9906 MPASS(only_ref || m->ref_count > 1);
9907 pmap_pti_free_page(m);
9911 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9916 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9917 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9918 MPASS(m->ref_count > 0);
9919 if (pmap_pti_free_page(m)) {
9920 pde = pmap_pti_pde(va);
9921 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9923 pmap_pti_unwire_pde(pde, false);
9928 pmap_pti_pde(vm_offset_t va)
9936 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9938 pdpe = pmap_pti_pdpe(va);
9940 m = pmap_pti_alloc_page();
9942 pmap_pti_free_page(m);
9943 MPASS((*pdpe & X86_PG_PS) == 0);
9944 mphys = *pdpe & ~PAGE_MASK;
9946 mphys = VM_PAGE_TO_PHYS(m);
9947 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9950 MPASS((*pdpe & X86_PG_PS) == 0);
9951 mphys = *pdpe & ~PAGE_MASK;
9954 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9955 pd_idx = pmap_pde_index(va);
9961 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9968 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9970 pde = pmap_pti_pde(va);
9971 if (unwire_pde != NULL) {
9973 pmap_pti_wire_pte(pde);
9976 m = pmap_pti_alloc_page();
9978 pmap_pti_free_page(m);
9979 MPASS((*pde & X86_PG_PS) == 0);
9980 mphys = *pde & ~(PAGE_MASK | pg_nx);
9982 mphys = VM_PAGE_TO_PHYS(m);
9983 *pde = mphys | X86_PG_RW | X86_PG_V;
9984 if (unwire_pde != NULL)
9985 *unwire_pde = false;
9988 MPASS((*pde & X86_PG_PS) == 0);
9989 mphys = *pde & ~(PAGE_MASK | pg_nx);
9992 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9993 pte += pmap_pte_index(va);
9999 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10003 pt_entry_t *pte, ptev;
10006 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10008 sva = trunc_page(sva);
10009 MPASS(sva > VM_MAXUSER_ADDRESS);
10010 eva = round_page(eva);
10012 for (; sva < eva; sva += PAGE_SIZE) {
10013 pte = pmap_pti_pte(sva, &unwire_pde);
10014 pa = pmap_kextract(sva);
10015 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10016 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10017 VM_MEMATTR_DEFAULT, FALSE);
10019 pte_store(pte, ptev);
10020 pmap_pti_wire_pte(pte);
10022 KASSERT(!pti_finalized,
10023 ("pti overlap after fin %#lx %#lx %#lx",
10025 KASSERT(*pte == ptev,
10026 ("pti non-identical pte after fin %#lx %#lx %#lx",
10030 pde = pmap_pti_pde(sva);
10031 pmap_pti_unwire_pde(pde, true);
10037 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10042 VM_OBJECT_WLOCK(pti_obj);
10043 pmap_pti_add_kva_locked(sva, eva, exec);
10044 VM_OBJECT_WUNLOCK(pti_obj);
10048 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10055 sva = rounddown2(sva, PAGE_SIZE);
10056 MPASS(sva > VM_MAXUSER_ADDRESS);
10057 eva = roundup2(eva, PAGE_SIZE);
10059 VM_OBJECT_WLOCK(pti_obj);
10060 for (va = sva; va < eva; va += PAGE_SIZE) {
10061 pte = pmap_pti_pte(va, NULL);
10062 KASSERT((*pte & X86_PG_V) != 0,
10063 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10064 (u_long)pte, *pte));
10066 pmap_pti_unwire_pte(pte, va);
10068 pmap_invalidate_range(kernel_pmap, sva, eva);
10069 VM_OBJECT_WUNLOCK(pti_obj);
10073 pkru_dup_range(void *ctx __unused, void *data)
10075 struct pmap_pkru_range *node, *new_node;
10077 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10078 if (new_node == NULL)
10081 memcpy(new_node, node, sizeof(*node));
10086 pkru_free_range(void *ctx __unused, void *node)
10089 uma_zfree(pmap_pkru_ranges_zone, node);
10093 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10096 struct pmap_pkru_range *ppr;
10099 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10100 MPASS(pmap->pm_type == PT_X86);
10101 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10102 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10103 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10105 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10108 ppr->pkru_keyidx = keyidx;
10109 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10110 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10112 uma_zfree(pmap_pkru_ranges_zone, ppr);
10117 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10120 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10121 MPASS(pmap->pm_type == PT_X86);
10122 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10123 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10127 pmap_pkru_deassign_all(pmap_t pmap)
10130 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10131 if (pmap->pm_type == PT_X86 &&
10132 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10133 rangeset_remove_all(&pmap->pm_pkru);
10137 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10139 struct pmap_pkru_range *ppr, *prev_ppr;
10142 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10143 if (pmap->pm_type != PT_X86 ||
10144 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10145 sva >= VM_MAXUSER_ADDRESS)
10147 MPASS(eva <= VM_MAXUSER_ADDRESS);
10148 for (va = sva, prev_ppr = NULL; va < eva;) {
10149 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10150 if ((ppr == NULL) ^ (prev_ppr == NULL))
10156 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10158 va = ppr->pkru_rs_el.re_end;
10164 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10166 struct pmap_pkru_range *ppr;
10168 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10169 if (pmap->pm_type != PT_X86 ||
10170 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10171 va >= VM_MAXUSER_ADDRESS)
10173 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10175 return (X86_PG_PKU(ppr->pkru_keyidx));
10180 pred_pkru_on_remove(void *ctx __unused, void *r)
10182 struct pmap_pkru_range *ppr;
10185 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10189 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10192 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10193 if (pmap->pm_type == PT_X86 &&
10194 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10195 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10196 pred_pkru_on_remove);
10201 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10204 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10205 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10206 MPASS(dst_pmap->pm_type == PT_X86);
10207 MPASS(src_pmap->pm_type == PT_X86);
10208 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10209 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10211 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10215 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10218 pml4_entry_t *pml4e;
10220 pd_entry_t newpde, ptpaddr, *pde;
10221 pt_entry_t newpte, *ptep, pte;
10222 vm_offset_t va, va_next;
10225 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10226 MPASS(pmap->pm_type == PT_X86);
10227 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10229 for (changed = false, va = sva; va < eva; va = va_next) {
10230 pml4e = pmap_pml4e(pmap, va);
10231 if ((*pml4e & X86_PG_V) == 0) {
10232 va_next = (va + NBPML4) & ~PML4MASK;
10238 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10239 if ((*pdpe & X86_PG_V) == 0) {
10240 va_next = (va + NBPDP) & ~PDPMASK;
10246 va_next = (va + NBPDR) & ~PDRMASK;
10250 pde = pmap_pdpe_to_pde(pdpe, va);
10255 MPASS((ptpaddr & X86_PG_V) != 0);
10256 if ((ptpaddr & PG_PS) != 0) {
10257 if (va + NBPDR == va_next && eva >= va_next) {
10258 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10259 X86_PG_PKU(keyidx);
10260 if (newpde != ptpaddr) {
10265 } else if (!pmap_demote_pde(pmap, pde, va)) {
10273 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10274 ptep++, va += PAGE_SIZE) {
10276 if ((pte & X86_PG_V) == 0)
10278 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10279 if (newpte != pte) {
10286 pmap_invalidate_range(pmap, sva, eva);
10290 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10291 u_int keyidx, int flags)
10294 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10295 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10297 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10299 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10305 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10310 sva = trunc_page(sva);
10311 eva = round_page(eva);
10312 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10317 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10319 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10321 if (error != ENOMEM)
10329 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10333 sva = trunc_page(sva);
10334 eva = round_page(eva);
10335 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10340 error = pmap_pkru_deassign(pmap, sva, eva);
10342 pmap_pkru_update_range(pmap, sva, eva, 0);
10344 if (error != ENOMEM)
10352 * Track a range of the kernel's virtual address space that is contiguous
10353 * in various mapping attributes.
10355 struct pmap_kernel_map_range {
10364 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10370 if (eva <= range->sva)
10373 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10374 for (i = 0; i < PAT_INDEX_SIZE; i++)
10375 if (pat_index[i] == pat_idx)
10379 case PAT_WRITE_BACK:
10382 case PAT_WRITE_THROUGH:
10385 case PAT_UNCACHEABLE:
10391 case PAT_WRITE_PROTECTED:
10394 case PAT_WRITE_COMBINING:
10398 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10399 __func__, pat_idx, range->sva, eva);
10404 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10406 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10407 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10408 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10409 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10410 mode, range->pdpes, range->pdes, range->ptes);
10412 /* Reset to sentinel value. */
10413 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10417 * Determine whether the attributes specified by a page table entry match those
10418 * being tracked by the current range. This is not quite as simple as a direct
10419 * flag comparison since some PAT modes have multiple representations.
10422 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10424 pt_entry_t diff, mask;
10426 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10427 diff = (range->attrs ^ attrs) & mask;
10430 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10431 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10432 pmap_pat_index(kernel_pmap, attrs, true))
10438 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10442 memset(range, 0, sizeof(*range));
10444 range->attrs = attrs;
10448 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10449 * those of the current run, dump the address range and its attributes, and
10453 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10454 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10459 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10461 attrs |= pdpe & pg_nx;
10462 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10463 if ((pdpe & PG_PS) != 0) {
10464 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10465 } else if (pde != 0) {
10466 attrs |= pde & pg_nx;
10467 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10469 if ((pde & PG_PS) != 0) {
10470 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10471 } else if (pte != 0) {
10472 attrs |= pte & pg_nx;
10473 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10474 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10476 /* Canonicalize by always using the PDE PAT bit. */
10477 if ((attrs & X86_PG_PTE_PAT) != 0)
10478 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10481 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10482 sysctl_kmaps_dump(sb, range, va);
10483 sysctl_kmaps_reinit(range, va, attrs);
10488 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10490 struct pmap_kernel_map_range range;
10491 struct sbuf sbuf, *sb;
10492 pml4_entry_t pml4e;
10493 pdp_entry_t *pdp, pdpe;
10494 pd_entry_t *pd, pde;
10495 pt_entry_t *pt, pte;
10498 int error, i, j, k, l;
10500 error = sysctl_wire_old_buffer(req, 0);
10504 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10506 /* Sentinel value. */
10507 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10510 * Iterate over the kernel page tables without holding the kernel pmap
10511 * lock. Outside of the large map, kernel page table pages are never
10512 * freed, so at worst we will observe inconsistencies in the output.
10513 * Within the large map, ensure that PDP and PD page addresses are
10514 * valid before descending.
10516 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10519 sbuf_printf(sb, "\nRecursive map:\n");
10522 sbuf_printf(sb, "\nDirect map:\n");
10525 sbuf_printf(sb, "\nKernel map:\n");
10528 sbuf_printf(sb, "\nLarge map:\n");
10532 /* Convert to canonical form. */
10533 if (sva == 1ul << 47)
10537 pml4e = kernel_pmap->pm_pml4[i];
10538 if ((pml4e & X86_PG_V) == 0) {
10539 sva = rounddown2(sva, NBPML4);
10540 sysctl_kmaps_dump(sb, &range, sva);
10544 pa = pml4e & PG_FRAME;
10545 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10547 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10549 if ((pdpe & X86_PG_V) == 0) {
10550 sva = rounddown2(sva, NBPDP);
10551 sysctl_kmaps_dump(sb, &range, sva);
10555 pa = pdpe & PG_FRAME;
10556 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10557 vm_phys_paddr_to_vm_page(pa) == NULL)
10559 if ((pdpe & PG_PS) != 0) {
10560 sva = rounddown2(sva, NBPDP);
10561 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10567 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10569 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10571 if ((pde & X86_PG_V) == 0) {
10572 sva = rounddown2(sva, NBPDR);
10573 sysctl_kmaps_dump(sb, &range, sva);
10577 pa = pde & PG_FRAME;
10578 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10579 vm_phys_paddr_to_vm_page(pa) == NULL)
10581 if ((pde & PG_PS) != 0) {
10582 sva = rounddown2(sva, NBPDR);
10583 sysctl_kmaps_check(sb, &range, sva,
10584 pml4e, pdpe, pde, 0);
10589 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10591 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10592 sva += PAGE_SIZE) {
10594 if ((pte & X86_PG_V) == 0) {
10595 sysctl_kmaps_dump(sb, &range,
10599 sysctl_kmaps_check(sb, &range, sva,
10600 pml4e, pdpe, pde, pte);
10607 error = sbuf_finish(sb);
10611 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10612 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10613 NULL, 0, sysctl_kmaps, "A",
10614 "Dump kernel address layout");
10617 DB_SHOW_COMMAND(pte, pmap_print_pte)
10620 pml4_entry_t *pml4;
10623 pt_entry_t *pte, PG_V;
10627 db_printf("show pte addr\n");
10630 va = (vm_offset_t)addr;
10632 if (kdb_thread != NULL)
10633 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10635 pmap = PCPU_GET(curpmap);
10637 PG_V = pmap_valid_bit(pmap);
10638 pml4 = pmap_pml4e(pmap, va);
10639 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10640 if ((*pml4 & PG_V) == 0) {
10644 pdp = pmap_pml4e_to_pdpe(pml4, va);
10645 db_printf(" pdpe 0x%016lx", *pdp);
10646 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10650 pde = pmap_pdpe_to_pde(pdp, va);
10651 db_printf(" pde 0x%016lx", *pde);
10652 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10656 pte = pmap_pde_to_pte(pde, va);
10657 db_printf(" pte 0x%016lx\n", *pte);
10660 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10665 a = (vm_paddr_t)addr;
10666 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10668 db_printf("show phys2dmap addr\n");