2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
327 #define pa_index(pa) ({ \
328 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
329 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_index(pa) ((pa) >> PDRSHIFT)
344 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
346 #define NPV_LIST_LOCKS MAXCPU
348 #define PHYS_TO_PV_LIST_LOCK(pa) \
349 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
352 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
353 struct rwlock **_lockp = (lockp); \
354 struct rwlock *_new_lock; \
356 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
357 if (_new_lock != *_lockp) { \
358 if (*_lockp != NULL) \
359 rw_wunlock(*_lockp); \
360 *_lockp = _new_lock; \
365 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
366 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
368 #define RELEASE_PV_LIST_LOCK(lockp) do { \
369 struct rwlock **_lockp = (lockp); \
371 if (*_lockp != NULL) { \
372 rw_wunlock(*_lockp); \
377 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
378 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
380 struct pmap kernel_pmap_store;
382 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
383 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
386 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
387 "Number of kernel page table pages allocated on bootup");
390 vm_paddr_t dmaplimit;
391 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
394 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
395 "VM/pmap parameters");
397 static int pg_ps_enabled = 1;
398 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
399 &pg_ps_enabled, 0, "Are large page mappings enabled?");
401 int __read_frequently la57 = 0;
402 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
404 "5-level paging for host is enabled");
407 pmap_is_la57(pmap_t pmap)
409 if (pmap->pm_type == PT_X86)
411 return (false); /* XXXKIB handle EPT */
414 #define PAT_INDEX_SIZE 8
415 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
417 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
418 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
419 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
420 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
421 u_int64_t KPML5phys; /* phys addr of kernel level 5,
424 static pml4_entry_t *kernel_pml4;
425 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
426 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
427 static int ndmpdpphys; /* number of DMPDPphys pages */
429 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
432 * pmap_mapdev support pre initialization (i.e. console)
434 #define PMAP_PREINIT_MAPPING_COUNT 8
435 static struct pmap_preinit_mapping {
440 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
441 static int pmap_initialized;
444 * Data for the pv entry allocation mechanism.
445 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
449 pc_to_domain(struct pv_chunk *pc)
452 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
456 pc_to_domain(struct pv_chunk *pc __unused)
463 struct pv_chunks_list {
465 TAILQ_HEAD(pch, pv_chunk) pvc_list;
467 } __aligned(CACHE_LINE_SIZE);
469 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
472 struct pmap_large_md_page {
473 struct rwlock pv_lock;
474 struct md_page pv_page;
477 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
478 #define pv_dummy pv_dummy_large.pv_page
479 __read_mostly static struct pmap_large_md_page *pv_table;
480 __read_mostly vm_paddr_t pmap_last_pa;
482 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
483 static u_long pv_invl_gen[NPV_LIST_LOCKS];
484 static struct md_page *pv_table;
485 static struct md_page pv_dummy;
489 * All those kernel PT submaps that BSD is so fond of
491 pt_entry_t *CMAP1 = NULL;
493 static vm_offset_t qframe = 0;
494 static struct mtx qframe_mtx;
496 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
498 static vmem_t *large_vmem;
499 static u_int lm_ents;
500 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
501 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
503 int pmap_pcid_enabled = 1;
504 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
505 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
506 int invpcid_works = 0;
507 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
508 "Is the invpcid instruction available ?");
510 int __read_frequently pti = 0;
511 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
513 "Page Table Isolation enabled");
514 static vm_object_t pti_obj;
515 static pml4_entry_t *pti_pml4;
516 static vm_pindex_t pti_pg_idx;
517 static bool pti_finalized;
519 struct pmap_pkru_range {
520 struct rs_el pkru_rs_el;
525 static uma_zone_t pmap_pkru_ranges_zone;
526 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
527 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
528 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
529 static void *pkru_dup_range(void *ctx, void *data);
530 static void pkru_free_range(void *ctx, void *node);
531 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
532 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
533 static void pmap_pkru_deassign_all(pmap_t pmap);
536 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
543 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
545 return (sysctl_handle_64(oidp, &res, 0, req));
547 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
548 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
549 "Count of saved TLB context on switch");
551 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
552 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
553 static struct mtx invl_gen_mtx;
554 /* Fake lock object to satisfy turnstiles interface. */
555 static struct lock_object invl_gen_ts = {
558 static struct pmap_invl_gen pmap_invl_gen_head = {
562 static u_long pmap_invl_gen = 1;
563 static int pmap_invl_waiters;
564 static struct callout pmap_invl_callout;
565 static bool pmap_invl_callout_inited;
567 #define PMAP_ASSERT_NOT_IN_DI() \
568 KASSERT(pmap_not_in_di(), ("DI already started"))
575 if ((cpu_feature2 & CPUID2_CX16) == 0)
578 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
583 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
587 locked = pmap_di_locked();
588 return (sysctl_handle_int(oidp, &locked, 0, req));
590 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
591 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
592 "Locked delayed invalidation");
594 static bool pmap_not_in_di_l(void);
595 static bool pmap_not_in_di_u(void);
596 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
599 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
603 pmap_not_in_di_l(void)
605 struct pmap_invl_gen *invl_gen;
607 invl_gen = &curthread->td_md.md_invl_gen;
608 return (invl_gen->gen == 0);
612 pmap_thread_init_invl_gen_l(struct thread *td)
614 struct pmap_invl_gen *invl_gen;
616 invl_gen = &td->td_md.md_invl_gen;
621 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
623 struct turnstile *ts;
625 ts = turnstile_trywait(&invl_gen_ts);
626 if (*m_gen > atomic_load_long(invl_gen))
627 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
629 turnstile_cancel(ts);
633 pmap_delayed_invl_finish_unblock(u_long new_gen)
635 struct turnstile *ts;
637 turnstile_chain_lock(&invl_gen_ts);
638 ts = turnstile_lookup(&invl_gen_ts);
640 pmap_invl_gen = new_gen;
642 turnstile_broadcast(ts, TS_SHARED_QUEUE);
643 turnstile_unpend(ts);
645 turnstile_chain_unlock(&invl_gen_ts);
649 * Start a new Delayed Invalidation (DI) block of code, executed by
650 * the current thread. Within a DI block, the current thread may
651 * destroy both the page table and PV list entries for a mapping and
652 * then release the corresponding PV list lock before ensuring that
653 * the mapping is flushed from the TLBs of any processors with the
657 pmap_delayed_invl_start_l(void)
659 struct pmap_invl_gen *invl_gen;
662 invl_gen = &curthread->td_md.md_invl_gen;
663 PMAP_ASSERT_NOT_IN_DI();
664 mtx_lock(&invl_gen_mtx);
665 if (LIST_EMPTY(&pmap_invl_gen_tracker))
666 currgen = pmap_invl_gen;
668 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
669 invl_gen->gen = currgen + 1;
670 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
671 mtx_unlock(&invl_gen_mtx);
675 * Finish the DI block, previously started by the current thread. All
676 * required TLB flushes for the pages marked by
677 * pmap_delayed_invl_page() must be finished before this function is
680 * This function works by bumping the global DI generation number to
681 * the generation number of the current thread's DI, unless there is a
682 * pending DI that started earlier. In the latter case, bumping the
683 * global DI generation number would incorrectly signal that the
684 * earlier DI had finished. Instead, this function bumps the earlier
685 * DI's generation number to match the generation number of the
686 * current thread's DI.
689 pmap_delayed_invl_finish_l(void)
691 struct pmap_invl_gen *invl_gen, *next;
693 invl_gen = &curthread->td_md.md_invl_gen;
694 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
695 mtx_lock(&invl_gen_mtx);
696 next = LIST_NEXT(invl_gen, link);
698 pmap_delayed_invl_finish_unblock(invl_gen->gen);
700 next->gen = invl_gen->gen;
701 LIST_REMOVE(invl_gen, link);
702 mtx_unlock(&invl_gen_mtx);
707 pmap_not_in_di_u(void)
709 struct pmap_invl_gen *invl_gen;
711 invl_gen = &curthread->td_md.md_invl_gen;
712 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
716 pmap_thread_init_invl_gen_u(struct thread *td)
718 struct pmap_invl_gen *invl_gen;
720 invl_gen = &td->td_md.md_invl_gen;
722 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
726 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
728 uint64_t new_high, new_low, old_high, old_low;
731 old_low = new_low = 0;
732 old_high = new_high = (uintptr_t)0;
734 __asm volatile("lock;cmpxchg16b\t%1"
735 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
736 : "b"(new_low), "c" (new_high)
739 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
742 out->next = (void *)old_high;
745 out->next = (void *)new_high;
751 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
752 struct pmap_invl_gen *new_val)
754 uint64_t new_high, new_low, old_high, old_low;
757 new_low = new_val->gen;
758 new_high = (uintptr_t)new_val->next;
759 old_low = old_val->gen;
760 old_high = (uintptr_t)old_val->next;
762 __asm volatile("lock;cmpxchg16b\t%1"
763 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
764 : "b"(new_low), "c" (new_high)
770 static long invl_start_restart;
771 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
772 &invl_start_restart, 0,
774 static long invl_finish_restart;
775 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
776 &invl_finish_restart, 0,
778 static int invl_max_qlen;
779 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
784 #define di_delay locks_delay
787 pmap_delayed_invl_start_u(void)
789 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
791 struct lock_delay_arg lda;
799 invl_gen = &td->td_md.md_invl_gen;
800 PMAP_ASSERT_NOT_IN_DI();
801 lock_delay_arg_init(&lda, &di_delay);
802 invl_gen->saved_pri = 0;
803 pri = td->td_base_pri;
806 pri = td->td_base_pri;
808 invl_gen->saved_pri = pri;
815 for (p = &pmap_invl_gen_head;; p = prev.next) {
817 prevl = (uintptr_t)atomic_load_ptr(&p->next);
818 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
819 PV_STAT(atomic_add_long(&invl_start_restart, 1));
825 prev.next = (void *)prevl;
828 if ((ii = invl_max_qlen) < i)
829 atomic_cmpset_int(&invl_max_qlen, ii, i);
832 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
833 PV_STAT(atomic_add_long(&invl_start_restart, 1));
838 new_prev.gen = prev.gen;
839 new_prev.next = invl_gen;
840 invl_gen->gen = prev.gen + 1;
842 /* Formal fence between store to invl->gen and updating *p. */
843 atomic_thread_fence_rel();
846 * After inserting an invl_gen element with invalid bit set,
847 * this thread blocks any other thread trying to enter the
848 * delayed invalidation block. Do not allow to remove us from
849 * the CPU, because it causes starvation for other threads.
854 * ABA for *p is not possible there, since p->gen can only
855 * increase. So if the *p thread finished its di, then
856 * started a new one and got inserted into the list at the
857 * same place, its gen will appear greater than the previously
860 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
862 PV_STAT(atomic_add_long(&invl_start_restart, 1));
868 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
869 * invl_gen->next, allowing other threads to iterate past us.
870 * pmap_di_store_invl() provides fence between the generation
871 * write and the update of next.
873 invl_gen->next = NULL;
878 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
879 struct pmap_invl_gen *p)
881 struct pmap_invl_gen prev, new_prev;
885 * Load invl_gen->gen after setting invl_gen->next
886 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
887 * generations to propagate to our invl_gen->gen. Lock prefix
888 * in atomic_set_ptr() worked as seq_cst fence.
890 mygen = atomic_load_long(&invl_gen->gen);
892 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
895 KASSERT(prev.gen < mygen,
896 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
897 new_prev.gen = mygen;
898 new_prev.next = (void *)((uintptr_t)invl_gen->next &
899 ~PMAP_INVL_GEN_NEXT_INVALID);
901 /* Formal fence between load of prev and storing update to it. */
902 atomic_thread_fence_rel();
904 return (pmap_di_store_invl(p, &prev, &new_prev));
908 pmap_delayed_invl_finish_u(void)
910 struct pmap_invl_gen *invl_gen, *p;
912 struct lock_delay_arg lda;
916 invl_gen = &td->td_md.md_invl_gen;
917 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
918 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
919 ("missed invl_start: INVALID"));
920 lock_delay_arg_init(&lda, &di_delay);
923 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
924 prevl = (uintptr_t)atomic_load_ptr(&p->next);
925 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
926 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
930 if ((void *)prevl == invl_gen)
935 * It is legitimate to not find ourself on the list if a
936 * thread before us finished its DI and started it again.
938 if (__predict_false(p == NULL)) {
939 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
945 atomic_set_ptr((uintptr_t *)&invl_gen->next,
946 PMAP_INVL_GEN_NEXT_INVALID);
947 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
948 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
949 PMAP_INVL_GEN_NEXT_INVALID);
951 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
956 if (atomic_load_int(&pmap_invl_waiters) > 0)
957 pmap_delayed_invl_finish_unblock(0);
958 if (invl_gen->saved_pri != 0) {
960 sched_prio(td, invl_gen->saved_pri);
966 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
968 struct pmap_invl_gen *p, *pn;
973 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
975 nextl = (uintptr_t)atomic_load_ptr(&p->next);
976 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
977 td = first ? NULL : __containerof(p, struct thread,
979 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
980 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
981 td != NULL ? td->td_tid : -1);
987 static long invl_wait;
988 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
989 "Number of times DI invalidation blocked pmap_remove_all/write");
990 static long invl_wait_slow;
991 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
992 "Number of slow invalidation waits for lockless DI");
997 pmap_delayed_invl_genp(vm_page_t m)
1002 pa = VM_PAGE_TO_PHYS(m);
1003 if (__predict_false((pa) > pmap_last_pa))
1004 gen = &pv_dummy_large.pv_invl_gen;
1006 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1012 pmap_delayed_invl_genp(vm_page_t m)
1015 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1020 pmap_delayed_invl_callout_func(void *arg __unused)
1023 if (atomic_load_int(&pmap_invl_waiters) == 0)
1025 pmap_delayed_invl_finish_unblock(0);
1029 pmap_delayed_invl_callout_init(void *arg __unused)
1032 if (pmap_di_locked())
1034 callout_init(&pmap_invl_callout, 1);
1035 pmap_invl_callout_inited = true;
1037 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1038 pmap_delayed_invl_callout_init, NULL);
1041 * Ensure that all currently executing DI blocks, that need to flush
1042 * TLB for the given page m, actually flushed the TLB at the time the
1043 * function returned. If the page m has an empty PV list and we call
1044 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1045 * valid mapping for the page m in either its page table or TLB.
1047 * This function works by blocking until the global DI generation
1048 * number catches up with the generation number associated with the
1049 * given page m and its PV list. Since this function's callers
1050 * typically own an object lock and sometimes own a page lock, it
1051 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1055 pmap_delayed_invl_wait_l(vm_page_t m)
1059 bool accounted = false;
1062 m_gen = pmap_delayed_invl_genp(m);
1063 while (*m_gen > pmap_invl_gen) {
1066 atomic_add_long(&invl_wait, 1);
1070 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1075 pmap_delayed_invl_wait_u(vm_page_t m)
1078 struct lock_delay_arg lda;
1082 m_gen = pmap_delayed_invl_genp(m);
1083 lock_delay_arg_init(&lda, &di_delay);
1084 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1085 if (fast || !pmap_invl_callout_inited) {
1086 PV_STAT(atomic_add_long(&invl_wait, 1));
1091 * The page's invalidation generation number
1092 * is still below the current thread's number.
1093 * Prepare to block so that we do not waste
1094 * CPU cycles or worse, suffer livelock.
1096 * Since it is impossible to block without
1097 * racing with pmap_delayed_invl_finish_u(),
1098 * prepare for the race by incrementing
1099 * pmap_invl_waiters and arming a 1-tick
1100 * callout which will unblock us if we lose
1103 atomic_add_int(&pmap_invl_waiters, 1);
1106 * Re-check the current thread's invalidation
1107 * generation after incrementing
1108 * pmap_invl_waiters, so that there is no race
1109 * with pmap_delayed_invl_finish_u() setting
1110 * the page generation and checking
1111 * pmap_invl_waiters. The only race allowed
1112 * is for a missed unblock, which is handled
1116 atomic_load_long(&pmap_invl_gen_head.gen)) {
1117 callout_reset(&pmap_invl_callout, 1,
1118 pmap_delayed_invl_callout_func, NULL);
1119 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1120 pmap_delayed_invl_wait_block(m_gen,
1121 &pmap_invl_gen_head.gen);
1123 atomic_add_int(&pmap_invl_waiters, -1);
1128 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1131 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1132 pmap_thread_init_invl_gen_u);
1135 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1138 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1139 pmap_delayed_invl_start_u);
1142 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1145 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1146 pmap_delayed_invl_finish_u);
1149 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1152 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1153 pmap_delayed_invl_wait_u);
1157 * Mark the page m's PV list as participating in the current thread's
1158 * DI block. Any threads concurrently using m's PV list to remove or
1159 * restrict all mappings to m will wait for the current thread's DI
1160 * block to complete before proceeding.
1162 * The function works by setting the DI generation number for m's PV
1163 * list to at least the DI generation number of the current thread.
1164 * This forces a caller of pmap_delayed_invl_wait() to block until
1165 * current thread calls pmap_delayed_invl_finish().
1168 pmap_delayed_invl_page(vm_page_t m)
1172 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1173 gen = curthread->td_md.md_invl_gen.gen;
1176 m_gen = pmap_delayed_invl_genp(m);
1184 static caddr_t crashdumpmap;
1187 * Internal flags for pmap_enter()'s helper functions.
1189 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1190 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1193 * Internal flags for pmap_mapdev_internal() and
1194 * pmap_change_props_locked().
1196 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1197 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1198 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1200 TAILQ_HEAD(pv_chunklist, pv_chunk);
1202 static void free_pv_chunk(struct pv_chunk *pc);
1203 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1204 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1205 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1206 static int popcnt_pc_map_pq(uint64_t *map);
1207 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1208 static void reserve_pv_entries(pmap_t pmap, int needed,
1209 struct rwlock **lockp);
1210 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1211 struct rwlock **lockp);
1212 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1213 u_int flags, struct rwlock **lockp);
1214 #if VM_NRESERVLEVEL > 0
1215 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1216 struct rwlock **lockp);
1218 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1219 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1222 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1223 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1224 vm_prot_t prot, int mode, int flags);
1225 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1226 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1227 vm_offset_t va, struct rwlock **lockp);
1228 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1230 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1231 vm_prot_t prot, struct rwlock **lockp);
1232 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1233 u_int flags, vm_page_t m, struct rwlock **lockp);
1234 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1235 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1236 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1237 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1238 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1240 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1242 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1244 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1245 static vm_page_t pmap_large_map_getptp_unlocked(void);
1246 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1247 #if VM_NRESERVLEVEL > 0
1248 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1249 struct rwlock **lockp);
1251 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1253 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1254 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1256 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1257 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1258 static void pmap_pti_wire_pte(void *pte);
1259 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1260 struct spglist *free, struct rwlock **lockp);
1261 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1262 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1263 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1264 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1265 struct spglist *free);
1266 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1267 pd_entry_t *pde, struct spglist *free,
1268 struct rwlock **lockp);
1269 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1270 vm_page_t m, struct rwlock **lockp);
1271 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1273 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1275 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1276 struct rwlock **lockp, vm_offset_t va);
1277 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1278 struct rwlock **lockp);
1279 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1280 struct rwlock **lockp);
1282 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1283 struct spglist *free);
1284 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1286 /********************/
1287 /* Inline functions */
1288 /********************/
1291 * Return a non-clipped indexes for a given VA, which are page table
1292 * pages indexes at the corresponding level.
1294 static __inline vm_pindex_t
1295 pmap_pde_pindex(vm_offset_t va)
1297 return (va >> PDRSHIFT);
1300 static __inline vm_pindex_t
1301 pmap_pdpe_pindex(vm_offset_t va)
1303 return (NUPDE + (va >> PDPSHIFT));
1306 static __inline vm_pindex_t
1307 pmap_pml4e_pindex(vm_offset_t va)
1309 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1312 static __inline vm_pindex_t
1313 pmap_pml5e_pindex(vm_offset_t va)
1315 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1318 static __inline pml4_entry_t *
1319 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1322 MPASS(pmap_is_la57(pmap));
1323 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1326 static __inline pml4_entry_t *
1327 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1330 MPASS(pmap_is_la57(pmap));
1331 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1334 static __inline pml4_entry_t *
1335 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1337 pml4_entry_t *pml4e;
1339 /* XXX MPASS(pmap_is_la57(pmap); */
1340 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1341 return (&pml4e[pmap_pml4e_index(va)]);
1344 /* Return a pointer to the PML4 slot that corresponds to a VA */
1345 static __inline pml4_entry_t *
1346 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1348 pml5_entry_t *pml5e;
1349 pml4_entry_t *pml4e;
1352 if (pmap_is_la57(pmap)) {
1353 pml5e = pmap_pml5e(pmap, va);
1354 PG_V = pmap_valid_bit(pmap);
1355 if ((*pml5e & PG_V) == 0)
1357 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1359 pml4e = pmap->pm_pmltop;
1361 return (&pml4e[pmap_pml4e_index(va)]);
1364 static __inline pml4_entry_t *
1365 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1367 MPASS(!pmap_is_la57(pmap));
1368 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1371 /* Return a pointer to the PDP slot that corresponds to a VA */
1372 static __inline pdp_entry_t *
1373 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1377 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1378 return (&pdpe[pmap_pdpe_index(va)]);
1381 /* Return a pointer to the PDP slot that corresponds to a VA */
1382 static __inline pdp_entry_t *
1383 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1385 pml4_entry_t *pml4e;
1388 PG_V = pmap_valid_bit(pmap);
1389 pml4e = pmap_pml4e(pmap, va);
1390 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1392 return (pmap_pml4e_to_pdpe(pml4e, va));
1395 /* Return a pointer to the PD slot that corresponds to a VA */
1396 static __inline pd_entry_t *
1397 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1401 KASSERT((*pdpe & PG_PS) == 0,
1402 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1403 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1404 return (&pde[pmap_pde_index(va)]);
1407 /* Return a pointer to the PD slot that corresponds to a VA */
1408 static __inline pd_entry_t *
1409 pmap_pde(pmap_t pmap, vm_offset_t va)
1414 PG_V = pmap_valid_bit(pmap);
1415 pdpe = pmap_pdpe(pmap, va);
1416 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1418 return (pmap_pdpe_to_pde(pdpe, va));
1421 /* Return a pointer to the PT slot that corresponds to a VA */
1422 static __inline pt_entry_t *
1423 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1427 KASSERT((*pde & PG_PS) == 0,
1428 ("%s: pde %#lx is a leaf", __func__, *pde));
1429 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1430 return (&pte[pmap_pte_index(va)]);
1433 /* Return a pointer to the PT slot that corresponds to a VA */
1434 static __inline pt_entry_t *
1435 pmap_pte(pmap_t pmap, vm_offset_t va)
1440 PG_V = pmap_valid_bit(pmap);
1441 pde = pmap_pde(pmap, va);
1442 if (pde == NULL || (*pde & PG_V) == 0)
1444 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1445 return ((pt_entry_t *)pde);
1446 return (pmap_pde_to_pte(pde, va));
1449 static __inline void
1450 pmap_resident_count_inc(pmap_t pmap, int count)
1453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1454 pmap->pm_stats.resident_count += count;
1457 static __inline void
1458 pmap_resident_count_dec(pmap_t pmap, int count)
1461 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1462 KASSERT(pmap->pm_stats.resident_count >= count,
1463 ("pmap %p resident count underflow %ld %d", pmap,
1464 pmap->pm_stats.resident_count, count));
1465 pmap->pm_stats.resident_count -= count;
1468 PMAP_INLINE pt_entry_t *
1469 vtopte(vm_offset_t va)
1473 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1476 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1477 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1478 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1480 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1481 NPML4EPGSHIFT)) - 1);
1482 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1486 static __inline pd_entry_t *
1487 vtopde(vm_offset_t va)
1491 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1494 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1495 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1496 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1498 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1499 NPML4EPGSHIFT)) - 1);
1500 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1505 allocpages(vm_paddr_t *firstaddr, int n)
1510 bzero((void *)ret, n * PAGE_SIZE);
1511 *firstaddr += n * PAGE_SIZE;
1515 CTASSERT(powerof2(NDMPML4E));
1517 /* number of kernel PDP slots */
1518 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1521 nkpt_init(vm_paddr_t addr)
1528 pt_pages = howmany(addr, 1 << PDRSHIFT);
1529 pt_pages += NKPDPE(pt_pages);
1532 * Add some slop beyond the bare minimum required for bootstrapping
1535 * This is quite important when allocating KVA for kernel modules.
1536 * The modules are required to be linked in the negative 2GB of
1537 * the address space. If we run out of KVA in this region then
1538 * pmap_growkernel() will need to allocate page table pages to map
1539 * the entire 512GB of KVA space which is an unnecessary tax on
1542 * Secondly, device memory mapped as part of setting up the low-
1543 * level console(s) is taken from KVA, starting at virtual_avail.
1544 * This is because cninit() is called after pmap_bootstrap() but
1545 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1548 pt_pages += 32; /* 64MB additional slop. */
1554 * Returns the proper write/execute permission for a physical page that is
1555 * part of the initial boot allocations.
1557 * If the page has kernel text, it is marked as read-only. If the page has
1558 * kernel read-only data, it is marked as read-only/not-executable. If the
1559 * page has only read-write data, it is marked as read-write/not-executable.
1560 * If the page is below/above the kernel range, it is marked as read-write.
1562 * This function operates on 2M pages, since we map the kernel space that
1565 static inline pt_entry_t
1566 bootaddr_rwx(vm_paddr_t pa)
1570 * The kernel is loaded at a 2MB-aligned address, and memory below that
1571 * need not be executable. The .bss section is padded to a 2MB
1572 * boundary, so memory following the kernel need not be executable
1573 * either. Preloaded kernel modules have their mapping permissions
1574 * fixed up by the linker.
1576 if (pa < trunc_2mpage(btext - KERNBASE) ||
1577 pa >= trunc_2mpage(_end - KERNBASE))
1578 return (X86_PG_RW | pg_nx);
1581 * The linker should ensure that the read-only and read-write
1582 * portions don't share the same 2M page, so this shouldn't
1583 * impact read-only data. However, in any case, any page with
1584 * read-write data needs to be read-write.
1586 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1587 return (X86_PG_RW | pg_nx);
1590 * Mark any 2M page containing kernel text as read-only. Mark
1591 * other pages with read-only data as read-only and not executable.
1592 * (It is likely a small portion of the read-only data section will
1593 * be marked as read-only, but executable. This should be acceptable
1594 * since the read-only protection will keep the data from changing.)
1595 * Note that fixups to the .text section will still work until we
1598 if (pa < round_2mpage(etext - KERNBASE))
1604 create_pagetables(vm_paddr_t *firstaddr)
1606 int i, j, ndm1g, nkpdpe, nkdmpde;
1610 uint64_t DMPDkernphys;
1612 /* Allocate page table pages for the direct map */
1613 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1614 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1616 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1617 if (ndmpdpphys > NDMPML4E) {
1619 * Each NDMPML4E allows 512 GB, so limit to that,
1620 * and then readjust ndmpdp and ndmpdpphys.
1622 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1623 Maxmem = atop(NDMPML4E * NBPML4);
1624 ndmpdpphys = NDMPML4E;
1625 ndmpdp = NDMPML4E * NPDEPG;
1627 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1629 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1631 * Calculate the number of 1G pages that will fully fit in
1634 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1637 * Allocate 2M pages for the kernel. These will be used in
1638 * place of the first one or more 1G pages from ndm1g.
1640 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1641 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1644 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1645 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1647 /* Allocate pages */
1648 KPML4phys = allocpages(firstaddr, 1);
1649 KPDPphys = allocpages(firstaddr, NKPML4E);
1652 * Allocate the initial number of kernel page table pages required to
1653 * bootstrap. We defer this until after all memory-size dependent
1654 * allocations are done (e.g. direct map), so that we don't have to
1655 * build in too much slop in our estimate.
1657 * Note that when NKPML4E > 1, we have an empty page underneath
1658 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1659 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1661 nkpt_init(*firstaddr);
1662 nkpdpe = NKPDPE(nkpt);
1664 KPTphys = allocpages(firstaddr, nkpt);
1665 KPDphys = allocpages(firstaddr, nkpdpe);
1668 * Connect the zero-filled PT pages to their PD entries. This
1669 * implicitly maps the PT pages at their correct locations within
1672 pd_p = (pd_entry_t *)KPDphys;
1673 for (i = 0; i < nkpt; i++)
1674 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1677 * Map from physical address zero to the end of loader preallocated
1678 * memory using 2MB pages. This replaces some of the PD entries
1681 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1682 /* Preset PG_M and PG_A because demotion expects it. */
1683 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1684 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1687 * Because we map the physical blocks in 2M pages, adjust firstaddr
1688 * to record the physical blocks we've actually mapped into kernel
1689 * virtual address space.
1691 if (*firstaddr < round_2mpage(KERNend))
1692 *firstaddr = round_2mpage(KERNend);
1694 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1695 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1696 for (i = 0; i < nkpdpe; i++)
1697 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1700 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1701 * the end of physical memory is not aligned to a 1GB page boundary,
1702 * then the residual physical memory is mapped with 2MB pages. Later,
1703 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1704 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1705 * that are partially used.
1707 pd_p = (pd_entry_t *)DMPDphys;
1708 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1709 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1710 /* Preset PG_M and PG_A because demotion expects it. */
1711 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1712 X86_PG_M | X86_PG_A | pg_nx;
1714 pdp_p = (pdp_entry_t *)DMPDPphys;
1715 for (i = 0; i < ndm1g; i++) {
1716 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1717 /* Preset PG_M and PG_A because demotion expects it. */
1718 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1719 X86_PG_M | X86_PG_A | pg_nx;
1721 for (j = 0; i < ndmpdp; i++, j++) {
1722 pdp_p[i] = DMPDphys + ptoa(j);
1723 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1727 * Instead of using a 1G page for the memory containing the kernel,
1728 * use 2M pages with read-only and no-execute permissions. (If using 1G
1729 * pages, this will partially overwrite the PDPEs above.)
1732 pd_p = (pd_entry_t *)DMPDkernphys;
1733 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1734 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1735 X86_PG_M | X86_PG_A | pg_nx |
1736 bootaddr_rwx(i << PDRSHIFT);
1737 for (i = 0; i < nkdmpde; i++)
1738 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1742 /* And recursively map PML4 to itself in order to get PTmap */
1743 p4_p = (pml4_entry_t *)KPML4phys;
1744 p4_p[PML4PML4I] = KPML4phys;
1745 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1747 /* Connect the Direct Map slot(s) up to the PML4. */
1748 for (i = 0; i < ndmpdpphys; i++) {
1749 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1750 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1753 /* Connect the KVA slots up to the PML4 */
1754 for (i = 0; i < NKPML4E; i++) {
1755 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1756 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1759 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1763 * Bootstrap the system enough to run with virtual memory.
1765 * On amd64 this is called after mapping has already been enabled
1766 * and just syncs the pmap module with what has already been done.
1767 * [We can't call it easily with mapping off since the kernel is not
1768 * mapped with PA == VA, hence we would have to relocate every address
1769 * from the linked base (virtual) address "KERNBASE" to the actual
1770 * (physical) address starting relative to 0]
1773 pmap_bootstrap(vm_paddr_t *firstaddr)
1776 pt_entry_t *pte, *pcpu_pte;
1777 struct region_descriptor r_gdt;
1778 uint64_t cr4, pcpu_phys;
1782 KERNend = *firstaddr;
1783 res = atop(KERNend - (vm_paddr_t)kernphys);
1789 * Create an initial set of page tables to run the kernel in.
1791 create_pagetables(firstaddr);
1793 pcpu_phys = allocpages(firstaddr, MAXCPU);
1796 * Add a physical memory segment (vm_phys_seg) corresponding to the
1797 * preallocated kernel page table pages so that vm_page structures
1798 * representing these pages will be created. The vm_page structures
1799 * are required for promotion of the corresponding kernel virtual
1800 * addresses to superpage mappings.
1802 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1805 * Account for the virtual addresses mapped by create_pagetables().
1807 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1808 virtual_end = VM_MAX_KERNEL_ADDRESS;
1811 * Enable PG_G global pages, then switch to the kernel page
1812 * table from the bootstrap page table. After the switch, it
1813 * is possible to enable SMEP and SMAP since PG_U bits are
1819 load_cr3(KPML4phys);
1820 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1822 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1827 * Initialize the kernel pmap (which is statically allocated).
1828 * Count bootstrap data as being resident in case any of this data is
1829 * later unmapped (using pmap_remove()) and freed.
1831 PMAP_LOCK_INIT(kernel_pmap);
1832 kernel_pmap->pm_pmltop = kernel_pml4;
1833 kernel_pmap->pm_cr3 = KPML4phys;
1834 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1835 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1836 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1837 kernel_pmap->pm_stats.resident_count = res;
1838 kernel_pmap->pm_flags = pmap_flags;
1841 * Initialize the TLB invalidations generation number lock.
1843 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1846 * Reserve some special page table entries/VA space for temporary
1849 #define SYSMAP(c, p, v, n) \
1850 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1856 * Crashdump maps. The first page is reused as CMAP1 for the
1859 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1860 CADDR1 = crashdumpmap;
1862 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1865 for (i = 0; i < MAXCPU; i++) {
1866 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1867 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1871 * Re-initialize PCPU area for BSP after switching.
1872 * Make hardware use gdt and common_tss from the new PCPU.
1874 STAILQ_INIT(&cpuhead);
1875 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1876 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1877 amd64_bsp_pcpu_init1(&__pcpu[0]);
1878 amd64_bsp_ist_init(&__pcpu[0]);
1879 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1881 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1882 sizeof(struct user_segment_descriptor));
1883 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1884 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1885 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1886 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1887 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1889 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1890 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1891 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1892 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1895 * Initialize the PAT MSR.
1896 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1897 * side-effect, invalidates stale PG_G TLB entries that might
1898 * have been created in our pre-boot environment.
1902 /* Initialize TLB Context Id. */
1903 if (pmap_pcid_enabled) {
1904 for (i = 0; i < MAXCPU; i++) {
1905 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1906 kernel_pmap->pm_pcids[i].pm_gen = 1;
1910 * PMAP_PCID_KERN + 1 is used for initialization of
1911 * proc0 pmap. The pmap' pcid state might be used by
1912 * EFIRT entry before first context switch, so it
1913 * needs to be valid.
1915 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1916 PCPU_SET(pcid_gen, 1);
1919 * pcpu area for APs is zeroed during AP startup.
1920 * pc_pcid_next and pc_pcid_gen are initialized by AP
1921 * during pcpu setup.
1923 load_cr4(rcr4() | CR4_PCIDE);
1928 * Setup the PAT MSR.
1937 /* Bail if this CPU doesn't implement PAT. */
1938 if ((cpu_feature & CPUID_PAT) == 0)
1941 /* Set default PAT index table. */
1942 for (i = 0; i < PAT_INDEX_SIZE; i++)
1944 pat_index[PAT_WRITE_BACK] = 0;
1945 pat_index[PAT_WRITE_THROUGH] = 1;
1946 pat_index[PAT_UNCACHEABLE] = 3;
1947 pat_index[PAT_WRITE_COMBINING] = 6;
1948 pat_index[PAT_WRITE_PROTECTED] = 5;
1949 pat_index[PAT_UNCACHED] = 2;
1952 * Initialize default PAT entries.
1953 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1954 * Program 5 and 6 as WP and WC.
1956 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1957 * mapping for a 2M page uses a PAT value with the bit 3 set due
1958 * to its overload with PG_PS.
1960 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1961 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1962 PAT_VALUE(2, PAT_UNCACHED) |
1963 PAT_VALUE(3, PAT_UNCACHEABLE) |
1964 PAT_VALUE(4, PAT_WRITE_BACK) |
1965 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1966 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1967 PAT_VALUE(7, PAT_UNCACHEABLE);
1971 load_cr4(cr4 & ~CR4_PGE);
1973 /* Disable caches (CD = 1, NW = 0). */
1975 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1977 /* Flushes caches and TLBs. */
1981 /* Update PAT and index table. */
1982 wrmsr(MSR_PAT, pat_msr);
1984 /* Flush caches and TLBs again. */
1988 /* Restore caches and PGE. */
1993 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1994 la57_trampoline_gdt[], la57_trampoline_end[];
1997 pmap_bootstrap_la57(void *arg __unused)
2000 pml5_entry_t *v_pml5;
2001 pml4_entry_t *v_pml4;
2005 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2006 void (*la57_tramp)(uint64_t pml5);
2007 struct region_descriptor r_gdt;
2009 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2011 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2016 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2017 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2019 m_code = vm_page_alloc_contig(NULL, 0,
2020 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2021 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2022 if ((m_code->flags & PG_ZERO) == 0)
2023 pmap_zero_page(m_code);
2024 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2025 m_pml5 = vm_page_alloc_contig(NULL, 0,
2026 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2027 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2028 if ((m_pml5->flags & PG_ZERO) == 0)
2029 pmap_zero_page(m_pml5);
2030 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2031 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2032 m_pml4 = vm_page_alloc_contig(NULL, 0,
2033 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2034 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2035 if ((m_pml4->flags & PG_ZERO) == 0)
2036 pmap_zero_page(m_pml4);
2037 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2038 m_pdp = vm_page_alloc_contig(NULL, 0,
2039 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2040 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2041 if ((m_pdp->flags & PG_ZERO) == 0)
2042 pmap_zero_page(m_pdp);
2043 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2044 m_pd = vm_page_alloc_contig(NULL, 0,
2045 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2046 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2047 if ((m_pd->flags & PG_ZERO) == 0)
2048 pmap_zero_page(m_pd);
2049 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2050 m_pt = vm_page_alloc_contig(NULL, 0,
2051 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2052 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2053 if ((m_pt->flags & PG_ZERO) == 0)
2054 pmap_zero_page(m_pt);
2055 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2058 * Map m_code 1:1, it appears below 4G in KVA due to physical
2059 * address being below 4G. Since kernel KVA is in upper half,
2060 * the pml4e should be zero and free for temporary use.
2062 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2063 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2065 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2066 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2068 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2069 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2071 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2072 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2076 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2077 * entering all existing kernel mappings into level 5 table.
2079 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2080 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2083 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2085 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2086 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2088 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2089 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2093 * Copy and call the 48->57 trampoline, hope we return there, alive.
2095 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2096 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2097 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2098 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2099 la57_tramp(KPML5phys);
2102 * gdt was necessary reset, switch back to our gdt.
2105 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2109 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2110 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2111 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2114 * Now unmap the trampoline, and free the pages.
2115 * Clear pml5 entry used for 1:1 trampoline mapping.
2117 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2118 invlpg((vm_offset_t)v_code);
2119 vm_page_free(m_code);
2120 vm_page_free(m_pdp);
2125 * Recursively map PML5 to itself in order to get PTmap and
2128 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2130 kernel_pmap->pm_cr3 = KPML5phys;
2131 kernel_pmap->pm_pmltop = v_pml5;
2133 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2136 * Initialize a vm_page's machine-dependent fields.
2139 pmap_page_init(vm_page_t m)
2142 TAILQ_INIT(&m->md.pv_list);
2143 m->md.pat_mode = PAT_WRITE_BACK;
2146 static int pmap_allow_2m_x_ept;
2147 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2148 &pmap_allow_2m_x_ept, 0,
2149 "Allow executable superpage mappings in EPT");
2152 pmap_allow_2m_x_ept_recalculate(void)
2155 * SKL002, SKL012S. Since the EPT format is only used by
2156 * Intel CPUs, the vendor check is merely a formality.
2158 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2159 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2160 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2161 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2162 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2163 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2164 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2165 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2166 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2167 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2168 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2169 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2170 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2171 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2172 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2173 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2174 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2175 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2176 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2177 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2178 CPUID_TO_MODEL(cpu_id) == 0x85))))
2179 pmap_allow_2m_x_ept = 1;
2180 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2184 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2187 return (pmap->pm_type != PT_EPT || !executable ||
2188 !pmap_allow_2m_x_ept);
2193 pmap_init_pv_table(void)
2195 struct pmap_large_md_page *pvd;
2197 long start, end, highest, pv_npg;
2198 int domain, i, j, pages;
2201 * We strongly depend on the size being a power of two, so the assert
2202 * is overzealous. However, should the struct be resized to a
2203 * different power of two, the code below needs to be revisited.
2205 CTASSERT((sizeof(*pvd) == 64));
2208 * Calculate the size of the array.
2210 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2211 pv_npg = howmany(pmap_last_pa, NBPDR);
2212 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2214 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2215 if (pv_table == NULL)
2216 panic("%s: kva_alloc failed\n", __func__);
2219 * Iterate physical segments to allocate space for respective pages.
2223 for (i = 0; i < vm_phys_nsegs; i++) {
2224 end = vm_phys_segs[i].end / NBPDR;
2225 domain = vm_phys_segs[i].domain;
2230 start = highest + 1;
2231 pvd = &pv_table[start];
2233 pages = end - start + 1;
2234 s = round_page(pages * sizeof(*pvd));
2235 highest = start + (s / sizeof(*pvd)) - 1;
2237 for (j = 0; j < s; j += PAGE_SIZE) {
2238 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2239 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2241 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2242 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2245 for (j = 0; j < s / sizeof(*pvd); j++) {
2246 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2247 TAILQ_INIT(&pvd->pv_page.pv_list);
2248 pvd->pv_page.pv_gen = 0;
2249 pvd->pv_page.pat_mode = 0;
2250 pvd->pv_invl_gen = 0;
2254 pvd = &pv_dummy_large;
2255 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2256 TAILQ_INIT(&pvd->pv_page.pv_list);
2257 pvd->pv_page.pv_gen = 0;
2258 pvd->pv_page.pat_mode = 0;
2259 pvd->pv_invl_gen = 0;
2263 pmap_init_pv_table(void)
2269 * Initialize the pool of pv list locks.
2271 for (i = 0; i < NPV_LIST_LOCKS; i++)
2272 rw_init(&pv_list_locks[i], "pmap pv list");
2275 * Calculate the size of the pv head table for superpages.
2277 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2280 * Allocate memory for the pv head table for superpages.
2282 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2284 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2285 for (i = 0; i < pv_npg; i++)
2286 TAILQ_INIT(&pv_table[i].pv_list);
2287 TAILQ_INIT(&pv_dummy.pv_list);
2292 * Initialize the pmap module.
2293 * Called by vm_init, to initialize any structures that the pmap
2294 * system needs to map virtual memory.
2299 struct pmap_preinit_mapping *ppim;
2301 int error, i, ret, skz63;
2303 /* L1TF, reserve page @0 unconditionally */
2304 vm_page_blacklist_add(0, bootverbose);
2306 /* Detect bare-metal Skylake Server and Skylake-X. */
2307 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2308 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2310 * Skylake-X errata SKZ63. Processor May Hang When
2311 * Executing Code In an HLE Transaction Region between
2312 * 40000000H and 403FFFFFH.
2314 * Mark the pages in the range as preallocated. It
2315 * seems to be impossible to distinguish between
2316 * Skylake Server and Skylake X.
2319 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2322 printf("SKZ63: skipping 4M RAM starting "
2323 "at physical 1G\n");
2324 for (i = 0; i < atop(0x400000); i++) {
2325 ret = vm_page_blacklist_add(0x40000000 +
2327 if (!ret && bootverbose)
2328 printf("page at %#lx already used\n",
2329 0x40000000 + ptoa(i));
2335 pmap_allow_2m_x_ept_recalculate();
2338 * Initialize the vm page array entries for the kernel pmap's
2341 PMAP_LOCK(kernel_pmap);
2342 for (i = 0; i < nkpt; i++) {
2343 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2344 KASSERT(mpte >= vm_page_array &&
2345 mpte < &vm_page_array[vm_page_array_size],
2346 ("pmap_init: page table page is out of range"));
2347 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2348 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2349 mpte->ref_count = 1;
2352 * Collect the page table pages that were replaced by a 2MB
2353 * page in create_pagetables(). They are zero filled.
2355 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2356 pmap_insert_pt_page(kernel_pmap, mpte, false))
2357 panic("pmap_init: pmap_insert_pt_page failed");
2359 PMAP_UNLOCK(kernel_pmap);
2363 * If the kernel is running on a virtual machine, then it must assume
2364 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2365 * be prepared for the hypervisor changing the vendor and family that
2366 * are reported by CPUID. Consequently, the workaround for AMD Family
2367 * 10h Erratum 383 is enabled if the processor's feature set does not
2368 * include at least one feature that is only supported by older Intel
2369 * or newer AMD processors.
2371 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2372 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2373 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2375 workaround_erratum383 = 1;
2378 * Are large page mappings enabled?
2380 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2381 if (pg_ps_enabled) {
2382 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2383 ("pmap_init: can't assign to pagesizes[1]"));
2384 pagesizes[1] = NBPDR;
2388 * Initialize pv chunk lists.
2390 for (i = 0; i < PMAP_MEMDOM; i++) {
2391 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2392 TAILQ_INIT(&pv_chunks[i].pvc_list);
2394 pmap_init_pv_table();
2396 pmap_initialized = 1;
2397 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2398 ppim = pmap_preinit_mapping + i;
2401 /* Make the direct map consistent */
2402 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2403 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2404 ppim->sz, ppim->mode);
2408 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2409 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2412 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2413 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2414 (vmem_addr_t *)&qframe);
2416 panic("qframe allocation failed");
2419 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2420 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2421 lm_ents = LMEPML4I - LMSPML4I + 1;
2423 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2424 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2426 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2427 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2428 if (large_vmem == NULL) {
2429 printf("pmap: cannot create large map\n");
2432 for (i = 0; i < lm_ents; i++) {
2433 m = pmap_large_map_getptp_unlocked();
2435 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2436 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2442 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2443 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2444 "Maximum number of PML4 entries for use by large map (tunable). "
2445 "Each entry corresponds to 512GB of address space.");
2447 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2448 "2MB page mapping counters");
2450 static u_long pmap_pde_demotions;
2451 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2452 &pmap_pde_demotions, 0, "2MB page demotions");
2454 static u_long pmap_pde_mappings;
2455 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2456 &pmap_pde_mappings, 0, "2MB page mappings");
2458 static u_long pmap_pde_p_failures;
2459 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2460 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2462 static u_long pmap_pde_promotions;
2463 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2464 &pmap_pde_promotions, 0, "2MB page promotions");
2466 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2467 "1GB page mapping counters");
2469 static u_long pmap_pdpe_demotions;
2470 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2471 &pmap_pdpe_demotions, 0, "1GB page demotions");
2473 /***************************************************
2474 * Low level helper routines.....
2475 ***************************************************/
2478 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2480 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2482 switch (pmap->pm_type) {
2485 /* Verify that both PAT bits are not set at the same time */
2486 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2487 ("Invalid PAT bits in entry %#lx", entry));
2489 /* Swap the PAT bits if one of them is set */
2490 if ((entry & x86_pat_bits) != 0)
2491 entry ^= x86_pat_bits;
2495 * Nothing to do - the memory attributes are represented
2496 * the same way for regular pages and superpages.
2500 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2507 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2510 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2511 pat_index[(int)mode] >= 0);
2515 * Determine the appropriate bits to set in a PTE or PDE for a specified
2519 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2521 int cache_bits, pat_flag, pat_idx;
2523 if (!pmap_is_valid_memattr(pmap, mode))
2524 panic("Unknown caching mode %d\n", mode);
2526 switch (pmap->pm_type) {
2529 /* The PAT bit is different for PTE's and PDE's. */
2530 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2532 /* Map the caching mode to a PAT index. */
2533 pat_idx = pat_index[mode];
2535 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2538 cache_bits |= pat_flag;
2540 cache_bits |= PG_NC_PCD;
2542 cache_bits |= PG_NC_PWT;
2546 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2550 panic("unsupported pmap type %d", pmap->pm_type);
2553 return (cache_bits);
2557 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2561 switch (pmap->pm_type) {
2564 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2567 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2570 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2577 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2579 int pat_flag, pat_idx;
2582 switch (pmap->pm_type) {
2585 /* The PAT bit is different for PTE's and PDE's. */
2586 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2588 if ((pte & pat_flag) != 0)
2590 if ((pte & PG_NC_PCD) != 0)
2592 if ((pte & PG_NC_PWT) != 0)
2596 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2597 panic("EPT PTE %#lx has no PAT memory type", pte);
2598 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2602 /* See pmap_init_pat(). */
2612 pmap_ps_enabled(pmap_t pmap)
2615 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2619 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2622 switch (pmap->pm_type) {
2629 * This is a little bogus since the generation number is
2630 * supposed to be bumped up when a region of the address
2631 * space is invalidated in the page tables.
2633 * In this case the old PDE entry is valid but yet we want
2634 * to make sure that any mappings using the old entry are
2635 * invalidated in the TLB.
2637 * The reason this works as expected is because we rendezvous
2638 * "all" host cpus and force any vcpu context to exit as a
2641 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2644 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2646 pde_store(pde, newpde);
2650 * After changing the page size for the specified virtual address in the page
2651 * table, flush the corresponding entries from the processor's TLB. Only the
2652 * calling processor's TLB is affected.
2654 * The calling thread must be pinned to a processor.
2657 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2661 if (pmap_type_guest(pmap))
2664 KASSERT(pmap->pm_type == PT_X86,
2665 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2667 PG_G = pmap_global_bit(pmap);
2669 if ((newpde & PG_PS) == 0)
2670 /* Demotion: flush a specific 2MB page mapping. */
2672 else if ((newpde & PG_G) == 0)
2674 * Promotion: flush every 4KB page mapping from the TLB
2675 * because there are too many to flush individually.
2680 * Promotion: flush every 4KB page mapping from the TLB,
2681 * including any global (PG_G) mappings.
2689 * For SMP, these functions have to use the IPI mechanism for coherence.
2691 * N.B.: Before calling any of the following TLB invalidation functions,
2692 * the calling processor must ensure that all stores updating a non-
2693 * kernel page table are globally performed. Otherwise, another
2694 * processor could cache an old, pre-update entry without being
2695 * invalidated. This can happen one of two ways: (1) The pmap becomes
2696 * active on another processor after its pm_active field is checked by
2697 * one of the following functions but before a store updating the page
2698 * table is globally performed. (2) The pmap becomes active on another
2699 * processor before its pm_active field is checked but due to
2700 * speculative loads one of the following functions stills reads the
2701 * pmap as inactive on the other processor.
2703 * The kernel page table is exempt because its pm_active field is
2704 * immutable. The kernel page table is always active on every
2709 * Interrupt the cpus that are executing in the guest context.
2710 * This will force the vcpu to exit and the cached EPT mappings
2711 * will be invalidated by the host before the next vmresume.
2713 static __inline void
2714 pmap_invalidate_ept(pmap_t pmap)
2719 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2720 ("pmap_invalidate_ept: absurd pm_active"));
2723 * The TLB mappings associated with a vcpu context are not
2724 * flushed each time a different vcpu is chosen to execute.
2726 * This is in contrast with a process's vtop mappings that
2727 * are flushed from the TLB on each context switch.
2729 * Therefore we need to do more than just a TLB shootdown on
2730 * the active cpus in 'pmap->pm_active'. To do this we keep
2731 * track of the number of invalidations performed on this pmap.
2733 * Each vcpu keeps a cache of this counter and compares it
2734 * just before a vmresume. If the counter is out-of-date an
2735 * invept will be done to flush stale mappings from the TLB.
2737 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2740 * Force the vcpu to exit and trap back into the hypervisor.
2742 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2743 ipi_selected(pmap->pm_active, ipinum);
2748 pmap_invalidate_cpu_mask(pmap_t pmap)
2751 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2755 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2756 const bool invpcid_works1)
2758 struct invpcid_descr d;
2759 uint64_t kcr3, ucr3;
2763 cpuid = PCPU_GET(cpuid);
2764 if (pmap == PCPU_GET(curpmap)) {
2765 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2767 * If we context-switched right after
2768 * PCPU_GET(ucr3_load_mask), we could read the
2769 * ~CR3_PCID_SAVE mask, which causes us to skip
2770 * the code below to invalidate user pages. This
2771 * is handled in pmap_activate_sw_pcid_pti() by
2772 * clearing pm_gen if ucr3_load_mask is ~CR3_PCID_SAVE.
2774 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2776 * Because pm_pcid is recalculated on a
2777 * context switch, we must disable switching.
2778 * Otherwise, we might use a stale value
2782 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2783 if (invpcid_works1) {
2784 d.pcid = pcid | PMAP_PCID_USER_PT;
2787 invpcid(&d, INVPCID_ADDR);
2789 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2790 ucr3 = pmap->pm_ucr3 | pcid |
2791 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2792 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2797 pmap->pm_pcids[cpuid].pm_gen = 0;
2801 pmap->pm_pcids[i].pm_gen = 0;
2805 * The fence is between stores to pm_gen and the read of the
2806 * pm_active mask. We need to ensure that it is impossible
2807 * for us to miss the bit update in pm_active and
2808 * simultaneously observe a non-zero pm_gen in
2809 * pmap_activate_sw(), otherwise TLB update is missed.
2810 * Without the fence, IA32 allows such an outcome. Note that
2811 * pm_active is updated by a locked operation, which provides
2812 * the reciprocal fence.
2814 atomic_thread_fence_seq_cst();
2818 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2821 pmap_invalidate_page_pcid(pmap, va, true);
2825 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2828 pmap_invalidate_page_pcid(pmap, va, false);
2832 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2836 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2839 if (pmap_pcid_enabled)
2840 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2841 pmap_invalidate_page_pcid_noinvpcid);
2842 return (pmap_invalidate_page_nopcid);
2846 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2847 vm_offset_t addr2 __unused)
2850 if (pmap == kernel_pmap) {
2853 if (pmap == PCPU_GET(curpmap))
2855 pmap_invalidate_page_mode(pmap, va);
2860 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2863 if (pmap_type_guest(pmap)) {
2864 pmap_invalidate_ept(pmap);
2868 KASSERT(pmap->pm_type == PT_X86,
2869 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2871 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2872 pmap_invalidate_page_curcpu_cb);
2875 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2876 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2879 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2880 const bool invpcid_works1)
2882 struct invpcid_descr d;
2883 uint64_t kcr3, ucr3;
2887 cpuid = PCPU_GET(cpuid);
2888 if (pmap == PCPU_GET(curpmap)) {
2889 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2890 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2892 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2893 if (invpcid_works1) {
2894 d.pcid = pcid | PMAP_PCID_USER_PT;
2897 for (; d.addr < eva; d.addr += PAGE_SIZE)
2898 invpcid(&d, INVPCID_ADDR);
2900 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2901 ucr3 = pmap->pm_ucr3 | pcid |
2902 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2903 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2908 pmap->pm_pcids[cpuid].pm_gen = 0;
2912 pmap->pm_pcids[i].pm_gen = 0;
2914 /* See the comment in pmap_invalidate_page_pcid(). */
2915 atomic_thread_fence_seq_cst();
2919 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2923 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2927 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2931 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2935 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2939 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2943 if (pmap_pcid_enabled)
2944 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2945 pmap_invalidate_range_pcid_noinvpcid);
2946 return (pmap_invalidate_range_nopcid);
2950 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2954 if (pmap == kernel_pmap) {
2955 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2958 if (pmap == PCPU_GET(curpmap)) {
2959 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2962 pmap_invalidate_range_mode(pmap, sva, eva);
2967 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2970 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2971 pmap_invalidate_all(pmap);
2975 if (pmap_type_guest(pmap)) {
2976 pmap_invalidate_ept(pmap);
2980 KASSERT(pmap->pm_type == PT_X86,
2981 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2983 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
2984 pmap_invalidate_range_curcpu_cb);
2988 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2990 struct invpcid_descr d;
2995 if (pmap == kernel_pmap) {
2996 if (invpcid_works1) {
2997 bzero(&d, sizeof(d));
2998 invpcid(&d, INVPCID_CTXGLOB);
3003 cpuid = PCPU_GET(cpuid);
3004 if (pmap == PCPU_GET(curpmap)) {
3006 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3007 if (invpcid_works1) {
3011 invpcid(&d, INVPCID_CTX);
3013 kcr3 = pmap->pm_cr3 | pcid;
3016 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3017 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3020 pmap->pm_pcids[cpuid].pm_gen = 0;
3023 pmap->pm_pcids[i].pm_gen = 0;
3026 /* See the comment in pmap_invalidate_page_pcid(). */
3027 atomic_thread_fence_seq_cst();
3031 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
3034 pmap_invalidate_all_pcid(pmap, true);
3038 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
3041 pmap_invalidate_all_pcid(pmap, false);
3045 pmap_invalidate_all_nopcid(pmap_t pmap)
3048 if (pmap == kernel_pmap)
3050 else if (pmap == PCPU_GET(curpmap))
3054 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
3057 if (pmap_pcid_enabled)
3058 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
3059 pmap_invalidate_all_pcid_noinvpcid);
3060 return (pmap_invalidate_all_nopcid);
3064 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3065 vm_offset_t addr2 __unused)
3068 pmap_invalidate_all_mode(pmap);
3072 pmap_invalidate_all(pmap_t pmap)
3075 if (pmap_type_guest(pmap)) {
3076 pmap_invalidate_ept(pmap);
3080 KASSERT(pmap->pm_type == PT_X86,
3081 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3083 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3084 pmap_invalidate_all_curcpu_cb);
3088 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3089 vm_offset_t addr2 __unused)
3096 pmap_invalidate_cache(void)
3099 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3103 cpuset_t invalidate; /* processors that invalidate their TLB */
3108 u_int store; /* processor that updates the PDE */
3112 pmap_update_pde_action(void *arg)
3114 struct pde_action *act = arg;
3116 if (act->store == PCPU_GET(cpuid))
3117 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3121 pmap_update_pde_teardown(void *arg)
3123 struct pde_action *act = arg;
3125 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3126 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3130 * Change the page size for the specified virtual address in a way that
3131 * prevents any possibility of the TLB ever having two entries that map the
3132 * same virtual address using different page sizes. This is the recommended
3133 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3134 * machine check exception for a TLB state that is improperly diagnosed as a
3138 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3140 struct pde_action act;
3141 cpuset_t active, other_cpus;
3145 cpuid = PCPU_GET(cpuid);
3146 other_cpus = all_cpus;
3147 CPU_CLR(cpuid, &other_cpus);
3148 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3151 active = pmap->pm_active;
3153 if (CPU_OVERLAP(&active, &other_cpus)) {
3155 act.invalidate = active;
3159 act.newpde = newpde;
3160 CPU_SET(cpuid, &active);
3161 smp_rendezvous_cpus(active,
3162 smp_no_rendezvous_barrier, pmap_update_pde_action,
3163 pmap_update_pde_teardown, &act);
3165 pmap_update_pde_store(pmap, pde, newpde);
3166 if (CPU_ISSET(cpuid, &active))
3167 pmap_update_pde_invalidate(pmap, va, newpde);
3173 * Normal, non-SMP, invalidation functions.
3176 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3178 struct invpcid_descr d;
3179 uint64_t kcr3, ucr3;
3182 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3186 KASSERT(pmap->pm_type == PT_X86,
3187 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3189 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3191 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3192 pmap->pm_ucr3 != PMAP_NO_CR3) {
3194 pcid = pmap->pm_pcids[0].pm_pcid;
3195 if (invpcid_works) {
3196 d.pcid = pcid | PMAP_PCID_USER_PT;
3199 invpcid(&d, INVPCID_ADDR);
3201 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3202 ucr3 = pmap->pm_ucr3 | pcid |
3203 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3204 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3208 } else if (pmap_pcid_enabled)
3209 pmap->pm_pcids[0].pm_gen = 0;
3213 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3215 struct invpcid_descr d;
3217 uint64_t kcr3, ucr3;
3219 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3223 KASSERT(pmap->pm_type == PT_X86,
3224 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3226 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3227 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3229 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3230 pmap->pm_ucr3 != PMAP_NO_CR3) {
3232 if (invpcid_works) {
3233 d.pcid = pmap->pm_pcids[0].pm_pcid |
3237 for (; d.addr < eva; d.addr += PAGE_SIZE)
3238 invpcid(&d, INVPCID_ADDR);
3240 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3241 pm_pcid | CR3_PCID_SAVE;
3242 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3243 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3244 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3248 } else if (pmap_pcid_enabled) {
3249 pmap->pm_pcids[0].pm_gen = 0;
3254 pmap_invalidate_all(pmap_t pmap)
3256 struct invpcid_descr d;
3257 uint64_t kcr3, ucr3;
3259 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3263 KASSERT(pmap->pm_type == PT_X86,
3264 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3266 if (pmap == kernel_pmap) {
3267 if (pmap_pcid_enabled && invpcid_works) {
3268 bzero(&d, sizeof(d));
3269 invpcid(&d, INVPCID_CTXGLOB);
3273 } else if (pmap == PCPU_GET(curpmap)) {
3274 if (pmap_pcid_enabled) {
3276 if (invpcid_works) {
3277 d.pcid = pmap->pm_pcids[0].pm_pcid;
3280 invpcid(&d, INVPCID_CTX);
3281 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3282 d.pcid |= PMAP_PCID_USER_PT;
3283 invpcid(&d, INVPCID_CTX);
3286 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3287 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3288 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3289 0].pm_pcid | PMAP_PCID_USER_PT;
3290 pmap_pti_pcid_invalidate(ucr3, kcr3);
3298 } else if (pmap_pcid_enabled) {
3299 pmap->pm_pcids[0].pm_gen = 0;
3304 pmap_invalidate_cache(void)
3311 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3314 pmap_update_pde_store(pmap, pde, newpde);
3315 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3316 pmap_update_pde_invalidate(pmap, va, newpde);
3318 pmap->pm_pcids[0].pm_gen = 0;
3323 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3327 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3328 * by a promotion that did not invalidate the 512 4KB page mappings
3329 * that might exist in the TLB. Consequently, at this point, the TLB
3330 * may hold both 4KB and 2MB page mappings for the address range [va,
3331 * va + NBPDR). Therefore, the entire range must be invalidated here.
3332 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3333 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3334 * single INVLPG suffices to invalidate the 2MB page mapping from the
3337 if ((pde & PG_PROMOTED) != 0)
3338 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3340 pmap_invalidate_page(pmap, va);
3343 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3344 (vm_offset_t sva, vm_offset_t eva))
3347 if ((cpu_feature & CPUID_SS) != 0)
3348 return (pmap_invalidate_cache_range_selfsnoop);
3349 if ((cpu_feature & CPUID_CLFSH) != 0)
3350 return (pmap_force_invalidate_cache_range);
3351 return (pmap_invalidate_cache_range_all);
3354 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3357 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3360 KASSERT((sva & PAGE_MASK) == 0,
3361 ("pmap_invalidate_cache_range: sva not page-aligned"));
3362 KASSERT((eva & PAGE_MASK) == 0,
3363 ("pmap_invalidate_cache_range: eva not page-aligned"));
3367 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3370 pmap_invalidate_cache_range_check_align(sva, eva);
3374 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3377 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3380 * XXX: Some CPUs fault, hang, or trash the local APIC
3381 * registers if we use CLFLUSH on the local APIC range. The
3382 * local APIC is always uncached, so we don't need to flush
3383 * for that range anyway.
3385 if (pmap_kextract(sva) == lapic_paddr)
3388 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3390 * Do per-cache line flush. Use a locked
3391 * instruction to insure that previous stores are
3392 * included in the write-back. The processor
3393 * propagates flush to other processors in the cache
3396 atomic_thread_fence_seq_cst();
3397 for (; sva < eva; sva += cpu_clflush_line_size)
3399 atomic_thread_fence_seq_cst();
3402 * Writes are ordered by CLFLUSH on Intel CPUs.
3404 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3406 for (; sva < eva; sva += cpu_clflush_line_size)
3408 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3414 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3417 pmap_invalidate_cache_range_check_align(sva, eva);
3418 pmap_invalidate_cache();
3422 * Remove the specified set of pages from the data and instruction caches.
3424 * In contrast to pmap_invalidate_cache_range(), this function does not
3425 * rely on the CPU's self-snoop feature, because it is intended for use
3426 * when moving pages into a different cache domain.
3429 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3431 vm_offset_t daddr, eva;
3435 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3436 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3437 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3438 pmap_invalidate_cache();
3441 atomic_thread_fence_seq_cst();
3442 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3444 for (i = 0; i < count; i++) {
3445 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3446 eva = daddr + PAGE_SIZE;
3447 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3455 atomic_thread_fence_seq_cst();
3456 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3462 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3465 pmap_invalidate_cache_range_check_align(sva, eva);
3467 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3468 pmap_force_invalidate_cache_range(sva, eva);
3472 /* See comment in pmap_force_invalidate_cache_range(). */
3473 if (pmap_kextract(sva) == lapic_paddr)
3476 atomic_thread_fence_seq_cst();
3477 for (; sva < eva; sva += cpu_clflush_line_size)
3479 atomic_thread_fence_seq_cst();
3483 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3487 int error, pte_bits;
3489 KASSERT((spa & PAGE_MASK) == 0,
3490 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3491 KASSERT((epa & PAGE_MASK) == 0,
3492 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3494 if (spa < dmaplimit) {
3495 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3497 if (dmaplimit >= epa)
3502 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3504 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3506 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3507 pte = vtopte(vaddr);
3508 for (; spa < epa; spa += PAGE_SIZE) {
3510 pte_store(pte, spa | pte_bits);
3512 /* XXXKIB atomic inside flush_cache_range are excessive */
3513 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3516 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3520 * Routine: pmap_extract
3522 * Extract the physical page address associated
3523 * with the given map/virtual_address pair.
3526 pmap_extract(pmap_t pmap, vm_offset_t va)
3530 pt_entry_t *pte, PG_V;
3534 PG_V = pmap_valid_bit(pmap);
3536 pdpe = pmap_pdpe(pmap, va);
3537 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3538 if ((*pdpe & PG_PS) != 0)
3539 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3541 pde = pmap_pdpe_to_pde(pdpe, va);
3542 if ((*pde & PG_V) != 0) {
3543 if ((*pde & PG_PS) != 0) {
3544 pa = (*pde & PG_PS_FRAME) |
3547 pte = pmap_pde_to_pte(pde, va);
3548 pa = (*pte & PG_FRAME) |
3559 * Routine: pmap_extract_and_hold
3561 * Atomically extract and hold the physical page
3562 * with the given pmap and virtual address pair
3563 * if that mapping permits the given protection.
3566 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3568 pd_entry_t pde, *pdep;
3569 pt_entry_t pte, PG_RW, PG_V;
3573 PG_RW = pmap_rw_bit(pmap);
3574 PG_V = pmap_valid_bit(pmap);
3577 pdep = pmap_pde(pmap, va);
3578 if (pdep != NULL && (pde = *pdep)) {
3580 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3581 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3584 pte = *pmap_pde_to_pte(pdep, va);
3585 if ((pte & PG_V) != 0 &&
3586 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3587 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3589 if (m != NULL && !vm_page_wire_mapped(m))
3597 pmap_kextract(vm_offset_t va)
3602 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3603 pa = DMAP_TO_PHYS(va);
3604 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3605 pa = pmap_large_map_kextract(va);
3609 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3612 * Beware of a concurrent promotion that changes the
3613 * PDE at this point! For example, vtopte() must not
3614 * be used to access the PTE because it would use the
3615 * new PDE. It is, however, safe to use the old PDE
3616 * because the page table page is preserved by the
3619 pa = *pmap_pde_to_pte(&pde, va);
3620 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3626 /***************************************************
3627 * Low level mapping routines.....
3628 ***************************************************/
3631 * Add a wired page to the kva.
3632 * Note: not SMP coherent.
3635 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3640 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3643 static __inline void
3644 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3650 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3651 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3655 * Remove a page from the kernel pagetables.
3656 * Note: not SMP coherent.
3659 pmap_kremove(vm_offset_t va)
3668 * Used to map a range of physical addresses into kernel
3669 * virtual address space.
3671 * The value passed in '*virt' is a suggested virtual address for
3672 * the mapping. Architectures which can support a direct-mapped
3673 * physical to virtual region can return the appropriate address
3674 * within that region, leaving '*virt' unchanged. Other
3675 * architectures should map the pages starting at '*virt' and
3676 * update '*virt' with the first usable address after the mapped
3680 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3682 return PHYS_TO_DMAP(start);
3686 * Add a list of wired pages to the kva
3687 * this routine is only used for temporary
3688 * kernel mappings that do not need to have
3689 * page modification or references recorded.
3690 * Note that old mappings are simply written
3691 * over. The page *must* be wired.
3692 * Note: SMP coherent. Uses a ranged shootdown IPI.
3695 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3697 pt_entry_t *endpte, oldpte, pa, *pte;
3703 endpte = pte + count;
3704 while (pte < endpte) {
3706 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3707 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3708 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3710 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3714 if (__predict_false((oldpte & X86_PG_V) != 0))
3715 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3720 * This routine tears out page mappings from the
3721 * kernel -- it is meant only for temporary mappings.
3722 * Note: SMP coherent. Uses a ranged shootdown IPI.
3725 pmap_qremove(vm_offset_t sva, int count)
3730 while (count-- > 0) {
3731 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3735 pmap_invalidate_range(kernel_pmap, sva, va);
3738 /***************************************************
3739 * Page table page management routines.....
3740 ***************************************************/
3742 * Schedule the specified unused page table page to be freed. Specifically,
3743 * add the page to the specified list of pages that will be released to the
3744 * physical memory manager after the TLB has been updated.
3746 static __inline void
3747 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3748 boolean_t set_PG_ZERO)
3752 m->flags |= PG_ZERO;
3754 m->flags &= ~PG_ZERO;
3755 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3759 * Inserts the specified page table page into the specified pmap's collection
3760 * of idle page table pages. Each of a pmap's page table pages is responsible
3761 * for mapping a distinct range of virtual addresses. The pmap's collection is
3762 * ordered by this virtual address range.
3764 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3767 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3770 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3771 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3772 return (vm_radix_insert(&pmap->pm_root, mpte));
3776 * Removes the page table page mapping the specified virtual address from the
3777 * specified pmap's collection of idle page table pages, and returns it.
3778 * Otherwise, returns NULL if there is no page table page corresponding to the
3779 * specified virtual address.
3781 static __inline vm_page_t
3782 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3786 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3790 * Decrements a page table page's reference count, which is used to record the
3791 * number of valid page table entries within the page. If the reference count
3792 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3793 * page table page was unmapped and FALSE otherwise.
3795 static inline boolean_t
3796 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3800 if (m->ref_count == 0) {
3801 _pmap_unwire_ptp(pmap, va, m, free);
3808 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3814 vm_page_t pdpg, pdppg, pml4pg;
3816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3819 * unmap the page table page
3821 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3823 MPASS(pmap_is_la57(pmap));
3824 pml5 = pmap_pml5e(pmap, va);
3826 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3827 pml5 = pmap_pml5e_u(pmap, va);
3830 } else if (m->pindex >= NUPDE + NUPDPE) {
3832 pml4 = pmap_pml4e(pmap, va);
3834 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3835 va <= VM_MAXUSER_ADDRESS) {
3836 pml4 = pmap_pml4e_u(pmap, va);
3839 } else if (m->pindex >= NUPDE) {
3841 pdp = pmap_pdpe(pmap, va);
3845 pd = pmap_pde(pmap, va);
3848 pmap_resident_count_dec(pmap, 1);
3849 if (m->pindex < NUPDE) {
3850 /* We just released a PT, unhold the matching PD */
3851 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3852 pmap_unwire_ptp(pmap, va, pdpg, free);
3853 } else if (m->pindex < NUPDE + NUPDPE) {
3854 /* We just released a PD, unhold the matching PDP */
3855 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3856 pmap_unwire_ptp(pmap, va, pdppg, free);
3857 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3858 /* We just released a PDP, unhold the matching PML4 */
3859 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3860 pmap_unwire_ptp(pmap, va, pml4pg, free);
3864 * Put page on a list so that it is released after
3865 * *ALL* TLB shootdown is done
3867 pmap_add_delayed_free_list(m, free, TRUE);
3871 * After removing a page table entry, this routine is used to
3872 * conditionally free the page, and manage the reference count.
3875 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3876 struct spglist *free)
3880 if (va >= VM_MAXUSER_ADDRESS)
3882 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3883 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3884 return (pmap_unwire_ptp(pmap, va, mpte, free));
3888 * Release a page table page reference after a failed attempt to create a
3892 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3894 struct spglist free;
3897 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3899 * Although "va" was never mapped, paging-structure caches
3900 * could nonetheless have entries that refer to the freed
3901 * page table pages. Invalidate those entries.
3903 pmap_invalidate_page(pmap, va);
3904 vm_page_free_pages_toq(&free, true);
3909 pmap_pinit0(pmap_t pmap)
3915 PMAP_LOCK_INIT(pmap);
3916 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3917 pmap->pm_pmltopu = NULL;
3918 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3919 /* hack to keep pmap_pti_pcid_invalidate() alive */
3920 pmap->pm_ucr3 = PMAP_NO_CR3;
3921 pmap->pm_root.rt_root = 0;
3922 CPU_ZERO(&pmap->pm_active);
3923 TAILQ_INIT(&pmap->pm_pvchunk);
3924 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3925 pmap->pm_flags = pmap_flags;
3927 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3928 pmap->pm_pcids[i].pm_gen = 1;
3930 pmap_activate_boot(pmap);
3935 p->p_md.md_flags |= P_MD_KPTI;
3938 pmap_thread_init_invl_gen(td);
3940 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3941 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3942 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3948 pmap_pinit_pml4(vm_page_t pml4pg)
3950 pml4_entry_t *pm_pml4;
3953 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3955 /* Wire in kernel global address entries. */
3956 for (i = 0; i < NKPML4E; i++) {
3957 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3960 for (i = 0; i < ndmpdpphys; i++) {
3961 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3965 /* install self-referential address mapping entry(s) */
3966 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3967 X86_PG_A | X86_PG_M;
3969 /* install large map entries if configured */
3970 for (i = 0; i < lm_ents; i++)
3971 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
3975 pmap_pinit_pml5(vm_page_t pml5pg)
3977 pml5_entry_t *pm_pml5;
3979 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
3982 * Add pml5 entry at top of KVA pointing to existing pml4 table,
3983 * entering all existing kernel mappings into level 5 table.
3985 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
3986 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
3987 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
3990 * Install self-referential address mapping entry.
3992 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
3993 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
3994 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
3998 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4000 pml4_entry_t *pm_pml4u;
4003 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4004 for (i = 0; i < NPML4EPG; i++)
4005 pm_pml4u[i] = pti_pml4[i];
4009 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4011 pml5_entry_t *pm_pml5u;
4013 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4016 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4017 * table, entering all kernel mappings needed for usermode
4018 * into level 5 table.
4020 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4021 pmap_kextract((vm_offset_t)pti_pml4) |
4022 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4023 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4027 * Initialize a preallocated and zeroed pmap structure,
4028 * such as one in a vmspace structure.
4031 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4033 vm_page_t pmltop_pg, pmltop_pgu;
4034 vm_paddr_t pmltop_phys;
4038 * allocate the page directory page
4040 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4041 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4043 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4044 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4047 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4048 pmap->pm_pcids[i].pm_gen = 0;
4050 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4051 pmap->pm_ucr3 = PMAP_NO_CR3;
4052 pmap->pm_pmltopu = NULL;
4054 pmap->pm_type = pm_type;
4055 if ((pmltop_pg->flags & PG_ZERO) == 0)
4056 pagezero(pmap->pm_pmltop);
4059 * Do not install the host kernel mappings in the nested page
4060 * tables. These mappings are meaningless in the guest physical
4062 * Install minimal kernel mappings in PTI case.
4064 if (pm_type == PT_X86) {
4065 pmap->pm_cr3 = pmltop_phys;
4066 if (pmap_is_la57(pmap))
4067 pmap_pinit_pml5(pmltop_pg);
4069 pmap_pinit_pml4(pmltop_pg);
4070 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4071 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4072 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4073 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4074 VM_PAGE_TO_PHYS(pmltop_pgu));
4075 if (pmap_is_la57(pmap))
4076 pmap_pinit_pml5_pti(pmltop_pgu);
4078 pmap_pinit_pml4_pti(pmltop_pgu);
4079 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4081 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4082 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4083 pkru_free_range, pmap, M_NOWAIT);
4087 pmap->pm_root.rt_root = 0;
4088 CPU_ZERO(&pmap->pm_active);
4089 TAILQ_INIT(&pmap->pm_pvchunk);
4090 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4091 pmap->pm_flags = flags;
4092 pmap->pm_eptgen = 0;
4098 pmap_pinit(pmap_t pmap)
4101 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4105 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4108 struct spglist free;
4110 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4111 if (mpg->ref_count != 0)
4114 _pmap_unwire_ptp(pmap, va, mpg, &free);
4115 pmap_invalidate_page(pmap, va);
4116 vm_page_free_pages_toq(&free, true);
4119 static pml4_entry_t *
4120 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4123 vm_pindex_t pml5index;
4130 if (!pmap_is_la57(pmap))
4131 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4133 PG_V = pmap_valid_bit(pmap);
4134 pml5index = pmap_pml5e_index(va);
4135 pml5 = &pmap->pm_pmltop[pml5index];
4136 if ((*pml5 & PG_V) == 0) {
4137 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4144 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4145 pml4 = &pml4[pmap_pml4e_index(va)];
4146 if ((*pml4 & PG_V) == 0) {
4147 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4148 if (allocated && !addref)
4149 pml4pg->ref_count--;
4150 else if (!allocated && addref)
4151 pml4pg->ref_count++;
4156 static pdp_entry_t *
4157 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4166 PG_V = pmap_valid_bit(pmap);
4168 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4172 if ((*pml4 & PG_V) == 0) {
4173 /* Have to allocate a new pdp, recurse */
4174 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4176 if (pmap_is_la57(pmap))
4177 pmap_allocpte_free_unref(pmap, va,
4178 pmap_pml5e(pmap, va));
4185 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4186 pdp = &pdp[pmap_pdpe_index(va)];
4187 if ((*pdp & PG_V) == 0) {
4188 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4189 if (allocated && !addref)
4191 else if (!allocated && addref)
4198 * This routine is called if the desired page table page does not exist.
4200 * If page table page allocation fails, this routine may sleep before
4201 * returning NULL. It sleeps only if a lock pointer was given.
4203 * Note: If a page allocation fails at page table level two, three, or four,
4204 * up to three pages may be held during the wait, only to be released
4205 * afterwards. This conservative approach is easily argued to avoid
4208 * The ptepindexes, i.e. page indices, of the page table pages encountered
4209 * while translating virtual address va are defined as follows:
4210 * - for the page table page (last level),
4211 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4212 * in other words, it is just the index of the PDE that maps the page
4214 * - for the page directory page,
4215 * ptepindex = NUPDE (number of userland PD entries) +
4216 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4217 * i.e. index of PDPE is put after the last index of PDE,
4218 * - for the page directory pointer page,
4219 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4221 * i.e. index of pml4e is put after the last index of PDPE,
4222 * - for the PML4 page (if LA57 mode is enabled),
4223 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4224 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4225 * i.e. index of pml5e is put after the last index of PML4E.
4227 * Define an order on the paging entries, where all entries of the
4228 * same height are put together, then heights are put from deepest to
4229 * root. Then ptexpindex is the sequential number of the
4230 * corresponding paging entry in this order.
4232 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4233 * LA57 paging structures even in LA48 paging mode. Moreover, the
4234 * ptepindexes are calculated as if the paging structures were 5-level
4235 * regardless of the actual mode of operation.
4237 * The root page at PML4/PML5 does not participate in this indexing scheme,
4238 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4241 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4242 vm_offset_t va __unused)
4244 vm_pindex_t pml5index, pml4index;
4245 pml5_entry_t *pml5, *pml5u;
4246 pml4_entry_t *pml4, *pml4u;
4250 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4252 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4254 PG_A = pmap_accessed_bit(pmap);
4255 PG_M = pmap_modified_bit(pmap);
4256 PG_V = pmap_valid_bit(pmap);
4257 PG_RW = pmap_rw_bit(pmap);
4260 * Allocate a page table page.
4262 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4263 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4264 if (lockp != NULL) {
4265 RELEASE_PV_LIST_LOCK(lockp);
4267 PMAP_ASSERT_NOT_IN_DI();
4273 * Indicate the need to retry. While waiting, the page table
4274 * page may have been allocated.
4278 if ((m->flags & PG_ZERO) == 0)
4282 * Map the pagetable page into the process address space, if
4283 * it isn't already there.
4285 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4286 MPASS(pmap_is_la57(pmap));
4288 pml5index = pmap_pml5e_index(va);
4289 pml5 = &pmap->pm_pmltop[pml5index];
4290 KASSERT((*pml5 & PG_V) == 0,
4291 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4292 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4294 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4295 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4298 pml5u = &pmap->pm_pmltopu[pml5index];
4299 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4302 } else if (ptepindex >= NUPDE + NUPDPE) {
4303 pml4index = pmap_pml4e_index(va);
4304 /* Wire up a new PDPE page */
4305 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4307 vm_page_unwire_noq(m);
4308 vm_page_free_zero(m);
4311 KASSERT((*pml4 & PG_V) == 0,
4312 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4313 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4315 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4316 pml4index < NUPML4E) {
4318 * PTI: Make all user-space mappings in the
4319 * kernel-mode page table no-execute so that
4320 * we detect any programming errors that leave
4321 * the kernel-mode page table active on return
4324 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4327 pml4u = &pmap->pm_pmltopu[pml4index];
4328 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4331 } else if (ptepindex >= NUPDE) {
4332 /* Wire up a new PDE page */
4333 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4335 vm_page_unwire_noq(m);
4336 vm_page_free_zero(m);
4339 KASSERT((*pdp & PG_V) == 0,
4340 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4341 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4343 /* Wire up a new PTE page */
4344 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4346 vm_page_unwire_noq(m);
4347 vm_page_free_zero(m);
4350 if ((*pdp & PG_V) == 0) {
4351 /* Have to allocate a new pd, recurse */
4352 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4353 lockp, va) == NULL) {
4354 pmap_allocpte_free_unref(pmap, va,
4355 pmap_pml4e(pmap, va));
4356 vm_page_unwire_noq(m);
4357 vm_page_free_zero(m);
4361 /* Add reference to the pd page */
4362 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4365 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4367 /* Now we know where the page directory page is */
4368 pd = &pd[pmap_pde_index(va)];
4369 KASSERT((*pd & PG_V) == 0,
4370 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4371 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4374 pmap_resident_count_inc(pmap, 1);
4380 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4381 struct rwlock **lockp)
4383 pdp_entry_t *pdpe, PG_V;
4386 vm_pindex_t pdpindex;
4388 PG_V = pmap_valid_bit(pmap);
4391 pdpe = pmap_pdpe(pmap, va);
4392 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4393 pde = pmap_pdpe_to_pde(pdpe, va);
4394 if (va < VM_MAXUSER_ADDRESS) {
4395 /* Add a reference to the pd page. */
4396 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4400 } else if (va < VM_MAXUSER_ADDRESS) {
4401 /* Allocate a pd page. */
4402 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4403 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4410 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4411 pde = &pde[pmap_pde_index(va)];
4413 panic("pmap_alloc_pde: missing page table page for va %#lx",
4420 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4422 vm_pindex_t ptepindex;
4423 pd_entry_t *pd, PG_V;
4426 PG_V = pmap_valid_bit(pmap);
4429 * Calculate pagetable page index
4431 ptepindex = pmap_pde_pindex(va);
4434 * Get the page directory entry
4436 pd = pmap_pde(pmap, va);
4439 * This supports switching from a 2MB page to a
4442 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4443 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4445 * Invalidation of the 2MB page mapping may have caused
4446 * the deallocation of the underlying PD page.
4453 * If the page table page is mapped, we just increment the
4454 * hold count, and activate it.
4456 if (pd != NULL && (*pd & PG_V) != 0) {
4457 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4461 * Here if the pte page isn't mapped, or if it has been
4464 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4465 if (m == NULL && lockp != NULL)
4471 /***************************************************
4472 * Pmap allocation/deallocation routines.
4473 ***************************************************/
4476 * Release any resources held by the given physical map.
4477 * Called when a pmap initialized by pmap_pinit is being released.
4478 * Should only be called if the map contains no valid mappings.
4481 pmap_release(pmap_t pmap)
4486 KASSERT(pmap->pm_stats.resident_count == 0,
4487 ("pmap_release: pmap %p resident count %ld != 0",
4488 pmap, pmap->pm_stats.resident_count));
4489 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4490 ("pmap_release: pmap %p has reserved page table page(s)",
4492 KASSERT(CPU_EMPTY(&pmap->pm_active),
4493 ("releasing active pmap %p", pmap));
4495 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4497 if (pmap_is_la57(pmap)) {
4498 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4499 pmap->pm_pmltop[PML5PML5I] = 0;
4501 for (i = 0; i < NKPML4E; i++) /* KVA */
4502 pmap->pm_pmltop[KPML4BASE + i] = 0;
4503 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4504 pmap->pm_pmltop[DMPML4I + i] = 0;
4505 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4506 for (i = 0; i < lm_ents; i++) /* Large Map */
4507 pmap->pm_pmltop[LMSPML4I + i] = 0;
4510 vm_page_unwire_noq(m);
4511 vm_page_free_zero(m);
4513 if (pmap->pm_pmltopu != NULL) {
4514 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4516 vm_page_unwire_noq(m);
4519 if (pmap->pm_type == PT_X86 &&
4520 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4521 rangeset_fini(&pmap->pm_pkru);
4525 kvm_size(SYSCTL_HANDLER_ARGS)
4527 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4529 return sysctl_handle_long(oidp, &ksize, 0, req);
4531 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4532 0, 0, kvm_size, "LU",
4536 kvm_free(SYSCTL_HANDLER_ARGS)
4538 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4540 return sysctl_handle_long(oidp, &kfree, 0, req);
4542 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4543 0, 0, kvm_free, "LU",
4544 "Amount of KVM free");
4547 * Allocate physical memory for the vm_page array and map it into KVA,
4548 * attempting to back the vm_pages with domain-local memory.
4551 pmap_page_array_startup(long pages)
4554 pd_entry_t *pde, newpdir;
4555 vm_offset_t va, start, end;
4560 vm_page_array_size = pages;
4562 start = VM_MIN_KERNEL_ADDRESS;
4563 end = start + pages * sizeof(struct vm_page);
4564 for (va = start; va < end; va += NBPDR) {
4565 pfn = first_page + (va - start) / sizeof(struct vm_page);
4566 domain = _vm_phys_domain(ptoa(pfn));
4567 pdpe = pmap_pdpe(kernel_pmap, va);
4568 if ((*pdpe & X86_PG_V) == 0) {
4569 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4571 pagezero((void *)PHYS_TO_DMAP(pa));
4572 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4573 X86_PG_A | X86_PG_M);
4575 pde = pmap_pdpe_to_pde(pdpe, va);
4576 if ((*pde & X86_PG_V) != 0)
4577 panic("Unexpected pde");
4578 pa = vm_phys_early_alloc(domain, NBPDR);
4579 for (i = 0; i < NPDEPG; i++)
4580 dump_add_page(pa + i * PAGE_SIZE);
4581 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4582 X86_PG_M | PG_PS | pg_g | pg_nx);
4583 pde_store(pde, newpdir);
4585 vm_page_array = (vm_page_t)start;
4589 * grow the number of kernel page table entries, if needed
4592 pmap_growkernel(vm_offset_t addr)
4596 pd_entry_t *pde, newpdir;
4599 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4602 * Return if "addr" is within the range of kernel page table pages
4603 * that were preallocated during pmap bootstrap. Moreover, leave
4604 * "kernel_vm_end" and the kernel page table as they were.
4606 * The correctness of this action is based on the following
4607 * argument: vm_map_insert() allocates contiguous ranges of the
4608 * kernel virtual address space. It calls this function if a range
4609 * ends after "kernel_vm_end". If the kernel is mapped between
4610 * "kernel_vm_end" and "addr", then the range cannot begin at
4611 * "kernel_vm_end". In fact, its beginning address cannot be less
4612 * than the kernel. Thus, there is no immediate need to allocate
4613 * any new kernel page table pages between "kernel_vm_end" and
4616 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4619 addr = roundup2(addr, NBPDR);
4620 if (addr - 1 >= vm_map_max(kernel_map))
4621 addr = vm_map_max(kernel_map);
4622 while (kernel_vm_end < addr) {
4623 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4624 if ((*pdpe & X86_PG_V) == 0) {
4625 /* We need a new PDP entry */
4626 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4627 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4628 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4630 panic("pmap_growkernel: no memory to grow kernel");
4631 if ((nkpg->flags & PG_ZERO) == 0)
4632 pmap_zero_page(nkpg);
4633 paddr = VM_PAGE_TO_PHYS(nkpg);
4634 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4635 X86_PG_A | X86_PG_M);
4636 continue; /* try again */
4638 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4639 if ((*pde & X86_PG_V) != 0) {
4640 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4641 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4642 kernel_vm_end = vm_map_max(kernel_map);
4648 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4649 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4652 panic("pmap_growkernel: no memory to grow kernel");
4653 if ((nkpg->flags & PG_ZERO) == 0)
4654 pmap_zero_page(nkpg);
4655 paddr = VM_PAGE_TO_PHYS(nkpg);
4656 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4657 pde_store(pde, newpdir);
4659 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4660 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4661 kernel_vm_end = vm_map_max(kernel_map);
4667 /***************************************************
4668 * page management routines.
4669 ***************************************************/
4671 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4672 CTASSERT(_NPCM == 3);
4673 CTASSERT(_NPCPV == 168);
4675 static __inline struct pv_chunk *
4676 pv_to_chunk(pv_entry_t pv)
4679 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4682 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4684 #define PC_FREE0 0xfffffffffffffffful
4685 #define PC_FREE1 0xfffffffffffffffful
4686 #define PC_FREE2 0x000000fffffffffful
4688 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4691 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4693 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4694 "Current number of pv entry chunks");
4695 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4696 "Current number of pv entry chunks allocated");
4697 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4698 "Current number of pv entry chunks frees");
4699 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4700 "Number of times tried to get a chunk page but failed.");
4702 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4703 static int pv_entry_spare;
4705 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4706 "Current number of pv entry frees");
4707 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4708 "Current number of pv entry allocs");
4709 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4710 "Current number of pv entries");
4711 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4712 "Current number of spare pv entries");
4716 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4721 pmap_invalidate_all(pmap);
4722 if (pmap != locked_pmap)
4725 pmap_delayed_invl_finish();
4729 * We are in a serious low memory condition. Resort to
4730 * drastic measures to free some pages so we can allocate
4731 * another pv entry chunk.
4733 * Returns NULL if PV entries were reclaimed from the specified pmap.
4735 * We do not, however, unmap 2mpages because subsequent accesses will
4736 * allocate per-page pv entries until repromotion occurs, thereby
4737 * exacerbating the shortage of free pv entries.
4740 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4742 struct pv_chunks_list *pvc;
4743 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4744 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4745 struct md_page *pvh;
4747 pmap_t next_pmap, pmap;
4748 pt_entry_t *pte, tpte;
4749 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4753 struct spglist free;
4755 int bit, field, freed;
4756 bool start_di, restart;
4758 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4759 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4762 PG_G = PG_A = PG_M = PG_RW = 0;
4764 bzero(&pc_marker_b, sizeof(pc_marker_b));
4765 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4766 pc_marker = (struct pv_chunk *)&pc_marker_b;
4767 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4770 * A delayed invalidation block should already be active if
4771 * pmap_advise() or pmap_remove() called this function by way
4772 * of pmap_demote_pde_locked().
4774 start_di = pmap_not_in_di();
4776 pvc = &pv_chunks[domain];
4777 mtx_lock(&pvc->pvc_lock);
4778 pvc->active_reclaims++;
4779 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4780 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4781 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4782 SLIST_EMPTY(&free)) {
4783 next_pmap = pc->pc_pmap;
4784 if (next_pmap == NULL) {
4786 * The next chunk is a marker. However, it is
4787 * not our marker, so active_reclaims must be
4788 * > 1. Consequently, the next_chunk code
4789 * will not rotate the pv_chunks list.
4793 mtx_unlock(&pvc->pvc_lock);
4796 * A pv_chunk can only be removed from the pc_lru list
4797 * when both pc_chunks_mutex is owned and the
4798 * corresponding pmap is locked.
4800 if (pmap != next_pmap) {
4802 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4805 /* Avoid deadlock and lock recursion. */
4806 if (pmap > locked_pmap) {
4807 RELEASE_PV_LIST_LOCK(lockp);
4810 pmap_delayed_invl_start();
4811 mtx_lock(&pvc->pvc_lock);
4813 } else if (pmap != locked_pmap) {
4814 if (PMAP_TRYLOCK(pmap)) {
4816 pmap_delayed_invl_start();
4817 mtx_lock(&pvc->pvc_lock);
4820 pmap = NULL; /* pmap is not locked */
4821 mtx_lock(&pvc->pvc_lock);
4822 pc = TAILQ_NEXT(pc_marker, pc_lru);
4824 pc->pc_pmap != next_pmap)
4828 } else if (start_di)
4829 pmap_delayed_invl_start();
4830 PG_G = pmap_global_bit(pmap);
4831 PG_A = pmap_accessed_bit(pmap);
4832 PG_M = pmap_modified_bit(pmap);
4833 PG_RW = pmap_rw_bit(pmap);
4839 * Destroy every non-wired, 4 KB page mapping in the chunk.
4842 for (field = 0; field < _NPCM; field++) {
4843 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4844 inuse != 0; inuse &= ~(1UL << bit)) {
4846 pv = &pc->pc_pventry[field * 64 + bit];
4848 pde = pmap_pde(pmap, va);
4849 if ((*pde & PG_PS) != 0)
4851 pte = pmap_pde_to_pte(pde, va);
4852 if ((*pte & PG_W) != 0)
4854 tpte = pte_load_clear(pte);
4855 if ((tpte & PG_G) != 0)
4856 pmap_invalidate_page(pmap, va);
4857 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4858 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4860 if ((tpte & PG_A) != 0)
4861 vm_page_aflag_set(m, PGA_REFERENCED);
4862 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4863 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4865 if (TAILQ_EMPTY(&m->md.pv_list) &&
4866 (m->flags & PG_FICTITIOUS) == 0) {
4867 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4868 if (TAILQ_EMPTY(&pvh->pv_list)) {
4869 vm_page_aflag_clear(m,
4873 pmap_delayed_invl_page(m);
4874 pc->pc_map[field] |= 1UL << bit;
4875 pmap_unuse_pt(pmap, va, *pde, &free);
4880 mtx_lock(&pvc->pvc_lock);
4883 /* Every freed mapping is for a 4 KB page. */
4884 pmap_resident_count_dec(pmap, freed);
4885 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4886 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4887 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4888 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4889 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4890 pc->pc_map[2] == PC_FREE2) {
4891 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4892 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4893 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4894 /* Entire chunk is free; return it. */
4895 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4896 dump_drop_page(m_pc->phys_addr);
4897 mtx_lock(&pvc->pvc_lock);
4898 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4901 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4902 mtx_lock(&pvc->pvc_lock);
4903 /* One freed pv entry in locked_pmap is sufficient. */
4904 if (pmap == locked_pmap)
4907 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4908 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4909 if (pvc->active_reclaims == 1 && pmap != NULL) {
4911 * Rotate the pv chunks list so that we do not
4912 * scan the same pv chunks that could not be
4913 * freed (because they contained a wired
4914 * and/or superpage mapping) on every
4915 * invocation of reclaim_pv_chunk().
4917 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4918 MPASS(pc->pc_pmap != NULL);
4919 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4920 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4924 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4925 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4926 pvc->active_reclaims--;
4927 mtx_unlock(&pvc->pvc_lock);
4928 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4929 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4930 m_pc = SLIST_FIRST(&free);
4931 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4932 /* Recycle a freed page table page. */
4933 m_pc->ref_count = 1;
4935 vm_page_free_pages_toq(&free, true);
4940 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4945 domain = PCPU_GET(domain);
4946 for (i = 0; i < vm_ndomains; i++) {
4947 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4950 domain = (domain + 1) % vm_ndomains;
4957 * free the pv_entry back to the free list
4960 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4962 struct pv_chunk *pc;
4963 int idx, field, bit;
4965 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4966 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4967 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4968 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4969 pc = pv_to_chunk(pv);
4970 idx = pv - &pc->pc_pventry[0];
4973 pc->pc_map[field] |= 1ul << bit;
4974 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4975 pc->pc_map[2] != PC_FREE2) {
4976 /* 98% of the time, pc is already at the head of the list. */
4977 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4978 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4979 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4983 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4988 free_pv_chunk_dequeued(struct pv_chunk *pc)
4992 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4993 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4994 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4995 /* entire chunk is free, return it */
4996 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4997 dump_drop_page(m->phys_addr);
4998 vm_page_unwire_noq(m);
5003 free_pv_chunk(struct pv_chunk *pc)
5005 struct pv_chunks_list *pvc;
5007 pvc = &pv_chunks[pc_to_domain(pc)];
5008 mtx_lock(&pvc->pvc_lock);
5009 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5010 mtx_unlock(&pvc->pvc_lock);
5011 free_pv_chunk_dequeued(pc);
5015 free_pv_chunk_batch(struct pv_chunklist *batch)
5017 struct pv_chunks_list *pvc;
5018 struct pv_chunk *pc, *npc;
5021 for (i = 0; i < vm_ndomains; i++) {
5022 if (TAILQ_EMPTY(&batch[i]))
5024 pvc = &pv_chunks[i];
5025 mtx_lock(&pvc->pvc_lock);
5026 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5027 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5029 mtx_unlock(&pvc->pvc_lock);
5032 for (i = 0; i < vm_ndomains; i++) {
5033 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5034 free_pv_chunk_dequeued(pc);
5040 * Returns a new PV entry, allocating a new PV chunk from the system when
5041 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5042 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5045 * The given PV list lock may be released.
5048 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5050 struct pv_chunks_list *pvc;
5053 struct pv_chunk *pc;
5056 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5057 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5059 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5061 for (field = 0; field < _NPCM; field++) {
5062 if (pc->pc_map[field]) {
5063 bit = bsfq(pc->pc_map[field]);
5067 if (field < _NPCM) {
5068 pv = &pc->pc_pventry[field * 64 + bit];
5069 pc->pc_map[field] &= ~(1ul << bit);
5070 /* If this was the last item, move it to tail */
5071 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5072 pc->pc_map[2] == 0) {
5073 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5074 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5077 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5078 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5082 /* No free items, allocate another chunk */
5083 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5086 if (lockp == NULL) {
5087 PV_STAT(pc_chunk_tryfail++);
5090 m = reclaim_pv_chunk(pmap, lockp);
5094 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5095 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5096 dump_add_page(m->phys_addr);
5097 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5099 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5100 pc->pc_map[1] = PC_FREE1;
5101 pc->pc_map[2] = PC_FREE2;
5102 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
5103 mtx_lock(&pvc->pvc_lock);
5104 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5105 mtx_unlock(&pvc->pvc_lock);
5106 pv = &pc->pc_pventry[0];
5107 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5108 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5109 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5114 * Returns the number of one bits within the given PV chunk map.
5116 * The erratas for Intel processors state that "POPCNT Instruction May
5117 * Take Longer to Execute Than Expected". It is believed that the
5118 * issue is the spurious dependency on the destination register.
5119 * Provide a hint to the register rename logic that the destination
5120 * value is overwritten, by clearing it, as suggested in the
5121 * optimization manual. It should be cheap for unaffected processors
5124 * Reference numbers for erratas are
5125 * 4th Gen Core: HSD146
5126 * 5th Gen Core: BDM85
5127 * 6th Gen Core: SKL029
5130 popcnt_pc_map_pq(uint64_t *map)
5134 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5135 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5136 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5137 : "=&r" (result), "=&r" (tmp)
5138 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5143 * Ensure that the number of spare PV entries in the specified pmap meets or
5144 * exceeds the given count, "needed".
5146 * The given PV list lock may be released.
5149 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5151 struct pv_chunks_list *pvc;
5152 struct pch new_tail[PMAP_MEMDOM];
5153 struct pv_chunk *pc;
5158 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5159 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5162 * Newly allocated PV chunks must be stored in a private list until
5163 * the required number of PV chunks have been allocated. Otherwise,
5164 * reclaim_pv_chunk() could recycle one of these chunks. In
5165 * contrast, these chunks must be added to the pmap upon allocation.
5167 for (i = 0; i < PMAP_MEMDOM; i++)
5168 TAILQ_INIT(&new_tail[i]);
5171 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5173 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5174 bit_count((bitstr_t *)pc->pc_map, 0,
5175 sizeof(pc->pc_map) * NBBY, &free);
5178 free = popcnt_pc_map_pq(pc->pc_map);
5182 if (avail >= needed)
5185 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5186 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5189 m = reclaim_pv_chunk(pmap, lockp);
5194 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5195 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5196 dump_add_page(m->phys_addr);
5197 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5199 pc->pc_map[0] = PC_FREE0;
5200 pc->pc_map[1] = PC_FREE1;
5201 pc->pc_map[2] = PC_FREE2;
5202 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5203 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5204 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5207 * The reclaim might have freed a chunk from the current pmap.
5208 * If that chunk contained available entries, we need to
5209 * re-count the number of available entries.
5214 for (i = 0; i < vm_ndomains; i++) {
5215 if (TAILQ_EMPTY(&new_tail[i]))
5217 pvc = &pv_chunks[i];
5218 mtx_lock(&pvc->pvc_lock);
5219 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5220 mtx_unlock(&pvc->pvc_lock);
5225 * First find and then remove the pv entry for the specified pmap and virtual
5226 * address from the specified pv list. Returns the pv entry if found and NULL
5227 * otherwise. This operation can be performed on pv lists for either 4KB or
5228 * 2MB page mappings.
5230 static __inline pv_entry_t
5231 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5235 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5236 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5237 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5246 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5247 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5248 * entries for each of the 4KB page mappings.
5251 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5252 struct rwlock **lockp)
5254 struct md_page *pvh;
5255 struct pv_chunk *pc;
5257 vm_offset_t va_last;
5261 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5262 KASSERT((pa & PDRMASK) == 0,
5263 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5264 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5267 * Transfer the 2mpage's pv entry for this mapping to the first
5268 * page's pv list. Once this transfer begins, the pv list lock
5269 * must not be released until the last pv entry is reinstantiated.
5271 pvh = pa_to_pvh(pa);
5272 va = trunc_2mpage(va);
5273 pv = pmap_pvh_remove(pvh, pmap, va);
5274 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5275 m = PHYS_TO_VM_PAGE(pa);
5276 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5278 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5279 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5280 va_last = va + NBPDR - PAGE_SIZE;
5282 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5283 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5284 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5285 for (field = 0; field < _NPCM; field++) {
5286 while (pc->pc_map[field]) {
5287 bit = bsfq(pc->pc_map[field]);
5288 pc->pc_map[field] &= ~(1ul << bit);
5289 pv = &pc->pc_pventry[field * 64 + bit];
5293 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5294 ("pmap_pv_demote_pde: page %p is not managed", m));
5295 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5301 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5302 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5305 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5306 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5307 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5309 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5310 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5313 #if VM_NRESERVLEVEL > 0
5315 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5316 * replace the many pv entries for the 4KB page mappings by a single pv entry
5317 * for the 2MB page mapping.
5320 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5321 struct rwlock **lockp)
5323 struct md_page *pvh;
5325 vm_offset_t va_last;
5328 KASSERT((pa & PDRMASK) == 0,
5329 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5330 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5333 * Transfer the first page's pv entry for this mapping to the 2mpage's
5334 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5335 * a transfer avoids the possibility that get_pv_entry() calls
5336 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5337 * mappings that is being promoted.
5339 m = PHYS_TO_VM_PAGE(pa);
5340 va = trunc_2mpage(va);
5341 pv = pmap_pvh_remove(&m->md, pmap, va);
5342 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5343 pvh = pa_to_pvh(pa);
5344 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5346 /* Free the remaining NPTEPG - 1 pv entries. */
5347 va_last = va + NBPDR - PAGE_SIZE;
5351 pmap_pvh_free(&m->md, pmap, va);
5352 } while (va < va_last);
5354 #endif /* VM_NRESERVLEVEL > 0 */
5357 * First find and then destroy the pv entry for the specified pmap and virtual
5358 * address. This operation can be performed on pv lists for either 4KB or 2MB
5362 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5366 pv = pmap_pvh_remove(pvh, pmap, va);
5367 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5368 free_pv_entry(pmap, pv);
5372 * Conditionally create the PV entry for a 4KB page mapping if the required
5373 * memory can be allocated without resorting to reclamation.
5376 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5377 struct rwlock **lockp)
5381 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5382 /* Pass NULL instead of the lock pointer to disable reclamation. */
5383 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5385 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5386 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5394 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5395 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5396 * false if the PV entry cannot be allocated without resorting to reclamation.
5399 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5400 struct rwlock **lockp)
5402 struct md_page *pvh;
5406 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5407 /* Pass NULL instead of the lock pointer to disable reclamation. */
5408 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5409 NULL : lockp)) == NULL)
5412 pa = pde & PG_PS_FRAME;
5413 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5414 pvh = pa_to_pvh(pa);
5415 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5421 * Fills a page table page with mappings to consecutive physical pages.
5424 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5428 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5430 newpte += PAGE_SIZE;
5435 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5436 * mapping is invalidated.
5439 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5441 struct rwlock *lock;
5445 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5452 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5456 pt_entry_t *xpte, *ypte;
5458 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5459 xpte++, newpte += PAGE_SIZE) {
5460 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5461 printf("pmap_demote_pde: xpte %zd and newpte map "
5462 "different pages: found %#lx, expected %#lx\n",
5463 xpte - firstpte, *xpte, newpte);
5464 printf("page table dump\n");
5465 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5466 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5471 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5472 ("pmap_demote_pde: firstpte and newpte map different physical"
5479 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5480 pd_entry_t oldpde, struct rwlock **lockp)
5482 struct spglist free;
5486 sva = trunc_2mpage(va);
5487 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5488 if ((oldpde & pmap_global_bit(pmap)) == 0)
5489 pmap_invalidate_pde_page(pmap, sva, oldpde);
5490 vm_page_free_pages_toq(&free, true);
5491 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5496 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5497 struct rwlock **lockp)
5499 pd_entry_t newpde, oldpde;
5500 pt_entry_t *firstpte, newpte;
5501 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5507 PG_A = pmap_accessed_bit(pmap);
5508 PG_G = pmap_global_bit(pmap);
5509 PG_M = pmap_modified_bit(pmap);
5510 PG_RW = pmap_rw_bit(pmap);
5511 PG_V = pmap_valid_bit(pmap);
5512 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5513 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5515 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5516 in_kernel = va >= VM_MAXUSER_ADDRESS;
5518 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5519 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5522 * Invalidate the 2MB page mapping and return "failure" if the
5523 * mapping was never accessed.
5525 if ((oldpde & PG_A) == 0) {
5526 KASSERT((oldpde & PG_W) == 0,
5527 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5528 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5532 mpte = pmap_remove_pt_page(pmap, va);
5534 KASSERT((oldpde & PG_W) == 0,
5535 ("pmap_demote_pde: page table page for a wired mapping"
5539 * If the page table page is missing and the mapping
5540 * is for a kernel address, the mapping must belong to
5541 * the direct map. Page table pages are preallocated
5542 * for every other part of the kernel address space,
5543 * so the direct map region is the only part of the
5544 * kernel address space that must be handled here.
5546 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5547 va < DMAP_MAX_ADDRESS),
5548 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5551 * If the 2MB page mapping belongs to the direct map
5552 * region of the kernel's address space, then the page
5553 * allocation request specifies the highest possible
5554 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5555 * priority is normal.
5557 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5558 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5559 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5562 * If the allocation of the new page table page fails,
5563 * invalidate the 2MB page mapping and return "failure".
5566 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5571 mpte->ref_count = NPTEPG;
5572 pmap_resident_count_inc(pmap, 1);
5575 mptepa = VM_PAGE_TO_PHYS(mpte);
5576 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5577 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5578 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5579 ("pmap_demote_pde: oldpde is missing PG_M"));
5580 newpte = oldpde & ~PG_PS;
5581 newpte = pmap_swap_pat(pmap, newpte);
5584 * If the page table page is not leftover from an earlier promotion,
5587 if (mpte->valid == 0)
5588 pmap_fill_ptp(firstpte, newpte);
5590 pmap_demote_pde_check(firstpte, newpte);
5593 * If the mapping has changed attributes, update the page table
5596 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5597 pmap_fill_ptp(firstpte, newpte);
5600 * The spare PV entries must be reserved prior to demoting the
5601 * mapping, that is, prior to changing the PDE. Otherwise, the state
5602 * of the PDE and the PV lists will be inconsistent, which can result
5603 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5604 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5605 * PV entry for the 2MB page mapping that is being demoted.
5607 if ((oldpde & PG_MANAGED) != 0)
5608 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5611 * Demote the mapping. This pmap is locked. The old PDE has
5612 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5613 * set. Thus, there is no danger of a race with another
5614 * processor changing the setting of PG_A and/or PG_M between
5615 * the read above and the store below.
5617 if (workaround_erratum383)
5618 pmap_update_pde(pmap, va, pde, newpde);
5620 pde_store(pde, newpde);
5623 * Invalidate a stale recursive mapping of the page table page.
5626 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5629 * Demote the PV entry.
5631 if ((oldpde & PG_MANAGED) != 0)
5632 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5634 atomic_add_long(&pmap_pde_demotions, 1);
5635 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5641 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5644 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5650 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5651 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5652 mpte = pmap_remove_pt_page(pmap, va);
5654 panic("pmap_remove_kernel_pde: Missing pt page.");
5656 mptepa = VM_PAGE_TO_PHYS(mpte);
5657 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5660 * If this page table page was unmapped by a promotion, then it
5661 * contains valid mappings. Zero it to invalidate those mappings.
5663 if (mpte->valid != 0)
5664 pagezero((void *)PHYS_TO_DMAP(mptepa));
5667 * Demote the mapping.
5669 if (workaround_erratum383)
5670 pmap_update_pde(pmap, va, pde, newpde);
5672 pde_store(pde, newpde);
5675 * Invalidate a stale recursive mapping of the page table page.
5677 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5681 * pmap_remove_pde: do the things to unmap a superpage in a process
5684 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5685 struct spglist *free, struct rwlock **lockp)
5687 struct md_page *pvh;
5689 vm_offset_t eva, va;
5691 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5693 PG_G = pmap_global_bit(pmap);
5694 PG_A = pmap_accessed_bit(pmap);
5695 PG_M = pmap_modified_bit(pmap);
5696 PG_RW = pmap_rw_bit(pmap);
5698 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5699 KASSERT((sva & PDRMASK) == 0,
5700 ("pmap_remove_pde: sva is not 2mpage aligned"));
5701 oldpde = pte_load_clear(pdq);
5703 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5704 if ((oldpde & PG_G) != 0)
5705 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5706 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5707 if (oldpde & PG_MANAGED) {
5708 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5709 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5710 pmap_pvh_free(pvh, pmap, sva);
5712 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5713 va < eva; va += PAGE_SIZE, m++) {
5714 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5717 vm_page_aflag_set(m, PGA_REFERENCED);
5718 if (TAILQ_EMPTY(&m->md.pv_list) &&
5719 TAILQ_EMPTY(&pvh->pv_list))
5720 vm_page_aflag_clear(m, PGA_WRITEABLE);
5721 pmap_delayed_invl_page(m);
5724 if (pmap == kernel_pmap) {
5725 pmap_remove_kernel_pde(pmap, pdq, sva);
5727 mpte = pmap_remove_pt_page(pmap, sva);
5729 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5730 ("pmap_remove_pde: pte page not promoted"));
5731 pmap_resident_count_dec(pmap, 1);
5732 KASSERT(mpte->ref_count == NPTEPG,
5733 ("pmap_remove_pde: pte page ref count error"));
5734 mpte->ref_count = 0;
5735 pmap_add_delayed_free_list(mpte, free, FALSE);
5738 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5742 * pmap_remove_pte: do the things to unmap a page in a process
5745 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5746 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5748 struct md_page *pvh;
5749 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5752 PG_A = pmap_accessed_bit(pmap);
5753 PG_M = pmap_modified_bit(pmap);
5754 PG_RW = pmap_rw_bit(pmap);
5756 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5757 oldpte = pte_load_clear(ptq);
5759 pmap->pm_stats.wired_count -= 1;
5760 pmap_resident_count_dec(pmap, 1);
5761 if (oldpte & PG_MANAGED) {
5762 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5763 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5766 vm_page_aflag_set(m, PGA_REFERENCED);
5767 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5768 pmap_pvh_free(&m->md, pmap, va);
5769 if (TAILQ_EMPTY(&m->md.pv_list) &&
5770 (m->flags & PG_FICTITIOUS) == 0) {
5771 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5772 if (TAILQ_EMPTY(&pvh->pv_list))
5773 vm_page_aflag_clear(m, PGA_WRITEABLE);
5775 pmap_delayed_invl_page(m);
5777 return (pmap_unuse_pt(pmap, va, ptepde, free));
5781 * Remove a single page from a process address space
5784 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5785 struct spglist *free)
5787 struct rwlock *lock;
5788 pt_entry_t *pte, PG_V;
5790 PG_V = pmap_valid_bit(pmap);
5791 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5792 if ((*pde & PG_V) == 0)
5794 pte = pmap_pde_to_pte(pde, va);
5795 if ((*pte & PG_V) == 0)
5798 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5801 pmap_invalidate_page(pmap, va);
5805 * Removes the specified range of addresses from the page table page.
5808 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5809 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5811 pt_entry_t PG_G, *pte;
5815 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5816 PG_G = pmap_global_bit(pmap);
5819 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5823 pmap_invalidate_range(pmap, va, sva);
5828 if ((*pte & PG_G) == 0)
5832 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5838 pmap_invalidate_range(pmap, va, sva);
5843 * Remove the given range of addresses from the specified map.
5845 * It is assumed that the start and end are properly
5846 * rounded to the page size.
5849 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5851 struct rwlock *lock;
5852 vm_offset_t va_next;
5853 pml5_entry_t *pml5e;
5854 pml4_entry_t *pml4e;
5856 pd_entry_t ptpaddr, *pde;
5857 pt_entry_t PG_G, PG_V;
5858 struct spglist free;
5861 PG_G = pmap_global_bit(pmap);
5862 PG_V = pmap_valid_bit(pmap);
5865 * Perform an unsynchronized read. This is, however, safe.
5867 if (pmap->pm_stats.resident_count == 0)
5873 pmap_delayed_invl_start();
5875 pmap_pkru_on_remove(pmap, sva, eva);
5878 * special handling of removing one page. a very
5879 * common operation and easy to short circuit some
5882 if (sva + PAGE_SIZE == eva) {
5883 pde = pmap_pde(pmap, sva);
5884 if (pde && (*pde & PG_PS) == 0) {
5885 pmap_remove_page(pmap, sva, pde, &free);
5891 for (; sva < eva; sva = va_next) {
5892 if (pmap->pm_stats.resident_count == 0)
5895 if (pmap_is_la57(pmap)) {
5896 pml5e = pmap_pml5e(pmap, sva);
5897 if ((*pml5e & PG_V) == 0) {
5898 va_next = (sva + NBPML5) & ~PML5MASK;
5903 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5905 pml4e = pmap_pml4e(pmap, sva);
5907 if ((*pml4e & PG_V) == 0) {
5908 va_next = (sva + NBPML4) & ~PML4MASK;
5914 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5915 if ((*pdpe & PG_V) == 0) {
5916 va_next = (sva + NBPDP) & ~PDPMASK;
5923 * Calculate index for next page table.
5925 va_next = (sva + NBPDR) & ~PDRMASK;
5929 pde = pmap_pdpe_to_pde(pdpe, sva);
5933 * Weed out invalid mappings.
5939 * Check for large page.
5941 if ((ptpaddr & PG_PS) != 0) {
5943 * Are we removing the entire large page? If not,
5944 * demote the mapping and fall through.
5946 if (sva + NBPDR == va_next && eva >= va_next) {
5948 * The TLB entry for a PG_G mapping is
5949 * invalidated by pmap_remove_pde().
5951 if ((ptpaddr & PG_G) == 0)
5953 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5955 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5957 /* The large page mapping was destroyed. */
5964 * Limit our scan to either the end of the va represented
5965 * by the current page table page, or to the end of the
5966 * range being removed.
5971 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5978 pmap_invalidate_all(pmap);
5980 pmap_delayed_invl_finish();
5981 vm_page_free_pages_toq(&free, true);
5985 * Routine: pmap_remove_all
5987 * Removes this physical page from
5988 * all physical maps in which it resides.
5989 * Reflects back modify bits to the pager.
5992 * Original versions of this routine were very
5993 * inefficient because they iteratively called
5994 * pmap_remove (slow...)
5998 pmap_remove_all(vm_page_t m)
6000 struct md_page *pvh;
6003 struct rwlock *lock;
6004 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6007 struct spglist free;
6008 int pvh_gen, md_gen;
6010 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6011 ("pmap_remove_all: page %p is not managed", m));
6013 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6014 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6015 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6018 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6020 if (!PMAP_TRYLOCK(pmap)) {
6021 pvh_gen = pvh->pv_gen;
6025 if (pvh_gen != pvh->pv_gen) {
6032 pde = pmap_pde(pmap, va);
6033 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6036 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6038 if (!PMAP_TRYLOCK(pmap)) {
6039 pvh_gen = pvh->pv_gen;
6040 md_gen = m->md.pv_gen;
6044 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6050 PG_A = pmap_accessed_bit(pmap);
6051 PG_M = pmap_modified_bit(pmap);
6052 PG_RW = pmap_rw_bit(pmap);
6053 pmap_resident_count_dec(pmap, 1);
6054 pde = pmap_pde(pmap, pv->pv_va);
6055 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6056 " a 2mpage in page %p's pv list", m));
6057 pte = pmap_pde_to_pte(pde, pv->pv_va);
6058 tpte = pte_load_clear(pte);
6060 pmap->pm_stats.wired_count--;
6062 vm_page_aflag_set(m, PGA_REFERENCED);
6065 * Update the vm_page_t clean and reference bits.
6067 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6069 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6070 pmap_invalidate_page(pmap, pv->pv_va);
6071 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6073 free_pv_entry(pmap, pv);
6076 vm_page_aflag_clear(m, PGA_WRITEABLE);
6078 pmap_delayed_invl_wait(m);
6079 vm_page_free_pages_toq(&free, true);
6083 * pmap_protect_pde: do the things to protect a 2mpage in a process
6086 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6088 pd_entry_t newpde, oldpde;
6090 boolean_t anychanged;
6091 pt_entry_t PG_G, PG_M, PG_RW;
6093 PG_G = pmap_global_bit(pmap);
6094 PG_M = pmap_modified_bit(pmap);
6095 PG_RW = pmap_rw_bit(pmap);
6097 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6098 KASSERT((sva & PDRMASK) == 0,
6099 ("pmap_protect_pde: sva is not 2mpage aligned"));
6102 oldpde = newpde = *pde;
6103 if ((prot & VM_PROT_WRITE) == 0) {
6104 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6105 (PG_MANAGED | PG_M | PG_RW)) {
6106 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6107 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6110 newpde &= ~(PG_RW | PG_M);
6112 if ((prot & VM_PROT_EXECUTE) == 0)
6114 if (newpde != oldpde) {
6116 * As an optimization to future operations on this PDE, clear
6117 * PG_PROMOTED. The impending invalidation will remove any
6118 * lingering 4KB page mappings from the TLB.
6120 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6122 if ((oldpde & PG_G) != 0)
6123 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6127 return (anychanged);
6131 * Set the physical protection on the
6132 * specified range of this map as requested.
6135 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6137 vm_offset_t va_next;
6138 pml4_entry_t *pml4e;
6140 pd_entry_t ptpaddr, *pde;
6141 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6142 boolean_t anychanged;
6144 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6145 if (prot == VM_PROT_NONE) {
6146 pmap_remove(pmap, sva, eva);
6150 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6151 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6154 PG_G = pmap_global_bit(pmap);
6155 PG_M = pmap_modified_bit(pmap);
6156 PG_V = pmap_valid_bit(pmap);
6157 PG_RW = pmap_rw_bit(pmap);
6161 * Although this function delays and batches the invalidation
6162 * of stale TLB entries, it does not need to call
6163 * pmap_delayed_invl_start() and
6164 * pmap_delayed_invl_finish(), because it does not
6165 * ordinarily destroy mappings. Stale TLB entries from
6166 * protection-only changes need only be invalidated before the
6167 * pmap lock is released, because protection-only changes do
6168 * not destroy PV entries. Even operations that iterate over
6169 * a physical page's PV list of mappings, like
6170 * pmap_remove_write(), acquire the pmap lock for each
6171 * mapping. Consequently, for protection-only changes, the
6172 * pmap lock suffices to synchronize both page table and TLB
6175 * This function only destroys a mapping if pmap_demote_pde()
6176 * fails. In that case, stale TLB entries are immediately
6181 for (; sva < eva; sva = va_next) {
6182 pml4e = pmap_pml4e(pmap, sva);
6183 if ((*pml4e & PG_V) == 0) {
6184 va_next = (sva + NBPML4) & ~PML4MASK;
6190 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6191 if ((*pdpe & PG_V) == 0) {
6192 va_next = (sva + NBPDP) & ~PDPMASK;
6198 va_next = (sva + NBPDR) & ~PDRMASK;
6202 pde = pmap_pdpe_to_pde(pdpe, sva);
6206 * Weed out invalid mappings.
6212 * Check for large page.
6214 if ((ptpaddr & PG_PS) != 0) {
6216 * Are we protecting the entire large page? If not,
6217 * demote the mapping and fall through.
6219 if (sva + NBPDR == va_next && eva >= va_next) {
6221 * The TLB entry for a PG_G mapping is
6222 * invalidated by pmap_protect_pde().
6224 if (pmap_protect_pde(pmap, pde, sva, prot))
6227 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6229 * The large page mapping was destroyed.
6238 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6240 pt_entry_t obits, pbits;
6244 obits = pbits = *pte;
6245 if ((pbits & PG_V) == 0)
6248 if ((prot & VM_PROT_WRITE) == 0) {
6249 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6250 (PG_MANAGED | PG_M | PG_RW)) {
6251 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6254 pbits &= ~(PG_RW | PG_M);
6256 if ((prot & VM_PROT_EXECUTE) == 0)
6259 if (pbits != obits) {
6260 if (!atomic_cmpset_long(pte, obits, pbits))
6263 pmap_invalidate_page(pmap, sva);
6270 pmap_invalidate_all(pmap);
6274 #if VM_NRESERVLEVEL > 0
6276 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6279 if (pmap->pm_type != PT_EPT)
6281 return ((pde & EPT_PG_EXECUTE) != 0);
6285 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6286 * single page table page (PTP) to a single 2MB page mapping. For promotion
6287 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6288 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6289 * identical characteristics.
6292 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6293 struct rwlock **lockp)
6296 pt_entry_t *firstpte, oldpte, pa, *pte;
6297 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6301 PG_A = pmap_accessed_bit(pmap);
6302 PG_G = pmap_global_bit(pmap);
6303 PG_M = pmap_modified_bit(pmap);
6304 PG_V = pmap_valid_bit(pmap);
6305 PG_RW = pmap_rw_bit(pmap);
6306 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6307 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6309 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6312 * Examine the first PTE in the specified PTP. Abort if this PTE is
6313 * either invalid, unused, or does not map the first 4KB physical page
6314 * within a 2MB page.
6316 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6319 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6320 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6322 atomic_add_long(&pmap_pde_p_failures, 1);
6323 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6324 " in pmap %p", va, pmap);
6327 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6329 * When PG_M is already clear, PG_RW can be cleared without
6330 * a TLB invalidation.
6332 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6338 * Examine each of the other PTEs in the specified PTP. Abort if this
6339 * PTE maps an unexpected 4KB physical page or does not have identical
6340 * characteristics to the first PTE.
6342 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6343 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6346 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6347 atomic_add_long(&pmap_pde_p_failures, 1);
6348 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6349 " in pmap %p", va, pmap);
6352 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6354 * When PG_M is already clear, PG_RW can be cleared
6355 * without a TLB invalidation.
6357 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6360 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6361 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6362 (va & ~PDRMASK), pmap);
6364 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6365 atomic_add_long(&pmap_pde_p_failures, 1);
6366 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6367 " in pmap %p", va, pmap);
6374 * Save the page table page in its current state until the PDE
6375 * mapping the superpage is demoted by pmap_demote_pde() or
6376 * destroyed by pmap_remove_pde().
6378 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6379 KASSERT(mpte >= vm_page_array &&
6380 mpte < &vm_page_array[vm_page_array_size],
6381 ("pmap_promote_pde: page table page is out of range"));
6382 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6383 ("pmap_promote_pde: page table page's pindex is wrong"));
6384 if (pmap_insert_pt_page(pmap, mpte, true)) {
6385 atomic_add_long(&pmap_pde_p_failures, 1);
6387 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6393 * Promote the pv entries.
6395 if ((newpde & PG_MANAGED) != 0)
6396 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6399 * Propagate the PAT index to its proper position.
6401 newpde = pmap_swap_pat(pmap, newpde);
6404 * Map the superpage.
6406 if (workaround_erratum383)
6407 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6409 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6411 atomic_add_long(&pmap_pde_promotions, 1);
6412 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6413 " in pmap %p", va, pmap);
6415 #endif /* VM_NRESERVLEVEL > 0 */
6418 * Insert the given physical page (p) at
6419 * the specified virtual address (v) in the
6420 * target physical map with the protection requested.
6422 * If specified, the page will be wired down, meaning
6423 * that the related pte can not be reclaimed.
6425 * NB: This is the only routine which MAY NOT lazy-evaluate
6426 * or lose information. That is, this routine must actually
6427 * insert this page into the given map NOW.
6429 * When destroying both a page table and PV entry, this function
6430 * performs the TLB invalidation before releasing the PV list
6431 * lock, so we do not need pmap_delayed_invl_page() calls here.
6434 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6435 u_int flags, int8_t psind)
6437 struct rwlock *lock;
6439 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6440 pt_entry_t newpte, origpte;
6447 PG_A = pmap_accessed_bit(pmap);
6448 PG_G = pmap_global_bit(pmap);
6449 PG_M = pmap_modified_bit(pmap);
6450 PG_V = pmap_valid_bit(pmap);
6451 PG_RW = pmap_rw_bit(pmap);
6453 va = trunc_page(va);
6454 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6455 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6456 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6458 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6459 va >= kmi.clean_eva,
6460 ("pmap_enter: managed mapping within the clean submap"));
6461 if ((m->oflags & VPO_UNMANAGED) == 0)
6462 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6463 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6464 ("pmap_enter: flags %u has reserved bits set", flags));
6465 pa = VM_PAGE_TO_PHYS(m);
6466 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6467 if ((flags & VM_PROT_WRITE) != 0)
6469 if ((prot & VM_PROT_WRITE) != 0)
6471 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6472 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6473 if ((prot & VM_PROT_EXECUTE) == 0)
6475 if ((flags & PMAP_ENTER_WIRED) != 0)
6477 if (va < VM_MAXUSER_ADDRESS)
6479 if (pmap == kernel_pmap)
6481 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6484 * Set modified bit gratuitously for writeable mappings if
6485 * the page is unmanaged. We do not want to take a fault
6486 * to do the dirty bit accounting for these mappings.
6488 if ((m->oflags & VPO_UNMANAGED) != 0) {
6489 if ((newpte & PG_RW) != 0)
6492 newpte |= PG_MANAGED;
6497 /* Assert the required virtual and physical alignment. */
6498 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6499 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6500 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6506 * In the case that a page table page is not
6507 * resident, we are creating it here.
6510 pde = pmap_pde(pmap, va);
6511 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6512 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6513 pte = pmap_pde_to_pte(pde, va);
6514 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6515 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6518 } else if (va < VM_MAXUSER_ADDRESS) {
6520 * Here if the pte page isn't mapped, or if it has been
6523 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6524 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6525 nosleep ? NULL : &lock, va);
6526 if (mpte == NULL && nosleep) {
6527 rv = KERN_RESOURCE_SHORTAGE;
6532 panic("pmap_enter: invalid page directory va=%#lx", va);
6536 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6537 newpte |= pmap_pkru_get(pmap, va);
6540 * Is the specified virtual address already mapped?
6542 if ((origpte & PG_V) != 0) {
6544 * Wiring change, just update stats. We don't worry about
6545 * wiring PT pages as they remain resident as long as there
6546 * are valid mappings in them. Hence, if a user page is wired,
6547 * the PT page will be also.
6549 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6550 pmap->pm_stats.wired_count++;
6551 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6552 pmap->pm_stats.wired_count--;
6555 * Remove the extra PT page reference.
6559 KASSERT(mpte->ref_count > 0,
6560 ("pmap_enter: missing reference to page table page,"
6565 * Has the physical page changed?
6567 opa = origpte & PG_FRAME;
6570 * No, might be a protection or wiring change.
6572 if ((origpte & PG_MANAGED) != 0 &&
6573 (newpte & PG_RW) != 0)
6574 vm_page_aflag_set(m, PGA_WRITEABLE);
6575 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6581 * The physical page has changed. Temporarily invalidate
6582 * the mapping. This ensures that all threads sharing the
6583 * pmap keep a consistent view of the mapping, which is
6584 * necessary for the correct handling of COW faults. It
6585 * also permits reuse of the old mapping's PV entry,
6586 * avoiding an allocation.
6588 * For consistency, handle unmanaged mappings the same way.
6590 origpte = pte_load_clear(pte);
6591 KASSERT((origpte & PG_FRAME) == opa,
6592 ("pmap_enter: unexpected pa update for %#lx", va));
6593 if ((origpte & PG_MANAGED) != 0) {
6594 om = PHYS_TO_VM_PAGE(opa);
6597 * The pmap lock is sufficient to synchronize with
6598 * concurrent calls to pmap_page_test_mappings() and
6599 * pmap_ts_referenced().
6601 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6603 if ((origpte & PG_A) != 0) {
6604 pmap_invalidate_page(pmap, va);
6605 vm_page_aflag_set(om, PGA_REFERENCED);
6607 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6608 pv = pmap_pvh_remove(&om->md, pmap, va);
6610 ("pmap_enter: no PV entry for %#lx", va));
6611 if ((newpte & PG_MANAGED) == 0)
6612 free_pv_entry(pmap, pv);
6613 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6614 TAILQ_EMPTY(&om->md.pv_list) &&
6615 ((om->flags & PG_FICTITIOUS) != 0 ||
6616 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6617 vm_page_aflag_clear(om, PGA_WRITEABLE);
6620 * Since this mapping is unmanaged, assume that PG_A
6623 pmap_invalidate_page(pmap, va);
6628 * Increment the counters.
6630 if ((newpte & PG_W) != 0)
6631 pmap->pm_stats.wired_count++;
6632 pmap_resident_count_inc(pmap, 1);
6636 * Enter on the PV list if part of our managed memory.
6638 if ((newpte & PG_MANAGED) != 0) {
6640 pv = get_pv_entry(pmap, &lock);
6643 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6644 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6646 if ((newpte & PG_RW) != 0)
6647 vm_page_aflag_set(m, PGA_WRITEABLE);
6653 if ((origpte & PG_V) != 0) {
6655 origpte = pte_load_store(pte, newpte);
6656 KASSERT((origpte & PG_FRAME) == pa,
6657 ("pmap_enter: unexpected pa update for %#lx", va));
6658 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6660 if ((origpte & PG_MANAGED) != 0)
6664 * Although the PTE may still have PG_RW set, TLB
6665 * invalidation may nonetheless be required because
6666 * the PTE no longer has PG_M set.
6668 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6670 * This PTE change does not require TLB invalidation.
6674 if ((origpte & PG_A) != 0)
6675 pmap_invalidate_page(pmap, va);
6677 pte_store(pte, newpte);
6681 #if VM_NRESERVLEVEL > 0
6683 * If both the page table page and the reservation are fully
6684 * populated, then attempt promotion.
6686 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6687 pmap_ps_enabled(pmap) &&
6688 (m->flags & PG_FICTITIOUS) == 0 &&
6689 vm_reserv_level_iffullpop(m) == 0)
6690 pmap_promote_pde(pmap, pde, va, &lock);
6702 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6703 * if successful. Returns false if (1) a page table page cannot be allocated
6704 * without sleeping, (2) a mapping already exists at the specified virtual
6705 * address, or (3) a PV entry cannot be allocated without reclaiming another
6709 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6710 struct rwlock **lockp)
6715 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6716 PG_V = pmap_valid_bit(pmap);
6717 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6719 if ((m->oflags & VPO_UNMANAGED) == 0)
6720 newpde |= PG_MANAGED;
6721 if ((prot & VM_PROT_EXECUTE) == 0)
6723 if (va < VM_MAXUSER_ADDRESS)
6725 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6726 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6731 * Returns true if every page table entry in the specified page table page is
6735 pmap_every_pte_zero(vm_paddr_t pa)
6737 pt_entry_t *pt_end, *pte;
6739 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6740 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6741 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6749 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6750 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6751 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6752 * a mapping already exists at the specified virtual address. Returns
6753 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6754 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6755 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6757 * The parameter "m" is only used when creating a managed, writeable mapping.
6760 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6761 vm_page_t m, struct rwlock **lockp)
6763 struct spglist free;
6764 pd_entry_t oldpde, *pde;
6765 pt_entry_t PG_G, PG_RW, PG_V;
6768 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6769 ("pmap_enter_pde: cannot create wired user mapping"));
6770 PG_G = pmap_global_bit(pmap);
6771 PG_RW = pmap_rw_bit(pmap);
6772 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6773 ("pmap_enter_pde: newpde is missing PG_M"));
6774 PG_V = pmap_valid_bit(pmap);
6775 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6777 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6779 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6780 " in pmap %p", va, pmap);
6781 return (KERN_FAILURE);
6783 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6784 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6785 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6786 " in pmap %p", va, pmap);
6787 return (KERN_RESOURCE_SHORTAGE);
6791 * If pkru is not same for the whole pde range, return failure
6792 * and let vm_fault() cope. Check after pde allocation, since
6795 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6796 pmap_abort_ptp(pmap, va, pdpg);
6797 return (KERN_FAILURE);
6799 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6800 newpde &= ~X86_PG_PKU_MASK;
6801 newpde |= pmap_pkru_get(pmap, va);
6805 * If there are existing mappings, either abort or remove them.
6808 if ((oldpde & PG_V) != 0) {
6809 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6810 ("pmap_enter_pde: pdpg's reference count is too low"));
6811 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6812 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6813 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6816 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6817 " in pmap %p", va, pmap);
6818 return (KERN_FAILURE);
6820 /* Break the existing mapping(s). */
6822 if ((oldpde & PG_PS) != 0) {
6824 * The reference to the PD page that was acquired by
6825 * pmap_alloc_pde() ensures that it won't be freed.
6826 * However, if the PDE resulted from a promotion, then
6827 * a reserved PT page could be freed.
6829 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6830 if ((oldpde & PG_G) == 0)
6831 pmap_invalidate_pde_page(pmap, va, oldpde);
6833 pmap_delayed_invl_start();
6834 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6836 pmap_invalidate_all(pmap);
6837 pmap_delayed_invl_finish();
6839 if (va < VM_MAXUSER_ADDRESS) {
6840 vm_page_free_pages_toq(&free, true);
6841 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6844 KASSERT(SLIST_EMPTY(&free),
6845 ("pmap_enter_pde: freed kernel page table page"));
6848 * Both pmap_remove_pde() and pmap_remove_ptes() will
6849 * leave the kernel page table page zero filled.
6851 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6852 if (pmap_insert_pt_page(pmap, mt, false))
6853 panic("pmap_enter_pde: trie insert failed");
6857 if ((newpde & PG_MANAGED) != 0) {
6859 * Abort this mapping if its PV entry could not be created.
6861 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6863 pmap_abort_ptp(pmap, va, pdpg);
6864 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6865 " in pmap %p", va, pmap);
6866 return (KERN_RESOURCE_SHORTAGE);
6868 if ((newpde & PG_RW) != 0) {
6869 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6870 vm_page_aflag_set(mt, PGA_WRITEABLE);
6875 * Increment counters.
6877 if ((newpde & PG_W) != 0)
6878 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6879 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6882 * Map the superpage. (This is not a promoted mapping; there will not
6883 * be any lingering 4KB page mappings in the TLB.)
6885 pde_store(pde, newpde);
6887 atomic_add_long(&pmap_pde_mappings, 1);
6888 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
6890 return (KERN_SUCCESS);
6894 * Maps a sequence of resident pages belonging to the same object.
6895 * The sequence begins with the given page m_start. This page is
6896 * mapped at the given virtual address start. Each subsequent page is
6897 * mapped at a virtual address that is offset from start by the same
6898 * amount as the page is offset from m_start within the object. The
6899 * last page in the sequence is the page with the largest offset from
6900 * m_start that can be mapped at a virtual address less than the given
6901 * virtual address end. Not every virtual page between start and end
6902 * is mapped; only those for which a resident page exists with the
6903 * corresponding offset from m_start are mapped.
6906 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6907 vm_page_t m_start, vm_prot_t prot)
6909 struct rwlock *lock;
6912 vm_pindex_t diff, psize;
6914 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6916 psize = atop(end - start);
6921 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6922 va = start + ptoa(diff);
6923 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6924 m->psind == 1 && pmap_ps_enabled(pmap) &&
6925 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6926 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6927 m = &m[NBPDR / PAGE_SIZE - 1];
6929 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6931 m = TAILQ_NEXT(m, listq);
6939 * this code makes some *MAJOR* assumptions:
6940 * 1. Current pmap & pmap exists.
6943 * 4. No page table pages.
6944 * but is *MUCH* faster than pmap_enter...
6948 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6950 struct rwlock *lock;
6954 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6961 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6962 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6964 pt_entry_t newpte, *pte, PG_V;
6966 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6967 (m->oflags & VPO_UNMANAGED) != 0,
6968 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6969 PG_V = pmap_valid_bit(pmap);
6970 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6973 * In the case that a page table page is not
6974 * resident, we are creating it here.
6976 if (va < VM_MAXUSER_ADDRESS) {
6977 vm_pindex_t ptepindex;
6981 * Calculate pagetable page index
6983 ptepindex = pmap_pde_pindex(va);
6984 if (mpte && (mpte->pindex == ptepindex)) {
6988 * Get the page directory entry
6990 ptepa = pmap_pde(pmap, va);
6993 * If the page table page is mapped, we just increment
6994 * the hold count, and activate it. Otherwise, we
6995 * attempt to allocate a page table page. If this
6996 * attempt fails, we don't retry. Instead, we give up.
6998 if (ptepa && (*ptepa & PG_V) != 0) {
7001 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7005 * Pass NULL instead of the PV list lock
7006 * pointer, because we don't intend to sleep.
7008 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
7014 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7015 pte = &pte[pmap_pte_index(va)];
7027 * Enter on the PV list if part of our managed memory.
7029 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7030 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7032 pmap_abort_ptp(pmap, va, mpte);
7037 * Increment counters
7039 pmap_resident_count_inc(pmap, 1);
7041 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7042 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7043 if ((m->oflags & VPO_UNMANAGED) == 0)
7044 newpte |= PG_MANAGED;
7045 if ((prot & VM_PROT_EXECUTE) == 0)
7047 if (va < VM_MAXUSER_ADDRESS)
7048 newpte |= PG_U | pmap_pkru_get(pmap, va);
7049 pte_store(pte, newpte);
7054 * Make a temporary mapping for a physical address. This is only intended
7055 * to be used for panic dumps.
7058 pmap_kenter_temporary(vm_paddr_t pa, int i)
7062 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7063 pmap_kenter(va, pa);
7065 return ((void *)crashdumpmap);
7069 * This code maps large physical mmap regions into the
7070 * processor address space. Note that some shortcuts
7071 * are taken, but the code works.
7074 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7075 vm_pindex_t pindex, vm_size_t size)
7078 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7079 vm_paddr_t pa, ptepa;
7083 PG_A = pmap_accessed_bit(pmap);
7084 PG_M = pmap_modified_bit(pmap);
7085 PG_V = pmap_valid_bit(pmap);
7086 PG_RW = pmap_rw_bit(pmap);
7088 VM_OBJECT_ASSERT_WLOCKED(object);
7089 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7090 ("pmap_object_init_pt: non-device object"));
7091 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7092 if (!pmap_ps_enabled(pmap))
7094 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7096 p = vm_page_lookup(object, pindex);
7097 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7098 ("pmap_object_init_pt: invalid page %p", p));
7099 pat_mode = p->md.pat_mode;
7102 * Abort the mapping if the first page is not physically
7103 * aligned to a 2MB page boundary.
7105 ptepa = VM_PAGE_TO_PHYS(p);
7106 if (ptepa & (NBPDR - 1))
7110 * Skip the first page. Abort the mapping if the rest of
7111 * the pages are not physically contiguous or have differing
7112 * memory attributes.
7114 p = TAILQ_NEXT(p, listq);
7115 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7117 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7118 ("pmap_object_init_pt: invalid page %p", p));
7119 if (pa != VM_PAGE_TO_PHYS(p) ||
7120 pat_mode != p->md.pat_mode)
7122 p = TAILQ_NEXT(p, listq);
7126 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7127 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7128 * will not affect the termination of this loop.
7131 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7132 pa < ptepa + size; pa += NBPDR) {
7133 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7136 * The creation of mappings below is only an
7137 * optimization. If a page directory page
7138 * cannot be allocated without blocking,
7139 * continue on to the next mapping rather than
7145 if ((*pde & PG_V) == 0) {
7146 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7147 PG_U | PG_RW | PG_V);
7148 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7149 atomic_add_long(&pmap_pde_mappings, 1);
7151 /* Continue on if the PDE is already valid. */
7153 KASSERT(pdpg->ref_count > 0,
7154 ("pmap_object_init_pt: missing reference "
7155 "to page directory page, va: 0x%lx", addr));
7164 * Clear the wired attribute from the mappings for the specified range of
7165 * addresses in the given pmap. Every valid mapping within that range
7166 * must have the wired attribute set. In contrast, invalid mappings
7167 * cannot have the wired attribute set, so they are ignored.
7169 * The wired attribute of the page table entry is not a hardware
7170 * feature, so there is no need to invalidate any TLB entries.
7171 * Since pmap_demote_pde() for the wired entry must never fail,
7172 * pmap_delayed_invl_start()/finish() calls around the
7173 * function are not needed.
7176 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7178 vm_offset_t va_next;
7179 pml4_entry_t *pml4e;
7182 pt_entry_t *pte, PG_V;
7184 PG_V = pmap_valid_bit(pmap);
7186 for (; sva < eva; sva = va_next) {
7187 pml4e = pmap_pml4e(pmap, sva);
7188 if ((*pml4e & PG_V) == 0) {
7189 va_next = (sva + NBPML4) & ~PML4MASK;
7194 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7195 if ((*pdpe & PG_V) == 0) {
7196 va_next = (sva + NBPDP) & ~PDPMASK;
7201 va_next = (sva + NBPDR) & ~PDRMASK;
7204 pde = pmap_pdpe_to_pde(pdpe, sva);
7205 if ((*pde & PG_V) == 0)
7207 if ((*pde & PG_PS) != 0) {
7208 if ((*pde & PG_W) == 0)
7209 panic("pmap_unwire: pde %#jx is missing PG_W",
7213 * Are we unwiring the entire large page? If not,
7214 * demote the mapping and fall through.
7216 if (sva + NBPDR == va_next && eva >= va_next) {
7217 atomic_clear_long(pde, PG_W);
7218 pmap->pm_stats.wired_count -= NBPDR /
7221 } else if (!pmap_demote_pde(pmap, pde, sva))
7222 panic("pmap_unwire: demotion failed");
7226 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7228 if ((*pte & PG_V) == 0)
7230 if ((*pte & PG_W) == 0)
7231 panic("pmap_unwire: pte %#jx is missing PG_W",
7235 * PG_W must be cleared atomically. Although the pmap
7236 * lock synchronizes access to PG_W, another processor
7237 * could be setting PG_M and/or PG_A concurrently.
7239 atomic_clear_long(pte, PG_W);
7240 pmap->pm_stats.wired_count--;
7247 * Copy the range specified by src_addr/len
7248 * from the source map to the range dst_addr/len
7249 * in the destination map.
7251 * This routine is only advisory and need not do anything.
7254 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7255 vm_offset_t src_addr)
7257 struct rwlock *lock;
7258 pml4_entry_t *pml4e;
7260 pd_entry_t *pde, srcptepaddr;
7261 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7262 vm_offset_t addr, end_addr, va_next;
7263 vm_page_t dst_pdpg, dstmpte, srcmpte;
7265 if (dst_addr != src_addr)
7268 if (dst_pmap->pm_type != src_pmap->pm_type)
7272 * EPT page table entries that require emulation of A/D bits are
7273 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7274 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7275 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7276 * implementations flag an EPT misconfiguration for exec-only
7277 * mappings we skip this function entirely for emulated pmaps.
7279 if (pmap_emulate_ad_bits(dst_pmap))
7282 end_addr = src_addr + len;
7284 if (dst_pmap < src_pmap) {
7285 PMAP_LOCK(dst_pmap);
7286 PMAP_LOCK(src_pmap);
7288 PMAP_LOCK(src_pmap);
7289 PMAP_LOCK(dst_pmap);
7292 PG_A = pmap_accessed_bit(dst_pmap);
7293 PG_M = pmap_modified_bit(dst_pmap);
7294 PG_V = pmap_valid_bit(dst_pmap);
7296 for (addr = src_addr; addr < end_addr; addr = va_next) {
7297 KASSERT(addr < UPT_MIN_ADDRESS,
7298 ("pmap_copy: invalid to pmap_copy page tables"));
7300 pml4e = pmap_pml4e(src_pmap, addr);
7301 if ((*pml4e & PG_V) == 0) {
7302 va_next = (addr + NBPML4) & ~PML4MASK;
7308 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7309 if ((*pdpe & PG_V) == 0) {
7310 va_next = (addr + NBPDP) & ~PDPMASK;
7316 va_next = (addr + NBPDR) & ~PDRMASK;
7320 pde = pmap_pdpe_to_pde(pdpe, addr);
7322 if (srcptepaddr == 0)
7325 if (srcptepaddr & PG_PS) {
7326 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7328 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7331 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7332 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7333 PMAP_ENTER_NORECLAIM, &lock))) {
7334 *pde = srcptepaddr & ~PG_W;
7335 pmap_resident_count_inc(dst_pmap, NBPDR /
7337 atomic_add_long(&pmap_pde_mappings, 1);
7339 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7343 srcptepaddr &= PG_FRAME;
7344 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7345 KASSERT(srcmpte->ref_count > 0,
7346 ("pmap_copy: source page table page is unused"));
7348 if (va_next > end_addr)
7351 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7352 src_pte = &src_pte[pmap_pte_index(addr)];
7354 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7358 * We only virtual copy managed pages.
7360 if ((ptetemp & PG_MANAGED) == 0)
7363 if (dstmpte != NULL) {
7364 KASSERT(dstmpte->pindex ==
7365 pmap_pde_pindex(addr),
7366 ("dstmpte pindex/addr mismatch"));
7367 dstmpte->ref_count++;
7368 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7371 dst_pte = (pt_entry_t *)
7372 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7373 dst_pte = &dst_pte[pmap_pte_index(addr)];
7374 if (*dst_pte == 0 &&
7375 pmap_try_insert_pv_entry(dst_pmap, addr,
7376 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7378 * Clear the wired, modified, and accessed
7379 * (referenced) bits during the copy.
7381 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7382 pmap_resident_count_inc(dst_pmap, 1);
7384 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7387 /* Have we copied all of the valid mappings? */
7388 if (dstmpte->ref_count >= srcmpte->ref_count)
7395 PMAP_UNLOCK(src_pmap);
7396 PMAP_UNLOCK(dst_pmap);
7400 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7404 if (dst_pmap->pm_type != src_pmap->pm_type ||
7405 dst_pmap->pm_type != PT_X86 ||
7406 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7409 if (dst_pmap < src_pmap) {
7410 PMAP_LOCK(dst_pmap);
7411 PMAP_LOCK(src_pmap);
7413 PMAP_LOCK(src_pmap);
7414 PMAP_LOCK(dst_pmap);
7416 error = pmap_pkru_copy(dst_pmap, src_pmap);
7417 /* Clean up partial copy on failure due to no memory. */
7418 if (error == ENOMEM)
7419 pmap_pkru_deassign_all(dst_pmap);
7420 PMAP_UNLOCK(src_pmap);
7421 PMAP_UNLOCK(dst_pmap);
7422 if (error != ENOMEM)
7430 * Zero the specified hardware page.
7433 pmap_zero_page(vm_page_t m)
7435 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7437 pagezero((void *)va);
7441 * Zero an an area within a single hardware page. off and size must not
7442 * cover an area beyond a single hardware page.
7445 pmap_zero_page_area(vm_page_t m, int off, int size)
7447 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7449 if (off == 0 && size == PAGE_SIZE)
7450 pagezero((void *)va);
7452 bzero((char *)va + off, size);
7456 * Copy 1 specified hardware page to another.
7459 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7461 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7462 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7464 pagecopy((void *)src, (void *)dst);
7467 int unmapped_buf_allowed = 1;
7470 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7471 vm_offset_t b_offset, int xfersize)
7475 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7479 while (xfersize > 0) {
7480 a_pg_offset = a_offset & PAGE_MASK;
7481 pages[0] = ma[a_offset >> PAGE_SHIFT];
7482 b_pg_offset = b_offset & PAGE_MASK;
7483 pages[1] = mb[b_offset >> PAGE_SHIFT];
7484 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7485 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7486 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7487 a_cp = (char *)vaddr[0] + a_pg_offset;
7488 b_cp = (char *)vaddr[1] + b_pg_offset;
7489 bcopy(a_cp, b_cp, cnt);
7490 if (__predict_false(mapped))
7491 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7499 * Returns true if the pmap's pv is one of the first
7500 * 16 pvs linked to from this page. This count may
7501 * be changed upwards or downwards in the future; it
7502 * is only necessary that true be returned for a small
7503 * subset of pmaps for proper page aging.
7506 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7508 struct md_page *pvh;
7509 struct rwlock *lock;
7514 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7515 ("pmap_page_exists_quick: page %p is not managed", m));
7517 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7519 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7520 if (PV_PMAP(pv) == pmap) {
7528 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7529 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7530 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7531 if (PV_PMAP(pv) == pmap) {
7545 * pmap_page_wired_mappings:
7547 * Return the number of managed mappings to the given physical page
7551 pmap_page_wired_mappings(vm_page_t m)
7553 struct rwlock *lock;
7554 struct md_page *pvh;
7558 int count, md_gen, pvh_gen;
7560 if ((m->oflags & VPO_UNMANAGED) != 0)
7562 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7566 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7568 if (!PMAP_TRYLOCK(pmap)) {
7569 md_gen = m->md.pv_gen;
7573 if (md_gen != m->md.pv_gen) {
7578 pte = pmap_pte(pmap, pv->pv_va);
7579 if ((*pte & PG_W) != 0)
7583 if ((m->flags & PG_FICTITIOUS) == 0) {
7584 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7585 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7587 if (!PMAP_TRYLOCK(pmap)) {
7588 md_gen = m->md.pv_gen;
7589 pvh_gen = pvh->pv_gen;
7593 if (md_gen != m->md.pv_gen ||
7594 pvh_gen != pvh->pv_gen) {
7599 pte = pmap_pde(pmap, pv->pv_va);
7600 if ((*pte & PG_W) != 0)
7610 * Returns TRUE if the given page is mapped individually or as part of
7611 * a 2mpage. Otherwise, returns FALSE.
7614 pmap_page_is_mapped(vm_page_t m)
7616 struct rwlock *lock;
7619 if ((m->oflags & VPO_UNMANAGED) != 0)
7621 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7623 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7624 ((m->flags & PG_FICTITIOUS) == 0 &&
7625 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7631 * Destroy all managed, non-wired mappings in the given user-space
7632 * pmap. This pmap cannot be active on any processor besides the
7635 * This function cannot be applied to the kernel pmap. Moreover, it
7636 * is not intended for general use. It is only to be used during
7637 * process termination. Consequently, it can be implemented in ways
7638 * that make it faster than pmap_remove(). First, it can more quickly
7639 * destroy mappings by iterating over the pmap's collection of PV
7640 * entries, rather than searching the page table. Second, it doesn't
7641 * have to test and clear the page table entries atomically, because
7642 * no processor is currently accessing the user address space. In
7643 * particular, a page table entry's dirty bit won't change state once
7644 * this function starts.
7646 * Although this function destroys all of the pmap's managed,
7647 * non-wired mappings, it can delay and batch the invalidation of TLB
7648 * entries without calling pmap_delayed_invl_start() and
7649 * pmap_delayed_invl_finish(). Because the pmap is not active on
7650 * any other processor, none of these TLB entries will ever be used
7651 * before their eventual invalidation. Consequently, there is no need
7652 * for either pmap_remove_all() or pmap_remove_write() to wait for
7653 * that eventual TLB invalidation.
7656 pmap_remove_pages(pmap_t pmap)
7659 pt_entry_t *pte, tpte;
7660 pt_entry_t PG_M, PG_RW, PG_V;
7661 struct spglist free;
7662 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7663 vm_page_t m, mpte, mt;
7665 struct md_page *pvh;
7666 struct pv_chunk *pc, *npc;
7667 struct rwlock *lock;
7669 uint64_t inuse, bitmask;
7670 int allfree, field, freed, i, idx;
7671 boolean_t superpage;
7675 * Assert that the given pmap is only active on the current
7676 * CPU. Unfortunately, we cannot block another CPU from
7677 * activating the pmap while this function is executing.
7679 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7682 cpuset_t other_cpus;
7684 other_cpus = all_cpus;
7686 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7687 CPU_AND(&other_cpus, &pmap->pm_active);
7689 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7694 PG_M = pmap_modified_bit(pmap);
7695 PG_V = pmap_valid_bit(pmap);
7696 PG_RW = pmap_rw_bit(pmap);
7698 for (i = 0; i < PMAP_MEMDOM; i++)
7699 TAILQ_INIT(&free_chunks[i]);
7702 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7705 for (field = 0; field < _NPCM; field++) {
7706 inuse = ~pc->pc_map[field] & pc_freemask[field];
7707 while (inuse != 0) {
7709 bitmask = 1UL << bit;
7710 idx = field * 64 + bit;
7711 pv = &pc->pc_pventry[idx];
7714 pte = pmap_pdpe(pmap, pv->pv_va);
7716 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7718 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7721 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7723 pte = &pte[pmap_pte_index(pv->pv_va)];
7727 * Keep track whether 'tpte' is a
7728 * superpage explicitly instead of
7729 * relying on PG_PS being set.
7731 * This is because PG_PS is numerically
7732 * identical to PG_PTE_PAT and thus a
7733 * regular page could be mistaken for
7739 if ((tpte & PG_V) == 0) {
7740 panic("bad pte va %lx pte %lx",
7745 * We cannot remove wired pages from a process' mapping at this time
7753 pa = tpte & PG_PS_FRAME;
7755 pa = tpte & PG_FRAME;
7757 m = PHYS_TO_VM_PAGE(pa);
7758 KASSERT(m->phys_addr == pa,
7759 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7760 m, (uintmax_t)m->phys_addr,
7763 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7764 m < &vm_page_array[vm_page_array_size],
7765 ("pmap_remove_pages: bad tpte %#jx",
7771 * Update the vm_page_t clean/reference bits.
7773 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7775 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7781 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7784 pc->pc_map[field] |= bitmask;
7786 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7787 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7788 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7790 if (TAILQ_EMPTY(&pvh->pv_list)) {
7791 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7792 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7793 TAILQ_EMPTY(&mt->md.pv_list))
7794 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7796 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7798 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7799 ("pmap_remove_pages: pte page not promoted"));
7800 pmap_resident_count_dec(pmap, 1);
7801 KASSERT(mpte->ref_count == NPTEPG,
7802 ("pmap_remove_pages: pte page reference count error"));
7803 mpte->ref_count = 0;
7804 pmap_add_delayed_free_list(mpte, &free, FALSE);
7807 pmap_resident_count_dec(pmap, 1);
7808 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7810 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
7811 TAILQ_EMPTY(&m->md.pv_list) &&
7812 (m->flags & PG_FICTITIOUS) == 0) {
7813 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7814 if (TAILQ_EMPTY(&pvh->pv_list))
7815 vm_page_aflag_clear(m, PGA_WRITEABLE);
7818 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7822 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7823 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7824 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7826 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7827 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7832 pmap_invalidate_all(pmap);
7833 pmap_pkru_deassign_all(pmap);
7834 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7836 vm_page_free_pages_toq(&free, true);
7840 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7842 struct rwlock *lock;
7844 struct md_page *pvh;
7845 pt_entry_t *pte, mask;
7846 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7848 int md_gen, pvh_gen;
7852 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7855 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7857 if (!PMAP_TRYLOCK(pmap)) {
7858 md_gen = m->md.pv_gen;
7862 if (md_gen != m->md.pv_gen) {
7867 pte = pmap_pte(pmap, pv->pv_va);
7870 PG_M = pmap_modified_bit(pmap);
7871 PG_RW = pmap_rw_bit(pmap);
7872 mask |= PG_RW | PG_M;
7875 PG_A = pmap_accessed_bit(pmap);
7876 PG_V = pmap_valid_bit(pmap);
7877 mask |= PG_V | PG_A;
7879 rv = (*pte & mask) == mask;
7884 if ((m->flags & PG_FICTITIOUS) == 0) {
7885 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7886 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7888 if (!PMAP_TRYLOCK(pmap)) {
7889 md_gen = m->md.pv_gen;
7890 pvh_gen = pvh->pv_gen;
7894 if (md_gen != m->md.pv_gen ||
7895 pvh_gen != pvh->pv_gen) {
7900 pte = pmap_pde(pmap, pv->pv_va);
7903 PG_M = pmap_modified_bit(pmap);
7904 PG_RW = pmap_rw_bit(pmap);
7905 mask |= PG_RW | PG_M;
7908 PG_A = pmap_accessed_bit(pmap);
7909 PG_V = pmap_valid_bit(pmap);
7910 mask |= PG_V | PG_A;
7912 rv = (*pte & mask) == mask;
7926 * Return whether or not the specified physical page was modified
7927 * in any physical maps.
7930 pmap_is_modified(vm_page_t m)
7933 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7934 ("pmap_is_modified: page %p is not managed", m));
7937 * If the page is not busied then this check is racy.
7939 if (!pmap_page_is_write_mapped(m))
7941 return (pmap_page_test_mappings(m, FALSE, TRUE));
7945 * pmap_is_prefaultable:
7947 * Return whether or not the specified virtual address is eligible
7951 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7954 pt_entry_t *pte, PG_V;
7957 PG_V = pmap_valid_bit(pmap);
7960 pde = pmap_pde(pmap, addr);
7961 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7962 pte = pmap_pde_to_pte(pde, addr);
7963 rv = (*pte & PG_V) == 0;
7970 * pmap_is_referenced:
7972 * Return whether or not the specified physical page was referenced
7973 * in any physical maps.
7976 pmap_is_referenced(vm_page_t m)
7979 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7980 ("pmap_is_referenced: page %p is not managed", m));
7981 return (pmap_page_test_mappings(m, TRUE, FALSE));
7985 * Clear the write and modified bits in each of the given page's mappings.
7988 pmap_remove_write(vm_page_t m)
7990 struct md_page *pvh;
7992 struct rwlock *lock;
7993 pv_entry_t next_pv, pv;
7995 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7997 int pvh_gen, md_gen;
7999 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8000 ("pmap_remove_write: page %p is not managed", m));
8002 vm_page_assert_busied(m);
8003 if (!pmap_page_is_write_mapped(m))
8006 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8007 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8008 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8011 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8013 if (!PMAP_TRYLOCK(pmap)) {
8014 pvh_gen = pvh->pv_gen;
8018 if (pvh_gen != pvh->pv_gen) {
8024 PG_RW = pmap_rw_bit(pmap);
8026 pde = pmap_pde(pmap, va);
8027 if ((*pde & PG_RW) != 0)
8028 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8029 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8030 ("inconsistent pv lock %p %p for page %p",
8031 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8034 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8036 if (!PMAP_TRYLOCK(pmap)) {
8037 pvh_gen = pvh->pv_gen;
8038 md_gen = m->md.pv_gen;
8042 if (pvh_gen != pvh->pv_gen ||
8043 md_gen != m->md.pv_gen) {
8049 PG_M = pmap_modified_bit(pmap);
8050 PG_RW = pmap_rw_bit(pmap);
8051 pde = pmap_pde(pmap, pv->pv_va);
8052 KASSERT((*pde & PG_PS) == 0,
8053 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8055 pte = pmap_pde_to_pte(pde, pv->pv_va);
8058 if (oldpte & PG_RW) {
8059 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8062 if ((oldpte & PG_M) != 0)
8064 pmap_invalidate_page(pmap, pv->pv_va);
8069 vm_page_aflag_clear(m, PGA_WRITEABLE);
8070 pmap_delayed_invl_wait(m);
8073 static __inline boolean_t
8074 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8077 if (!pmap_emulate_ad_bits(pmap))
8080 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8083 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8084 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8085 * if the EPT_PG_WRITE bit is set.
8087 if ((pte & EPT_PG_WRITE) != 0)
8091 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8093 if ((pte & EPT_PG_EXECUTE) == 0 ||
8094 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8101 * pmap_ts_referenced:
8103 * Return a count of reference bits for a page, clearing those bits.
8104 * It is not necessary for every reference bit to be cleared, but it
8105 * is necessary that 0 only be returned when there are truly no
8106 * reference bits set.
8108 * As an optimization, update the page's dirty field if a modified bit is
8109 * found while counting reference bits. This opportunistic update can be
8110 * performed at low cost and can eliminate the need for some future calls
8111 * to pmap_is_modified(). However, since this function stops after
8112 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8113 * dirty pages. Those dirty pages will only be detected by a future call
8114 * to pmap_is_modified().
8116 * A DI block is not needed within this function, because
8117 * invalidations are performed before the PV list lock is
8121 pmap_ts_referenced(vm_page_t m)
8123 struct md_page *pvh;
8126 struct rwlock *lock;
8127 pd_entry_t oldpde, *pde;
8128 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8131 int cleared, md_gen, not_cleared, pvh_gen;
8132 struct spglist free;
8135 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8136 ("pmap_ts_referenced: page %p is not managed", m));
8139 pa = VM_PAGE_TO_PHYS(m);
8140 lock = PHYS_TO_PV_LIST_LOCK(pa);
8141 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8145 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8146 goto small_mappings;
8152 if (!PMAP_TRYLOCK(pmap)) {
8153 pvh_gen = pvh->pv_gen;
8157 if (pvh_gen != pvh->pv_gen) {
8162 PG_A = pmap_accessed_bit(pmap);
8163 PG_M = pmap_modified_bit(pmap);
8164 PG_RW = pmap_rw_bit(pmap);
8166 pde = pmap_pde(pmap, pv->pv_va);
8168 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8170 * Although "oldpde" is mapping a 2MB page, because
8171 * this function is called at a 4KB page granularity,
8172 * we only update the 4KB page under test.
8176 if ((oldpde & PG_A) != 0) {
8178 * Since this reference bit is shared by 512 4KB
8179 * pages, it should not be cleared every time it is
8180 * tested. Apply a simple "hash" function on the
8181 * physical page number, the virtual superpage number,
8182 * and the pmap address to select one 4KB page out of
8183 * the 512 on which testing the reference bit will
8184 * result in clearing that reference bit. This
8185 * function is designed to avoid the selection of the
8186 * same 4KB page for every 2MB page mapping.
8188 * On demotion, a mapping that hasn't been referenced
8189 * is simply destroyed. To avoid the possibility of a
8190 * subsequent page fault on a demoted wired mapping,
8191 * always leave its reference bit set. Moreover,
8192 * since the superpage is wired, the current state of
8193 * its reference bit won't affect page replacement.
8195 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8196 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8197 (oldpde & PG_W) == 0) {
8198 if (safe_to_clear_referenced(pmap, oldpde)) {
8199 atomic_clear_long(pde, PG_A);
8200 pmap_invalidate_page(pmap, pv->pv_va);
8202 } else if (pmap_demote_pde_locked(pmap, pde,
8203 pv->pv_va, &lock)) {
8205 * Remove the mapping to a single page
8206 * so that a subsequent access may
8207 * repromote. Since the underlying
8208 * page table page is fully populated,
8209 * this removal never frees a page
8213 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8215 pte = pmap_pde_to_pte(pde, va);
8216 pmap_remove_pte(pmap, pte, va, *pde,
8218 pmap_invalidate_page(pmap, va);
8224 * The superpage mapping was removed
8225 * entirely and therefore 'pv' is no
8233 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8234 ("inconsistent pv lock %p %p for page %p",
8235 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8240 /* Rotate the PV list if it has more than one entry. */
8241 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8242 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8243 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8246 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8248 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8250 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8257 if (!PMAP_TRYLOCK(pmap)) {
8258 pvh_gen = pvh->pv_gen;
8259 md_gen = m->md.pv_gen;
8263 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8268 PG_A = pmap_accessed_bit(pmap);
8269 PG_M = pmap_modified_bit(pmap);
8270 PG_RW = pmap_rw_bit(pmap);
8271 pde = pmap_pde(pmap, pv->pv_va);
8272 KASSERT((*pde & PG_PS) == 0,
8273 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8275 pte = pmap_pde_to_pte(pde, pv->pv_va);
8276 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8278 if ((*pte & PG_A) != 0) {
8279 if (safe_to_clear_referenced(pmap, *pte)) {
8280 atomic_clear_long(pte, PG_A);
8281 pmap_invalidate_page(pmap, pv->pv_va);
8283 } else if ((*pte & PG_W) == 0) {
8285 * Wired pages cannot be paged out so
8286 * doing accessed bit emulation for
8287 * them is wasted effort. We do the
8288 * hard work for unwired pages only.
8290 pmap_remove_pte(pmap, pte, pv->pv_va,
8291 *pde, &free, &lock);
8292 pmap_invalidate_page(pmap, pv->pv_va);
8297 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8298 ("inconsistent pv lock %p %p for page %p",
8299 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8304 /* Rotate the PV list if it has more than one entry. */
8305 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8306 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8307 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8310 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8311 not_cleared < PMAP_TS_REFERENCED_MAX);
8314 vm_page_free_pages_toq(&free, true);
8315 return (cleared + not_cleared);
8319 * Apply the given advice to the specified range of addresses within the
8320 * given pmap. Depending on the advice, clear the referenced and/or
8321 * modified flags in each mapping and set the mapped page's dirty field.
8324 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8326 struct rwlock *lock;
8327 pml4_entry_t *pml4e;
8329 pd_entry_t oldpde, *pde;
8330 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8331 vm_offset_t va, va_next;
8335 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8339 * A/D bit emulation requires an alternate code path when clearing
8340 * the modified and accessed bits below. Since this function is
8341 * advisory in nature we skip it entirely for pmaps that require
8342 * A/D bit emulation.
8344 if (pmap_emulate_ad_bits(pmap))
8347 PG_A = pmap_accessed_bit(pmap);
8348 PG_G = pmap_global_bit(pmap);
8349 PG_M = pmap_modified_bit(pmap);
8350 PG_V = pmap_valid_bit(pmap);
8351 PG_RW = pmap_rw_bit(pmap);
8353 pmap_delayed_invl_start();
8355 for (; sva < eva; sva = va_next) {
8356 pml4e = pmap_pml4e(pmap, sva);
8357 if ((*pml4e & PG_V) == 0) {
8358 va_next = (sva + NBPML4) & ~PML4MASK;
8363 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8364 if ((*pdpe & PG_V) == 0) {
8365 va_next = (sva + NBPDP) & ~PDPMASK;
8370 va_next = (sva + NBPDR) & ~PDRMASK;
8373 pde = pmap_pdpe_to_pde(pdpe, sva);
8375 if ((oldpde & PG_V) == 0)
8377 else if ((oldpde & PG_PS) != 0) {
8378 if ((oldpde & PG_MANAGED) == 0)
8381 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8386 * The large page mapping was destroyed.
8392 * Unless the page mappings are wired, remove the
8393 * mapping to a single page so that a subsequent
8394 * access may repromote. Choosing the last page
8395 * within the address range [sva, min(va_next, eva))
8396 * generally results in more repromotions. Since the
8397 * underlying page table page is fully populated, this
8398 * removal never frees a page table page.
8400 if ((oldpde & PG_W) == 0) {
8406 ("pmap_advise: no address gap"));
8407 pte = pmap_pde_to_pte(pde, va);
8408 KASSERT((*pte & PG_V) != 0,
8409 ("pmap_advise: invalid PTE"));
8410 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8420 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8422 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8424 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8425 if (advice == MADV_DONTNEED) {
8427 * Future calls to pmap_is_modified()
8428 * can be avoided by making the page
8431 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8434 atomic_clear_long(pte, PG_M | PG_A);
8435 } else if ((*pte & PG_A) != 0)
8436 atomic_clear_long(pte, PG_A);
8440 if ((*pte & PG_G) != 0) {
8447 if (va != va_next) {
8448 pmap_invalidate_range(pmap, va, sva);
8453 pmap_invalidate_range(pmap, va, sva);
8456 pmap_invalidate_all(pmap);
8458 pmap_delayed_invl_finish();
8462 * Clear the modify bits on the specified physical page.
8465 pmap_clear_modify(vm_page_t m)
8467 struct md_page *pvh;
8469 pv_entry_t next_pv, pv;
8470 pd_entry_t oldpde, *pde;
8471 pt_entry_t *pte, PG_M, PG_RW;
8472 struct rwlock *lock;
8474 int md_gen, pvh_gen;
8476 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8477 ("pmap_clear_modify: page %p is not managed", m));
8478 vm_page_assert_busied(m);
8480 if (!pmap_page_is_write_mapped(m))
8482 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8483 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8484 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8487 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8489 if (!PMAP_TRYLOCK(pmap)) {
8490 pvh_gen = pvh->pv_gen;
8494 if (pvh_gen != pvh->pv_gen) {
8499 PG_M = pmap_modified_bit(pmap);
8500 PG_RW = pmap_rw_bit(pmap);
8502 pde = pmap_pde(pmap, va);
8504 /* If oldpde has PG_RW set, then it also has PG_M set. */
8505 if ((oldpde & PG_RW) != 0 &&
8506 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8507 (oldpde & PG_W) == 0) {
8509 * Write protect the mapping to a single page so that
8510 * a subsequent write access may repromote.
8512 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8513 pte = pmap_pde_to_pte(pde, va);
8514 atomic_clear_long(pte, PG_M | PG_RW);
8516 pmap_invalidate_page(pmap, va);
8520 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8522 if (!PMAP_TRYLOCK(pmap)) {
8523 md_gen = m->md.pv_gen;
8524 pvh_gen = pvh->pv_gen;
8528 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8533 PG_M = pmap_modified_bit(pmap);
8534 PG_RW = pmap_rw_bit(pmap);
8535 pde = pmap_pde(pmap, pv->pv_va);
8536 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8537 " a 2mpage in page %p's pv list", m));
8538 pte = pmap_pde_to_pte(pde, pv->pv_va);
8539 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8540 atomic_clear_long(pte, PG_M);
8541 pmap_invalidate_page(pmap, pv->pv_va);
8549 * Miscellaneous support routines follow
8552 /* Adjust the properties for a leaf page table entry. */
8553 static __inline void
8554 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8558 opte = *(u_long *)pte;
8560 npte = opte & ~mask;
8562 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8567 * Map a set of physical memory pages into the kernel virtual
8568 * address space. Return a pointer to where it is mapped. This
8569 * routine is intended to be used for mapping device memory,
8573 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8575 struct pmap_preinit_mapping *ppim;
8576 vm_offset_t va, offset;
8580 offset = pa & PAGE_MASK;
8581 size = round_page(offset + size);
8582 pa = trunc_page(pa);
8584 if (!pmap_initialized) {
8586 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8587 ppim = pmap_preinit_mapping + i;
8588 if (ppim->va == 0) {
8592 ppim->va = virtual_avail;
8593 virtual_avail += size;
8599 panic("%s: too many preinit mappings", __func__);
8602 * If we have a preinit mapping, re-use it.
8604 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8605 ppim = pmap_preinit_mapping + i;
8606 if (ppim->pa == pa && ppim->sz == size &&
8607 (ppim->mode == mode ||
8608 (flags & MAPDEV_SETATTR) == 0))
8609 return ((void *)(ppim->va + offset));
8612 * If the specified range of physical addresses fits within
8613 * the direct map window, use the direct map.
8615 if (pa < dmaplimit && pa + size <= dmaplimit) {
8616 va = PHYS_TO_DMAP(pa);
8617 if ((flags & MAPDEV_SETATTR) != 0) {
8618 PMAP_LOCK(kernel_pmap);
8619 i = pmap_change_props_locked(va, size,
8620 PROT_NONE, mode, flags);
8621 PMAP_UNLOCK(kernel_pmap);
8625 return ((void *)(va + offset));
8627 va = kva_alloc(size);
8629 panic("%s: Couldn't allocate KVA", __func__);
8631 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8632 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8633 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8634 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8635 pmap_invalidate_cache_range(va, va + tmpsize);
8636 return ((void *)(va + offset));
8640 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8643 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8648 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8651 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8655 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8658 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8663 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8666 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8667 MAPDEV_FLUSHCACHE));
8671 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8673 struct pmap_preinit_mapping *ppim;
8677 /* If we gave a direct map region in pmap_mapdev, do nothing */
8678 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8680 offset = va & PAGE_MASK;
8681 size = round_page(offset + size);
8682 va = trunc_page(va);
8683 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8684 ppim = pmap_preinit_mapping + i;
8685 if (ppim->va == va && ppim->sz == size) {
8686 if (pmap_initialized)
8692 if (va + size == virtual_avail)
8697 if (pmap_initialized) {
8698 pmap_qremove(va, atop(size));
8704 * Tries to demote a 1GB page mapping.
8707 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8709 pdp_entry_t newpdpe, oldpdpe;
8710 pd_entry_t *firstpde, newpde, *pde;
8711 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8715 PG_A = pmap_accessed_bit(pmap);
8716 PG_M = pmap_modified_bit(pmap);
8717 PG_V = pmap_valid_bit(pmap);
8718 PG_RW = pmap_rw_bit(pmap);
8720 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8722 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8723 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8724 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8725 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8726 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8727 " in pmap %p", va, pmap);
8730 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8731 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8732 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8733 KASSERT((oldpdpe & PG_A) != 0,
8734 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8735 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8736 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8740 * Initialize the page directory page.
8742 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8748 * Demote the mapping.
8753 * Invalidate a stale recursive mapping of the page directory page.
8755 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8757 pmap_pdpe_demotions++;
8758 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8759 " in pmap %p", va, pmap);
8764 * Sets the memory attribute for the specified page.
8767 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8770 m->md.pat_mode = ma;
8773 * If "m" is a normal page, update its direct mapping. This update
8774 * can be relied upon to perform any cache operations that are
8775 * required for data coherence.
8777 if ((m->flags & PG_FICTITIOUS) == 0 &&
8778 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8780 panic("memory attribute change on the direct map failed");
8784 * Changes the specified virtual address range's memory type to that given by
8785 * the parameter "mode". The specified virtual address range must be
8786 * completely contained within either the direct map or the kernel map. If
8787 * the virtual address range is contained within the kernel map, then the
8788 * memory type for each of the corresponding ranges of the direct map is also
8789 * changed. (The corresponding ranges of the direct map are those ranges that
8790 * map the same physical pages as the specified virtual address range.) These
8791 * changes to the direct map are necessary because Intel describes the
8792 * behavior of their processors as "undefined" if two or more mappings to the
8793 * same physical page have different memory types.
8795 * Returns zero if the change completed successfully, and either EINVAL or
8796 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8797 * of the virtual address range was not mapped, and ENOMEM is returned if
8798 * there was insufficient memory available to complete the change. In the
8799 * latter case, the memory type may have been changed on some part of the
8800 * virtual address range or the direct map.
8803 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8807 PMAP_LOCK(kernel_pmap);
8808 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8810 PMAP_UNLOCK(kernel_pmap);
8815 * Changes the specified virtual address range's protections to those
8816 * specified by "prot". Like pmap_change_attr(), protections for aliases
8817 * in the direct map are updated as well. Protections on aliasing mappings may
8818 * be a subset of the requested protections; for example, mappings in the direct
8819 * map are never executable.
8822 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8826 /* Only supported within the kernel map. */
8827 if (va < VM_MIN_KERNEL_ADDRESS)
8830 PMAP_LOCK(kernel_pmap);
8831 error = pmap_change_props_locked(va, size, prot, -1,
8832 MAPDEV_ASSERTVALID);
8833 PMAP_UNLOCK(kernel_pmap);
8838 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8839 int mode, int flags)
8841 vm_offset_t base, offset, tmpva;
8842 vm_paddr_t pa_start, pa_end, pa_end1;
8844 pd_entry_t *pde, pde_bits, pde_mask;
8845 pt_entry_t *pte, pte_bits, pte_mask;
8849 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8850 base = trunc_page(va);
8851 offset = va & PAGE_MASK;
8852 size = round_page(offset + size);
8855 * Only supported on kernel virtual addresses, including the direct
8856 * map but excluding the recursive map.
8858 if (base < DMAP_MIN_ADDRESS)
8862 * Construct our flag sets and masks. "bits" is the subset of
8863 * "mask" that will be set in each modified PTE.
8865 * Mappings in the direct map are never allowed to be executable.
8867 pde_bits = pte_bits = 0;
8868 pde_mask = pte_mask = 0;
8870 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8871 pde_mask |= X86_PG_PDE_CACHE;
8872 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8873 pte_mask |= X86_PG_PTE_CACHE;
8875 if (prot != VM_PROT_NONE) {
8876 if ((prot & VM_PROT_WRITE) != 0) {
8877 pde_bits |= X86_PG_RW;
8878 pte_bits |= X86_PG_RW;
8880 if ((prot & VM_PROT_EXECUTE) == 0 ||
8881 va < VM_MIN_KERNEL_ADDRESS) {
8885 pde_mask |= X86_PG_RW | pg_nx;
8886 pte_mask |= X86_PG_RW | pg_nx;
8890 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8891 * into 4KB pages if required.
8893 for (tmpva = base; tmpva < base + size; ) {
8894 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8895 if (pdpe == NULL || *pdpe == 0) {
8896 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8897 ("%s: addr %#lx is not mapped", __func__, tmpva));
8900 if (*pdpe & PG_PS) {
8902 * If the current 1GB page already has the required
8903 * properties, then we need not demote this page. Just
8904 * increment tmpva to the next 1GB page frame.
8906 if ((*pdpe & pde_mask) == pde_bits) {
8907 tmpva = trunc_1gpage(tmpva) + NBPDP;
8912 * If the current offset aligns with a 1GB page frame
8913 * and there is at least 1GB left within the range, then
8914 * we need not break down this page into 2MB pages.
8916 if ((tmpva & PDPMASK) == 0 &&
8917 tmpva + PDPMASK < base + size) {
8921 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8924 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8926 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8927 ("%s: addr %#lx is not mapped", __func__, tmpva));
8932 * If the current 2MB page already has the required
8933 * properties, then we need not demote this page. Just
8934 * increment tmpva to the next 2MB page frame.
8936 if ((*pde & pde_mask) == pde_bits) {
8937 tmpva = trunc_2mpage(tmpva) + NBPDR;
8942 * If the current offset aligns with a 2MB page frame
8943 * and there is at least 2MB left within the range, then
8944 * we need not break down this page into 4KB pages.
8946 if ((tmpva & PDRMASK) == 0 &&
8947 tmpva + PDRMASK < base + size) {
8951 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8954 pte = pmap_pde_to_pte(pde, tmpva);
8956 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8957 ("%s: addr %#lx is not mapped", __func__, tmpva));
8965 * Ok, all the pages exist, so run through them updating their
8966 * properties if required.
8969 pa_start = pa_end = 0;
8970 for (tmpva = base; tmpva < base + size; ) {
8971 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8972 if (*pdpe & PG_PS) {
8973 if ((*pdpe & pde_mask) != pde_bits) {
8974 pmap_pte_props(pdpe, pde_bits, pde_mask);
8977 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8978 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8979 if (pa_start == pa_end) {
8980 /* Start physical address run. */
8981 pa_start = *pdpe & PG_PS_FRAME;
8982 pa_end = pa_start + NBPDP;
8983 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8986 /* Run ended, update direct map. */
8987 error = pmap_change_props_locked(
8988 PHYS_TO_DMAP(pa_start),
8989 pa_end - pa_start, prot, mode,
8993 /* Start physical address run. */
8994 pa_start = *pdpe & PG_PS_FRAME;
8995 pa_end = pa_start + NBPDP;
8998 tmpva = trunc_1gpage(tmpva) + NBPDP;
9001 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9003 if ((*pde & pde_mask) != pde_bits) {
9004 pmap_pte_props(pde, pde_bits, pde_mask);
9007 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9008 (*pde & PG_PS_FRAME) < dmaplimit) {
9009 if (pa_start == pa_end) {
9010 /* Start physical address run. */
9011 pa_start = *pde & PG_PS_FRAME;
9012 pa_end = pa_start + NBPDR;
9013 } else if (pa_end == (*pde & PG_PS_FRAME))
9016 /* Run ended, update direct map. */
9017 error = pmap_change_props_locked(
9018 PHYS_TO_DMAP(pa_start),
9019 pa_end - pa_start, prot, mode,
9023 /* Start physical address run. */
9024 pa_start = *pde & PG_PS_FRAME;
9025 pa_end = pa_start + NBPDR;
9028 tmpva = trunc_2mpage(tmpva) + NBPDR;
9030 pte = pmap_pde_to_pte(pde, tmpva);
9031 if ((*pte & pte_mask) != pte_bits) {
9032 pmap_pte_props(pte, pte_bits, pte_mask);
9035 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9036 (*pte & PG_FRAME) < dmaplimit) {
9037 if (pa_start == pa_end) {
9038 /* Start physical address run. */
9039 pa_start = *pte & PG_FRAME;
9040 pa_end = pa_start + PAGE_SIZE;
9041 } else if (pa_end == (*pte & PG_FRAME))
9042 pa_end += PAGE_SIZE;
9044 /* Run ended, update direct map. */
9045 error = pmap_change_props_locked(
9046 PHYS_TO_DMAP(pa_start),
9047 pa_end - pa_start, prot, mode,
9051 /* Start physical address run. */
9052 pa_start = *pte & PG_FRAME;
9053 pa_end = pa_start + PAGE_SIZE;
9059 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9060 pa_end1 = MIN(pa_end, dmaplimit);
9061 if (pa_start != pa_end1)
9062 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9063 pa_end1 - pa_start, prot, mode, flags);
9067 * Flush CPU caches if required to make sure any data isn't cached that
9068 * shouldn't be, etc.
9071 pmap_invalidate_range(kernel_pmap, base, tmpva);
9072 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9073 pmap_invalidate_cache_range(base, tmpva);
9079 * Demotes any mapping within the direct map region that covers more than the
9080 * specified range of physical addresses. This range's size must be a power
9081 * of two and its starting address must be a multiple of its size. Since the
9082 * demotion does not change any attributes of the mapping, a TLB invalidation
9083 * is not mandatory. The caller may, however, request a TLB invalidation.
9086 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9095 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9096 KASSERT((base & (len - 1)) == 0,
9097 ("pmap_demote_DMAP: base is not a multiple of len"));
9098 if (len < NBPDP && base < dmaplimit) {
9099 va = PHYS_TO_DMAP(base);
9101 PMAP_LOCK(kernel_pmap);
9102 pdpe = pmap_pdpe(kernel_pmap, va);
9103 if ((*pdpe & X86_PG_V) == 0)
9104 panic("pmap_demote_DMAP: invalid PDPE");
9105 if ((*pdpe & PG_PS) != 0) {
9106 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9107 panic("pmap_demote_DMAP: PDPE failed");
9111 pde = pmap_pdpe_to_pde(pdpe, va);
9112 if ((*pde & X86_PG_V) == 0)
9113 panic("pmap_demote_DMAP: invalid PDE");
9114 if ((*pde & PG_PS) != 0) {
9115 if (!pmap_demote_pde(kernel_pmap, pde, va))
9116 panic("pmap_demote_DMAP: PDE failed");
9120 if (changed && invalidate)
9121 pmap_invalidate_page(kernel_pmap, va);
9122 PMAP_UNLOCK(kernel_pmap);
9127 * Perform the pmap work for mincore(2). If the page is not both referenced and
9128 * modified by this pmap, returns its physical address so that the caller can
9129 * find other mappings.
9132 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9135 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9139 PG_A = pmap_accessed_bit(pmap);
9140 PG_M = pmap_modified_bit(pmap);
9141 PG_V = pmap_valid_bit(pmap);
9142 PG_RW = pmap_rw_bit(pmap);
9145 pdep = pmap_pde(pmap, addr);
9146 if (pdep != NULL && (*pdep & PG_V)) {
9147 if (*pdep & PG_PS) {
9149 /* Compute the physical address of the 4KB page. */
9150 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
9152 val = MINCORE_PSIND(1);
9154 pte = *pmap_pde_to_pte(pdep, addr);
9155 pa = pte & PG_FRAME;
9163 if ((pte & PG_V) != 0) {
9164 val |= MINCORE_INCORE;
9165 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9166 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9167 if ((pte & PG_A) != 0)
9168 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9170 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9171 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9172 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9180 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9182 uint32_t gen, new_gen, pcid_next;
9184 CRITICAL_ASSERT(curthread);
9185 gen = PCPU_GET(pcid_gen);
9186 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9187 return (pti ? 0 : CR3_PCID_SAVE);
9188 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9189 return (CR3_PCID_SAVE);
9190 pcid_next = PCPU_GET(pcid_next);
9191 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9192 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9193 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9194 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9195 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9199 PCPU_SET(pcid_gen, new_gen);
9200 pcid_next = PMAP_PCID_KERN + 1;
9204 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9205 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9206 PCPU_SET(pcid_next, pcid_next + 1);
9211 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9215 cached = pmap_pcid_alloc(pmap, cpuid);
9216 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9217 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9218 pmap->pm_pcids[cpuid].pm_pcid));
9219 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9220 pmap == kernel_pmap,
9221 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9222 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9227 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9230 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9231 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9235 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9238 uint64_t cached, cr3, kcr3, ucr3;
9240 KASSERT((read_rflags() & PSL_I) == 0,
9241 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9243 /* See the comment in pmap_invalidate_page_pcid(). */
9244 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9245 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9246 old_pmap = PCPU_GET(curpmap);
9247 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9248 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9251 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9253 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9254 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9255 PCPU_SET(curpmap, pmap);
9256 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9257 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9260 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9261 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9263 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9264 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9266 PCPU_INC(pm_save_cnt);
9268 pmap_activate_sw_pti_post(td, pmap);
9272 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9275 uint64_t cached, cr3;
9277 KASSERT((read_rflags() & PSL_I) == 0,
9278 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9280 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9282 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9283 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9285 PCPU_SET(curpmap, pmap);
9287 PCPU_INC(pm_save_cnt);
9291 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9292 u_int cpuid __unused)
9295 load_cr3(pmap->pm_cr3);
9296 PCPU_SET(curpmap, pmap);
9300 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9301 u_int cpuid __unused)
9304 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9305 PCPU_SET(kcr3, pmap->pm_cr3);
9306 PCPU_SET(ucr3, pmap->pm_ucr3);
9307 pmap_activate_sw_pti_post(td, pmap);
9310 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9314 if (pmap_pcid_enabled && pti)
9315 return (pmap_activate_sw_pcid_pti);
9316 else if (pmap_pcid_enabled && !pti)
9317 return (pmap_activate_sw_pcid_nopti);
9318 else if (!pmap_pcid_enabled && pti)
9319 return (pmap_activate_sw_nopcid_pti);
9320 else /* if (!pmap_pcid_enabled && !pti) */
9321 return (pmap_activate_sw_nopcid_nopti);
9325 pmap_activate_sw(struct thread *td)
9327 pmap_t oldpmap, pmap;
9330 oldpmap = PCPU_GET(curpmap);
9331 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9332 if (oldpmap == pmap) {
9333 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9337 cpuid = PCPU_GET(cpuid);
9339 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9341 CPU_SET(cpuid, &pmap->pm_active);
9343 pmap_activate_sw_mode(td, pmap, cpuid);
9345 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9347 CPU_CLR(cpuid, &oldpmap->pm_active);
9352 pmap_activate(struct thread *td)
9355 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9356 * invalidate_all IPI, which checks for curpmap ==
9357 * smp_tlb_pmap. The below sequence of operations has a
9358 * window where %CR3 is loaded with the new pmap's PML4
9359 * address, but the curpmap value has not yet been updated.
9360 * This causes the invltlb IPI handler, which is called
9361 * between the updates, to execute as a NOP, which leaves
9362 * stale TLB entries.
9364 * Note that the most common use of pmap_activate_sw(), from
9365 * a context switch, is immune to this race, because
9366 * interrupts are disabled (while the thread lock is owned),
9367 * so the IPI is delayed until after curpmap is updated. Protect
9368 * other callers in a similar way, by disabling interrupts
9369 * around the %cr3 register reload and curpmap assignment.
9372 pmap_activate_sw(td);
9377 pmap_activate_boot(pmap_t pmap)
9383 * kernel_pmap must be never deactivated, and we ensure that
9384 * by never activating it at all.
9386 MPASS(pmap != kernel_pmap);
9388 cpuid = PCPU_GET(cpuid);
9390 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9392 CPU_SET(cpuid, &pmap->pm_active);
9394 PCPU_SET(curpmap, pmap);
9396 kcr3 = pmap->pm_cr3;
9397 if (pmap_pcid_enabled)
9398 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9402 PCPU_SET(kcr3, kcr3);
9403 PCPU_SET(ucr3, PMAP_NO_CR3);
9407 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9412 * Increase the starting virtual address of the given mapping if a
9413 * different alignment might result in more superpage mappings.
9416 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9417 vm_offset_t *addr, vm_size_t size)
9419 vm_offset_t superpage_offset;
9423 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9424 offset += ptoa(object->pg_color);
9425 superpage_offset = offset & PDRMASK;
9426 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9427 (*addr & PDRMASK) == superpage_offset)
9429 if ((*addr & PDRMASK) < superpage_offset)
9430 *addr = (*addr & ~PDRMASK) + superpage_offset;
9432 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9436 static unsigned long num_dirty_emulations;
9437 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9438 &num_dirty_emulations, 0, NULL);
9440 static unsigned long num_accessed_emulations;
9441 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9442 &num_accessed_emulations, 0, NULL);
9444 static unsigned long num_superpage_accessed_emulations;
9445 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9446 &num_superpage_accessed_emulations, 0, NULL);
9448 static unsigned long ad_emulation_superpage_promotions;
9449 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9450 &ad_emulation_superpage_promotions, 0, NULL);
9451 #endif /* INVARIANTS */
9454 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9457 struct rwlock *lock;
9458 #if VM_NRESERVLEVEL > 0
9462 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9464 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9465 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9467 if (!pmap_emulate_ad_bits(pmap))
9470 PG_A = pmap_accessed_bit(pmap);
9471 PG_M = pmap_modified_bit(pmap);
9472 PG_V = pmap_valid_bit(pmap);
9473 PG_RW = pmap_rw_bit(pmap);
9479 pde = pmap_pde(pmap, va);
9480 if (pde == NULL || (*pde & PG_V) == 0)
9483 if ((*pde & PG_PS) != 0) {
9484 if (ftype == VM_PROT_READ) {
9486 atomic_add_long(&num_superpage_accessed_emulations, 1);
9494 pte = pmap_pde_to_pte(pde, va);
9495 if ((*pte & PG_V) == 0)
9498 if (ftype == VM_PROT_WRITE) {
9499 if ((*pte & PG_RW) == 0)
9502 * Set the modified and accessed bits simultaneously.
9504 * Intel EPT PTEs that do software emulation of A/D bits map
9505 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9506 * An EPT misconfiguration is triggered if the PTE is writable
9507 * but not readable (WR=10). This is avoided by setting PG_A
9508 * and PG_M simultaneously.
9510 *pte |= PG_M | PG_A;
9515 #if VM_NRESERVLEVEL > 0
9516 /* try to promote the mapping */
9517 if (va < VM_MAXUSER_ADDRESS)
9518 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9522 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9524 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9525 pmap_ps_enabled(pmap) &&
9526 (m->flags & PG_FICTITIOUS) == 0 &&
9527 vm_reserv_level_iffullpop(m) == 0) {
9528 pmap_promote_pde(pmap, pde, va, &lock);
9530 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9536 if (ftype == VM_PROT_WRITE)
9537 atomic_add_long(&num_dirty_emulations, 1);
9539 atomic_add_long(&num_accessed_emulations, 1);
9541 rv = 0; /* success */
9550 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9555 pt_entry_t *pte, PG_V;
9559 PG_V = pmap_valid_bit(pmap);
9562 pml4 = pmap_pml4e(pmap, va);
9564 if ((*pml4 & PG_V) == 0)
9567 pdp = pmap_pml4e_to_pdpe(pml4, va);
9569 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9572 pde = pmap_pdpe_to_pde(pdp, va);
9574 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9577 pte = pmap_pde_to_pte(pde, va);
9586 * Get the kernel virtual address of a set of physical pages. If there are
9587 * physical addresses not covered by the DMAP perform a transient mapping
9588 * that will be removed when calling pmap_unmap_io_transient.
9590 * \param page The pages the caller wishes to obtain the virtual
9591 * address on the kernel memory map.
9592 * \param vaddr On return contains the kernel virtual memory address
9593 * of the pages passed in the page parameter.
9594 * \param count Number of pages passed in.
9595 * \param can_fault TRUE if the thread using the mapped pages can take
9596 * page faults, FALSE otherwise.
9598 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9599 * finished or FALSE otherwise.
9603 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9604 boolean_t can_fault)
9607 boolean_t needs_mapping;
9609 int cache_bits, error __unused, i;
9612 * Allocate any KVA space that we need, this is done in a separate
9613 * loop to prevent calling vmem_alloc while pinned.
9615 needs_mapping = FALSE;
9616 for (i = 0; i < count; i++) {
9617 paddr = VM_PAGE_TO_PHYS(page[i]);
9618 if (__predict_false(paddr >= dmaplimit)) {
9619 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9620 M_BESTFIT | M_WAITOK, &vaddr[i]);
9621 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9622 needs_mapping = TRUE;
9624 vaddr[i] = PHYS_TO_DMAP(paddr);
9628 /* Exit early if everything is covered by the DMAP */
9633 * NB: The sequence of updating a page table followed by accesses
9634 * to the corresponding pages used in the !DMAP case is subject to
9635 * the situation described in the "AMD64 Architecture Programmer's
9636 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9637 * Coherency Considerations". Therefore, issuing the INVLPG right
9638 * after modifying the PTE bits is crucial.
9642 for (i = 0; i < count; i++) {
9643 paddr = VM_PAGE_TO_PHYS(page[i]);
9644 if (paddr >= dmaplimit) {
9647 * Slow path, since we can get page faults
9648 * while mappings are active don't pin the
9649 * thread to the CPU and instead add a global
9650 * mapping visible to all CPUs.
9652 pmap_qenter(vaddr[i], &page[i], 1);
9654 pte = vtopte(vaddr[i]);
9655 cache_bits = pmap_cache_bits(kernel_pmap,
9656 page[i]->md.pat_mode, 0);
9657 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9664 return (needs_mapping);
9668 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9669 boolean_t can_fault)
9676 for (i = 0; i < count; i++) {
9677 paddr = VM_PAGE_TO_PHYS(page[i]);
9678 if (paddr >= dmaplimit) {
9680 pmap_qremove(vaddr[i], 1);
9681 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9687 pmap_quick_enter_page(vm_page_t m)
9691 paddr = VM_PAGE_TO_PHYS(m);
9692 if (paddr < dmaplimit)
9693 return (PHYS_TO_DMAP(paddr));
9694 mtx_lock_spin(&qframe_mtx);
9695 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9696 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9697 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9702 pmap_quick_remove_page(vm_offset_t addr)
9707 pte_store(vtopte(qframe), 0);
9709 mtx_unlock_spin(&qframe_mtx);
9713 * Pdp pages from the large map are managed differently from either
9714 * kernel or user page table pages. They are permanently allocated at
9715 * initialization time, and their reference count is permanently set to
9716 * zero. The pml4 entries pointing to those pages are copied into
9717 * each allocated pmap.
9719 * In contrast, pd and pt pages are managed like user page table
9720 * pages. They are dynamically allocated, and their reference count
9721 * represents the number of valid entries within the page.
9724 pmap_large_map_getptp_unlocked(void)
9728 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9730 if (m != NULL && (m->flags & PG_ZERO) == 0)
9736 pmap_large_map_getptp(void)
9740 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9741 m = pmap_large_map_getptp_unlocked();
9743 PMAP_UNLOCK(kernel_pmap);
9745 PMAP_LOCK(kernel_pmap);
9746 /* Callers retry. */
9751 static pdp_entry_t *
9752 pmap_large_map_pdpe(vm_offset_t va)
9754 vm_pindex_t pml4_idx;
9757 pml4_idx = pmap_pml4e_index(va);
9758 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9759 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9761 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9762 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
9763 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9764 "LMSPML4I %#jx lm_ents %d",
9765 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9766 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
9767 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9771 pmap_large_map_pde(vm_offset_t va)
9778 pdpe = pmap_large_map_pdpe(va);
9780 m = pmap_large_map_getptp();
9783 mphys = VM_PAGE_TO_PHYS(m);
9784 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9786 MPASS((*pdpe & X86_PG_PS) == 0);
9787 mphys = *pdpe & PG_FRAME;
9789 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9793 pmap_large_map_pte(vm_offset_t va)
9800 pde = pmap_large_map_pde(va);
9802 m = pmap_large_map_getptp();
9805 mphys = VM_PAGE_TO_PHYS(m);
9806 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9807 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9809 MPASS((*pde & X86_PG_PS) == 0);
9810 mphys = *pde & PG_FRAME;
9812 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9816 pmap_large_map_kextract(vm_offset_t va)
9818 pdp_entry_t *pdpe, pdp;
9819 pd_entry_t *pde, pd;
9820 pt_entry_t *pte, pt;
9822 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9823 ("not largemap range %#lx", (u_long)va));
9824 pdpe = pmap_large_map_pdpe(va);
9826 KASSERT((pdp & X86_PG_V) != 0,
9827 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9828 (u_long)pdpe, pdp));
9829 if ((pdp & X86_PG_PS) != 0) {
9830 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9831 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9832 (u_long)pdpe, pdp));
9833 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9835 pde = pmap_pdpe_to_pde(pdpe, va);
9837 KASSERT((pd & X86_PG_V) != 0,
9838 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9839 if ((pd & X86_PG_PS) != 0)
9840 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9841 pte = pmap_pde_to_pte(pde, va);
9843 KASSERT((pt & X86_PG_V) != 0,
9844 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9845 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9849 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9850 vmem_addr_t *vmem_res)
9854 * Large mappings are all but static. Consequently, there
9855 * is no point in waiting for an earlier allocation to be
9858 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9859 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9863 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9869 vm_offset_t va, inc;
9870 vmem_addr_t vmem_res;
9874 if (len == 0 || spa + len < spa)
9877 /* See if DMAP can serve. */
9878 if (spa + len <= dmaplimit) {
9879 va = PHYS_TO_DMAP(spa);
9881 return (pmap_change_attr(va, len, mattr));
9885 * No, allocate KVA. Fit the address with best possible
9886 * alignment for superpages. Fall back to worse align if
9890 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9891 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9892 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9894 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9896 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9899 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9904 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9905 * in the pagetable to minimize flushing. No need to
9906 * invalidate TLB, since we only update invalid entries.
9908 PMAP_LOCK(kernel_pmap);
9909 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9911 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9912 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9913 pdpe = pmap_large_map_pdpe(va);
9915 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9916 X86_PG_V | X86_PG_A | pg_nx |
9917 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9919 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9920 (va & PDRMASK) == 0) {
9921 pde = pmap_large_map_pde(va);
9923 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9924 X86_PG_V | X86_PG_A | pg_nx |
9925 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9926 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9930 pte = pmap_large_map_pte(va);
9932 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9933 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9935 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9940 PMAP_UNLOCK(kernel_pmap);
9943 *addr = (void *)vmem_res;
9948 pmap_large_unmap(void *svaa, vm_size_t len)
9950 vm_offset_t sva, va;
9952 pdp_entry_t *pdpe, pdp;
9953 pd_entry_t *pde, pd;
9956 struct spglist spgf;
9958 sva = (vm_offset_t)svaa;
9959 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9960 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9964 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9965 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9966 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9967 PMAP_LOCK(kernel_pmap);
9968 for (va = sva; va < sva + len; va += inc) {
9969 pdpe = pmap_large_map_pdpe(va);
9971 KASSERT((pdp & X86_PG_V) != 0,
9972 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9973 (u_long)pdpe, pdp));
9974 if ((pdp & X86_PG_PS) != 0) {
9975 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9976 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9977 (u_long)pdpe, pdp));
9978 KASSERT((va & PDPMASK) == 0,
9979 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9980 (u_long)pdpe, pdp));
9981 KASSERT(va + NBPDP <= sva + len,
9982 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9983 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9984 (u_long)pdpe, pdp, len));
9989 pde = pmap_pdpe_to_pde(pdpe, va);
9991 KASSERT((pd & X86_PG_V) != 0,
9992 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9994 if ((pd & X86_PG_PS) != 0) {
9995 KASSERT((va & PDRMASK) == 0,
9996 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9998 KASSERT(va + NBPDR <= sva + len,
9999 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10000 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10004 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10006 if (m->ref_count == 0) {
10008 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10012 pte = pmap_pde_to_pte(pde, va);
10013 KASSERT((*pte & X86_PG_V) != 0,
10014 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10015 (u_long)pte, *pte));
10018 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10020 if (m->ref_count == 0) {
10022 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10023 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10025 if (m->ref_count == 0) {
10027 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10031 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10032 PMAP_UNLOCK(kernel_pmap);
10033 vm_page_free_pages_toq(&spgf, false);
10034 vmem_free(large_vmem, sva, len);
10038 pmap_large_map_wb_fence_mfence(void)
10045 pmap_large_map_wb_fence_atomic(void)
10048 atomic_thread_fence_seq_cst();
10052 pmap_large_map_wb_fence_nop(void)
10056 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10059 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10060 return (pmap_large_map_wb_fence_mfence);
10061 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10062 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10063 return (pmap_large_map_wb_fence_atomic);
10065 /* clflush is strongly enough ordered */
10066 return (pmap_large_map_wb_fence_nop);
10070 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10073 for (; len > 0; len -= cpu_clflush_line_size,
10074 va += cpu_clflush_line_size)
10079 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10082 for (; len > 0; len -= cpu_clflush_line_size,
10083 va += cpu_clflush_line_size)
10088 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10091 for (; len > 0; len -= cpu_clflush_line_size,
10092 va += cpu_clflush_line_size)
10097 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10101 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10104 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10105 return (pmap_large_map_flush_range_clwb);
10106 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10107 return (pmap_large_map_flush_range_clflushopt);
10108 else if ((cpu_feature & CPUID_CLFSH) != 0)
10109 return (pmap_large_map_flush_range_clflush);
10111 return (pmap_large_map_flush_range_nop);
10115 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10117 volatile u_long *pe;
10123 for (va = sva; va < eva; va += inc) {
10125 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10126 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10128 if ((p & X86_PG_PS) != 0)
10132 pe = (volatile u_long *)pmap_large_map_pde(va);
10134 if ((p & X86_PG_PS) != 0)
10138 pe = (volatile u_long *)pmap_large_map_pte(va);
10142 seen_other = false;
10144 if ((p & X86_PG_AVAIL1) != 0) {
10146 * Spin-wait for the end of a parallel
10153 * If we saw other write-back
10154 * occuring, we cannot rely on PG_M to
10155 * indicate state of the cache. The
10156 * PG_M bit is cleared before the
10157 * flush to avoid ignoring new writes,
10158 * and writes which are relevant for
10159 * us might happen after.
10165 if ((p & X86_PG_M) != 0 || seen_other) {
10166 if (!atomic_fcmpset_long(pe, &p,
10167 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10169 * If we saw PG_M without
10170 * PG_AVAIL1, and then on the
10171 * next attempt we do not
10172 * observe either PG_M or
10173 * PG_AVAIL1, the other
10174 * write-back started after us
10175 * and finished before us. We
10176 * can rely on it doing our
10180 pmap_large_map_flush_range(va, inc);
10181 atomic_clear_long(pe, X86_PG_AVAIL1);
10190 * Write-back cache lines for the given address range.
10192 * Must be called only on the range or sub-range returned from
10193 * pmap_large_map(). Must not be called on the coalesced ranges.
10195 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10196 * instructions support.
10199 pmap_large_map_wb(void *svap, vm_size_t len)
10201 vm_offset_t eva, sva;
10203 sva = (vm_offset_t)svap;
10205 pmap_large_map_wb_fence();
10206 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10207 pmap_large_map_flush_range(sva, len);
10209 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10210 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10211 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10212 pmap_large_map_wb_large(sva, eva);
10214 pmap_large_map_wb_fence();
10218 pmap_pti_alloc_page(void)
10222 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10223 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10224 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10229 pmap_pti_free_page(vm_page_t m)
10232 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10233 if (!vm_page_unwire_noq(m))
10235 vm_page_free_zero(m);
10240 pmap_pti_init(void)
10249 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10250 VM_OBJECT_WLOCK(pti_obj);
10251 pml4_pg = pmap_pti_alloc_page();
10252 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10253 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10254 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10255 pdpe = pmap_pti_pdpe(va);
10256 pmap_pti_wire_pte(pdpe);
10258 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10259 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10260 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10261 sizeof(struct gate_descriptor) * NIDT, false);
10263 /* Doublefault stack IST 1 */
10264 va = __pcpu[i].pc_common_tss.tss_ist1;
10265 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10266 /* NMI stack IST 2 */
10267 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10268 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10269 /* MC# stack IST 3 */
10270 va = __pcpu[i].pc_common_tss.tss_ist3 +
10271 sizeof(struct nmi_pcpu);
10272 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10273 /* DB# stack IST 4 */
10274 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10275 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10277 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10278 (vm_offset_t)etext, true);
10279 pti_finalized = true;
10280 VM_OBJECT_WUNLOCK(pti_obj);
10282 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10284 static pdp_entry_t *
10285 pmap_pti_pdpe(vm_offset_t va)
10287 pml4_entry_t *pml4e;
10290 vm_pindex_t pml4_idx;
10293 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10295 pml4_idx = pmap_pml4e_index(va);
10296 pml4e = &pti_pml4[pml4_idx];
10300 panic("pml4 alloc after finalization\n");
10301 m = pmap_pti_alloc_page();
10303 pmap_pti_free_page(m);
10304 mphys = *pml4e & ~PAGE_MASK;
10306 mphys = VM_PAGE_TO_PHYS(m);
10307 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10310 mphys = *pml4e & ~PAGE_MASK;
10312 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10317 pmap_pti_wire_pte(void *pte)
10321 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10322 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10327 pmap_pti_unwire_pde(void *pde, bool only_ref)
10331 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10332 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10333 MPASS(m->ref_count > 0);
10334 MPASS(only_ref || m->ref_count > 1);
10335 pmap_pti_free_page(m);
10339 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10344 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10345 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10346 MPASS(m->ref_count > 0);
10347 if (pmap_pti_free_page(m)) {
10348 pde = pmap_pti_pde(va);
10349 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10351 pmap_pti_unwire_pde(pde, false);
10355 static pd_entry_t *
10356 pmap_pti_pde(vm_offset_t va)
10361 vm_pindex_t pd_idx;
10364 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10366 pdpe = pmap_pti_pdpe(va);
10368 m = pmap_pti_alloc_page();
10370 pmap_pti_free_page(m);
10371 MPASS((*pdpe & X86_PG_PS) == 0);
10372 mphys = *pdpe & ~PAGE_MASK;
10374 mphys = VM_PAGE_TO_PHYS(m);
10375 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10378 MPASS((*pdpe & X86_PG_PS) == 0);
10379 mphys = *pdpe & ~PAGE_MASK;
10382 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10383 pd_idx = pmap_pde_index(va);
10388 static pt_entry_t *
10389 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10396 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10398 pde = pmap_pti_pde(va);
10399 if (unwire_pde != NULL) {
10400 *unwire_pde = true;
10401 pmap_pti_wire_pte(pde);
10404 m = pmap_pti_alloc_page();
10406 pmap_pti_free_page(m);
10407 MPASS((*pde & X86_PG_PS) == 0);
10408 mphys = *pde & ~(PAGE_MASK | pg_nx);
10410 mphys = VM_PAGE_TO_PHYS(m);
10411 *pde = mphys | X86_PG_RW | X86_PG_V;
10412 if (unwire_pde != NULL)
10413 *unwire_pde = false;
10416 MPASS((*pde & X86_PG_PS) == 0);
10417 mphys = *pde & ~(PAGE_MASK | pg_nx);
10420 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10421 pte += pmap_pte_index(va);
10427 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10431 pt_entry_t *pte, ptev;
10434 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10436 sva = trunc_page(sva);
10437 MPASS(sva > VM_MAXUSER_ADDRESS);
10438 eva = round_page(eva);
10440 for (; sva < eva; sva += PAGE_SIZE) {
10441 pte = pmap_pti_pte(sva, &unwire_pde);
10442 pa = pmap_kextract(sva);
10443 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10444 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10445 VM_MEMATTR_DEFAULT, FALSE);
10447 pte_store(pte, ptev);
10448 pmap_pti_wire_pte(pte);
10450 KASSERT(!pti_finalized,
10451 ("pti overlap after fin %#lx %#lx %#lx",
10453 KASSERT(*pte == ptev,
10454 ("pti non-identical pte after fin %#lx %#lx %#lx",
10458 pde = pmap_pti_pde(sva);
10459 pmap_pti_unwire_pde(pde, true);
10465 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10470 VM_OBJECT_WLOCK(pti_obj);
10471 pmap_pti_add_kva_locked(sva, eva, exec);
10472 VM_OBJECT_WUNLOCK(pti_obj);
10476 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10483 sva = rounddown2(sva, PAGE_SIZE);
10484 MPASS(sva > VM_MAXUSER_ADDRESS);
10485 eva = roundup2(eva, PAGE_SIZE);
10487 VM_OBJECT_WLOCK(pti_obj);
10488 for (va = sva; va < eva; va += PAGE_SIZE) {
10489 pte = pmap_pti_pte(va, NULL);
10490 KASSERT((*pte & X86_PG_V) != 0,
10491 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10492 (u_long)pte, *pte));
10494 pmap_pti_unwire_pte(pte, va);
10496 pmap_invalidate_range(kernel_pmap, sva, eva);
10497 VM_OBJECT_WUNLOCK(pti_obj);
10501 pkru_dup_range(void *ctx __unused, void *data)
10503 struct pmap_pkru_range *node, *new_node;
10505 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10506 if (new_node == NULL)
10509 memcpy(new_node, node, sizeof(*node));
10514 pkru_free_range(void *ctx __unused, void *node)
10517 uma_zfree(pmap_pkru_ranges_zone, node);
10521 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10524 struct pmap_pkru_range *ppr;
10527 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10528 MPASS(pmap->pm_type == PT_X86);
10529 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10530 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10531 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10533 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10536 ppr->pkru_keyidx = keyidx;
10537 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10538 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10540 uma_zfree(pmap_pkru_ranges_zone, ppr);
10545 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10548 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10549 MPASS(pmap->pm_type == PT_X86);
10550 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10551 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10555 pmap_pkru_deassign_all(pmap_t pmap)
10558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10559 if (pmap->pm_type == PT_X86 &&
10560 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10561 rangeset_remove_all(&pmap->pm_pkru);
10565 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10567 struct pmap_pkru_range *ppr, *prev_ppr;
10570 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10571 if (pmap->pm_type != PT_X86 ||
10572 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10573 sva >= VM_MAXUSER_ADDRESS)
10575 MPASS(eva <= VM_MAXUSER_ADDRESS);
10576 for (va = sva, prev_ppr = NULL; va < eva;) {
10577 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10578 if ((ppr == NULL) ^ (prev_ppr == NULL))
10584 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10586 va = ppr->pkru_rs_el.re_end;
10592 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10594 struct pmap_pkru_range *ppr;
10596 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10597 if (pmap->pm_type != PT_X86 ||
10598 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10599 va >= VM_MAXUSER_ADDRESS)
10601 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10603 return (X86_PG_PKU(ppr->pkru_keyidx));
10608 pred_pkru_on_remove(void *ctx __unused, void *r)
10610 struct pmap_pkru_range *ppr;
10613 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10617 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10620 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10621 if (pmap->pm_type == PT_X86 &&
10622 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10623 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10624 pred_pkru_on_remove);
10629 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10632 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10633 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10634 MPASS(dst_pmap->pm_type == PT_X86);
10635 MPASS(src_pmap->pm_type == PT_X86);
10636 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10637 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10639 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10643 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10646 pml4_entry_t *pml4e;
10648 pd_entry_t newpde, ptpaddr, *pde;
10649 pt_entry_t newpte, *ptep, pte;
10650 vm_offset_t va, va_next;
10653 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10654 MPASS(pmap->pm_type == PT_X86);
10655 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10657 for (changed = false, va = sva; va < eva; va = va_next) {
10658 pml4e = pmap_pml4e(pmap, va);
10659 if ((*pml4e & X86_PG_V) == 0) {
10660 va_next = (va + NBPML4) & ~PML4MASK;
10666 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10667 if ((*pdpe & X86_PG_V) == 0) {
10668 va_next = (va + NBPDP) & ~PDPMASK;
10674 va_next = (va + NBPDR) & ~PDRMASK;
10678 pde = pmap_pdpe_to_pde(pdpe, va);
10683 MPASS((ptpaddr & X86_PG_V) != 0);
10684 if ((ptpaddr & PG_PS) != 0) {
10685 if (va + NBPDR == va_next && eva >= va_next) {
10686 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10687 X86_PG_PKU(keyidx);
10688 if (newpde != ptpaddr) {
10693 } else if (!pmap_demote_pde(pmap, pde, va)) {
10701 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10702 ptep++, va += PAGE_SIZE) {
10704 if ((pte & X86_PG_V) == 0)
10706 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10707 if (newpte != pte) {
10714 pmap_invalidate_range(pmap, sva, eva);
10718 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10719 u_int keyidx, int flags)
10722 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10723 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10725 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10727 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10733 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10738 sva = trunc_page(sva);
10739 eva = round_page(eva);
10740 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10745 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10747 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10749 if (error != ENOMEM)
10757 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10761 sva = trunc_page(sva);
10762 eva = round_page(eva);
10763 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10768 error = pmap_pkru_deassign(pmap, sva, eva);
10770 pmap_pkru_update_range(pmap, sva, eva, 0);
10772 if (error != ENOMEM)
10780 * Track a range of the kernel's virtual address space that is contiguous
10781 * in various mapping attributes.
10783 struct pmap_kernel_map_range {
10792 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10798 if (eva <= range->sva)
10801 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10802 for (i = 0; i < PAT_INDEX_SIZE; i++)
10803 if (pat_index[i] == pat_idx)
10807 case PAT_WRITE_BACK:
10810 case PAT_WRITE_THROUGH:
10813 case PAT_UNCACHEABLE:
10819 case PAT_WRITE_PROTECTED:
10822 case PAT_WRITE_COMBINING:
10826 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10827 __func__, pat_idx, range->sva, eva);
10832 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10834 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10835 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10836 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10837 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10838 mode, range->pdpes, range->pdes, range->ptes);
10840 /* Reset to sentinel value. */
10841 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
10842 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
10843 NPDEPG - 1, NPTEPG - 1);
10847 * Determine whether the attributes specified by a page table entry match those
10848 * being tracked by the current range. This is not quite as simple as a direct
10849 * flag comparison since some PAT modes have multiple representations.
10852 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10854 pt_entry_t diff, mask;
10856 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10857 diff = (range->attrs ^ attrs) & mask;
10860 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10861 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10862 pmap_pat_index(kernel_pmap, attrs, true))
10868 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10872 memset(range, 0, sizeof(*range));
10874 range->attrs = attrs;
10878 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10879 * those of the current run, dump the address range and its attributes, and
10883 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10884 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10889 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10891 attrs |= pdpe & pg_nx;
10892 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10893 if ((pdpe & PG_PS) != 0) {
10894 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10895 } else if (pde != 0) {
10896 attrs |= pde & pg_nx;
10897 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10899 if ((pde & PG_PS) != 0) {
10900 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10901 } else if (pte != 0) {
10902 attrs |= pte & pg_nx;
10903 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10904 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10906 /* Canonicalize by always using the PDE PAT bit. */
10907 if ((attrs & X86_PG_PTE_PAT) != 0)
10908 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10911 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10912 sysctl_kmaps_dump(sb, range, va);
10913 sysctl_kmaps_reinit(range, va, attrs);
10918 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10920 struct pmap_kernel_map_range range;
10921 struct sbuf sbuf, *sb;
10922 pml4_entry_t pml4e;
10923 pdp_entry_t *pdp, pdpe;
10924 pd_entry_t *pd, pde;
10925 pt_entry_t *pt, pte;
10928 int error, i, j, k, l;
10930 error = sysctl_wire_old_buffer(req, 0);
10934 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10936 /* Sentinel value. */
10937 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
10938 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
10939 NPDEPG - 1, NPTEPG - 1);
10942 * Iterate over the kernel page tables without holding the kernel pmap
10943 * lock. Outside of the large map, kernel page table pages are never
10944 * freed, so at worst we will observe inconsistencies in the output.
10945 * Within the large map, ensure that PDP and PD page addresses are
10946 * valid before descending.
10948 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10951 sbuf_printf(sb, "\nRecursive map:\n");
10954 sbuf_printf(sb, "\nDirect map:\n");
10957 sbuf_printf(sb, "\nKernel map:\n");
10960 sbuf_printf(sb, "\nLarge map:\n");
10964 /* Convert to canonical form. */
10965 if (sva == 1ul << 47)
10969 pml4e = kernel_pml4[i];
10970 if ((pml4e & X86_PG_V) == 0) {
10971 sva = rounddown2(sva, NBPML4);
10972 sysctl_kmaps_dump(sb, &range, sva);
10976 pa = pml4e & PG_FRAME;
10977 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10979 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10981 if ((pdpe & X86_PG_V) == 0) {
10982 sva = rounddown2(sva, NBPDP);
10983 sysctl_kmaps_dump(sb, &range, sva);
10987 pa = pdpe & PG_FRAME;
10988 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10989 vm_phys_paddr_to_vm_page(pa) == NULL)
10991 if ((pdpe & PG_PS) != 0) {
10992 sva = rounddown2(sva, NBPDP);
10993 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10999 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11001 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11003 if ((pde & X86_PG_V) == 0) {
11004 sva = rounddown2(sva, NBPDR);
11005 sysctl_kmaps_dump(sb, &range, sva);
11009 pa = pde & PG_FRAME;
11010 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11011 vm_phys_paddr_to_vm_page(pa) == NULL)
11013 if ((pde & PG_PS) != 0) {
11014 sva = rounddown2(sva, NBPDR);
11015 sysctl_kmaps_check(sb, &range, sva,
11016 pml4e, pdpe, pde, 0);
11021 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11023 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11024 sva += PAGE_SIZE) {
11026 if ((pte & X86_PG_V) == 0) {
11027 sysctl_kmaps_dump(sb, &range,
11031 sysctl_kmaps_check(sb, &range, sva,
11032 pml4e, pdpe, pde, pte);
11039 error = sbuf_finish(sb);
11043 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11044 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
11045 NULL, 0, sysctl_kmaps, "A",
11046 "Dump kernel address layout");
11049 DB_SHOW_COMMAND(pte, pmap_print_pte)
11052 pml5_entry_t *pml5;
11053 pml4_entry_t *pml4;
11056 pt_entry_t *pte, PG_V;
11060 db_printf("show pte addr\n");
11063 va = (vm_offset_t)addr;
11065 if (kdb_thread != NULL)
11066 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11068 pmap = PCPU_GET(curpmap);
11070 PG_V = pmap_valid_bit(pmap);
11071 db_printf("VA 0x%016lx", va);
11073 if (pmap_is_la57(pmap)) {
11074 pml5 = pmap_pml5e(pmap, va);
11075 db_printf(" pml5e 0x%016lx", *pml5);
11076 if ((*pml5 & PG_V) == 0) {
11080 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11082 pml4 = pmap_pml4e(pmap, va);
11084 db_printf(" pml4e 0x%016lx", *pml4);
11085 if ((*pml4 & PG_V) == 0) {
11089 pdp = pmap_pml4e_to_pdpe(pml4, va);
11090 db_printf(" pdpe 0x%016lx", *pdp);
11091 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11095 pde = pmap_pdpe_to_pde(pdp, va);
11096 db_printf(" pde 0x%016lx", *pde);
11097 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11101 pte = pmap_pde_to_pte(pde, va);
11102 db_printf(" pte 0x%016lx\n", *pte);
11105 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11110 a = (vm_paddr_t)addr;
11111 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11113 db_printf("show phys2dmap addr\n");
11118 ptpages_show_page(int level, int idx, vm_page_t pg)
11120 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11121 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11125 ptpages_show_complain(int level, int idx, uint64_t pte)
11127 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11131 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11133 vm_page_t pg3, pg2, pg1;
11134 pml4_entry_t *pml4;
11139 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11140 for (i4 = 0; i4 < num_entries; i4++) {
11141 if ((pml4[i4] & PG_V) == 0)
11143 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11145 ptpages_show_complain(3, i4, pml4[i4]);
11148 ptpages_show_page(3, i4, pg3);
11149 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11150 for (i3 = 0; i3 < NPDPEPG; i3++) {
11151 if ((pdp[i3] & PG_V) == 0)
11153 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11155 ptpages_show_complain(2, i3, pdp[i3]);
11158 ptpages_show_page(2, i3, pg2);
11159 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11160 for (i2 = 0; i2 < NPDEPG; i2++) {
11161 if ((pd[i2] & PG_V) == 0)
11163 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11165 ptpages_show_complain(1, i2, pd[i2]);
11168 ptpages_show_page(1, i2, pg1);
11174 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11178 pml5_entry_t *pml5;
11183 pmap = (pmap_t)addr;
11185 pmap = PCPU_GET(curpmap);
11187 PG_V = pmap_valid_bit(pmap);
11189 if (pmap_is_la57(pmap)) {
11190 pml5 = pmap->pm_pmltop;
11191 for (i5 = 0; i5 < NUPML5E; i5++) {
11192 if ((pml5[i5] & PG_V) == 0)
11194 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11196 ptpages_show_complain(4, i5, pml5[i5]);
11199 ptpages_show_page(4, i5, pg);
11200 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11203 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11204 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);