2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/_unrhdr.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
132 #include <vm/vm_pager.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
137 #include <machine/intr_machdep.h>
138 #include <x86/apicvar.h>
139 #include <machine/cpu.h>
140 #include <machine/cputypes.h>
141 #include <machine/md_var.h>
142 #include <machine/pcb.h>
143 #include <machine/specialreg.h>
145 #include <machine/smp.h>
148 static __inline boolean_t
149 pmap_type_guest(pmap_t pmap)
152 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
155 static __inline boolean_t
156 pmap_emulate_ad_bits(pmap_t pmap)
159 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
162 static __inline pt_entry_t
163 pmap_valid_bit(pmap_t pmap)
167 switch (pmap->pm_type) {
173 if (pmap_emulate_ad_bits(pmap))
174 mask = EPT_PG_EMUL_V;
179 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
185 static __inline pt_entry_t
186 pmap_rw_bit(pmap_t pmap)
190 switch (pmap->pm_type) {
196 if (pmap_emulate_ad_bits(pmap))
197 mask = EPT_PG_EMUL_RW;
202 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
208 static __inline pt_entry_t
209 pmap_global_bit(pmap_t pmap)
213 switch (pmap->pm_type) {
222 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
228 static __inline pt_entry_t
229 pmap_accessed_bit(pmap_t pmap)
233 switch (pmap->pm_type) {
239 if (pmap_emulate_ad_bits(pmap))
245 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
251 static __inline pt_entry_t
252 pmap_modified_bit(pmap_t pmap)
256 switch (pmap->pm_type) {
262 if (pmap_emulate_ad_bits(pmap))
268 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
274 #if !defined(DIAGNOSTIC)
275 #ifdef __GNUC_GNU_INLINE__
276 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
278 #define PMAP_INLINE extern inline
285 #define PV_STAT(x) do { x ; } while (0)
287 #define PV_STAT(x) do { } while (0)
290 #define pa_index(pa) ((pa) >> PDRSHIFT)
291 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
293 #define NPV_LIST_LOCKS MAXCPU
295 #define PHYS_TO_PV_LIST_LOCK(pa) \
296 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
298 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
299 struct rwlock **_lockp = (lockp); \
300 struct rwlock *_new_lock; \
302 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
303 if (_new_lock != *_lockp) { \
304 if (*_lockp != NULL) \
305 rw_wunlock(*_lockp); \
306 *_lockp = _new_lock; \
311 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
312 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
314 #define RELEASE_PV_LIST_LOCK(lockp) do { \
315 struct rwlock **_lockp = (lockp); \
317 if (*_lockp != NULL) { \
318 rw_wunlock(*_lockp); \
323 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
324 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
326 struct pmap kernel_pmap_store;
328 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
329 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
332 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
333 "Number of kernel page table pages allocated on bootup");
336 vm_paddr_t dmaplimit;
337 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
340 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
342 static int pat_works = 1;
343 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
344 "Is page attribute table fully functional?");
346 static int pg_ps_enabled = 1;
347 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
348 &pg_ps_enabled, 0, "Are large page mappings enabled?");
350 #define PAT_INDEX_SIZE 8
351 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
353 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
354 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
355 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
356 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
358 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
359 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
360 static int ndmpdpphys; /* number of DMPDPphys pages */
362 static struct rwlock_padalign pvh_global_lock;
365 * Data for the pv entry allocation mechanism
367 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
368 static struct mtx pv_chunks_mutex;
369 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
370 static struct md_page *pv_table;
373 * All those kernel PT submaps that BSD is so fond of
375 pt_entry_t *CMAP1 = 0;
378 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
380 static struct unrhdr pcid_unr;
381 static struct mtx pcid_mtx;
382 int pmap_pcid_enabled = 0;
383 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
384 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
385 int invpcid_works = 0;
386 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
387 "Is the invpcid instruction available ?");
390 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
397 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
399 return (sysctl_handle_64(oidp, &res, 0, req));
401 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
402 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
403 "Count of saved TLB context on switch");
405 /* pmap_copy_pages() over non-DMAP */
406 static struct mtx cpage_lock;
407 static vm_offset_t cpage_a;
408 static vm_offset_t cpage_b;
413 static caddr_t crashdumpmap;
415 static void free_pv_chunk(struct pv_chunk *pc);
416 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
417 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
418 static int popcnt_pc_map_elem(uint64_t elem);
419 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
420 static void reserve_pv_entries(pmap_t pmap, int needed,
421 struct rwlock **lockp);
422 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
423 struct rwlock **lockp);
424 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
425 struct rwlock **lockp);
426 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
427 struct rwlock **lockp);
428 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
429 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
432 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
433 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
434 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
435 vm_offset_t va, struct rwlock **lockp);
436 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
438 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
439 vm_prot_t prot, struct rwlock **lockp);
440 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
441 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
442 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
443 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
444 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
445 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
446 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
447 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
448 struct rwlock **lockp);
449 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
451 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
452 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
453 struct spglist *free, struct rwlock **lockp);
454 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
455 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
456 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
457 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
458 struct spglist *free);
459 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
460 vm_page_t m, struct rwlock **lockp);
461 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
463 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
465 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
466 struct rwlock **lockp);
467 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
468 struct rwlock **lockp);
469 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
470 struct rwlock **lockp);
472 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
473 struct spglist *free);
474 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
475 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
478 * Move the kernel virtual free pointer to the next
479 * 2MB. This is used to help improve performance
480 * by using a large (2MB) page for much of the kernel
481 * (.text, .data, .bss)
484 pmap_kmem_choose(vm_offset_t addr)
486 vm_offset_t newaddr = addr;
488 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
492 /********************/
493 /* Inline functions */
494 /********************/
496 /* Return a non-clipped PD index for a given VA */
497 static __inline vm_pindex_t
498 pmap_pde_pindex(vm_offset_t va)
500 return (va >> PDRSHIFT);
504 /* Return various clipped indexes for a given VA */
505 static __inline vm_pindex_t
506 pmap_pte_index(vm_offset_t va)
509 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
512 static __inline vm_pindex_t
513 pmap_pde_index(vm_offset_t va)
516 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
519 static __inline vm_pindex_t
520 pmap_pdpe_index(vm_offset_t va)
523 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
526 static __inline vm_pindex_t
527 pmap_pml4e_index(vm_offset_t va)
530 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
533 /* Return a pointer to the PML4 slot that corresponds to a VA */
534 static __inline pml4_entry_t *
535 pmap_pml4e(pmap_t pmap, vm_offset_t va)
538 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
541 /* Return a pointer to the PDP slot that corresponds to a VA */
542 static __inline pdp_entry_t *
543 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
547 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
548 return (&pdpe[pmap_pdpe_index(va)]);
551 /* Return a pointer to the PDP slot that corresponds to a VA */
552 static __inline pdp_entry_t *
553 pmap_pdpe(pmap_t pmap, vm_offset_t va)
558 PG_V = pmap_valid_bit(pmap);
559 pml4e = pmap_pml4e(pmap, va);
560 if ((*pml4e & PG_V) == 0)
562 return (pmap_pml4e_to_pdpe(pml4e, va));
565 /* Return a pointer to the PD slot that corresponds to a VA */
566 static __inline pd_entry_t *
567 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
571 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
572 return (&pde[pmap_pde_index(va)]);
575 /* Return a pointer to the PD slot that corresponds to a VA */
576 static __inline pd_entry_t *
577 pmap_pde(pmap_t pmap, vm_offset_t va)
582 PG_V = pmap_valid_bit(pmap);
583 pdpe = pmap_pdpe(pmap, va);
584 if (pdpe == NULL || (*pdpe & PG_V) == 0)
586 return (pmap_pdpe_to_pde(pdpe, va));
589 /* Return a pointer to the PT slot that corresponds to a VA */
590 static __inline pt_entry_t *
591 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
595 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
596 return (&pte[pmap_pte_index(va)]);
599 /* Return a pointer to the PT slot that corresponds to a VA */
600 static __inline pt_entry_t *
601 pmap_pte(pmap_t pmap, vm_offset_t va)
606 PG_V = pmap_valid_bit(pmap);
607 pde = pmap_pde(pmap, va);
608 if (pde == NULL || (*pde & PG_V) == 0)
610 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
611 return ((pt_entry_t *)pde);
612 return (pmap_pde_to_pte(pde, va));
616 pmap_resident_count_inc(pmap_t pmap, int count)
619 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
620 pmap->pm_stats.resident_count += count;
624 pmap_resident_count_dec(pmap_t pmap, int count)
627 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
628 KASSERT(pmap->pm_stats.resident_count >= count,
629 ("pmap %p resident count underflow %ld %d", pmap,
630 pmap->pm_stats.resident_count, count));
631 pmap->pm_stats.resident_count -= count;
634 PMAP_INLINE pt_entry_t *
635 vtopte(vm_offset_t va)
637 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
639 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
641 return (PTmap + ((va >> PAGE_SHIFT) & mask));
644 static __inline pd_entry_t *
645 vtopde(vm_offset_t va)
647 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
649 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
651 return (PDmap + ((va >> PDRSHIFT) & mask));
655 allocpages(vm_paddr_t *firstaddr, int n)
660 bzero((void *)ret, n * PAGE_SIZE);
661 *firstaddr += n * PAGE_SIZE;
665 CTASSERT(powerof2(NDMPML4E));
667 /* number of kernel PDP slots */
668 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
671 nkpt_init(vm_paddr_t addr)
678 pt_pages = howmany(addr, 1 << PDRSHIFT);
679 pt_pages += NKPDPE(pt_pages);
682 * Add some slop beyond the bare minimum required for bootstrapping
685 * This is quite important when allocating KVA for kernel modules.
686 * The modules are required to be linked in the negative 2GB of
687 * the address space. If we run out of KVA in this region then
688 * pmap_growkernel() will need to allocate page table pages to map
689 * the entire 512GB of KVA space which is an unnecessary tax on
692 pt_pages += 8; /* 16MB additional slop for kernel modules */
698 create_pagetables(vm_paddr_t *firstaddr)
700 int i, j, ndm1g, nkpdpe;
706 /* Allocate page table pages for the direct map */
707 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
708 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
710 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
711 if (ndmpdpphys > NDMPML4E) {
713 * Each NDMPML4E allows 512 GB, so limit to that,
714 * and then readjust ndmpdp and ndmpdpphys.
716 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
717 Maxmem = atop(NDMPML4E * NBPML4);
718 ndmpdpphys = NDMPML4E;
719 ndmpdp = NDMPML4E * NPDEPG;
721 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
723 if ((amd_feature & AMDID_PAGE1GB) != 0)
724 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
726 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
727 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
730 KPML4phys = allocpages(firstaddr, 1);
731 KPDPphys = allocpages(firstaddr, NKPML4E);
734 * Allocate the initial number of kernel page table pages required to
735 * bootstrap. We defer this until after all memory-size dependent
736 * allocations are done (e.g. direct map), so that we don't have to
737 * build in too much slop in our estimate.
739 * Note that when NKPML4E > 1, we have an empty page underneath
740 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
741 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
743 nkpt_init(*firstaddr);
744 nkpdpe = NKPDPE(nkpt);
746 KPTphys = allocpages(firstaddr, nkpt);
747 KPDphys = allocpages(firstaddr, nkpdpe);
749 /* Fill in the underlying page table pages */
750 /* Nominally read-only (but really R/W) from zero to physfree */
751 /* XXX not fully used, underneath 2M pages */
752 pt_p = (pt_entry_t *)KPTphys;
753 for (i = 0; ptoa(i) < *firstaddr; i++)
754 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
756 /* Now map the page tables at their location within PTmap */
757 pd_p = (pd_entry_t *)KPDphys;
758 for (i = 0; i < nkpt; i++)
759 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
761 /* Map from zero to end of allocations under 2M pages */
762 /* This replaces some of the KPTphys entries above */
763 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
764 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
767 /* And connect up the PD to the PDP (leaving room for L4 pages) */
768 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
769 for (i = 0; i < nkpdpe; i++)
770 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
774 * Now, set up the direct map region using 2MB and/or 1GB pages. If
775 * the end of physical memory is not aligned to a 1GB page boundary,
776 * then the residual physical memory is mapped with 2MB pages. Later,
777 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
778 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
779 * that are partially used.
781 pd_p = (pd_entry_t *)DMPDphys;
782 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
783 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
784 /* Preset PG_M and PG_A because demotion expects it. */
785 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
788 pdp_p = (pdp_entry_t *)DMPDPphys;
789 for (i = 0; i < ndm1g; i++) {
790 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
791 /* Preset PG_M and PG_A because demotion expects it. */
792 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
795 for (j = 0; i < ndmpdp; i++, j++) {
796 pdp_p[i] = DMPDphys + ptoa(j);
797 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
800 /* And recursively map PML4 to itself in order to get PTmap */
801 p4_p = (pml4_entry_t *)KPML4phys;
802 p4_p[PML4PML4I] = KPML4phys;
803 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
805 /* Connect the Direct Map slot(s) up to the PML4. */
806 for (i = 0; i < ndmpdpphys; i++) {
807 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
808 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
811 /* Connect the KVA slots up to the PML4 */
812 for (i = 0; i < NKPML4E; i++) {
813 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
814 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
819 * Bootstrap the system enough to run with virtual memory.
821 * On amd64 this is called after mapping has already been enabled
822 * and just syncs the pmap module with what has already been done.
823 * [We can't call it easily with mapping off since the kernel is not
824 * mapped with PA == VA, hence we would have to relocate every address
825 * from the linked base (virtual) address "KERNBASE" to the actual
826 * (physical) address starting relative to 0]
829 pmap_bootstrap(vm_paddr_t *firstaddr)
835 * Create an initial set of page tables to run the kernel in.
837 create_pagetables(firstaddr);
839 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
840 virtual_avail = pmap_kmem_choose(virtual_avail);
842 virtual_end = VM_MAX_KERNEL_ADDRESS;
845 /* XXX do %cr0 as well */
846 load_cr4(rcr4() | CR4_PGE);
848 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
849 load_cr4(rcr4() | CR4_SMEP);
852 * Initialize the kernel pmap (which is statically allocated).
854 PMAP_LOCK_INIT(kernel_pmap);
855 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
856 kernel_pmap->pm_cr3 = KPML4phys;
857 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
858 CPU_FILL(&kernel_pmap->pm_save); /* always superset of pm_active */
859 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
860 kernel_pmap->pm_flags = pmap_flags;
863 * Initialize the global pv list lock.
865 rw_init(&pvh_global_lock, "pmap pv global");
868 * Reserve some special page table entries/VA space for temporary
871 #define SYSMAP(c, p, v, n) \
872 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
878 * Crashdump maps. The first page is reused as CMAP1 for the
881 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
882 CADDR1 = crashdumpmap;
886 /* Initialize the PAT MSR. */
889 /* Initialize TLB Context Id. */
890 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
891 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
892 load_cr4(rcr4() | CR4_PCIDE);
893 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
894 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
895 /* Check for INVPCID support */
896 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
898 kernel_pmap->pm_pcid = 0;
900 pmap_pcid_enabled = 0;
903 pmap_pcid_enabled = 0;
912 int pat_table[PAT_INDEX_SIZE];
917 /* Bail if this CPU doesn't implement PAT. */
918 if ((cpu_feature & CPUID_PAT) == 0)
921 /* Set default PAT index table. */
922 for (i = 0; i < PAT_INDEX_SIZE; i++)
924 pat_table[PAT_WRITE_BACK] = 0;
925 pat_table[PAT_WRITE_THROUGH] = 1;
926 pat_table[PAT_UNCACHEABLE] = 3;
927 pat_table[PAT_WRITE_COMBINING] = 3;
928 pat_table[PAT_WRITE_PROTECTED] = 3;
929 pat_table[PAT_UNCACHED] = 3;
931 /* Initialize default PAT entries. */
932 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
933 PAT_VALUE(1, PAT_WRITE_THROUGH) |
934 PAT_VALUE(2, PAT_UNCACHED) |
935 PAT_VALUE(3, PAT_UNCACHEABLE) |
936 PAT_VALUE(4, PAT_WRITE_BACK) |
937 PAT_VALUE(5, PAT_WRITE_THROUGH) |
938 PAT_VALUE(6, PAT_UNCACHED) |
939 PAT_VALUE(7, PAT_UNCACHEABLE);
943 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
944 * Program 5 and 6 as WP and WC.
945 * Leave 4 and 7 as WB and UC.
947 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
948 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
949 PAT_VALUE(6, PAT_WRITE_COMBINING);
950 pat_table[PAT_UNCACHED] = 2;
951 pat_table[PAT_WRITE_PROTECTED] = 5;
952 pat_table[PAT_WRITE_COMBINING] = 6;
955 * Just replace PAT Index 2 with WC instead of UC-.
957 pat_msr &= ~PAT_MASK(2);
958 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
959 pat_table[PAT_WRITE_COMBINING] = 2;
964 load_cr4(cr4 & ~CR4_PGE);
966 /* Disable caches (CD = 1, NW = 0). */
968 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
970 /* Flushes caches and TLBs. */
974 /* Update PAT and index table. */
975 wrmsr(MSR_PAT, pat_msr);
976 for (i = 0; i < PAT_INDEX_SIZE; i++)
977 pat_index[i] = pat_table[i];
979 /* Flush caches and TLBs again. */
983 /* Restore caches and PGE. */
989 * Initialize a vm_page's machine-dependent fields.
992 pmap_page_init(vm_page_t m)
995 TAILQ_INIT(&m->md.pv_list);
996 m->md.pat_mode = PAT_WRITE_BACK;
1000 * Initialize the pmap module.
1001 * Called by vm_init, to initialize any structures that the pmap
1002 * system needs to map virtual memory.
1012 * Initialize the vm page array entries for the kernel pmap's
1015 for (i = 0; i < nkpt; i++) {
1016 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1017 KASSERT(mpte >= vm_page_array &&
1018 mpte < &vm_page_array[vm_page_array_size],
1019 ("pmap_init: page table page is out of range"));
1020 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1021 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1025 * If the kernel is running on a virtual machine, then it must assume
1026 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1027 * be prepared for the hypervisor changing the vendor and family that
1028 * are reported by CPUID. Consequently, the workaround for AMD Family
1029 * 10h Erratum 383 is enabled if the processor's feature set does not
1030 * include at least one feature that is only supported by older Intel
1031 * or newer AMD processors.
1033 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1034 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1035 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1037 workaround_erratum383 = 1;
1040 * Are large page mappings enabled?
1042 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1043 if (pg_ps_enabled) {
1044 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1045 ("pmap_init: can't assign to pagesizes[1]"));
1046 pagesizes[1] = NBPDR;
1050 * Initialize the pv chunk list mutex.
1052 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1055 * Initialize the pool of pv list locks.
1057 for (i = 0; i < NPV_LIST_LOCKS; i++)
1058 rw_init(&pv_list_locks[i], "pmap pv list");
1061 * Calculate the size of the pv head table for superpages.
1063 for (i = 0; phys_avail[i + 1]; i += 2);
1064 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
1067 * Allocate memory for the pv head table for superpages.
1069 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1071 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1073 for (i = 0; i < pv_npg; i++)
1074 TAILQ_INIT(&pv_table[i].pv_list);
1076 mtx_init(&cpage_lock, "cpage", NULL, MTX_DEF);
1077 cpage_a = kva_alloc(PAGE_SIZE);
1078 cpage_b = kva_alloc(PAGE_SIZE);
1081 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1082 "2MB page mapping counters");
1084 static u_long pmap_pde_demotions;
1085 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1086 &pmap_pde_demotions, 0, "2MB page demotions");
1088 static u_long pmap_pde_mappings;
1089 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1090 &pmap_pde_mappings, 0, "2MB page mappings");
1092 static u_long pmap_pde_p_failures;
1093 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1094 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1096 static u_long pmap_pde_promotions;
1097 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1098 &pmap_pde_promotions, 0, "2MB page promotions");
1100 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1101 "1GB page mapping counters");
1103 static u_long pmap_pdpe_demotions;
1104 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1105 &pmap_pdpe_demotions, 0, "1GB page demotions");
1107 /***************************************************
1108 * Low level helper routines.....
1109 ***************************************************/
1112 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1114 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1116 switch (pmap->pm_type) {
1119 /* Verify that both PAT bits are not set at the same time */
1120 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1121 ("Invalid PAT bits in entry %#lx", entry));
1123 /* Swap the PAT bits if one of them is set */
1124 if ((entry & x86_pat_bits) != 0)
1125 entry ^= x86_pat_bits;
1129 * Nothing to do - the memory attributes are represented
1130 * the same way for regular pages and superpages.
1134 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1141 * Determine the appropriate bits to set in a PTE or PDE for a specified
1145 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1147 int cache_bits, pat_flag, pat_idx;
1149 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1150 panic("Unknown caching mode %d\n", mode);
1152 switch (pmap->pm_type) {
1155 /* The PAT bit is different for PTE's and PDE's. */
1156 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1158 /* Map the caching mode to a PAT index. */
1159 pat_idx = pat_index[mode];
1161 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1164 cache_bits |= pat_flag;
1166 cache_bits |= PG_NC_PCD;
1168 cache_bits |= PG_NC_PWT;
1172 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1176 panic("unsupported pmap type %d", pmap->pm_type);
1179 return (cache_bits);
1183 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1187 switch (pmap->pm_type) {
1190 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1193 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1196 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1202 static __inline boolean_t
1203 pmap_ps_enabled(pmap_t pmap)
1206 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1210 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1213 switch (pmap->pm_type) {
1220 * This is a little bogus since the generation number is
1221 * supposed to be bumped up when a region of the address
1222 * space is invalidated in the page tables.
1224 * In this case the old PDE entry is valid but yet we want
1225 * to make sure that any mappings using the old entry are
1226 * invalidated in the TLB.
1228 * The reason this works as expected is because we rendezvous
1229 * "all" host cpus and force any vcpu context to exit as a
1232 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1235 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1237 pde_store(pde, newpde);
1241 * After changing the page size for the specified virtual address in the page
1242 * table, flush the corresponding entries from the processor's TLB. Only the
1243 * calling processor's TLB is affected.
1245 * The calling thread must be pinned to a processor.
1248 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1252 if (pmap_type_guest(pmap))
1255 KASSERT(pmap->pm_type == PT_X86,
1256 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1258 PG_G = pmap_global_bit(pmap);
1260 if ((newpde & PG_PS) == 0)
1261 /* Demotion: flush a specific 2MB page mapping. */
1263 else if ((newpde & PG_G) == 0)
1265 * Promotion: flush every 4KB page mapping from the TLB
1266 * because there are too many to flush individually.
1271 * Promotion: flush every 4KB page mapping from the TLB,
1272 * including any global (PG_G) mappings.
1280 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1282 struct invpcid_descr d;
1285 if (invpcid_works) {
1286 d.pcid = pmap->pm_pcid;
1289 invpcid(&d, INVPCID_ADDR);
1295 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1297 load_cr3(cr3 | CR3_PCID_SAVE);
1302 * For SMP, these functions have to use the IPI mechanism for coherence.
1304 * N.B.: Before calling any of the following TLB invalidation functions,
1305 * the calling processor must ensure that all stores updating a non-
1306 * kernel page table are globally performed. Otherwise, another
1307 * processor could cache an old, pre-update entry without being
1308 * invalidated. This can happen one of two ways: (1) The pmap becomes
1309 * active on another processor after its pm_active field is checked by
1310 * one of the following functions but before a store updating the page
1311 * table is globally performed. (2) The pmap becomes active on another
1312 * processor before its pm_active field is checked but due to
1313 * speculative loads one of the following functions stills reads the
1314 * pmap as inactive on the other processor.
1316 * The kernel page table is exempt because its pm_active field is
1317 * immutable. The kernel page table is always active on every
1322 * Interrupt the cpus that are executing in the guest context.
1323 * This will force the vcpu to exit and the cached EPT mappings
1324 * will be invalidated by the host before the next vmresume.
1326 static __inline void
1327 pmap_invalidate_ept(pmap_t pmap)
1332 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1333 ("pmap_invalidate_ept: absurd pm_active"));
1336 * The TLB mappings associated with a vcpu context are not
1337 * flushed each time a different vcpu is chosen to execute.
1339 * This is in contrast with a process's vtop mappings that
1340 * are flushed from the TLB on each context switch.
1342 * Therefore we need to do more than just a TLB shootdown on
1343 * the active cpus in 'pmap->pm_active'. To do this we keep
1344 * track of the number of invalidations performed on this pmap.
1346 * Each vcpu keeps a cache of this counter and compares it
1347 * just before a vmresume. If the counter is out-of-date an
1348 * invept will be done to flush stale mappings from the TLB.
1350 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1353 * Force the vcpu to exit and trap back into the hypervisor.
1355 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1356 ipi_selected(pmap->pm_active, ipinum);
1361 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1363 cpuset_t other_cpus;
1366 if (pmap_type_guest(pmap)) {
1367 pmap_invalidate_ept(pmap);
1371 KASSERT(pmap->pm_type == PT_X86,
1372 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1375 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1376 if (!pmap_pcid_enabled) {
1379 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1380 if (pmap == PCPU_GET(curpmap))
1383 pmap_invalidate_page_pcid(pmap, va);
1388 smp_invlpg(pmap, va);
1390 cpuid = PCPU_GET(cpuid);
1391 other_cpus = all_cpus;
1392 CPU_CLR(cpuid, &other_cpus);
1393 if (CPU_ISSET(cpuid, &pmap->pm_active))
1395 else if (pmap_pcid_enabled) {
1396 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1397 pmap_invalidate_page_pcid(pmap, va);
1401 if (pmap_pcid_enabled)
1402 CPU_AND(&other_cpus, &pmap->pm_save);
1404 CPU_AND(&other_cpus, &pmap->pm_active);
1405 if (!CPU_EMPTY(&other_cpus))
1406 smp_masked_invlpg(other_cpus, pmap, va);
1412 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1414 struct invpcid_descr d;
1418 if (invpcid_works) {
1419 d.pcid = pmap->pm_pcid;
1421 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1423 invpcid(&d, INVPCID_ADDR);
1430 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1431 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1433 load_cr3(cr3 | CR3_PCID_SAVE);
1438 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1440 cpuset_t other_cpus;
1444 if (pmap_type_guest(pmap)) {
1445 pmap_invalidate_ept(pmap);
1449 KASSERT(pmap->pm_type == PT_X86,
1450 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1453 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1454 if (!pmap_pcid_enabled) {
1455 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1458 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1459 if (pmap == PCPU_GET(curpmap)) {
1460 for (addr = sva; addr < eva;
1464 pmap_invalidate_range_pcid(pmap,
1471 smp_invlpg_range(pmap, sva, eva);
1473 cpuid = PCPU_GET(cpuid);
1474 other_cpus = all_cpus;
1475 CPU_CLR(cpuid, &other_cpus);
1476 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1477 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1479 } else if (pmap_pcid_enabled) {
1480 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1481 pmap_invalidate_range_pcid(pmap, sva, eva);
1485 if (pmap_pcid_enabled)
1486 CPU_AND(&other_cpus, &pmap->pm_save);
1488 CPU_AND(&other_cpus, &pmap->pm_active);
1489 if (!CPU_EMPTY(&other_cpus))
1490 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1496 pmap_invalidate_all(pmap_t pmap)
1498 cpuset_t other_cpus;
1499 struct invpcid_descr d;
1503 if (pmap_type_guest(pmap)) {
1504 pmap_invalidate_ept(pmap);
1508 KASSERT(pmap->pm_type == PT_X86,
1509 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1512 cpuid = PCPU_GET(cpuid);
1513 if (pmap == kernel_pmap ||
1514 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1515 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1516 if (invpcid_works) {
1517 bzero(&d, sizeof(d));
1518 invpcid(&d, INVPCID_CTXGLOB);
1522 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1523 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1526 other_cpus = all_cpus;
1527 CPU_CLR(cpuid, &other_cpus);
1530 * This logic is duplicated in the Xinvltlb shootdown
1533 if (pmap_pcid_enabled) {
1534 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1535 if (invpcid_works) {
1536 d.pcid = pmap->pm_pcid;
1539 invpcid(&d, INVPCID_CTX);
1545 * Bit 63 is clear, pcid TLB
1546 * entries are invalidated.
1548 load_cr3(pmap->pm_cr3);
1549 load_cr3(cr3 | CR3_PCID_SAVE);
1555 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1557 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1558 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1559 if (pmap_pcid_enabled)
1560 CPU_AND(&other_cpus, &pmap->pm_save);
1562 CPU_AND(&other_cpus, &pmap->pm_active);
1563 if (!CPU_EMPTY(&other_cpus))
1564 smp_masked_invltlb(other_cpus, pmap);
1570 pmap_invalidate_cache(void)
1580 cpuset_t invalidate; /* processors that invalidate their TLB */
1585 u_int store; /* processor that updates the PDE */
1589 pmap_update_pde_action(void *arg)
1591 struct pde_action *act = arg;
1593 if (act->store == PCPU_GET(cpuid))
1594 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1598 pmap_update_pde_teardown(void *arg)
1600 struct pde_action *act = arg;
1602 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1603 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1607 * Change the page size for the specified virtual address in a way that
1608 * prevents any possibility of the TLB ever having two entries that map the
1609 * same virtual address using different page sizes. This is the recommended
1610 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1611 * machine check exception for a TLB state that is improperly diagnosed as a
1615 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1617 struct pde_action act;
1618 cpuset_t active, other_cpus;
1622 cpuid = PCPU_GET(cpuid);
1623 other_cpus = all_cpus;
1624 CPU_CLR(cpuid, &other_cpus);
1625 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1628 active = pmap->pm_active;
1629 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1631 if (CPU_OVERLAP(&active, &other_cpus)) {
1633 act.invalidate = active;
1637 act.newpde = newpde;
1638 CPU_SET(cpuid, &active);
1639 smp_rendezvous_cpus(active,
1640 smp_no_rendevous_barrier, pmap_update_pde_action,
1641 pmap_update_pde_teardown, &act);
1643 pmap_update_pde_store(pmap, pde, newpde);
1644 if (CPU_ISSET(cpuid, &active))
1645 pmap_update_pde_invalidate(pmap, va, newpde);
1651 * Normal, non-SMP, invalidation functions.
1652 * We inline these within pmap.c for speed.
1655 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1658 switch (pmap->pm_type) {
1660 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1668 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type);
1673 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1677 switch (pmap->pm_type) {
1679 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1680 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1688 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type);
1693 pmap_invalidate_all(pmap_t pmap)
1696 switch (pmap->pm_type) {
1698 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1706 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type);
1711 pmap_invalidate_cache(void)
1718 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1721 pmap_update_pde_store(pmap, pde, newpde);
1722 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1723 pmap_update_pde_invalidate(pmap, va, newpde);
1725 CPU_ZERO(&pmap->pm_save);
1729 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1732 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1736 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1738 KASSERT((sva & PAGE_MASK) == 0,
1739 ("pmap_invalidate_cache_range: sva not page-aligned"));
1740 KASSERT((eva & PAGE_MASK) == 0,
1741 ("pmap_invalidate_cache_range: eva not page-aligned"));
1744 if ((cpu_feature & CPUID_SS) != 0 && !force)
1745 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1746 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1747 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1750 * XXX: Some CPUs fault, hang, or trash the local APIC
1751 * registers if we use CLFLUSH on the local APIC
1752 * range. The local APIC is always uncached, so we
1753 * don't need to flush for that range anyway.
1755 if (pmap_kextract(sva) == lapic_paddr)
1759 * Otherwise, do per-cache line flush. Use the mfence
1760 * instruction to insure that previous stores are
1761 * included in the write-back. The processor
1762 * propagates flush to other processors in the cache
1766 for (; sva < eva; sva += cpu_clflush_line_size)
1772 * No targeted cache flush methods are supported by CPU,
1773 * or the supplied range is bigger than 2MB.
1774 * Globally invalidate cache.
1776 pmap_invalidate_cache();
1781 * Remove the specified set of pages from the data and instruction caches.
1783 * In contrast to pmap_invalidate_cache_range(), this function does not
1784 * rely on the CPU's self-snoop feature, because it is intended for use
1785 * when moving pages into a different cache domain.
1788 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1790 vm_offset_t daddr, eva;
1793 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1794 (cpu_feature & CPUID_CLFSH) == 0)
1795 pmap_invalidate_cache();
1798 for (i = 0; i < count; i++) {
1799 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1800 eva = daddr + PAGE_SIZE;
1801 for (; daddr < eva; daddr += cpu_clflush_line_size)
1809 * Routine: pmap_extract
1811 * Extract the physical page address associated
1812 * with the given map/virtual_address pair.
1815 pmap_extract(pmap_t pmap, vm_offset_t va)
1819 pt_entry_t *pte, PG_V;
1823 PG_V = pmap_valid_bit(pmap);
1825 pdpe = pmap_pdpe(pmap, va);
1826 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1827 if ((*pdpe & PG_PS) != 0)
1828 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1830 pde = pmap_pdpe_to_pde(pdpe, va);
1831 if ((*pde & PG_V) != 0) {
1832 if ((*pde & PG_PS) != 0) {
1833 pa = (*pde & PG_PS_FRAME) |
1836 pte = pmap_pde_to_pte(pde, va);
1837 pa = (*pte & PG_FRAME) |
1848 * Routine: pmap_extract_and_hold
1850 * Atomically extract and hold the physical page
1851 * with the given pmap and virtual address pair
1852 * if that mapping permits the given protection.
1855 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1857 pd_entry_t pde, *pdep;
1858 pt_entry_t pte, PG_RW, PG_V;
1864 PG_RW = pmap_rw_bit(pmap);
1865 PG_V = pmap_valid_bit(pmap);
1868 pdep = pmap_pde(pmap, va);
1869 if (pdep != NULL && (pde = *pdep)) {
1871 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1872 if (vm_page_pa_tryrelock(pmap, (pde &
1873 PG_PS_FRAME) | (va & PDRMASK), &pa))
1875 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1880 pte = *pmap_pde_to_pte(pdep, va);
1882 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1883 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1886 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1897 pmap_kextract(vm_offset_t va)
1902 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1903 pa = DMAP_TO_PHYS(va);
1907 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1910 * Beware of a concurrent promotion that changes the
1911 * PDE at this point! For example, vtopte() must not
1912 * be used to access the PTE because it would use the
1913 * new PDE. It is, however, safe to use the old PDE
1914 * because the page table page is preserved by the
1917 pa = *pmap_pde_to_pte(&pde, va);
1918 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1924 /***************************************************
1925 * Low level mapping routines.....
1926 ***************************************************/
1929 * Add a wired page to the kva.
1930 * Note: not SMP coherent.
1933 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1938 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1941 static __inline void
1942 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1948 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1949 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1953 * Remove a page from the kernel pagetables.
1954 * Note: not SMP coherent.
1957 pmap_kremove(vm_offset_t va)
1966 * Used to map a range of physical addresses into kernel
1967 * virtual address space.
1969 * The value passed in '*virt' is a suggested virtual address for
1970 * the mapping. Architectures which can support a direct-mapped
1971 * physical to virtual region can return the appropriate address
1972 * within that region, leaving '*virt' unchanged. Other
1973 * architectures should map the pages starting at '*virt' and
1974 * update '*virt' with the first usable address after the mapped
1978 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1980 return PHYS_TO_DMAP(start);
1985 * Add a list of wired pages to the kva
1986 * this routine is only used for temporary
1987 * kernel mappings that do not need to have
1988 * page modification or references recorded.
1989 * Note that old mappings are simply written
1990 * over. The page *must* be wired.
1991 * Note: SMP coherent. Uses a ranged shootdown IPI.
1994 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1996 pt_entry_t *endpte, oldpte, pa, *pte;
2002 endpte = pte + count;
2003 while (pte < endpte) {
2005 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2006 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2007 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2009 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
2013 if (__predict_false((oldpte & X86_PG_V) != 0))
2014 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2019 * This routine tears out page mappings from the
2020 * kernel -- it is meant only for temporary mappings.
2021 * Note: SMP coherent. Uses a ranged shootdown IPI.
2024 pmap_qremove(vm_offset_t sva, int count)
2029 while (count-- > 0) {
2030 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2034 pmap_invalidate_range(kernel_pmap, sva, va);
2037 /***************************************************
2038 * Page table page management routines.....
2039 ***************************************************/
2040 static __inline void
2041 pmap_free_zero_pages(struct spglist *free)
2045 while ((m = SLIST_FIRST(free)) != NULL) {
2046 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2047 /* Preserve the page's PG_ZERO setting. */
2048 vm_page_free_toq(m);
2053 * Schedule the specified unused page table page to be freed. Specifically,
2054 * add the page to the specified list of pages that will be released to the
2055 * physical memory manager after the TLB has been updated.
2057 static __inline void
2058 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2059 boolean_t set_PG_ZERO)
2063 m->flags |= PG_ZERO;
2065 m->flags &= ~PG_ZERO;
2066 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2070 * Inserts the specified page table page into the specified pmap's collection
2071 * of idle page table pages. Each of a pmap's page table pages is responsible
2072 * for mapping a distinct range of virtual addresses. The pmap's collection is
2073 * ordered by this virtual address range.
2076 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2079 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2080 return (vm_radix_insert(&pmap->pm_root, mpte));
2084 * Looks for a page table page mapping the specified virtual address in the
2085 * specified pmap's collection of idle page table pages. Returns NULL if there
2086 * is no page table page corresponding to the specified virtual address.
2088 static __inline vm_page_t
2089 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2092 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2093 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2097 * Removes the specified page table page from the specified pmap's collection
2098 * of idle page table pages. The specified page table page must be a member of
2099 * the pmap's collection.
2101 static __inline void
2102 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2105 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2106 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2110 * Decrements a page table page's wire count, which is used to record the
2111 * number of valid page table entries within the page. If the wire count
2112 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2113 * page table page was unmapped and FALSE otherwise.
2115 static inline boolean_t
2116 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2120 if (m->wire_count == 0) {
2121 _pmap_unwire_ptp(pmap, va, m, free);
2128 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2131 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2133 * unmap the page table page
2135 if (m->pindex >= (NUPDE + NUPDPE)) {
2138 pml4 = pmap_pml4e(pmap, va);
2140 } else if (m->pindex >= NUPDE) {
2143 pdp = pmap_pdpe(pmap, va);
2148 pd = pmap_pde(pmap, va);
2151 pmap_resident_count_dec(pmap, 1);
2152 if (m->pindex < NUPDE) {
2153 /* We just released a PT, unhold the matching PD */
2156 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2157 pmap_unwire_ptp(pmap, va, pdpg, free);
2159 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2160 /* We just released a PD, unhold the matching PDP */
2163 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2164 pmap_unwire_ptp(pmap, va, pdppg, free);
2168 * This is a release store so that the ordinary store unmapping
2169 * the page table page is globally performed before TLB shoot-
2172 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2175 * Put page on a list so that it is released after
2176 * *ALL* TLB shootdown is done
2178 pmap_add_delayed_free_list(m, free, TRUE);
2182 * After removing a page table entry, this routine is used to
2183 * conditionally free the page, and manage the hold/wire counts.
2186 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2187 struct spglist *free)
2191 if (va >= VM_MAXUSER_ADDRESS)
2193 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2194 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2195 return (pmap_unwire_ptp(pmap, va, mpte, free));
2199 pmap_pinit0(pmap_t pmap)
2202 PMAP_LOCK_INIT(pmap);
2203 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2204 pmap->pm_cr3 = KPML4phys;
2205 pmap->pm_root.rt_root = 0;
2206 CPU_ZERO(&pmap->pm_active);
2207 CPU_ZERO(&pmap->pm_save);
2208 PCPU_SET(curpmap, pmap);
2209 TAILQ_INIT(&pmap->pm_pvchunk);
2210 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2211 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
2212 pmap->pm_flags = pmap_flags;
2216 * Initialize a preallocated and zeroed pmap structure,
2217 * such as one in a vmspace structure.
2220 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2223 vm_paddr_t pml4phys;
2227 * allocate the page directory page
2229 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2230 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2233 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2234 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2236 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2238 if ((pml4pg->flags & PG_ZERO) == 0)
2239 pagezero(pmap->pm_pml4);
2242 * Do not install the host kernel mappings in the nested page
2243 * tables. These mappings are meaningless in the guest physical
2246 if ((pmap->pm_type = pm_type) == PT_X86) {
2247 pmap->pm_cr3 = pml4phys;
2249 /* Wire in kernel global address entries. */
2250 for (i = 0; i < NKPML4E; i++) {
2251 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2252 X86_PG_RW | X86_PG_V | PG_U;
2254 for (i = 0; i < ndmpdpphys; i++) {
2255 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2256 X86_PG_RW | X86_PG_V | PG_U;
2259 /* install self-referential address mapping entry(s) */
2260 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2261 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2263 if (pmap_pcid_enabled) {
2264 pmap->pm_pcid = alloc_unr(&pcid_unr);
2265 if (pmap->pm_pcid != -1)
2266 pmap->pm_cr3 |= pmap->pm_pcid;
2270 pmap->pm_root.rt_root = 0;
2271 CPU_ZERO(&pmap->pm_active);
2272 TAILQ_INIT(&pmap->pm_pvchunk);
2273 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2274 pmap->pm_flags = flags;
2275 pmap->pm_eptgen = 0;
2276 CPU_ZERO(&pmap->pm_save);
2282 pmap_pinit(pmap_t pmap)
2285 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2289 * This routine is called if the desired page table page does not exist.
2291 * If page table page allocation fails, this routine may sleep before
2292 * returning NULL. It sleeps only if a lock pointer was given.
2294 * Note: If a page allocation fails at page table level two or three,
2295 * one or two pages may be held during the wait, only to be released
2296 * afterwards. This conservative approach is easily argued to avoid
2300 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2302 vm_page_t m, pdppg, pdpg;
2303 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2305 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2307 PG_A = pmap_accessed_bit(pmap);
2308 PG_M = pmap_modified_bit(pmap);
2309 PG_V = pmap_valid_bit(pmap);
2310 PG_RW = pmap_rw_bit(pmap);
2313 * Allocate a page table page.
2315 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2316 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2317 if (lockp != NULL) {
2318 RELEASE_PV_LIST_LOCK(lockp);
2320 rw_runlock(&pvh_global_lock);
2322 rw_rlock(&pvh_global_lock);
2327 * Indicate the need to retry. While waiting, the page table
2328 * page may have been allocated.
2332 if ((m->flags & PG_ZERO) == 0)
2336 * Map the pagetable page into the process address space, if
2337 * it isn't already there.
2340 if (ptepindex >= (NUPDE + NUPDPE)) {
2342 vm_pindex_t pml4index;
2344 /* Wire up a new PDPE page */
2345 pml4index = ptepindex - (NUPDE + NUPDPE);
2346 pml4 = &pmap->pm_pml4[pml4index];
2347 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2349 } else if (ptepindex >= NUPDE) {
2350 vm_pindex_t pml4index;
2351 vm_pindex_t pdpindex;
2355 /* Wire up a new PDE page */
2356 pdpindex = ptepindex - NUPDE;
2357 pml4index = pdpindex >> NPML4EPGSHIFT;
2359 pml4 = &pmap->pm_pml4[pml4index];
2360 if ((*pml4 & PG_V) == 0) {
2361 /* Have to allocate a new pdp, recurse */
2362 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2365 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2366 vm_page_free_zero(m);
2370 /* Add reference to pdp page */
2371 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2372 pdppg->wire_count++;
2374 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2376 /* Now find the pdp page */
2377 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2378 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2381 vm_pindex_t pml4index;
2382 vm_pindex_t pdpindex;
2387 /* Wire up a new PTE page */
2388 pdpindex = ptepindex >> NPDPEPGSHIFT;
2389 pml4index = pdpindex >> NPML4EPGSHIFT;
2391 /* First, find the pdp and check that its valid. */
2392 pml4 = &pmap->pm_pml4[pml4index];
2393 if ((*pml4 & PG_V) == 0) {
2394 /* Have to allocate a new pd, recurse */
2395 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2398 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2399 vm_page_free_zero(m);
2402 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2403 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2405 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2406 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2407 if ((*pdp & PG_V) == 0) {
2408 /* Have to allocate a new pd, recurse */
2409 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2412 atomic_subtract_int(&vm_cnt.v_wire_count,
2414 vm_page_free_zero(m);
2418 /* Add reference to the pd page */
2419 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2423 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2425 /* Now we know where the page directory page is */
2426 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2427 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2430 pmap_resident_count_inc(pmap, 1);
2436 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2438 vm_pindex_t pdpindex, ptepindex;
2439 pdp_entry_t *pdpe, PG_V;
2442 PG_V = pmap_valid_bit(pmap);
2445 pdpe = pmap_pdpe(pmap, va);
2446 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2447 /* Add a reference to the pd page. */
2448 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2451 /* Allocate a pd page. */
2452 ptepindex = pmap_pde_pindex(va);
2453 pdpindex = ptepindex >> NPDPEPGSHIFT;
2454 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2455 if (pdpg == NULL && lockp != NULL)
2462 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2464 vm_pindex_t ptepindex;
2465 pd_entry_t *pd, PG_V;
2468 PG_V = pmap_valid_bit(pmap);
2471 * Calculate pagetable page index
2473 ptepindex = pmap_pde_pindex(va);
2476 * Get the page directory entry
2478 pd = pmap_pde(pmap, va);
2481 * This supports switching from a 2MB page to a
2484 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2485 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2487 * Invalidation of the 2MB page mapping may have caused
2488 * the deallocation of the underlying PD page.
2495 * If the page table page is mapped, we just increment the
2496 * hold count, and activate it.
2498 if (pd != NULL && (*pd & PG_V) != 0) {
2499 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2503 * Here if the pte page isn't mapped, or if it has been
2506 m = _pmap_allocpte(pmap, ptepindex, lockp);
2507 if (m == NULL && lockp != NULL)
2514 /***************************************************
2515 * Pmap allocation/deallocation routines.
2516 ***************************************************/
2519 * Release any resources held by the given physical map.
2520 * Called when a pmap initialized by pmap_pinit is being released.
2521 * Should only be called if the map contains no valid mappings.
2524 pmap_release(pmap_t pmap)
2529 KASSERT(pmap->pm_stats.resident_count == 0,
2530 ("pmap_release: pmap resident count %ld != 0",
2531 pmap->pm_stats.resident_count));
2532 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2533 ("pmap_release: pmap has reserved page table page(s)"));
2535 if (pmap_pcid_enabled) {
2537 * Invalidate any left TLB entries, to allow the reuse
2540 pmap_invalidate_all(pmap);
2543 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2545 for (i = 0; i < NKPML4E; i++) /* KVA */
2546 pmap->pm_pml4[KPML4BASE + i] = 0;
2547 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2548 pmap->pm_pml4[DMPML4I + i] = 0;
2549 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2552 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2553 vm_page_free_zero(m);
2554 if (pmap->pm_pcid != -1)
2555 free_unr(&pcid_unr, pmap->pm_pcid);
2559 kvm_size(SYSCTL_HANDLER_ARGS)
2561 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2563 return sysctl_handle_long(oidp, &ksize, 0, req);
2565 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2566 0, 0, kvm_size, "LU", "Size of KVM");
2569 kvm_free(SYSCTL_HANDLER_ARGS)
2571 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2573 return sysctl_handle_long(oidp, &kfree, 0, req);
2575 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2576 0, 0, kvm_free, "LU", "Amount of KVM free");
2579 * grow the number of kernel page table entries, if needed
2582 pmap_growkernel(vm_offset_t addr)
2586 pd_entry_t *pde, newpdir;
2589 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2592 * Return if "addr" is within the range of kernel page table pages
2593 * that were preallocated during pmap bootstrap. Moreover, leave
2594 * "kernel_vm_end" and the kernel page table as they were.
2596 * The correctness of this action is based on the following
2597 * argument: vm_map_insert() allocates contiguous ranges of the
2598 * kernel virtual address space. It calls this function if a range
2599 * ends after "kernel_vm_end". If the kernel is mapped between
2600 * "kernel_vm_end" and "addr", then the range cannot begin at
2601 * "kernel_vm_end". In fact, its beginning address cannot be less
2602 * than the kernel. Thus, there is no immediate need to allocate
2603 * any new kernel page table pages between "kernel_vm_end" and
2606 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2609 addr = roundup2(addr, NBPDR);
2610 if (addr - 1 >= kernel_map->max_offset)
2611 addr = kernel_map->max_offset;
2612 while (kernel_vm_end < addr) {
2613 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2614 if ((*pdpe & X86_PG_V) == 0) {
2615 /* We need a new PDP entry */
2616 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2617 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2618 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2620 panic("pmap_growkernel: no memory to grow kernel");
2621 if ((nkpg->flags & PG_ZERO) == 0)
2622 pmap_zero_page(nkpg);
2623 paddr = VM_PAGE_TO_PHYS(nkpg);
2624 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2625 X86_PG_A | X86_PG_M);
2626 continue; /* try again */
2628 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2629 if ((*pde & X86_PG_V) != 0) {
2630 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2631 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2632 kernel_vm_end = kernel_map->max_offset;
2638 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2639 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2642 panic("pmap_growkernel: no memory to grow kernel");
2643 if ((nkpg->flags & PG_ZERO) == 0)
2644 pmap_zero_page(nkpg);
2645 paddr = VM_PAGE_TO_PHYS(nkpg);
2646 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2647 pde_store(pde, newpdir);
2649 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2650 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2651 kernel_vm_end = kernel_map->max_offset;
2658 /***************************************************
2659 * page management routines.
2660 ***************************************************/
2662 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2663 CTASSERT(_NPCM == 3);
2664 CTASSERT(_NPCPV == 168);
2666 static __inline struct pv_chunk *
2667 pv_to_chunk(pv_entry_t pv)
2670 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2673 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2675 #define PC_FREE0 0xfffffffffffffffful
2676 #define PC_FREE1 0xfffffffffffffffful
2677 #define PC_FREE2 0x000000fffffffffful
2679 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2682 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2684 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2685 "Current number of pv entry chunks");
2686 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2687 "Current number of pv entry chunks allocated");
2688 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2689 "Current number of pv entry chunks frees");
2690 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2691 "Number of times tried to get a chunk page but failed.");
2693 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2694 static int pv_entry_spare;
2696 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2697 "Current number of pv entry frees");
2698 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2699 "Current number of pv entry allocs");
2700 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2701 "Current number of pv entries");
2702 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2703 "Current number of spare pv entries");
2707 * We are in a serious low memory condition. Resort to
2708 * drastic measures to free some pages so we can allocate
2709 * another pv entry chunk.
2711 * Returns NULL if PV entries were reclaimed from the specified pmap.
2713 * We do not, however, unmap 2mpages because subsequent accesses will
2714 * allocate per-page pv entries until repromotion occurs, thereby
2715 * exacerbating the shortage of free pv entries.
2718 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2720 struct pch new_tail;
2721 struct pv_chunk *pc;
2722 struct md_page *pvh;
2725 pt_entry_t *pte, tpte;
2726 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2730 struct spglist free;
2732 int bit, field, freed;
2734 rw_assert(&pvh_global_lock, RA_LOCKED);
2735 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2736 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2739 PG_G = PG_A = PG_M = PG_RW = 0;
2741 TAILQ_INIT(&new_tail);
2742 mtx_lock(&pv_chunks_mutex);
2743 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2744 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2745 mtx_unlock(&pv_chunks_mutex);
2746 if (pmap != pc->pc_pmap) {
2748 pmap_invalidate_all(pmap);
2749 if (pmap != locked_pmap)
2753 /* Avoid deadlock and lock recursion. */
2754 if (pmap > locked_pmap) {
2755 RELEASE_PV_LIST_LOCK(lockp);
2757 } else if (pmap != locked_pmap &&
2758 !PMAP_TRYLOCK(pmap)) {
2760 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2761 mtx_lock(&pv_chunks_mutex);
2764 PG_G = pmap_global_bit(pmap);
2765 PG_A = pmap_accessed_bit(pmap);
2766 PG_M = pmap_modified_bit(pmap);
2767 PG_RW = pmap_rw_bit(pmap);
2771 * Destroy every non-wired, 4 KB page mapping in the chunk.
2774 for (field = 0; field < _NPCM; field++) {
2775 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2776 inuse != 0; inuse &= ~(1UL << bit)) {
2778 pv = &pc->pc_pventry[field * 64 + bit];
2780 pde = pmap_pde(pmap, va);
2781 if ((*pde & PG_PS) != 0)
2783 pte = pmap_pde_to_pte(pde, va);
2784 if ((*pte & PG_W) != 0)
2786 tpte = pte_load_clear(pte);
2787 if ((tpte & PG_G) != 0)
2788 pmap_invalidate_page(pmap, va);
2789 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2790 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2792 if ((tpte & PG_A) != 0)
2793 vm_page_aflag_set(m, PGA_REFERENCED);
2794 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2795 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2797 if (TAILQ_EMPTY(&m->md.pv_list) &&
2798 (m->flags & PG_FICTITIOUS) == 0) {
2799 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2800 if (TAILQ_EMPTY(&pvh->pv_list)) {
2801 vm_page_aflag_clear(m,
2805 pc->pc_map[field] |= 1UL << bit;
2806 pmap_unuse_pt(pmap, va, *pde, &free);
2811 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2812 mtx_lock(&pv_chunks_mutex);
2815 /* Every freed mapping is for a 4 KB page. */
2816 pmap_resident_count_dec(pmap, freed);
2817 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2818 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2819 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2820 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2821 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2822 pc->pc_map[2] == PC_FREE2) {
2823 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2824 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2825 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2826 /* Entire chunk is free; return it. */
2827 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2828 dump_drop_page(m_pc->phys_addr);
2829 mtx_lock(&pv_chunks_mutex);
2832 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2833 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2834 mtx_lock(&pv_chunks_mutex);
2835 /* One freed pv entry in locked_pmap is sufficient. */
2836 if (pmap == locked_pmap)
2839 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2840 mtx_unlock(&pv_chunks_mutex);
2842 pmap_invalidate_all(pmap);
2843 if (pmap != locked_pmap)
2846 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2847 m_pc = SLIST_FIRST(&free);
2848 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2849 /* Recycle a freed page table page. */
2850 m_pc->wire_count = 1;
2851 atomic_add_int(&vm_cnt.v_wire_count, 1);
2853 pmap_free_zero_pages(&free);
2858 * free the pv_entry back to the free list
2861 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2863 struct pv_chunk *pc;
2864 int idx, field, bit;
2866 rw_assert(&pvh_global_lock, RA_LOCKED);
2867 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2868 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2869 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2870 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2871 pc = pv_to_chunk(pv);
2872 idx = pv - &pc->pc_pventry[0];
2875 pc->pc_map[field] |= 1ul << bit;
2876 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2877 pc->pc_map[2] != PC_FREE2) {
2878 /* 98% of the time, pc is already at the head of the list. */
2879 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2880 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2881 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2885 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2890 free_pv_chunk(struct pv_chunk *pc)
2894 mtx_lock(&pv_chunks_mutex);
2895 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2896 mtx_unlock(&pv_chunks_mutex);
2897 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2898 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2899 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2900 /* entire chunk is free, return it */
2901 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2902 dump_drop_page(m->phys_addr);
2903 vm_page_unwire(m, PQ_INACTIVE);
2908 * Returns a new PV entry, allocating a new PV chunk from the system when
2909 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2910 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2913 * The given PV list lock may be released.
2916 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2920 struct pv_chunk *pc;
2923 rw_assert(&pvh_global_lock, RA_LOCKED);
2924 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2925 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2927 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2929 for (field = 0; field < _NPCM; field++) {
2930 if (pc->pc_map[field]) {
2931 bit = bsfq(pc->pc_map[field]);
2935 if (field < _NPCM) {
2936 pv = &pc->pc_pventry[field * 64 + bit];
2937 pc->pc_map[field] &= ~(1ul << bit);
2938 /* If this was the last item, move it to tail */
2939 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2940 pc->pc_map[2] == 0) {
2941 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2942 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2945 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2946 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2950 /* No free items, allocate another chunk */
2951 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2954 if (lockp == NULL) {
2955 PV_STAT(pc_chunk_tryfail++);
2958 m = reclaim_pv_chunk(pmap, lockp);
2962 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2963 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2964 dump_add_page(m->phys_addr);
2965 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2967 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2968 pc->pc_map[1] = PC_FREE1;
2969 pc->pc_map[2] = PC_FREE2;
2970 mtx_lock(&pv_chunks_mutex);
2971 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2972 mtx_unlock(&pv_chunks_mutex);
2973 pv = &pc->pc_pventry[0];
2974 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2975 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2976 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2981 * Returns the number of one bits within the given PV chunk map element.
2984 popcnt_pc_map_elem(uint64_t elem)
2989 * This simple method of counting the one bits performs well because
2990 * the given element typically contains more zero bits than one bits.
2993 for (; elem != 0; elem &= elem - 1)
2999 * Ensure that the number of spare PV entries in the specified pmap meets or
3000 * exceeds the given count, "needed".
3002 * The given PV list lock may be released.
3005 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3007 struct pch new_tail;
3008 struct pv_chunk *pc;
3012 rw_assert(&pvh_global_lock, RA_LOCKED);
3013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3014 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3017 * Newly allocated PV chunks must be stored in a private list until
3018 * the required number of PV chunks have been allocated. Otherwise,
3019 * reclaim_pv_chunk() could recycle one of these chunks. In
3020 * contrast, these chunks must be added to the pmap upon allocation.
3022 TAILQ_INIT(&new_tail);
3025 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3026 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
3027 free = popcnt_pc_map_elem(pc->pc_map[0]);
3028 free += popcnt_pc_map_elem(pc->pc_map[1]);
3029 free += popcnt_pc_map_elem(pc->pc_map[2]);
3031 free = popcntq(pc->pc_map[0]);
3032 free += popcntq(pc->pc_map[1]);
3033 free += popcntq(pc->pc_map[2]);
3038 if (avail >= needed)
3041 for (; avail < needed; avail += _NPCPV) {
3042 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3045 m = reclaim_pv_chunk(pmap, lockp);
3049 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3050 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3051 dump_add_page(m->phys_addr);
3052 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3054 pc->pc_map[0] = PC_FREE0;
3055 pc->pc_map[1] = PC_FREE1;
3056 pc->pc_map[2] = PC_FREE2;
3057 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3058 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3059 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3061 if (!TAILQ_EMPTY(&new_tail)) {
3062 mtx_lock(&pv_chunks_mutex);
3063 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3064 mtx_unlock(&pv_chunks_mutex);
3069 * First find and then remove the pv entry for the specified pmap and virtual
3070 * address from the specified pv list. Returns the pv entry if found and NULL
3071 * otherwise. This operation can be performed on pv lists for either 4KB or
3072 * 2MB page mappings.
3074 static __inline pv_entry_t
3075 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3079 rw_assert(&pvh_global_lock, RA_LOCKED);
3080 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3081 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3082 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3091 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3092 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3093 * entries for each of the 4KB page mappings.
3096 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3097 struct rwlock **lockp)
3099 struct md_page *pvh;
3100 struct pv_chunk *pc;
3102 vm_offset_t va_last;
3106 rw_assert(&pvh_global_lock, RA_LOCKED);
3107 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3108 KASSERT((pa & PDRMASK) == 0,
3109 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3110 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3113 * Transfer the 2mpage's pv entry for this mapping to the first
3114 * page's pv list. Once this transfer begins, the pv list lock
3115 * must not be released until the last pv entry is reinstantiated.
3117 pvh = pa_to_pvh(pa);
3118 va = trunc_2mpage(va);
3119 pv = pmap_pvh_remove(pvh, pmap, va);
3120 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3121 m = PHYS_TO_VM_PAGE(pa);
3122 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3124 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3125 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3126 va_last = va + NBPDR - PAGE_SIZE;
3128 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3129 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3130 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3131 for (field = 0; field < _NPCM; field++) {
3132 while (pc->pc_map[field]) {
3133 bit = bsfq(pc->pc_map[field]);
3134 pc->pc_map[field] &= ~(1ul << bit);
3135 pv = &pc->pc_pventry[field * 64 + bit];
3139 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3140 ("pmap_pv_demote_pde: page %p is not managed", m));
3141 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3147 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3148 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3151 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3152 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3153 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3155 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3156 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3160 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3161 * replace the many pv entries for the 4KB page mappings by a single pv entry
3162 * for the 2MB page mapping.
3165 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3166 struct rwlock **lockp)
3168 struct md_page *pvh;
3170 vm_offset_t va_last;
3173 rw_assert(&pvh_global_lock, RA_LOCKED);
3174 KASSERT((pa & PDRMASK) == 0,
3175 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3176 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3179 * Transfer the first page's pv entry for this mapping to the 2mpage's
3180 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3181 * a transfer avoids the possibility that get_pv_entry() calls
3182 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3183 * mappings that is being promoted.
3185 m = PHYS_TO_VM_PAGE(pa);
3186 va = trunc_2mpage(va);
3187 pv = pmap_pvh_remove(&m->md, pmap, va);
3188 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3189 pvh = pa_to_pvh(pa);
3190 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3192 /* Free the remaining NPTEPG - 1 pv entries. */
3193 va_last = va + NBPDR - PAGE_SIZE;
3197 pmap_pvh_free(&m->md, pmap, va);
3198 } while (va < va_last);
3202 * First find and then destroy the pv entry for the specified pmap and virtual
3203 * address. This operation can be performed on pv lists for either 4KB or 2MB
3207 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3211 pv = pmap_pvh_remove(pvh, pmap, va);
3212 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3213 free_pv_entry(pmap, pv);
3217 * Conditionally create the PV entry for a 4KB page mapping if the required
3218 * memory can be allocated without resorting to reclamation.
3221 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3222 struct rwlock **lockp)
3226 rw_assert(&pvh_global_lock, RA_LOCKED);
3227 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3228 /* Pass NULL instead of the lock pointer to disable reclamation. */
3229 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3231 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3232 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3240 * Conditionally create the PV entry for a 2MB page mapping if the required
3241 * memory can be allocated without resorting to reclamation.
3244 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3245 struct rwlock **lockp)
3247 struct md_page *pvh;
3250 rw_assert(&pvh_global_lock, RA_LOCKED);
3251 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3252 /* Pass NULL instead of the lock pointer to disable reclamation. */
3253 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3255 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3256 pvh = pa_to_pvh(pa);
3257 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3265 * Fills a page table page with mappings to consecutive physical pages.
3268 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3272 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3274 newpte += PAGE_SIZE;
3279 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3280 * mapping is invalidated.
3283 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3285 struct rwlock *lock;
3289 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3296 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3297 struct rwlock **lockp)
3299 pd_entry_t newpde, oldpde;
3300 pt_entry_t *firstpte, newpte;
3301 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3304 struct spglist free;
3307 PG_G = pmap_global_bit(pmap);
3308 PG_A = pmap_accessed_bit(pmap);
3309 PG_M = pmap_modified_bit(pmap);
3310 PG_RW = pmap_rw_bit(pmap);
3311 PG_V = pmap_valid_bit(pmap);
3312 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3314 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3316 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3317 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3318 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3320 pmap_remove_pt_page(pmap, mpte);
3322 KASSERT((oldpde & PG_W) == 0,
3323 ("pmap_demote_pde: page table page for a wired mapping"
3327 * Invalidate the 2MB page mapping and return "failure" if the
3328 * mapping was never accessed or the allocation of the new
3329 * page table page fails. If the 2MB page mapping belongs to
3330 * the direct map region of the kernel's address space, then
3331 * the page allocation request specifies the highest possible
3332 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3333 * normal. Page table pages are preallocated for every other
3334 * part of the kernel address space, so the direct map region
3335 * is the only part of the kernel address space that must be
3338 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3339 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3340 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3341 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3343 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3345 pmap_invalidate_page(pmap, trunc_2mpage(va));
3346 pmap_free_zero_pages(&free);
3347 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3348 " in pmap %p", va, pmap);
3351 if (va < VM_MAXUSER_ADDRESS)
3352 pmap_resident_count_inc(pmap, 1);
3354 mptepa = VM_PAGE_TO_PHYS(mpte);
3355 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3356 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3357 KASSERT((oldpde & PG_A) != 0,
3358 ("pmap_demote_pde: oldpde is missing PG_A"));
3359 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3360 ("pmap_demote_pde: oldpde is missing PG_M"));
3361 newpte = oldpde & ~PG_PS;
3362 newpte = pmap_swap_pat(pmap, newpte);
3365 * If the page table page is new, initialize it.
3367 if (mpte->wire_count == 1) {
3368 mpte->wire_count = NPTEPG;
3369 pmap_fill_ptp(firstpte, newpte);
3371 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3372 ("pmap_demote_pde: firstpte and newpte map different physical"
3376 * If the mapping has changed attributes, update the page table
3379 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3380 pmap_fill_ptp(firstpte, newpte);
3383 * The spare PV entries must be reserved prior to demoting the
3384 * mapping, that is, prior to changing the PDE. Otherwise, the state
3385 * of the PDE and the PV lists will be inconsistent, which can result
3386 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3387 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3388 * PV entry for the 2MB page mapping that is being demoted.
3390 if ((oldpde & PG_MANAGED) != 0)
3391 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3394 * Demote the mapping. This pmap is locked. The old PDE has
3395 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3396 * set. Thus, there is no danger of a race with another
3397 * processor changing the setting of PG_A and/or PG_M between
3398 * the read above and the store below.
3400 if (workaround_erratum383)
3401 pmap_update_pde(pmap, va, pde, newpde);
3403 pde_store(pde, newpde);
3406 * Invalidate a stale recursive mapping of the page table page.
3408 if (va >= VM_MAXUSER_ADDRESS)
3409 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3412 * Demote the PV entry.
3414 if ((oldpde & PG_MANAGED) != 0)
3415 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3417 atomic_add_long(&pmap_pde_demotions, 1);
3418 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3419 " in pmap %p", va, pmap);
3424 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3427 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3433 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3434 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3435 mpte = pmap_lookup_pt_page(pmap, va);
3437 panic("pmap_remove_kernel_pde: Missing pt page.");
3439 pmap_remove_pt_page(pmap, mpte);
3440 mptepa = VM_PAGE_TO_PHYS(mpte);
3441 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3444 * Initialize the page table page.
3446 pagezero((void *)PHYS_TO_DMAP(mptepa));
3449 * Demote the mapping.
3451 if (workaround_erratum383)
3452 pmap_update_pde(pmap, va, pde, newpde);
3454 pde_store(pde, newpde);
3457 * Invalidate a stale recursive mapping of the page table page.
3459 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3463 * pmap_remove_pde: do the things to unmap a superpage in a process
3466 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3467 struct spglist *free, struct rwlock **lockp)
3469 struct md_page *pvh;
3471 vm_offset_t eva, va;
3473 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3475 PG_G = pmap_global_bit(pmap);
3476 PG_A = pmap_accessed_bit(pmap);
3477 PG_M = pmap_modified_bit(pmap);
3478 PG_RW = pmap_rw_bit(pmap);
3480 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3481 KASSERT((sva & PDRMASK) == 0,
3482 ("pmap_remove_pde: sva is not 2mpage aligned"));
3483 oldpde = pte_load_clear(pdq);
3485 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3488 * Machines that don't support invlpg, also don't support
3492 pmap_invalidate_page(kernel_pmap, sva);
3493 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3494 if (oldpde & PG_MANAGED) {
3495 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3496 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3497 pmap_pvh_free(pvh, pmap, sva);
3499 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3500 va < eva; va += PAGE_SIZE, m++) {
3501 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3504 vm_page_aflag_set(m, PGA_REFERENCED);
3505 if (TAILQ_EMPTY(&m->md.pv_list) &&
3506 TAILQ_EMPTY(&pvh->pv_list))
3507 vm_page_aflag_clear(m, PGA_WRITEABLE);
3510 if (pmap == kernel_pmap) {
3511 pmap_remove_kernel_pde(pmap, pdq, sva);
3513 mpte = pmap_lookup_pt_page(pmap, sva);
3515 pmap_remove_pt_page(pmap, mpte);
3516 pmap_resident_count_dec(pmap, 1);
3517 KASSERT(mpte->wire_count == NPTEPG,
3518 ("pmap_remove_pde: pte page wire count error"));
3519 mpte->wire_count = 0;
3520 pmap_add_delayed_free_list(mpte, free, FALSE);
3521 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
3524 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3528 * pmap_remove_pte: do the things to unmap a page in a process
3531 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3532 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3534 struct md_page *pvh;
3535 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3538 PG_A = pmap_accessed_bit(pmap);
3539 PG_M = pmap_modified_bit(pmap);
3540 PG_RW = pmap_rw_bit(pmap);
3542 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3543 oldpte = pte_load_clear(ptq);
3545 pmap->pm_stats.wired_count -= 1;
3546 pmap_resident_count_dec(pmap, 1);
3547 if (oldpte & PG_MANAGED) {
3548 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3549 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3552 vm_page_aflag_set(m, PGA_REFERENCED);
3553 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3554 pmap_pvh_free(&m->md, pmap, va);
3555 if (TAILQ_EMPTY(&m->md.pv_list) &&
3556 (m->flags & PG_FICTITIOUS) == 0) {
3557 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3558 if (TAILQ_EMPTY(&pvh->pv_list))
3559 vm_page_aflag_clear(m, PGA_WRITEABLE);
3562 return (pmap_unuse_pt(pmap, va, ptepde, free));
3566 * Remove a single page from a process address space
3569 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3570 struct spglist *free)
3572 struct rwlock *lock;
3573 pt_entry_t *pte, PG_V;
3575 PG_V = pmap_valid_bit(pmap);
3576 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3577 if ((*pde & PG_V) == 0)
3579 pte = pmap_pde_to_pte(pde, va);
3580 if ((*pte & PG_V) == 0)
3583 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3586 pmap_invalidate_page(pmap, va);
3590 * Remove the given range of addresses from the specified map.
3592 * It is assumed that the start and end are properly
3593 * rounded to the page size.
3596 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3598 struct rwlock *lock;
3599 vm_offset_t va, va_next;
3600 pml4_entry_t *pml4e;
3602 pd_entry_t ptpaddr, *pde;
3603 pt_entry_t *pte, PG_G, PG_V;
3604 struct spglist free;
3607 PG_G = pmap_global_bit(pmap);
3608 PG_V = pmap_valid_bit(pmap);
3611 * Perform an unsynchronized read. This is, however, safe.
3613 if (pmap->pm_stats.resident_count == 0)
3619 rw_rlock(&pvh_global_lock);
3623 * special handling of removing one page. a very
3624 * common operation and easy to short circuit some
3627 if (sva + PAGE_SIZE == eva) {
3628 pde = pmap_pde(pmap, sva);
3629 if (pde && (*pde & PG_PS) == 0) {
3630 pmap_remove_page(pmap, sva, pde, &free);
3636 for (; sva < eva; sva = va_next) {
3638 if (pmap->pm_stats.resident_count == 0)
3641 pml4e = pmap_pml4e(pmap, sva);
3642 if ((*pml4e & PG_V) == 0) {
3643 va_next = (sva + NBPML4) & ~PML4MASK;
3649 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3650 if ((*pdpe & PG_V) == 0) {
3651 va_next = (sva + NBPDP) & ~PDPMASK;
3658 * Calculate index for next page table.
3660 va_next = (sva + NBPDR) & ~PDRMASK;
3664 pde = pmap_pdpe_to_pde(pdpe, sva);
3668 * Weed out invalid mappings.
3674 * Check for large page.
3676 if ((ptpaddr & PG_PS) != 0) {
3678 * Are we removing the entire large page? If not,
3679 * demote the mapping and fall through.
3681 if (sva + NBPDR == va_next && eva >= va_next) {
3683 * The TLB entry for a PG_G mapping is
3684 * invalidated by pmap_remove_pde().
3686 if ((ptpaddr & PG_G) == 0)
3688 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3690 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3692 /* The large page mapping was destroyed. */
3699 * Limit our scan to either the end of the va represented
3700 * by the current page table page, or to the end of the
3701 * range being removed.
3707 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3710 if (va != va_next) {
3711 pmap_invalidate_range(pmap, va, sva);
3716 if ((*pte & PG_G) == 0)
3718 else if (va == va_next)
3720 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3727 pmap_invalidate_range(pmap, va, sva);
3733 pmap_invalidate_all(pmap);
3734 rw_runlock(&pvh_global_lock);
3736 pmap_free_zero_pages(&free);
3740 * Routine: pmap_remove_all
3742 * Removes this physical page from
3743 * all physical maps in which it resides.
3744 * Reflects back modify bits to the pager.
3747 * Original versions of this routine were very
3748 * inefficient because they iteratively called
3749 * pmap_remove (slow...)
3753 pmap_remove_all(vm_page_t m)
3755 struct md_page *pvh;
3758 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3761 struct spglist free;
3763 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3764 ("pmap_remove_all: page %p is not managed", m));
3766 rw_wlock(&pvh_global_lock);
3767 if ((m->flags & PG_FICTITIOUS) != 0)
3768 goto small_mappings;
3769 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3770 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3774 pde = pmap_pde(pmap, va);
3775 (void)pmap_demote_pde(pmap, pde, va);
3779 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3782 PG_A = pmap_accessed_bit(pmap);
3783 PG_M = pmap_modified_bit(pmap);
3784 PG_RW = pmap_rw_bit(pmap);
3785 pmap_resident_count_dec(pmap, 1);
3786 pde = pmap_pde(pmap, pv->pv_va);
3787 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3788 " a 2mpage in page %p's pv list", m));
3789 pte = pmap_pde_to_pte(pde, pv->pv_va);
3790 tpte = pte_load_clear(pte);
3792 pmap->pm_stats.wired_count--;
3794 vm_page_aflag_set(m, PGA_REFERENCED);
3797 * Update the vm_page_t clean and reference bits.
3799 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3801 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3802 pmap_invalidate_page(pmap, pv->pv_va);
3803 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3805 free_pv_entry(pmap, pv);
3808 vm_page_aflag_clear(m, PGA_WRITEABLE);
3809 rw_wunlock(&pvh_global_lock);
3810 pmap_free_zero_pages(&free);
3814 * pmap_protect_pde: do the things to protect a 2mpage in a process
3817 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3819 pd_entry_t newpde, oldpde;
3820 vm_offset_t eva, va;
3822 boolean_t anychanged;
3823 pt_entry_t PG_G, PG_M, PG_RW;
3825 PG_G = pmap_global_bit(pmap);
3826 PG_M = pmap_modified_bit(pmap);
3827 PG_RW = pmap_rw_bit(pmap);
3829 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3830 KASSERT((sva & PDRMASK) == 0,
3831 ("pmap_protect_pde: sva is not 2mpage aligned"));
3834 oldpde = newpde = *pde;
3835 if (oldpde & PG_MANAGED) {
3837 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3838 va < eva; va += PAGE_SIZE, m++)
3839 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3842 if ((prot & VM_PROT_WRITE) == 0)
3843 newpde &= ~(PG_RW | PG_M);
3844 if ((prot & VM_PROT_EXECUTE) == 0)
3846 if (newpde != oldpde) {
3847 if (!atomic_cmpset_long(pde, oldpde, newpde))
3850 pmap_invalidate_page(pmap, sva);
3854 return (anychanged);
3858 * Set the physical protection on the
3859 * specified range of this map as requested.
3862 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3864 vm_offset_t va_next;
3865 pml4_entry_t *pml4e;
3867 pd_entry_t ptpaddr, *pde;
3868 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3869 boolean_t anychanged, pv_lists_locked;
3871 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3872 if (prot == VM_PROT_NONE) {
3873 pmap_remove(pmap, sva, eva);
3877 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3878 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3881 PG_G = pmap_global_bit(pmap);
3882 PG_M = pmap_modified_bit(pmap);
3883 PG_V = pmap_valid_bit(pmap);
3884 PG_RW = pmap_rw_bit(pmap);
3885 pv_lists_locked = FALSE;
3890 for (; sva < eva; sva = va_next) {
3892 pml4e = pmap_pml4e(pmap, sva);
3893 if ((*pml4e & PG_V) == 0) {
3894 va_next = (sva + NBPML4) & ~PML4MASK;
3900 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3901 if ((*pdpe & PG_V) == 0) {
3902 va_next = (sva + NBPDP) & ~PDPMASK;
3908 va_next = (sva + NBPDR) & ~PDRMASK;
3912 pde = pmap_pdpe_to_pde(pdpe, sva);
3916 * Weed out invalid mappings.
3922 * Check for large page.
3924 if ((ptpaddr & PG_PS) != 0) {
3926 * Are we protecting the entire large page? If not,
3927 * demote the mapping and fall through.
3929 if (sva + NBPDR == va_next && eva >= va_next) {
3931 * The TLB entry for a PG_G mapping is
3932 * invalidated by pmap_protect_pde().
3934 if (pmap_protect_pde(pmap, pde, sva, prot))
3938 if (!pv_lists_locked) {
3939 pv_lists_locked = TRUE;
3940 if (!rw_try_rlock(&pvh_global_lock)) {
3942 pmap_invalidate_all(
3945 rw_rlock(&pvh_global_lock);
3949 if (!pmap_demote_pde(pmap, pde, sva)) {
3951 * The large page mapping was
3962 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3964 pt_entry_t obits, pbits;
3968 obits = pbits = *pte;
3969 if ((pbits & PG_V) == 0)
3972 if ((prot & VM_PROT_WRITE) == 0) {
3973 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3974 (PG_MANAGED | PG_M | PG_RW)) {
3975 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3978 pbits &= ~(PG_RW | PG_M);
3980 if ((prot & VM_PROT_EXECUTE) == 0)
3983 if (pbits != obits) {
3984 if (!atomic_cmpset_long(pte, obits, pbits))
3987 pmap_invalidate_page(pmap, sva);
3994 pmap_invalidate_all(pmap);
3995 if (pv_lists_locked)
3996 rw_runlock(&pvh_global_lock);
4001 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4002 * single page table page (PTP) to a single 2MB page mapping. For promotion
4003 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4004 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4005 * identical characteristics.
4008 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4009 struct rwlock **lockp)
4012 pt_entry_t *firstpte, oldpte, pa, *pte;
4013 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4014 vm_offset_t oldpteva;
4018 PG_A = pmap_accessed_bit(pmap);
4019 PG_G = pmap_global_bit(pmap);
4020 PG_M = pmap_modified_bit(pmap);
4021 PG_V = pmap_valid_bit(pmap);
4022 PG_RW = pmap_rw_bit(pmap);
4023 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4025 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4028 * Examine the first PTE in the specified PTP. Abort if this PTE is
4029 * either invalid, unused, or does not map the first 4KB physical page
4030 * within a 2MB page.
4032 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4035 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4036 atomic_add_long(&pmap_pde_p_failures, 1);
4037 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4038 " in pmap %p", va, pmap);
4041 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4043 * When PG_M is already clear, PG_RW can be cleared without
4044 * a TLB invalidation.
4046 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4052 * Examine each of the other PTEs in the specified PTP. Abort if this
4053 * PTE maps an unexpected 4KB physical page or does not have identical
4054 * characteristics to the first PTE.
4056 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4057 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4060 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4061 atomic_add_long(&pmap_pde_p_failures, 1);
4062 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4063 " in pmap %p", va, pmap);
4066 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4068 * When PG_M is already clear, PG_RW can be cleared
4069 * without a TLB invalidation.
4071 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4074 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
4076 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4077 " in pmap %p", oldpteva, pmap);
4079 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4080 atomic_add_long(&pmap_pde_p_failures, 1);
4081 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4082 " in pmap %p", va, pmap);
4089 * Save the page table page in its current state until the PDE
4090 * mapping the superpage is demoted by pmap_demote_pde() or
4091 * destroyed by pmap_remove_pde().
4093 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4094 KASSERT(mpte >= vm_page_array &&
4095 mpte < &vm_page_array[vm_page_array_size],
4096 ("pmap_promote_pde: page table page is out of range"));
4097 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4098 ("pmap_promote_pde: page table page's pindex is wrong"));
4099 if (pmap_insert_pt_page(pmap, mpte)) {
4100 atomic_add_long(&pmap_pde_p_failures, 1);
4102 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4108 * Promote the pv entries.
4110 if ((newpde & PG_MANAGED) != 0)
4111 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4114 * Propagate the PAT index to its proper position.
4116 newpde = pmap_swap_pat(pmap, newpde);
4119 * Map the superpage.
4121 if (workaround_erratum383)
4122 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4124 pde_store(pde, PG_PS | newpde);
4126 atomic_add_long(&pmap_pde_promotions, 1);
4127 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4128 " in pmap %p", va, pmap);
4132 * Insert the given physical page (p) at
4133 * the specified virtual address (v) in the
4134 * target physical map with the protection requested.
4136 * If specified, the page will be wired down, meaning
4137 * that the related pte can not be reclaimed.
4139 * NB: This is the only routine which MAY NOT lazy-evaluate
4140 * or lose information. That is, this routine must actually
4141 * insert this page into the given map NOW.
4144 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4145 u_int flags, int8_t psind __unused)
4147 struct rwlock *lock;
4149 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4150 pt_entry_t newpte, origpte;
4156 PG_A = pmap_accessed_bit(pmap);
4157 PG_G = pmap_global_bit(pmap);
4158 PG_M = pmap_modified_bit(pmap);
4159 PG_V = pmap_valid_bit(pmap);
4160 PG_RW = pmap_rw_bit(pmap);
4162 va = trunc_page(va);
4163 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4164 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4165 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4167 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4168 va >= kmi.clean_eva,
4169 ("pmap_enter: managed mapping within the clean submap"));
4170 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4171 VM_OBJECT_ASSERT_LOCKED(m->object);
4172 pa = VM_PAGE_TO_PHYS(m);
4173 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4174 if ((flags & VM_PROT_WRITE) != 0)
4176 if ((prot & VM_PROT_WRITE) != 0)
4178 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4179 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4180 if ((prot & VM_PROT_EXECUTE) == 0)
4182 if ((flags & PMAP_ENTER_WIRED) != 0)
4184 if (va < VM_MAXUSER_ADDRESS)
4186 if (pmap == kernel_pmap)
4188 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4191 * Set modified bit gratuitously for writeable mappings if
4192 * the page is unmanaged. We do not want to take a fault
4193 * to do the dirty bit accounting for these mappings.
4195 if ((m->oflags & VPO_UNMANAGED) != 0) {
4196 if ((newpte & PG_RW) != 0)
4203 rw_rlock(&pvh_global_lock);
4207 * In the case that a page table page is not
4208 * resident, we are creating it here.
4211 pde = pmap_pde(pmap, va);
4212 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4213 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4214 pte = pmap_pde_to_pte(pde, va);
4215 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4216 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4219 } else if (va < VM_MAXUSER_ADDRESS) {
4221 * Here if the pte page isn't mapped, or if it has been
4224 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4225 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4226 nosleep ? NULL : &lock);
4227 if (mpte == NULL && nosleep) {
4230 rw_runlock(&pvh_global_lock);
4232 return (KERN_RESOURCE_SHORTAGE);
4236 panic("pmap_enter: invalid page directory va=%#lx", va);
4241 * Is the specified virtual address already mapped?
4243 if ((origpte & PG_V) != 0) {
4245 * Wiring change, just update stats. We don't worry about
4246 * wiring PT pages as they remain resident as long as there
4247 * are valid mappings in them. Hence, if a user page is wired,
4248 * the PT page will be also.
4250 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4251 pmap->pm_stats.wired_count++;
4252 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4253 pmap->pm_stats.wired_count--;
4256 * Remove the extra PT page reference.
4260 KASSERT(mpte->wire_count > 0,
4261 ("pmap_enter: missing reference to page table page,"
4266 * Has the physical page changed?
4268 opa = origpte & PG_FRAME;
4271 * No, might be a protection or wiring change.
4273 if ((origpte & PG_MANAGED) != 0) {
4274 newpte |= PG_MANAGED;
4275 if ((newpte & PG_RW) != 0)
4276 vm_page_aflag_set(m, PGA_WRITEABLE);
4278 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4284 * Increment the counters.
4286 if ((newpte & PG_W) != 0)
4287 pmap->pm_stats.wired_count++;
4288 pmap_resident_count_inc(pmap, 1);
4292 * Enter on the PV list if part of our managed memory.
4294 if ((m->oflags & VPO_UNMANAGED) == 0) {
4295 newpte |= PG_MANAGED;
4296 pv = get_pv_entry(pmap, &lock);
4298 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4299 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4301 if ((newpte & PG_RW) != 0)
4302 vm_page_aflag_set(m, PGA_WRITEABLE);
4308 if ((origpte & PG_V) != 0) {
4310 origpte = pte_load_store(pte, newpte);
4311 opa = origpte & PG_FRAME;
4313 if ((origpte & PG_MANAGED) != 0) {
4314 om = PHYS_TO_VM_PAGE(opa);
4315 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4318 if ((origpte & PG_A) != 0)
4319 vm_page_aflag_set(om, PGA_REFERENCED);
4320 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4321 pmap_pvh_free(&om->md, pmap, va);
4322 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4323 TAILQ_EMPTY(&om->md.pv_list) &&
4324 ((om->flags & PG_FICTITIOUS) != 0 ||
4325 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4326 vm_page_aflag_clear(om, PGA_WRITEABLE);
4328 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4329 PG_RW)) == (PG_M | PG_RW)) {
4330 if ((origpte & PG_MANAGED) != 0)
4334 * Although the PTE may still have PG_RW set, TLB
4335 * invalidation may nonetheless be required because
4336 * the PTE no longer has PG_M set.
4338 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4340 * This PTE change does not require TLB invalidation.
4344 if ((origpte & PG_A) != 0)
4345 pmap_invalidate_page(pmap, va);
4347 pte_store(pte, newpte);
4352 * If both the page table page and the reservation are fully
4353 * populated, then attempt promotion.
4355 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4356 pmap_ps_enabled(pmap) &&
4357 (m->flags & PG_FICTITIOUS) == 0 &&
4358 vm_reserv_level_iffullpop(m) == 0)
4359 pmap_promote_pde(pmap, pde, va, &lock);
4363 rw_runlock(&pvh_global_lock);
4365 return (KERN_SUCCESS);
4369 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4370 * otherwise. Fails if (1) a page table page cannot be allocated without
4371 * blocking, (2) a mapping already exists at the specified virtual address, or
4372 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4375 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4376 struct rwlock **lockp)
4378 pd_entry_t *pde, newpde;
4381 struct spglist free;
4383 PG_V = pmap_valid_bit(pmap);
4384 rw_assert(&pvh_global_lock, RA_LOCKED);
4385 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4387 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4388 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4389 " in pmap %p", va, pmap);
4392 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4393 pde = &pde[pmap_pde_index(va)];
4394 if ((*pde & PG_V) != 0) {
4395 KASSERT(mpde->wire_count > 1,
4396 ("pmap_enter_pde: mpde's wire count is too low"));
4398 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4399 " in pmap %p", va, pmap);
4402 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4404 if ((m->oflags & VPO_UNMANAGED) == 0) {
4405 newpde |= PG_MANAGED;
4408 * Abort this mapping if its PV entry could not be created.
4410 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4413 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4414 pmap_invalidate_page(pmap, va);
4415 pmap_free_zero_pages(&free);
4417 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4418 " in pmap %p", va, pmap);
4422 if ((prot & VM_PROT_EXECUTE) == 0)
4424 if (va < VM_MAXUSER_ADDRESS)
4428 * Increment counters.
4430 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4433 * Map the superpage.
4435 pde_store(pde, newpde);
4437 atomic_add_long(&pmap_pde_mappings, 1);
4438 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4439 " in pmap %p", va, pmap);
4444 * Maps a sequence of resident pages belonging to the same object.
4445 * The sequence begins with the given page m_start. This page is
4446 * mapped at the given virtual address start. Each subsequent page is
4447 * mapped at a virtual address that is offset from start by the same
4448 * amount as the page is offset from m_start within the object. The
4449 * last page in the sequence is the page with the largest offset from
4450 * m_start that can be mapped at a virtual address less than the given
4451 * virtual address end. Not every virtual page between start and end
4452 * is mapped; only those for which a resident page exists with the
4453 * corresponding offset from m_start are mapped.
4456 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4457 vm_page_t m_start, vm_prot_t prot)
4459 struct rwlock *lock;
4462 vm_pindex_t diff, psize;
4464 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4466 psize = atop(end - start);
4470 rw_rlock(&pvh_global_lock);
4472 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4473 va = start + ptoa(diff);
4474 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4475 m->psind == 1 && pmap_ps_enabled(pmap) &&
4476 pmap_enter_pde(pmap, va, m, prot, &lock))
4477 m = &m[NBPDR / PAGE_SIZE - 1];
4479 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4481 m = TAILQ_NEXT(m, listq);
4485 rw_runlock(&pvh_global_lock);
4490 * this code makes some *MAJOR* assumptions:
4491 * 1. Current pmap & pmap exists.
4494 * 4. No page table pages.
4495 * but is *MUCH* faster than pmap_enter...
4499 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4501 struct rwlock *lock;
4504 rw_rlock(&pvh_global_lock);
4506 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4509 rw_runlock(&pvh_global_lock);
4514 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4515 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4517 struct spglist free;
4518 pt_entry_t *pte, PG_V;
4521 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4522 (m->oflags & VPO_UNMANAGED) != 0,
4523 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4524 PG_V = pmap_valid_bit(pmap);
4525 rw_assert(&pvh_global_lock, RA_LOCKED);
4526 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4529 * In the case that a page table page is not
4530 * resident, we are creating it here.
4532 if (va < VM_MAXUSER_ADDRESS) {
4533 vm_pindex_t ptepindex;
4537 * Calculate pagetable page index
4539 ptepindex = pmap_pde_pindex(va);
4540 if (mpte && (mpte->pindex == ptepindex)) {
4544 * Get the page directory entry
4546 ptepa = pmap_pde(pmap, va);
4549 * If the page table page is mapped, we just increment
4550 * the hold count, and activate it. Otherwise, we
4551 * attempt to allocate a page table page. If this
4552 * attempt fails, we don't retry. Instead, we give up.
4554 if (ptepa && (*ptepa & PG_V) != 0) {
4557 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4561 * Pass NULL instead of the PV list lock
4562 * pointer, because we don't intend to sleep.
4564 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4569 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4570 pte = &pte[pmap_pte_index(va)];
4584 * Enter on the PV list if part of our managed memory.
4586 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4587 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4590 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4591 pmap_invalidate_page(pmap, va);
4592 pmap_free_zero_pages(&free);
4600 * Increment counters
4602 pmap_resident_count_inc(pmap, 1);
4604 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4605 if ((prot & VM_PROT_EXECUTE) == 0)
4609 * Now validate mapping with RO protection
4611 if ((m->oflags & VPO_UNMANAGED) != 0)
4612 pte_store(pte, pa | PG_V | PG_U);
4614 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4619 * Make a temporary mapping for a physical address. This is only intended
4620 * to be used for panic dumps.
4623 pmap_kenter_temporary(vm_paddr_t pa, int i)
4627 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4628 pmap_kenter(va, pa);
4630 return ((void *)crashdumpmap);
4634 * This code maps large physical mmap regions into the
4635 * processor address space. Note that some shortcuts
4636 * are taken, but the code works.
4639 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4640 vm_pindex_t pindex, vm_size_t size)
4643 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4644 vm_paddr_t pa, ptepa;
4648 PG_A = pmap_accessed_bit(pmap);
4649 PG_M = pmap_modified_bit(pmap);
4650 PG_V = pmap_valid_bit(pmap);
4651 PG_RW = pmap_rw_bit(pmap);
4653 VM_OBJECT_ASSERT_WLOCKED(object);
4654 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4655 ("pmap_object_init_pt: non-device object"));
4656 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4657 if (!pmap_ps_enabled(pmap))
4659 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4661 p = vm_page_lookup(object, pindex);
4662 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4663 ("pmap_object_init_pt: invalid page %p", p));
4664 pat_mode = p->md.pat_mode;
4667 * Abort the mapping if the first page is not physically
4668 * aligned to a 2MB page boundary.
4670 ptepa = VM_PAGE_TO_PHYS(p);
4671 if (ptepa & (NBPDR - 1))
4675 * Skip the first page. Abort the mapping if the rest of
4676 * the pages are not physically contiguous or have differing
4677 * memory attributes.
4679 p = TAILQ_NEXT(p, listq);
4680 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4682 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4683 ("pmap_object_init_pt: invalid page %p", p));
4684 if (pa != VM_PAGE_TO_PHYS(p) ||
4685 pat_mode != p->md.pat_mode)
4687 p = TAILQ_NEXT(p, listq);
4691 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4692 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4693 * will not affect the termination of this loop.
4696 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4697 pa < ptepa + size; pa += NBPDR) {
4698 pdpg = pmap_allocpde(pmap, addr, NULL);
4701 * The creation of mappings below is only an
4702 * optimization. If a page directory page
4703 * cannot be allocated without blocking,
4704 * continue on to the next mapping rather than
4710 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4711 pde = &pde[pmap_pde_index(addr)];
4712 if ((*pde & PG_V) == 0) {
4713 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4714 PG_U | PG_RW | PG_V);
4715 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4716 atomic_add_long(&pmap_pde_mappings, 1);
4718 /* Continue on if the PDE is already valid. */
4720 KASSERT(pdpg->wire_count > 0,
4721 ("pmap_object_init_pt: missing reference "
4722 "to page directory page, va: 0x%lx", addr));
4731 * Clear the wired attribute from the mappings for the specified range of
4732 * addresses in the given pmap. Every valid mapping within that range
4733 * must have the wired attribute set. In contrast, invalid mappings
4734 * cannot have the wired attribute set, so they are ignored.
4736 * The wired attribute of the page table entry is not a hardware feature,
4737 * so there is no need to invalidate any TLB entries.
4740 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4742 vm_offset_t va_next;
4743 pml4_entry_t *pml4e;
4746 pt_entry_t *pte, PG_V;
4747 boolean_t pv_lists_locked;
4749 PG_V = pmap_valid_bit(pmap);
4750 pv_lists_locked = FALSE;
4753 for (; sva < eva; sva = va_next) {
4754 pml4e = pmap_pml4e(pmap, sva);
4755 if ((*pml4e & PG_V) == 0) {
4756 va_next = (sva + NBPML4) & ~PML4MASK;
4761 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4762 if ((*pdpe & PG_V) == 0) {
4763 va_next = (sva + NBPDP) & ~PDPMASK;
4768 va_next = (sva + NBPDR) & ~PDRMASK;
4771 pde = pmap_pdpe_to_pde(pdpe, sva);
4772 if ((*pde & PG_V) == 0)
4774 if ((*pde & PG_PS) != 0) {
4775 if ((*pde & PG_W) == 0)
4776 panic("pmap_unwire: pde %#jx is missing PG_W",
4780 * Are we unwiring the entire large page? If not,
4781 * demote the mapping and fall through.
4783 if (sva + NBPDR == va_next && eva >= va_next) {
4784 atomic_clear_long(pde, PG_W);
4785 pmap->pm_stats.wired_count -= NBPDR /
4789 if (!pv_lists_locked) {
4790 pv_lists_locked = TRUE;
4791 if (!rw_try_rlock(&pvh_global_lock)) {
4793 rw_rlock(&pvh_global_lock);
4798 if (!pmap_demote_pde(pmap, pde, sva))
4799 panic("pmap_unwire: demotion failed");
4804 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4806 if ((*pte & PG_V) == 0)
4808 if ((*pte & PG_W) == 0)
4809 panic("pmap_unwire: pte %#jx is missing PG_W",
4813 * PG_W must be cleared atomically. Although the pmap
4814 * lock synchronizes access to PG_W, another processor
4815 * could be setting PG_M and/or PG_A concurrently.
4817 atomic_clear_long(pte, PG_W);
4818 pmap->pm_stats.wired_count--;
4821 if (pv_lists_locked)
4822 rw_runlock(&pvh_global_lock);
4827 * Copy the range specified by src_addr/len
4828 * from the source map to the range dst_addr/len
4829 * in the destination map.
4831 * This routine is only advisory and need not do anything.
4835 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4836 vm_offset_t src_addr)
4838 struct rwlock *lock;
4839 struct spglist free;
4841 vm_offset_t end_addr = src_addr + len;
4842 vm_offset_t va_next;
4843 pt_entry_t PG_A, PG_M, PG_V;
4845 if (dst_addr != src_addr)
4848 if (dst_pmap->pm_type != src_pmap->pm_type)
4852 * EPT page table entries that require emulation of A/D bits are
4853 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4854 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4855 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4856 * implementations flag an EPT misconfiguration for exec-only
4857 * mappings we skip this function entirely for emulated pmaps.
4859 if (pmap_emulate_ad_bits(dst_pmap))
4863 rw_rlock(&pvh_global_lock);
4864 if (dst_pmap < src_pmap) {
4865 PMAP_LOCK(dst_pmap);
4866 PMAP_LOCK(src_pmap);
4868 PMAP_LOCK(src_pmap);
4869 PMAP_LOCK(dst_pmap);
4872 PG_A = pmap_accessed_bit(dst_pmap);
4873 PG_M = pmap_modified_bit(dst_pmap);
4874 PG_V = pmap_valid_bit(dst_pmap);
4876 for (addr = src_addr; addr < end_addr; addr = va_next) {
4877 pt_entry_t *src_pte, *dst_pte;
4878 vm_page_t dstmpde, dstmpte, srcmpte;
4879 pml4_entry_t *pml4e;
4881 pd_entry_t srcptepaddr, *pde;
4883 KASSERT(addr < UPT_MIN_ADDRESS,
4884 ("pmap_copy: invalid to pmap_copy page tables"));
4886 pml4e = pmap_pml4e(src_pmap, addr);
4887 if ((*pml4e & PG_V) == 0) {
4888 va_next = (addr + NBPML4) & ~PML4MASK;
4894 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4895 if ((*pdpe & PG_V) == 0) {
4896 va_next = (addr + NBPDP) & ~PDPMASK;
4902 va_next = (addr + NBPDR) & ~PDRMASK;
4906 pde = pmap_pdpe_to_pde(pdpe, addr);
4908 if (srcptepaddr == 0)
4911 if (srcptepaddr & PG_PS) {
4912 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4914 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4915 if (dstmpde == NULL)
4917 pde = (pd_entry_t *)
4918 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4919 pde = &pde[pmap_pde_index(addr)];
4920 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4921 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4922 PG_PS_FRAME, &lock))) {
4923 *pde = srcptepaddr & ~PG_W;
4924 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4926 dstmpde->wire_count--;
4930 srcptepaddr &= PG_FRAME;
4931 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4932 KASSERT(srcmpte->wire_count > 0,
4933 ("pmap_copy: source page table page is unused"));
4935 if (va_next > end_addr)
4938 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4939 src_pte = &src_pte[pmap_pte_index(addr)];
4941 while (addr < va_next) {
4945 * we only virtual copy managed pages
4947 if ((ptetemp & PG_MANAGED) != 0) {
4948 if (dstmpte != NULL &&
4949 dstmpte->pindex == pmap_pde_pindex(addr))
4950 dstmpte->wire_count++;
4951 else if ((dstmpte = pmap_allocpte(dst_pmap,
4952 addr, NULL)) == NULL)
4954 dst_pte = (pt_entry_t *)
4955 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4956 dst_pte = &dst_pte[pmap_pte_index(addr)];
4957 if (*dst_pte == 0 &&
4958 pmap_try_insert_pv_entry(dst_pmap, addr,
4959 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4962 * Clear the wired, modified, and
4963 * accessed (referenced) bits
4966 *dst_pte = ptetemp & ~(PG_W | PG_M |
4968 pmap_resident_count_inc(dst_pmap, 1);
4971 if (pmap_unwire_ptp(dst_pmap, addr,
4973 pmap_invalidate_page(dst_pmap,
4975 pmap_free_zero_pages(&free);
4979 if (dstmpte->wire_count >= srcmpte->wire_count)
4989 rw_runlock(&pvh_global_lock);
4990 PMAP_UNLOCK(src_pmap);
4991 PMAP_UNLOCK(dst_pmap);
4995 * pmap_zero_page zeros the specified hardware page by mapping
4996 * the page into KVM and using bzero to clear its contents.
4999 pmap_zero_page(vm_page_t m)
5001 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5003 pagezero((void *)va);
5007 * pmap_zero_page_area zeros the specified hardware page by mapping
5008 * the page into KVM and using bzero to clear its contents.
5010 * off and size may not cover an area beyond a single hardware page.
5013 pmap_zero_page_area(vm_page_t m, int off, int size)
5015 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5017 if (off == 0 && size == PAGE_SIZE)
5018 pagezero((void *)va);
5020 bzero((char *)va + off, size);
5024 * pmap_zero_page_idle zeros the specified hardware page by mapping
5025 * the page into KVM and using bzero to clear its contents. This
5026 * is intended to be called from the vm_pagezero process only and
5030 pmap_zero_page_idle(vm_page_t m)
5032 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5034 pagezero((void *)va);
5038 * pmap_copy_page copies the specified (machine independent)
5039 * page by mapping the page into virtual memory and using
5040 * bcopy to copy the page, one machine dependent page at a
5044 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5046 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5047 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5049 pagecopy((void *)src, (void *)dst);
5052 int unmapped_buf_allowed = 1;
5055 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5056 vm_offset_t b_offset, int xfersize)
5060 vm_paddr_t p_a, p_b;
5062 vm_offset_t a_pg_offset, b_pg_offset;
5067 * NB: The sequence of updating a page table followed by accesses
5068 * to the corresponding pages used in the !DMAP case is subject to
5069 * the situation described in the "AMD64 Architecture Programmer's
5070 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
5071 * Coherency Considerations". Therefore, issuing the INVLPG right
5072 * after modifying the PTE bits is crucial.
5075 while (xfersize > 0) {
5076 a_pg_offset = a_offset & PAGE_MASK;
5077 m_a = ma[a_offset >> PAGE_SHIFT];
5078 p_a = m_a->phys_addr;
5079 b_pg_offset = b_offset & PAGE_MASK;
5080 m_b = mb[b_offset >> PAGE_SHIFT];
5081 p_b = m_b->phys_addr;
5082 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5083 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5084 if (__predict_false(p_a < DMAP_MIN_ADDRESS ||
5085 p_a > DMAP_MIN_ADDRESS + dmaplimit)) {
5086 mtx_lock(&cpage_lock);
5089 pte = vtopte(cpage_a);
5090 *pte = p_a | X86_PG_A | X86_PG_V |
5091 pmap_cache_bits(kernel_pmap, m_a->md.pat_mode, 0);
5093 a_cp = (char *)cpage_a + a_pg_offset;
5095 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5097 if (__predict_false(p_b < DMAP_MIN_ADDRESS ||
5098 p_b > DMAP_MIN_ADDRESS + dmaplimit)) {
5100 mtx_lock(&cpage_lock);
5104 pte = vtopte(cpage_b);
5105 *pte = p_b | X86_PG_A | X86_PG_M | X86_PG_RW |
5106 X86_PG_V | pmap_cache_bits(kernel_pmap,
5107 m_b->md.pat_mode, 0);
5109 b_cp = (char *)cpage_b + b_pg_offset;
5111 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5113 bcopy(a_cp, b_cp, cnt);
5114 if (__predict_false(pinned)) {
5116 mtx_unlock(&cpage_lock);
5126 * Returns true if the pmap's pv is one of the first
5127 * 16 pvs linked to from this page. This count may
5128 * be changed upwards or downwards in the future; it
5129 * is only necessary that true be returned for a small
5130 * subset of pmaps for proper page aging.
5133 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5135 struct md_page *pvh;
5136 struct rwlock *lock;
5141 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5142 ("pmap_page_exists_quick: page %p is not managed", m));
5144 rw_rlock(&pvh_global_lock);
5145 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5147 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5148 if (PV_PMAP(pv) == pmap) {
5156 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5157 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5158 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5159 if (PV_PMAP(pv) == pmap) {
5169 rw_runlock(&pvh_global_lock);
5174 * pmap_page_wired_mappings:
5176 * Return the number of managed mappings to the given physical page
5180 pmap_page_wired_mappings(vm_page_t m)
5182 struct rwlock *lock;
5183 struct md_page *pvh;
5187 int count, md_gen, pvh_gen;
5189 if ((m->oflags & VPO_UNMANAGED) != 0)
5191 rw_rlock(&pvh_global_lock);
5192 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5196 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5198 if (!PMAP_TRYLOCK(pmap)) {
5199 md_gen = m->md.pv_gen;
5203 if (md_gen != m->md.pv_gen) {
5208 pte = pmap_pte(pmap, pv->pv_va);
5209 if ((*pte & PG_W) != 0)
5213 if ((m->flags & PG_FICTITIOUS) == 0) {
5214 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5215 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5217 if (!PMAP_TRYLOCK(pmap)) {
5218 md_gen = m->md.pv_gen;
5219 pvh_gen = pvh->pv_gen;
5223 if (md_gen != m->md.pv_gen ||
5224 pvh_gen != pvh->pv_gen) {
5229 pte = pmap_pde(pmap, pv->pv_va);
5230 if ((*pte & PG_W) != 0)
5236 rw_runlock(&pvh_global_lock);
5241 * Returns TRUE if the given page is mapped individually or as part of
5242 * a 2mpage. Otherwise, returns FALSE.
5245 pmap_page_is_mapped(vm_page_t m)
5247 struct rwlock *lock;
5250 if ((m->oflags & VPO_UNMANAGED) != 0)
5252 rw_rlock(&pvh_global_lock);
5253 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5255 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5256 ((m->flags & PG_FICTITIOUS) == 0 &&
5257 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5259 rw_runlock(&pvh_global_lock);
5264 * Destroy all managed, non-wired mappings in the given user-space
5265 * pmap. This pmap cannot be active on any processor besides the
5268 * This function cannot be applied to the kernel pmap. Moreover, it
5269 * is not intended for general use. It is only to be used during
5270 * process termination. Consequently, it can be implemented in ways
5271 * that make it faster than pmap_remove(). First, it can more quickly
5272 * destroy mappings by iterating over the pmap's collection of PV
5273 * entries, rather than searching the page table. Second, it doesn't
5274 * have to test and clear the page table entries atomically, because
5275 * no processor is currently accessing the user address space. In
5276 * particular, a page table entry's dirty bit won't change state once
5277 * this function starts.
5280 pmap_remove_pages(pmap_t pmap)
5283 pt_entry_t *pte, tpte;
5284 pt_entry_t PG_M, PG_RW, PG_V;
5285 struct spglist free;
5286 vm_page_t m, mpte, mt;
5288 struct md_page *pvh;
5289 struct pv_chunk *pc, *npc;
5290 struct rwlock *lock;
5292 uint64_t inuse, bitmask;
5293 int allfree, field, freed, idx;
5294 boolean_t superpage;
5298 * Assert that the given pmap is only active on the current
5299 * CPU. Unfortunately, we cannot block another CPU from
5300 * activating the pmap while this function is executing.
5302 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5305 cpuset_t other_cpus;
5307 other_cpus = all_cpus;
5309 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5310 CPU_AND(&other_cpus, &pmap->pm_active);
5312 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5317 PG_M = pmap_modified_bit(pmap);
5318 PG_V = pmap_valid_bit(pmap);
5319 PG_RW = pmap_rw_bit(pmap);
5322 rw_rlock(&pvh_global_lock);
5324 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5327 for (field = 0; field < _NPCM; field++) {
5328 inuse = ~pc->pc_map[field] & pc_freemask[field];
5329 while (inuse != 0) {
5331 bitmask = 1UL << bit;
5332 idx = field * 64 + bit;
5333 pv = &pc->pc_pventry[idx];
5336 pte = pmap_pdpe(pmap, pv->pv_va);
5338 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5340 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5343 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5345 pte = &pte[pmap_pte_index(pv->pv_va)];
5349 * Keep track whether 'tpte' is a
5350 * superpage explicitly instead of
5351 * relying on PG_PS being set.
5353 * This is because PG_PS is numerically
5354 * identical to PG_PTE_PAT and thus a
5355 * regular page could be mistaken for
5361 if ((tpte & PG_V) == 0) {
5362 panic("bad pte va %lx pte %lx",
5367 * We cannot remove wired pages from a process' mapping at this time
5375 pa = tpte & PG_PS_FRAME;
5377 pa = tpte & PG_FRAME;
5379 m = PHYS_TO_VM_PAGE(pa);
5380 KASSERT(m->phys_addr == pa,
5381 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5382 m, (uintmax_t)m->phys_addr,
5385 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5386 m < &vm_page_array[vm_page_array_size],
5387 ("pmap_remove_pages: bad tpte %#jx",
5393 * Update the vm_page_t clean/reference bits.
5395 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5397 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5403 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5406 pc->pc_map[field] |= bitmask;
5408 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5409 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5410 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5412 if (TAILQ_EMPTY(&pvh->pv_list)) {
5413 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5414 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5415 TAILQ_EMPTY(&mt->md.pv_list))
5416 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5418 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5420 pmap_remove_pt_page(pmap, mpte);
5421 pmap_resident_count_dec(pmap, 1);
5422 KASSERT(mpte->wire_count == NPTEPG,
5423 ("pmap_remove_pages: pte page wire count error"));
5424 mpte->wire_count = 0;
5425 pmap_add_delayed_free_list(mpte, &free, FALSE);
5426 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
5429 pmap_resident_count_dec(pmap, 1);
5430 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5432 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5433 TAILQ_EMPTY(&m->md.pv_list) &&
5434 (m->flags & PG_FICTITIOUS) == 0) {
5435 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5436 if (TAILQ_EMPTY(&pvh->pv_list))
5437 vm_page_aflag_clear(m, PGA_WRITEABLE);
5440 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5444 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5445 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5446 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5448 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5454 pmap_invalidate_all(pmap);
5455 rw_runlock(&pvh_global_lock);
5457 pmap_free_zero_pages(&free);
5461 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5463 struct rwlock *lock;
5465 struct md_page *pvh;
5466 pt_entry_t *pte, mask;
5467 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5469 int md_gen, pvh_gen;
5473 rw_rlock(&pvh_global_lock);
5474 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5477 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5479 if (!PMAP_TRYLOCK(pmap)) {
5480 md_gen = m->md.pv_gen;
5484 if (md_gen != m->md.pv_gen) {
5489 pte = pmap_pte(pmap, pv->pv_va);
5492 PG_M = pmap_modified_bit(pmap);
5493 PG_RW = pmap_rw_bit(pmap);
5494 mask |= PG_RW | PG_M;
5497 PG_A = pmap_accessed_bit(pmap);
5498 PG_V = pmap_valid_bit(pmap);
5499 mask |= PG_V | PG_A;
5501 rv = (*pte & mask) == mask;
5506 if ((m->flags & PG_FICTITIOUS) == 0) {
5507 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5508 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5510 if (!PMAP_TRYLOCK(pmap)) {
5511 md_gen = m->md.pv_gen;
5512 pvh_gen = pvh->pv_gen;
5516 if (md_gen != m->md.pv_gen ||
5517 pvh_gen != pvh->pv_gen) {
5522 pte = pmap_pde(pmap, pv->pv_va);
5525 PG_M = pmap_modified_bit(pmap);
5526 PG_RW = pmap_rw_bit(pmap);
5527 mask |= PG_RW | PG_M;
5530 PG_A = pmap_accessed_bit(pmap);
5531 PG_V = pmap_valid_bit(pmap);
5532 mask |= PG_V | PG_A;
5534 rv = (*pte & mask) == mask;
5542 rw_runlock(&pvh_global_lock);
5549 * Return whether or not the specified physical page was modified
5550 * in any physical maps.
5553 pmap_is_modified(vm_page_t m)
5556 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5557 ("pmap_is_modified: page %p is not managed", m));
5560 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5561 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5562 * is clear, no PTEs can have PG_M set.
5564 VM_OBJECT_ASSERT_WLOCKED(m->object);
5565 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5567 return (pmap_page_test_mappings(m, FALSE, TRUE));
5571 * pmap_is_prefaultable:
5573 * Return whether or not the specified virtual address is eligible
5577 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5580 pt_entry_t *pte, PG_V;
5583 PG_V = pmap_valid_bit(pmap);
5586 pde = pmap_pde(pmap, addr);
5587 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5588 pte = pmap_pde_to_pte(pde, addr);
5589 rv = (*pte & PG_V) == 0;
5596 * pmap_is_referenced:
5598 * Return whether or not the specified physical page was referenced
5599 * in any physical maps.
5602 pmap_is_referenced(vm_page_t m)
5605 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5606 ("pmap_is_referenced: page %p is not managed", m));
5607 return (pmap_page_test_mappings(m, TRUE, FALSE));
5611 * Clear the write and modified bits in each of the given page's mappings.
5614 pmap_remove_write(vm_page_t m)
5616 struct md_page *pvh;
5618 struct rwlock *lock;
5619 pv_entry_t next_pv, pv;
5621 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5623 int pvh_gen, md_gen;
5625 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5626 ("pmap_remove_write: page %p is not managed", m));
5629 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5630 * set by another thread while the object is locked. Thus,
5631 * if PGA_WRITEABLE is clear, no page table entries need updating.
5633 VM_OBJECT_ASSERT_WLOCKED(m->object);
5634 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5636 rw_rlock(&pvh_global_lock);
5637 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5638 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5641 if ((m->flags & PG_FICTITIOUS) != 0)
5642 goto small_mappings;
5643 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5645 if (!PMAP_TRYLOCK(pmap)) {
5646 pvh_gen = pvh->pv_gen;
5650 if (pvh_gen != pvh->pv_gen) {
5656 PG_RW = pmap_rw_bit(pmap);
5658 pde = pmap_pde(pmap, va);
5659 if ((*pde & PG_RW) != 0)
5660 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5661 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5662 ("inconsistent pv lock %p %p for page %p",
5663 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5667 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5669 if (!PMAP_TRYLOCK(pmap)) {
5670 pvh_gen = pvh->pv_gen;
5671 md_gen = m->md.pv_gen;
5675 if (pvh_gen != pvh->pv_gen ||
5676 md_gen != m->md.pv_gen) {
5682 PG_M = pmap_modified_bit(pmap);
5683 PG_RW = pmap_rw_bit(pmap);
5684 pde = pmap_pde(pmap, pv->pv_va);
5685 KASSERT((*pde & PG_PS) == 0,
5686 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5688 pte = pmap_pde_to_pte(pde, pv->pv_va);
5691 if (oldpte & PG_RW) {
5692 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5695 if ((oldpte & PG_M) != 0)
5697 pmap_invalidate_page(pmap, pv->pv_va);
5702 vm_page_aflag_clear(m, PGA_WRITEABLE);
5703 rw_runlock(&pvh_global_lock);
5706 static __inline boolean_t
5707 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5710 if (!pmap_emulate_ad_bits(pmap))
5713 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5716 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
5717 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5718 * if the EPT_PG_WRITE bit is set.
5720 if ((pte & EPT_PG_WRITE) != 0)
5724 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5726 if ((pte & EPT_PG_EXECUTE) == 0 ||
5727 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5733 #define PMAP_TS_REFERENCED_MAX 5
5736 * pmap_ts_referenced:
5738 * Return a count of reference bits for a page, clearing those bits.
5739 * It is not necessary for every reference bit to be cleared, but it
5740 * is necessary that 0 only be returned when there are truly no
5741 * reference bits set.
5743 * XXX: The exact number of bits to check and clear is a matter that
5744 * should be tested and standardized at some point in the future for
5745 * optimal aging of shared pages.
5748 pmap_ts_referenced(vm_page_t m)
5750 struct md_page *pvh;
5753 struct rwlock *lock;
5754 pd_entry_t oldpde, *pde;
5755 pt_entry_t *pte, PG_A;
5758 int cleared, md_gen, not_cleared, pvh_gen;
5759 struct spglist free;
5762 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5763 ("pmap_ts_referenced: page %p is not managed", m));
5766 pa = VM_PAGE_TO_PHYS(m);
5767 lock = PHYS_TO_PV_LIST_LOCK(pa);
5768 pvh = pa_to_pvh(pa);
5769 rw_rlock(&pvh_global_lock);
5773 if ((m->flags & PG_FICTITIOUS) != 0 ||
5774 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5775 goto small_mappings;
5781 if (!PMAP_TRYLOCK(pmap)) {
5782 pvh_gen = pvh->pv_gen;
5786 if (pvh_gen != pvh->pv_gen) {
5791 PG_A = pmap_accessed_bit(pmap);
5793 pde = pmap_pde(pmap, pv->pv_va);
5795 if ((*pde & PG_A) != 0) {
5797 * Since this reference bit is shared by 512 4KB
5798 * pages, it should not be cleared every time it is
5799 * tested. Apply a simple "hash" function on the
5800 * physical page number, the virtual superpage number,
5801 * and the pmap address to select one 4KB page out of
5802 * the 512 on which testing the reference bit will
5803 * result in clearing that reference bit. This
5804 * function is designed to avoid the selection of the
5805 * same 4KB page for every 2MB page mapping.
5807 * On demotion, a mapping that hasn't been referenced
5808 * is simply destroyed. To avoid the possibility of a
5809 * subsequent page fault on a demoted wired mapping,
5810 * always leave its reference bit set. Moreover,
5811 * since the superpage is wired, the current state of
5812 * its reference bit won't affect page replacement.
5814 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5815 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5816 (*pde & PG_W) == 0) {
5817 if (safe_to_clear_referenced(pmap, oldpde)) {
5818 atomic_clear_long(pde, PG_A);
5819 pmap_invalidate_page(pmap, pv->pv_va);
5821 } else if (pmap_demote_pde_locked(pmap, pde,
5822 pv->pv_va, &lock)) {
5824 * Remove the mapping to a single page
5825 * so that a subsequent access may
5826 * repromote. Since the underlying
5827 * page table page is fully populated,
5828 * this removal never frees a page
5832 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5834 pte = pmap_pde_to_pte(pde, va);
5835 pmap_remove_pte(pmap, pte, va, *pde,
5837 pmap_invalidate_page(pmap, va);
5843 * The superpage mapping was removed
5844 * entirely and therefore 'pv' is no
5852 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5853 ("inconsistent pv lock %p %p for page %p",
5854 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5859 /* Rotate the PV list if it has more than one entry. */
5860 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5861 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5862 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5865 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5867 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5869 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5876 if (!PMAP_TRYLOCK(pmap)) {
5877 pvh_gen = pvh->pv_gen;
5878 md_gen = m->md.pv_gen;
5882 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5887 PG_A = pmap_accessed_bit(pmap);
5888 pde = pmap_pde(pmap, pv->pv_va);
5889 KASSERT((*pde & PG_PS) == 0,
5890 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5892 pte = pmap_pde_to_pte(pde, pv->pv_va);
5893 if ((*pte & PG_A) != 0) {
5894 if (safe_to_clear_referenced(pmap, *pte)) {
5895 atomic_clear_long(pte, PG_A);
5896 pmap_invalidate_page(pmap, pv->pv_va);
5898 } else if ((*pte & PG_W) == 0) {
5900 * Wired pages cannot be paged out so
5901 * doing accessed bit emulation for
5902 * them is wasted effort. We do the
5903 * hard work for unwired pages only.
5905 pmap_remove_pte(pmap, pte, pv->pv_va,
5906 *pde, &free, &lock);
5907 pmap_invalidate_page(pmap, pv->pv_va);
5912 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5913 ("inconsistent pv lock %p %p for page %p",
5914 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5919 /* Rotate the PV list if it has more than one entry. */
5920 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5921 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5922 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5925 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5926 not_cleared < PMAP_TS_REFERENCED_MAX);
5929 rw_runlock(&pvh_global_lock);
5930 pmap_free_zero_pages(&free);
5931 return (cleared + not_cleared);
5935 * Apply the given advice to the specified range of addresses within the
5936 * given pmap. Depending on the advice, clear the referenced and/or
5937 * modified flags in each mapping and set the mapped page's dirty field.
5940 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5942 struct rwlock *lock;
5943 pml4_entry_t *pml4e;
5945 pd_entry_t oldpde, *pde;
5946 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5947 vm_offset_t va_next;
5949 boolean_t anychanged, pv_lists_locked;
5951 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5955 * A/D bit emulation requires an alternate code path when clearing
5956 * the modified and accessed bits below. Since this function is
5957 * advisory in nature we skip it entirely for pmaps that require
5958 * A/D bit emulation.
5960 if (pmap_emulate_ad_bits(pmap))
5963 PG_A = pmap_accessed_bit(pmap);
5964 PG_G = pmap_global_bit(pmap);
5965 PG_M = pmap_modified_bit(pmap);
5966 PG_V = pmap_valid_bit(pmap);
5967 PG_RW = pmap_rw_bit(pmap);
5969 pv_lists_locked = FALSE;
5973 for (; sva < eva; sva = va_next) {
5974 pml4e = pmap_pml4e(pmap, sva);
5975 if ((*pml4e & PG_V) == 0) {
5976 va_next = (sva + NBPML4) & ~PML4MASK;
5981 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5982 if ((*pdpe & PG_V) == 0) {
5983 va_next = (sva + NBPDP) & ~PDPMASK;
5988 va_next = (sva + NBPDR) & ~PDRMASK;
5991 pde = pmap_pdpe_to_pde(pdpe, sva);
5993 if ((oldpde & PG_V) == 0)
5995 else if ((oldpde & PG_PS) != 0) {
5996 if ((oldpde & PG_MANAGED) == 0)
5998 if (!pv_lists_locked) {
5999 pv_lists_locked = TRUE;
6000 if (!rw_try_rlock(&pvh_global_lock)) {
6002 pmap_invalidate_all(pmap);
6004 rw_rlock(&pvh_global_lock);
6009 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6014 * The large page mapping was destroyed.
6020 * Unless the page mappings are wired, remove the
6021 * mapping to a single page so that a subsequent
6022 * access may repromote. Since the underlying page
6023 * table page is fully populated, this removal never
6024 * frees a page table page.
6026 if ((oldpde & PG_W) == 0) {
6027 pte = pmap_pde_to_pte(pde, sva);
6028 KASSERT((*pte & PG_V) != 0,
6029 ("pmap_advise: invalid PTE"));
6030 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6039 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6041 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
6044 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6045 if (advice == MADV_DONTNEED) {
6047 * Future calls to pmap_is_modified()
6048 * can be avoided by making the page
6051 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6054 atomic_clear_long(pte, PG_M | PG_A);
6055 } else if ((*pte & PG_A) != 0)
6056 atomic_clear_long(pte, PG_A);
6059 if ((*pte & PG_G) != 0)
6060 pmap_invalidate_page(pmap, sva);
6066 pmap_invalidate_all(pmap);
6067 if (pv_lists_locked)
6068 rw_runlock(&pvh_global_lock);
6073 * Clear the modify bits on the specified physical page.
6076 pmap_clear_modify(vm_page_t m)
6078 struct md_page *pvh;
6080 pv_entry_t next_pv, pv;
6081 pd_entry_t oldpde, *pde;
6082 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6083 struct rwlock *lock;
6085 int md_gen, pvh_gen;
6087 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6088 ("pmap_clear_modify: page %p is not managed", m));
6089 VM_OBJECT_ASSERT_WLOCKED(m->object);
6090 KASSERT(!vm_page_xbusied(m),
6091 ("pmap_clear_modify: page %p is exclusive busied", m));
6094 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6095 * If the object containing the page is locked and the page is not
6096 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6098 if ((m->aflags & PGA_WRITEABLE) == 0)
6100 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6101 rw_rlock(&pvh_global_lock);
6102 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6105 if ((m->flags & PG_FICTITIOUS) != 0)
6106 goto small_mappings;
6107 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6109 if (!PMAP_TRYLOCK(pmap)) {
6110 pvh_gen = pvh->pv_gen;
6114 if (pvh_gen != pvh->pv_gen) {
6119 PG_M = pmap_modified_bit(pmap);
6120 PG_V = pmap_valid_bit(pmap);
6121 PG_RW = pmap_rw_bit(pmap);
6123 pde = pmap_pde(pmap, va);
6125 if ((oldpde & PG_RW) != 0) {
6126 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6127 if ((oldpde & PG_W) == 0) {
6129 * Write protect the mapping to a
6130 * single page so that a subsequent
6131 * write access may repromote.
6133 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6135 pte = pmap_pde_to_pte(pde, va);
6137 if ((oldpte & PG_V) != 0) {
6138 while (!atomic_cmpset_long(pte,
6140 oldpte & ~(PG_M | PG_RW)))
6143 pmap_invalidate_page(pmap, va);
6151 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6153 if (!PMAP_TRYLOCK(pmap)) {
6154 md_gen = m->md.pv_gen;
6155 pvh_gen = pvh->pv_gen;
6159 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6164 PG_M = pmap_modified_bit(pmap);
6165 PG_RW = pmap_rw_bit(pmap);
6166 pde = pmap_pde(pmap, pv->pv_va);
6167 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6168 " a 2mpage in page %p's pv list", m));
6169 pte = pmap_pde_to_pte(pde, pv->pv_va);
6170 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6171 atomic_clear_long(pte, PG_M);
6172 pmap_invalidate_page(pmap, pv->pv_va);
6177 rw_runlock(&pvh_global_lock);
6181 * Miscellaneous support routines follow
6184 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6185 static __inline void
6186 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6191 * The cache mode bits are all in the low 32-bits of the
6192 * PTE, so we can just spin on updating the low 32-bits.
6195 opte = *(u_int *)pte;
6196 npte = opte & ~mask;
6198 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6201 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6202 static __inline void
6203 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6208 * The cache mode bits are all in the low 32-bits of the
6209 * PDE, so we can just spin on updating the low 32-bits.
6212 opde = *(u_int *)pde;
6213 npde = opde & ~mask;
6215 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6219 * Map a set of physical memory pages into the kernel virtual
6220 * address space. Return a pointer to where it is mapped. This
6221 * routine is intended to be used for mapping device memory,
6225 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6227 vm_offset_t va, offset;
6231 * If the specified range of physical addresses fits within the direct
6232 * map window, use the direct map.
6234 if (pa < dmaplimit && pa + size < dmaplimit) {
6235 va = PHYS_TO_DMAP(pa);
6236 if (!pmap_change_attr(va, size, mode))
6237 return ((void *)va);
6239 offset = pa & PAGE_MASK;
6240 size = round_page(offset + size);
6241 va = kva_alloc(size);
6243 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
6244 pa = trunc_page(pa);
6245 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6246 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6247 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6248 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6249 return ((void *)(va + offset));
6253 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6256 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6260 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6263 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6267 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6269 vm_offset_t base, offset;
6271 /* If we gave a direct map region in pmap_mapdev, do nothing */
6272 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6274 base = trunc_page(va);
6275 offset = va & PAGE_MASK;
6276 size = round_page(offset + size);
6277 kva_free(base, size);
6281 * Tries to demote a 1GB page mapping.
6284 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6286 pdp_entry_t newpdpe, oldpdpe;
6287 pd_entry_t *firstpde, newpde, *pde;
6288 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6292 PG_A = pmap_accessed_bit(pmap);
6293 PG_M = pmap_modified_bit(pmap);
6294 PG_V = pmap_valid_bit(pmap);
6295 PG_RW = pmap_rw_bit(pmap);
6297 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6299 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6300 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6301 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6302 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6303 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6304 " in pmap %p", va, pmap);
6307 mpdepa = VM_PAGE_TO_PHYS(mpde);
6308 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6309 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6310 KASSERT((oldpdpe & PG_A) != 0,
6311 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6312 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6313 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6317 * Initialize the page directory page.
6319 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6325 * Demote the mapping.
6330 * Invalidate a stale recursive mapping of the page directory page.
6332 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6334 pmap_pdpe_demotions++;
6335 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6336 " in pmap %p", va, pmap);
6341 * Sets the memory attribute for the specified page.
6344 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6347 m->md.pat_mode = ma;
6350 * If "m" is a normal page, update its direct mapping. This update
6351 * can be relied upon to perform any cache operations that are
6352 * required for data coherence.
6354 if ((m->flags & PG_FICTITIOUS) == 0 &&
6355 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6357 panic("memory attribute change on the direct map failed");
6361 * Changes the specified virtual address range's memory type to that given by
6362 * the parameter "mode". The specified virtual address range must be
6363 * completely contained within either the direct map or the kernel map. If
6364 * the virtual address range is contained within the kernel map, then the
6365 * memory type for each of the corresponding ranges of the direct map is also
6366 * changed. (The corresponding ranges of the direct map are those ranges that
6367 * map the same physical pages as the specified virtual address range.) These
6368 * changes to the direct map are necessary because Intel describes the
6369 * behavior of their processors as "undefined" if two or more mappings to the
6370 * same physical page have different memory types.
6372 * Returns zero if the change completed successfully, and either EINVAL or
6373 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6374 * of the virtual address range was not mapped, and ENOMEM is returned if
6375 * there was insufficient memory available to complete the change. In the
6376 * latter case, the memory type may have been changed on some part of the
6377 * virtual address range or the direct map.
6380 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6384 PMAP_LOCK(kernel_pmap);
6385 error = pmap_change_attr_locked(va, size, mode);
6386 PMAP_UNLOCK(kernel_pmap);
6391 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6393 vm_offset_t base, offset, tmpva;
6394 vm_paddr_t pa_start, pa_end;
6398 int cache_bits_pte, cache_bits_pde, error;
6401 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6402 base = trunc_page(va);
6403 offset = va & PAGE_MASK;
6404 size = round_page(offset + size);
6407 * Only supported on kernel virtual addresses, including the direct
6408 * map but excluding the recursive map.
6410 if (base < DMAP_MIN_ADDRESS)
6413 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6414 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6418 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6419 * into 4KB pages if required.
6421 for (tmpva = base; tmpva < base + size; ) {
6422 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6425 if (*pdpe & PG_PS) {
6427 * If the current 1GB page already has the required
6428 * memory type, then we need not demote this page. Just
6429 * increment tmpva to the next 1GB page frame.
6431 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6432 tmpva = trunc_1gpage(tmpva) + NBPDP;
6437 * If the current offset aligns with a 1GB page frame
6438 * and there is at least 1GB left within the range, then
6439 * we need not break down this page into 2MB pages.
6441 if ((tmpva & PDPMASK) == 0 &&
6442 tmpva + PDPMASK < base + size) {
6446 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6449 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6454 * If the current 2MB page already has the required
6455 * memory type, then we need not demote this page. Just
6456 * increment tmpva to the next 2MB page frame.
6458 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6459 tmpva = trunc_2mpage(tmpva) + NBPDR;
6464 * If the current offset aligns with a 2MB page frame
6465 * and there is at least 2MB left within the range, then
6466 * we need not break down this page into 4KB pages.
6468 if ((tmpva & PDRMASK) == 0 &&
6469 tmpva + PDRMASK < base + size) {
6473 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6476 pte = pmap_pde_to_pte(pde, tmpva);
6484 * Ok, all the pages exist, so run through them updating their
6485 * cache mode if required.
6487 pa_start = pa_end = 0;
6488 for (tmpva = base; tmpva < base + size; ) {
6489 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6490 if (*pdpe & PG_PS) {
6491 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6492 pmap_pde_attr(pdpe, cache_bits_pde,
6496 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6497 if (pa_start == pa_end) {
6498 /* Start physical address run. */
6499 pa_start = *pdpe & PG_PS_FRAME;
6500 pa_end = pa_start + NBPDP;
6501 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6504 /* Run ended, update direct map. */
6505 error = pmap_change_attr_locked(
6506 PHYS_TO_DMAP(pa_start),
6507 pa_end - pa_start, mode);
6510 /* Start physical address run. */
6511 pa_start = *pdpe & PG_PS_FRAME;
6512 pa_end = pa_start + NBPDP;
6515 tmpva = trunc_1gpage(tmpva) + NBPDP;
6518 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6520 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6521 pmap_pde_attr(pde, cache_bits_pde,
6525 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6526 if (pa_start == pa_end) {
6527 /* Start physical address run. */
6528 pa_start = *pde & PG_PS_FRAME;
6529 pa_end = pa_start + NBPDR;
6530 } else if (pa_end == (*pde & PG_PS_FRAME))
6533 /* Run ended, update direct map. */
6534 error = pmap_change_attr_locked(
6535 PHYS_TO_DMAP(pa_start),
6536 pa_end - pa_start, mode);
6539 /* Start physical address run. */
6540 pa_start = *pde & PG_PS_FRAME;
6541 pa_end = pa_start + NBPDR;
6544 tmpva = trunc_2mpage(tmpva) + NBPDR;
6546 pte = pmap_pde_to_pte(pde, tmpva);
6547 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6548 pmap_pte_attr(pte, cache_bits_pte,
6552 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6553 if (pa_start == pa_end) {
6554 /* Start physical address run. */
6555 pa_start = *pte & PG_FRAME;
6556 pa_end = pa_start + PAGE_SIZE;
6557 } else if (pa_end == (*pte & PG_FRAME))
6558 pa_end += PAGE_SIZE;
6560 /* Run ended, update direct map. */
6561 error = pmap_change_attr_locked(
6562 PHYS_TO_DMAP(pa_start),
6563 pa_end - pa_start, mode);
6566 /* Start physical address run. */
6567 pa_start = *pte & PG_FRAME;
6568 pa_end = pa_start + PAGE_SIZE;
6574 if (error == 0 && pa_start != pa_end)
6575 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6576 pa_end - pa_start, mode);
6579 * Flush CPU caches if required to make sure any data isn't cached that
6580 * shouldn't be, etc.
6583 pmap_invalidate_range(kernel_pmap, base, tmpva);
6584 pmap_invalidate_cache_range(base, tmpva, FALSE);
6590 * Demotes any mapping within the direct map region that covers more than the
6591 * specified range of physical addresses. This range's size must be a power
6592 * of two and its starting address must be a multiple of its size. Since the
6593 * demotion does not change any attributes of the mapping, a TLB invalidation
6594 * is not mandatory. The caller may, however, request a TLB invalidation.
6597 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6606 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6607 KASSERT((base & (len - 1)) == 0,
6608 ("pmap_demote_DMAP: base is not a multiple of len"));
6609 if (len < NBPDP && base < dmaplimit) {
6610 va = PHYS_TO_DMAP(base);
6612 PMAP_LOCK(kernel_pmap);
6613 pdpe = pmap_pdpe(kernel_pmap, va);
6614 if ((*pdpe & X86_PG_V) == 0)
6615 panic("pmap_demote_DMAP: invalid PDPE");
6616 if ((*pdpe & PG_PS) != 0) {
6617 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6618 panic("pmap_demote_DMAP: PDPE failed");
6622 pde = pmap_pdpe_to_pde(pdpe, va);
6623 if ((*pde & X86_PG_V) == 0)
6624 panic("pmap_demote_DMAP: invalid PDE");
6625 if ((*pde & PG_PS) != 0) {
6626 if (!pmap_demote_pde(kernel_pmap, pde, va))
6627 panic("pmap_demote_DMAP: PDE failed");
6631 if (changed && invalidate)
6632 pmap_invalidate_page(kernel_pmap, va);
6633 PMAP_UNLOCK(kernel_pmap);
6638 * perform the pmap work for mincore
6641 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6644 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6648 PG_A = pmap_accessed_bit(pmap);
6649 PG_M = pmap_modified_bit(pmap);
6650 PG_V = pmap_valid_bit(pmap);
6651 PG_RW = pmap_rw_bit(pmap);
6655 pdep = pmap_pde(pmap, addr);
6656 if (pdep != NULL && (*pdep & PG_V)) {
6657 if (*pdep & PG_PS) {
6659 /* Compute the physical address of the 4KB page. */
6660 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6662 val = MINCORE_SUPER;
6664 pte = *pmap_pde_to_pte(pdep, addr);
6665 pa = pte & PG_FRAME;
6673 if ((pte & PG_V) != 0) {
6674 val |= MINCORE_INCORE;
6675 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6676 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6677 if ((pte & PG_A) != 0)
6678 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6680 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6681 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6682 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6683 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6684 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6687 PA_UNLOCK_COND(*locked_pa);
6693 pmap_activate(struct thread *td)
6695 pmap_t pmap, oldpmap;
6699 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6700 oldpmap = PCPU_GET(curpmap);
6701 cpuid = PCPU_GET(cpuid);
6703 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6704 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6705 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
6707 CPU_CLR(cpuid, &oldpmap->pm_active);
6708 CPU_SET(cpuid, &pmap->pm_active);
6709 CPU_SET(cpuid, &pmap->pm_save);
6711 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
6712 load_cr3(pmap->pm_cr3);
6713 PCPU_SET(curpmap, pmap);
6718 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6723 * Increase the starting virtual address of the given mapping if a
6724 * different alignment might result in more superpage mappings.
6727 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6728 vm_offset_t *addr, vm_size_t size)
6730 vm_offset_t superpage_offset;
6734 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6735 offset += ptoa(object->pg_color);
6736 superpage_offset = offset & PDRMASK;
6737 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6738 (*addr & PDRMASK) == superpage_offset)
6740 if ((*addr & PDRMASK) < superpage_offset)
6741 *addr = (*addr & ~PDRMASK) + superpage_offset;
6743 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6747 static unsigned long num_dirty_emulations;
6748 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6749 &num_dirty_emulations, 0, NULL);
6751 static unsigned long num_accessed_emulations;
6752 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6753 &num_accessed_emulations, 0, NULL);
6755 static unsigned long num_superpage_accessed_emulations;
6756 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6757 &num_superpage_accessed_emulations, 0, NULL);
6759 static unsigned long ad_emulation_superpage_promotions;
6760 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6761 &ad_emulation_superpage_promotions, 0, NULL);
6762 #endif /* INVARIANTS */
6765 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6768 struct rwlock *lock;
6771 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6772 boolean_t pv_lists_locked;
6774 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6775 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6777 if (!pmap_emulate_ad_bits(pmap))
6780 PG_A = pmap_accessed_bit(pmap);
6781 PG_M = pmap_modified_bit(pmap);
6782 PG_V = pmap_valid_bit(pmap);
6783 PG_RW = pmap_rw_bit(pmap);
6787 pv_lists_locked = FALSE;
6791 pde = pmap_pde(pmap, va);
6792 if (pde == NULL || (*pde & PG_V) == 0)
6795 if ((*pde & PG_PS) != 0) {
6796 if (ftype == VM_PROT_READ) {
6798 atomic_add_long(&num_superpage_accessed_emulations, 1);
6806 pte = pmap_pde_to_pte(pde, va);
6807 if ((*pte & PG_V) == 0)
6810 if (ftype == VM_PROT_WRITE) {
6811 if ((*pte & PG_RW) == 0)
6817 /* try to promote the mapping */
6818 if (va < VM_MAXUSER_ADDRESS)
6819 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6823 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6825 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6826 pmap_ps_enabled(pmap) &&
6827 (m->flags & PG_FICTITIOUS) == 0 &&
6828 vm_reserv_level_iffullpop(m) == 0) {
6829 if (!pv_lists_locked) {
6830 pv_lists_locked = TRUE;
6831 if (!rw_try_rlock(&pvh_global_lock)) {
6833 rw_rlock(&pvh_global_lock);
6837 pmap_promote_pde(pmap, pde, va, &lock);
6839 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6843 if (ftype == VM_PROT_WRITE)
6844 atomic_add_long(&num_dirty_emulations, 1);
6846 atomic_add_long(&num_accessed_emulations, 1);
6848 rv = 0; /* success */
6852 if (pv_lists_locked)
6853 rw_runlock(&pvh_global_lock);
6859 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6864 pt_entry_t *pte, PG_V;
6868 PG_V = pmap_valid_bit(pmap);
6871 pml4 = pmap_pml4e(pmap, va);
6873 if ((*pml4 & PG_V) == 0)
6876 pdp = pmap_pml4e_to_pdpe(pml4, va);
6878 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6881 pde = pmap_pdpe_to_pde(pdp, va);
6883 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6886 pte = pmap_pde_to_pte(pde, va);
6894 #include "opt_ddb.h"
6896 #include <ddb/ddb.h>
6898 DB_SHOW_COMMAND(pte, pmap_print_pte)
6904 pt_entry_t *pte, PG_V;
6908 va = (vm_offset_t)addr;
6909 pmap = PCPU_GET(curpmap); /* XXX */
6911 db_printf("show pte addr\n");
6914 PG_V = pmap_valid_bit(pmap);
6915 pml4 = pmap_pml4e(pmap, va);
6916 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
6917 if ((*pml4 & PG_V) == 0) {
6921 pdp = pmap_pml4e_to_pdpe(pml4, va);
6922 db_printf(" pdpe %#016lx", *pdp);
6923 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
6927 pde = pmap_pdpe_to_pde(pdp, va);
6928 db_printf(" pde %#016lx", *pde);
6929 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
6933 pte = pmap_pde_to_pte(pde, va);
6934 db_printf(" pte %#016lx\n", *pte);
6937 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
6942 a = (vm_paddr_t)addr;
6943 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
6945 db_printf("show phys2dmap addr\n");