2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/asan.h>
116 #include <sys/bitstring.h>
118 #include <sys/systm.h>
119 #include <sys/counter.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/malloc.h>
124 #include <sys/mman.h>
125 #include <sys/mutex.h>
126 #include <sys/proc.h>
127 #include <sys/rangeset.h>
128 #include <sys/rwlock.h>
129 #include <sys/sbuf.h>
132 #include <sys/turnstile.h>
133 #include <sys/vmem.h>
134 #include <sys/vmmeter.h>
135 #include <sys/sched.h>
136 #include <sys/sysctl.h>
144 #include <vm/vm_param.h>
145 #include <vm/vm_kern.h>
146 #include <vm/vm_page.h>
147 #include <vm/vm_map.h>
148 #include <vm/vm_object.h>
149 #include <vm/vm_extern.h>
150 #include <vm/vm_pageout.h>
151 #include <vm/vm_pager.h>
152 #include <vm/vm_phys.h>
153 #include <vm/vm_radix.h>
154 #include <vm/vm_reserv.h>
155 #include <vm/vm_dumpset.h>
158 #include <machine/asan.h>
159 #include <machine/intr_machdep.h>
160 #include <x86/apicvar.h>
161 #include <x86/ifunc.h>
162 #include <machine/cpu.h>
163 #include <machine/cputypes.h>
164 #include <machine/intr_machdep.h>
165 #include <machine/md_var.h>
166 #include <machine/pcb.h>
167 #include <machine/specialreg.h>
169 #include <machine/smp.h>
171 #include <machine/sysarch.h>
172 #include <machine/tss.h>
175 #define PMAP_MEMDOM MAXMEMDOM
177 #define PMAP_MEMDOM 1
180 static __inline boolean_t
181 pmap_type_guest(pmap_t pmap)
184 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
187 static __inline boolean_t
188 pmap_emulate_ad_bits(pmap_t pmap)
191 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
194 static __inline pt_entry_t
195 pmap_valid_bit(pmap_t pmap)
199 switch (pmap->pm_type) {
205 if (pmap_emulate_ad_bits(pmap))
206 mask = EPT_PG_EMUL_V;
211 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
217 static __inline pt_entry_t
218 pmap_rw_bit(pmap_t pmap)
222 switch (pmap->pm_type) {
228 if (pmap_emulate_ad_bits(pmap))
229 mask = EPT_PG_EMUL_RW;
234 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
240 static pt_entry_t pg_g;
242 static __inline pt_entry_t
243 pmap_global_bit(pmap_t pmap)
247 switch (pmap->pm_type) {
256 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
262 static __inline pt_entry_t
263 pmap_accessed_bit(pmap_t pmap)
267 switch (pmap->pm_type) {
273 if (pmap_emulate_ad_bits(pmap))
279 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
285 static __inline pt_entry_t
286 pmap_modified_bit(pmap_t pmap)
290 switch (pmap->pm_type) {
296 if (pmap_emulate_ad_bits(pmap))
302 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
308 static __inline pt_entry_t
309 pmap_pku_mask_bit(pmap_t pmap)
312 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
315 #if !defined(DIAGNOSTIC)
316 #ifdef __GNUC_GNU_INLINE__
317 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
319 #define PMAP_INLINE extern inline
326 #define PV_STAT(x) do { x ; } while (0)
328 #define PV_STAT(x) do { } while (0)
333 #define pa_index(pa) ({ \
334 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
335 ("address %lx beyond the last segment", (pa))); \
338 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
339 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
340 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
341 struct rwlock *_lock; \
342 if (__predict_false((pa) > pmap_last_pa)) \
343 _lock = &pv_dummy_large.pv_lock; \
345 _lock = &(pa_to_pmdp(pa)->pv_lock); \
349 #define pa_index(pa) ((pa) >> PDRSHIFT)
350 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
352 #define NPV_LIST_LOCKS MAXCPU
354 #define PHYS_TO_PV_LIST_LOCK(pa) \
355 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
358 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
359 struct rwlock **_lockp = (lockp); \
360 struct rwlock *_new_lock; \
362 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
363 if (_new_lock != *_lockp) { \
364 if (*_lockp != NULL) \
365 rw_wunlock(*_lockp); \
366 *_lockp = _new_lock; \
371 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
372 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
374 #define RELEASE_PV_LIST_LOCK(lockp) do { \
375 struct rwlock **_lockp = (lockp); \
377 if (*_lockp != NULL) { \
378 rw_wunlock(*_lockp); \
383 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
384 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
386 struct pmap kernel_pmap_store;
388 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
389 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
392 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
393 "Number of kernel page table pages allocated on bootup");
396 vm_paddr_t dmaplimit;
397 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
400 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
401 "VM/pmap parameters");
403 static int pg_ps_enabled = 1;
404 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
405 &pg_ps_enabled, 0, "Are large page mappings enabled?");
407 int __read_frequently la57 = 0;
408 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
410 "5-level paging for host is enabled");
413 pmap_is_la57(pmap_t pmap)
415 if (pmap->pm_type == PT_X86)
417 return (false); /* XXXKIB handle EPT */
420 #define PAT_INDEX_SIZE 8
421 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
423 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
424 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
425 static u_int64_t KPDPphys; /* phys addr of kernel level 3 */
426 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
427 u_int64_t KPML5phys; /* phys addr of kernel level 5,
431 static uint64_t KASANPDPphys;
434 static pml4_entry_t *kernel_pml4;
435 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
436 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
437 static int ndmpdpphys; /* number of DMPDPphys pages */
439 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
442 * pmap_mapdev support pre initialization (i.e. console)
444 #define PMAP_PREINIT_MAPPING_COUNT 8
445 static struct pmap_preinit_mapping {
450 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
451 static int pmap_initialized;
454 * Data for the pv entry allocation mechanism.
455 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
459 pc_to_domain(struct pv_chunk *pc)
462 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
466 pc_to_domain(struct pv_chunk *pc __unused)
473 struct pv_chunks_list {
475 TAILQ_HEAD(pch, pv_chunk) pvc_list;
477 } __aligned(CACHE_LINE_SIZE);
479 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
482 struct pmap_large_md_page {
483 struct rwlock pv_lock;
484 struct md_page pv_page;
487 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
488 #define pv_dummy pv_dummy_large.pv_page
489 __read_mostly static struct pmap_large_md_page *pv_table;
490 __read_mostly vm_paddr_t pmap_last_pa;
492 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
493 static u_long pv_invl_gen[NPV_LIST_LOCKS];
494 static struct md_page *pv_table;
495 static struct md_page pv_dummy;
499 * All those kernel PT submaps that BSD is so fond of
501 pt_entry_t *CMAP1 = NULL;
503 static vm_offset_t qframe = 0;
504 static struct mtx qframe_mtx;
506 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
508 static vmem_t *large_vmem;
509 static u_int lm_ents;
510 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
511 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
513 int pmap_pcid_enabled = 1;
514 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
515 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
516 int invpcid_works = 0;
517 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
518 "Is the invpcid instruction available ?");
520 int __read_frequently pti = 0;
521 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
523 "Page Table Isolation enabled");
524 static vm_object_t pti_obj;
525 static pml4_entry_t *pti_pml4;
526 static vm_pindex_t pti_pg_idx;
527 static bool pti_finalized;
529 struct pmap_pkru_range {
530 struct rs_el pkru_rs_el;
535 static uma_zone_t pmap_pkru_ranges_zone;
536 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
537 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
538 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
539 static void *pkru_dup_range(void *ctx, void *data);
540 static void pkru_free_range(void *ctx, void *node);
541 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
542 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
543 static void pmap_pkru_deassign_all(pmap_t pmap);
545 static COUNTER_U64_DEFINE_EARLY(pcid_save_cnt);
546 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLFLAG_RD,
547 &pcid_save_cnt, "Count of saved TLB context on switch");
549 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
550 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
551 static struct mtx invl_gen_mtx;
552 /* Fake lock object to satisfy turnstiles interface. */
553 static struct lock_object invl_gen_ts = {
556 static struct pmap_invl_gen pmap_invl_gen_head = {
560 static u_long pmap_invl_gen = 1;
561 static int pmap_invl_waiters;
562 static struct callout pmap_invl_callout;
563 static bool pmap_invl_callout_inited;
565 #define PMAP_ASSERT_NOT_IN_DI() \
566 KASSERT(pmap_not_in_di(), ("DI already started"))
573 if ((cpu_feature2 & CPUID2_CX16) == 0)
576 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
581 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
585 locked = pmap_di_locked();
586 return (sysctl_handle_int(oidp, &locked, 0, req));
588 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
589 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
590 "Locked delayed invalidation");
592 static bool pmap_not_in_di_l(void);
593 static bool pmap_not_in_di_u(void);
594 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
597 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
601 pmap_not_in_di_l(void)
603 struct pmap_invl_gen *invl_gen;
605 invl_gen = &curthread->td_md.md_invl_gen;
606 return (invl_gen->gen == 0);
610 pmap_thread_init_invl_gen_l(struct thread *td)
612 struct pmap_invl_gen *invl_gen;
614 invl_gen = &td->td_md.md_invl_gen;
619 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
621 struct turnstile *ts;
623 ts = turnstile_trywait(&invl_gen_ts);
624 if (*m_gen > atomic_load_long(invl_gen))
625 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
627 turnstile_cancel(ts);
631 pmap_delayed_invl_finish_unblock(u_long new_gen)
633 struct turnstile *ts;
635 turnstile_chain_lock(&invl_gen_ts);
636 ts = turnstile_lookup(&invl_gen_ts);
638 pmap_invl_gen = new_gen;
640 turnstile_broadcast(ts, TS_SHARED_QUEUE);
641 turnstile_unpend(ts);
643 turnstile_chain_unlock(&invl_gen_ts);
647 * Start a new Delayed Invalidation (DI) block of code, executed by
648 * the current thread. Within a DI block, the current thread may
649 * destroy both the page table and PV list entries for a mapping and
650 * then release the corresponding PV list lock before ensuring that
651 * the mapping is flushed from the TLBs of any processors with the
655 pmap_delayed_invl_start_l(void)
657 struct pmap_invl_gen *invl_gen;
660 invl_gen = &curthread->td_md.md_invl_gen;
661 PMAP_ASSERT_NOT_IN_DI();
662 mtx_lock(&invl_gen_mtx);
663 if (LIST_EMPTY(&pmap_invl_gen_tracker))
664 currgen = pmap_invl_gen;
666 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
667 invl_gen->gen = currgen + 1;
668 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
669 mtx_unlock(&invl_gen_mtx);
673 * Finish the DI block, previously started by the current thread. All
674 * required TLB flushes for the pages marked by
675 * pmap_delayed_invl_page() must be finished before this function is
678 * This function works by bumping the global DI generation number to
679 * the generation number of the current thread's DI, unless there is a
680 * pending DI that started earlier. In the latter case, bumping the
681 * global DI generation number would incorrectly signal that the
682 * earlier DI had finished. Instead, this function bumps the earlier
683 * DI's generation number to match the generation number of the
684 * current thread's DI.
687 pmap_delayed_invl_finish_l(void)
689 struct pmap_invl_gen *invl_gen, *next;
691 invl_gen = &curthread->td_md.md_invl_gen;
692 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
693 mtx_lock(&invl_gen_mtx);
694 next = LIST_NEXT(invl_gen, link);
696 pmap_delayed_invl_finish_unblock(invl_gen->gen);
698 next->gen = invl_gen->gen;
699 LIST_REMOVE(invl_gen, link);
700 mtx_unlock(&invl_gen_mtx);
705 pmap_not_in_di_u(void)
707 struct pmap_invl_gen *invl_gen;
709 invl_gen = &curthread->td_md.md_invl_gen;
710 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
714 pmap_thread_init_invl_gen_u(struct thread *td)
716 struct pmap_invl_gen *invl_gen;
718 invl_gen = &td->td_md.md_invl_gen;
720 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
724 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
726 uint64_t new_high, new_low, old_high, old_low;
729 old_low = new_low = 0;
730 old_high = new_high = (uintptr_t)0;
732 __asm volatile("lock;cmpxchg16b\t%1"
733 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
734 : "b"(new_low), "c" (new_high)
737 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
740 out->next = (void *)old_high;
743 out->next = (void *)new_high;
749 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
750 struct pmap_invl_gen *new_val)
752 uint64_t new_high, new_low, old_high, old_low;
755 new_low = new_val->gen;
756 new_high = (uintptr_t)new_val->next;
757 old_low = old_val->gen;
758 old_high = (uintptr_t)old_val->next;
760 __asm volatile("lock;cmpxchg16b\t%1"
761 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
762 : "b"(new_low), "c" (new_high)
767 static COUNTER_U64_DEFINE_EARLY(pv_page_count);
768 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_page_count, CTLFLAG_RD,
769 &pv_page_count, "Current number of allocated pv pages");
771 static COUNTER_U64_DEFINE_EARLY(user_pt_page_count);
772 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, user_pt_page_count, CTLFLAG_RD,
774 "Current number of allocated page table pages for userspace");
776 static COUNTER_U64_DEFINE_EARLY(kernel_pt_page_count);
777 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, kernel_pt_page_count, CTLFLAG_RD,
778 &kernel_pt_page_count,
779 "Current number of allocated page table pages for the kernel");
783 static COUNTER_U64_DEFINE_EARLY(invl_start_restart);
784 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_start_restart,
785 CTLFLAG_RD, &invl_start_restart,
786 "Number of delayed TLB invalidation request restarts");
788 static COUNTER_U64_DEFINE_EARLY(invl_finish_restart);
789 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
790 &invl_finish_restart,
791 "Number of delayed TLB invalidation completion restarts");
793 static int invl_max_qlen;
794 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
796 "Maximum delayed TLB invalidation request queue length");
799 #define di_delay locks_delay
802 pmap_delayed_invl_start_u(void)
804 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
806 struct lock_delay_arg lda;
814 invl_gen = &td->td_md.md_invl_gen;
815 PMAP_ASSERT_NOT_IN_DI();
816 lock_delay_arg_init(&lda, &di_delay);
817 invl_gen->saved_pri = 0;
818 pri = td->td_base_pri;
821 pri = td->td_base_pri;
823 invl_gen->saved_pri = pri;
830 for (p = &pmap_invl_gen_head;; p = prev.next) {
832 prevl = (uintptr_t)atomic_load_ptr(&p->next);
833 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
834 PV_STAT(counter_u64_add(invl_start_restart, 1));
840 prev.next = (void *)prevl;
843 if ((ii = invl_max_qlen) < i)
844 atomic_cmpset_int(&invl_max_qlen, ii, i);
847 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
848 PV_STAT(counter_u64_add(invl_start_restart, 1));
853 new_prev.gen = prev.gen;
854 new_prev.next = invl_gen;
855 invl_gen->gen = prev.gen + 1;
857 /* Formal fence between store to invl->gen and updating *p. */
858 atomic_thread_fence_rel();
861 * After inserting an invl_gen element with invalid bit set,
862 * this thread blocks any other thread trying to enter the
863 * delayed invalidation block. Do not allow to remove us from
864 * the CPU, because it causes starvation for other threads.
869 * ABA for *p is not possible there, since p->gen can only
870 * increase. So if the *p thread finished its di, then
871 * started a new one and got inserted into the list at the
872 * same place, its gen will appear greater than the previously
875 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
877 PV_STAT(counter_u64_add(invl_start_restart, 1));
883 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
884 * invl_gen->next, allowing other threads to iterate past us.
885 * pmap_di_store_invl() provides fence between the generation
886 * write and the update of next.
888 invl_gen->next = NULL;
893 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
894 struct pmap_invl_gen *p)
896 struct pmap_invl_gen prev, new_prev;
900 * Load invl_gen->gen after setting invl_gen->next
901 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
902 * generations to propagate to our invl_gen->gen. Lock prefix
903 * in atomic_set_ptr() worked as seq_cst fence.
905 mygen = atomic_load_long(&invl_gen->gen);
907 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
910 KASSERT(prev.gen < mygen,
911 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
912 new_prev.gen = mygen;
913 new_prev.next = (void *)((uintptr_t)invl_gen->next &
914 ~PMAP_INVL_GEN_NEXT_INVALID);
916 /* Formal fence between load of prev and storing update to it. */
917 atomic_thread_fence_rel();
919 return (pmap_di_store_invl(p, &prev, &new_prev));
923 pmap_delayed_invl_finish_u(void)
925 struct pmap_invl_gen *invl_gen, *p;
927 struct lock_delay_arg lda;
931 invl_gen = &td->td_md.md_invl_gen;
932 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
933 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
934 ("missed invl_start: INVALID"));
935 lock_delay_arg_init(&lda, &di_delay);
938 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
939 prevl = (uintptr_t)atomic_load_ptr(&p->next);
940 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
941 PV_STAT(counter_u64_add(invl_finish_restart, 1));
945 if ((void *)prevl == invl_gen)
950 * It is legitimate to not find ourself on the list if a
951 * thread before us finished its DI and started it again.
953 if (__predict_false(p == NULL)) {
954 PV_STAT(counter_u64_add(invl_finish_restart, 1));
960 atomic_set_ptr((uintptr_t *)&invl_gen->next,
961 PMAP_INVL_GEN_NEXT_INVALID);
962 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
963 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
964 PMAP_INVL_GEN_NEXT_INVALID);
966 PV_STAT(counter_u64_add(invl_finish_restart, 1));
971 if (atomic_load_int(&pmap_invl_waiters) > 0)
972 pmap_delayed_invl_finish_unblock(0);
973 if (invl_gen->saved_pri != 0) {
975 sched_prio(td, invl_gen->saved_pri);
981 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
983 struct pmap_invl_gen *p, *pn;
988 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
990 nextl = (uintptr_t)atomic_load_ptr(&p->next);
991 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
992 td = first ? NULL : __containerof(p, struct thread,
994 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
995 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
996 td != NULL ? td->td_tid : -1);
1002 static COUNTER_U64_DEFINE_EARLY(invl_wait);
1003 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait,
1004 CTLFLAG_RD, &invl_wait,
1005 "Number of times DI invalidation blocked pmap_remove_all/write");
1007 static COUNTER_U64_DEFINE_EARLY(invl_wait_slow);
1008 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD,
1009 &invl_wait_slow, "Number of slow invalidation waits for lockless DI");
1015 pmap_delayed_invl_genp(vm_page_t m)
1020 pa = VM_PAGE_TO_PHYS(m);
1021 if (__predict_false((pa) > pmap_last_pa))
1022 gen = &pv_dummy_large.pv_invl_gen;
1024 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1030 pmap_delayed_invl_genp(vm_page_t m)
1033 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1038 pmap_delayed_invl_callout_func(void *arg __unused)
1041 if (atomic_load_int(&pmap_invl_waiters) == 0)
1043 pmap_delayed_invl_finish_unblock(0);
1047 pmap_delayed_invl_callout_init(void *arg __unused)
1050 if (pmap_di_locked())
1052 callout_init(&pmap_invl_callout, 1);
1053 pmap_invl_callout_inited = true;
1055 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1056 pmap_delayed_invl_callout_init, NULL);
1059 * Ensure that all currently executing DI blocks, that need to flush
1060 * TLB for the given page m, actually flushed the TLB at the time the
1061 * function returned. If the page m has an empty PV list and we call
1062 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1063 * valid mapping for the page m in either its page table or TLB.
1065 * This function works by blocking until the global DI generation
1066 * number catches up with the generation number associated with the
1067 * given page m and its PV list. Since this function's callers
1068 * typically own an object lock and sometimes own a page lock, it
1069 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1073 pmap_delayed_invl_wait_l(vm_page_t m)
1077 bool accounted = false;
1080 m_gen = pmap_delayed_invl_genp(m);
1081 while (*m_gen > pmap_invl_gen) {
1084 counter_u64_add(invl_wait, 1);
1088 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1093 pmap_delayed_invl_wait_u(vm_page_t m)
1096 struct lock_delay_arg lda;
1100 m_gen = pmap_delayed_invl_genp(m);
1101 lock_delay_arg_init(&lda, &di_delay);
1102 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1103 if (fast || !pmap_invl_callout_inited) {
1104 PV_STAT(counter_u64_add(invl_wait, 1));
1109 * The page's invalidation generation number
1110 * is still below the current thread's number.
1111 * Prepare to block so that we do not waste
1112 * CPU cycles or worse, suffer livelock.
1114 * Since it is impossible to block without
1115 * racing with pmap_delayed_invl_finish_u(),
1116 * prepare for the race by incrementing
1117 * pmap_invl_waiters and arming a 1-tick
1118 * callout which will unblock us if we lose
1121 atomic_add_int(&pmap_invl_waiters, 1);
1124 * Re-check the current thread's invalidation
1125 * generation after incrementing
1126 * pmap_invl_waiters, so that there is no race
1127 * with pmap_delayed_invl_finish_u() setting
1128 * the page generation and checking
1129 * pmap_invl_waiters. The only race allowed
1130 * is for a missed unblock, which is handled
1134 atomic_load_long(&pmap_invl_gen_head.gen)) {
1135 callout_reset(&pmap_invl_callout, 1,
1136 pmap_delayed_invl_callout_func, NULL);
1137 PV_STAT(counter_u64_add(invl_wait_slow, 1));
1138 pmap_delayed_invl_wait_block(m_gen,
1139 &pmap_invl_gen_head.gen);
1141 atomic_add_int(&pmap_invl_waiters, -1);
1146 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1149 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1150 pmap_thread_init_invl_gen_u);
1153 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1156 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1157 pmap_delayed_invl_start_u);
1160 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1163 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1164 pmap_delayed_invl_finish_u);
1167 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1170 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1171 pmap_delayed_invl_wait_u);
1175 * Mark the page m's PV list as participating in the current thread's
1176 * DI block. Any threads concurrently using m's PV list to remove or
1177 * restrict all mappings to m will wait for the current thread's DI
1178 * block to complete before proceeding.
1180 * The function works by setting the DI generation number for m's PV
1181 * list to at least the DI generation number of the current thread.
1182 * This forces a caller of pmap_delayed_invl_wait() to block until
1183 * current thread calls pmap_delayed_invl_finish().
1186 pmap_delayed_invl_page(vm_page_t m)
1190 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1191 gen = curthread->td_md.md_invl_gen.gen;
1194 m_gen = pmap_delayed_invl_genp(m);
1202 static caddr_t crashdumpmap;
1205 * Internal flags for pmap_enter()'s helper functions.
1207 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1208 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1211 * Internal flags for pmap_mapdev_internal() and
1212 * pmap_change_props_locked().
1214 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1215 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1216 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1218 TAILQ_HEAD(pv_chunklist, pv_chunk);
1220 static void free_pv_chunk(struct pv_chunk *pc);
1221 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1222 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1223 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1224 static int popcnt_pc_map_pq(uint64_t *map);
1225 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1226 static void reserve_pv_entries(pmap_t pmap, int needed,
1227 struct rwlock **lockp);
1228 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1229 struct rwlock **lockp);
1230 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1231 u_int flags, struct rwlock **lockp);
1232 #if VM_NRESERVLEVEL > 0
1233 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1234 struct rwlock **lockp);
1236 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1237 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1240 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1241 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1242 vm_prot_t prot, int mode, int flags);
1243 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1244 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1245 vm_offset_t va, struct rwlock **lockp);
1246 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1248 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1249 vm_prot_t prot, struct rwlock **lockp);
1250 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1251 u_int flags, vm_page_t m, struct rwlock **lockp);
1252 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1253 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1254 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1255 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1256 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1258 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1260 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1262 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1263 static vm_page_t pmap_large_map_getptp_unlocked(void);
1264 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1265 #if VM_NRESERVLEVEL > 0
1266 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1267 struct rwlock **lockp);
1269 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1271 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1272 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1274 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1275 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1276 static void pmap_pti_wire_pte(void *pte);
1277 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1278 struct spglist *free, struct rwlock **lockp);
1279 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1280 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1281 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1282 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1283 struct spglist *free);
1284 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1285 pd_entry_t *pde, struct spglist *free,
1286 struct rwlock **lockp);
1287 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1288 vm_page_t m, struct rwlock **lockp);
1289 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1291 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1293 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1294 struct rwlock **lockp);
1295 static vm_page_t pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex,
1296 struct rwlock **lockp, vm_offset_t va);
1297 static vm_page_t pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex,
1298 struct rwlock **lockp, vm_offset_t va);
1299 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1300 struct rwlock **lockp);
1302 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1303 struct spglist *free);
1304 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1306 static vm_page_t pmap_alloc_pt_page(pmap_t, vm_pindex_t, int);
1307 static void pmap_free_pt_page(pmap_t, vm_page_t, bool);
1309 /********************/
1310 /* Inline functions */
1311 /********************/
1314 * Return a non-clipped indexes for a given VA, which are page table
1315 * pages indexes at the corresponding level.
1317 static __inline vm_pindex_t
1318 pmap_pde_pindex(vm_offset_t va)
1320 return (va >> PDRSHIFT);
1323 static __inline vm_pindex_t
1324 pmap_pdpe_pindex(vm_offset_t va)
1326 return (NUPDE + (va >> PDPSHIFT));
1329 static __inline vm_pindex_t
1330 pmap_pml4e_pindex(vm_offset_t va)
1332 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1335 static __inline vm_pindex_t
1336 pmap_pml5e_pindex(vm_offset_t va)
1338 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1341 static __inline pml4_entry_t *
1342 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1345 MPASS(pmap_is_la57(pmap));
1346 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1349 static __inline pml4_entry_t *
1350 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1353 MPASS(pmap_is_la57(pmap));
1354 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1357 static __inline pml4_entry_t *
1358 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1360 pml4_entry_t *pml4e;
1362 /* XXX MPASS(pmap_is_la57(pmap); */
1363 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1364 return (&pml4e[pmap_pml4e_index(va)]);
1367 /* Return a pointer to the PML4 slot that corresponds to a VA */
1368 static __inline pml4_entry_t *
1369 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1371 pml5_entry_t *pml5e;
1372 pml4_entry_t *pml4e;
1375 if (pmap_is_la57(pmap)) {
1376 pml5e = pmap_pml5e(pmap, va);
1377 PG_V = pmap_valid_bit(pmap);
1378 if ((*pml5e & PG_V) == 0)
1380 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1382 pml4e = pmap->pm_pmltop;
1384 return (&pml4e[pmap_pml4e_index(va)]);
1387 static __inline pml4_entry_t *
1388 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1390 MPASS(!pmap_is_la57(pmap));
1391 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1394 /* Return a pointer to the PDP slot that corresponds to a VA */
1395 static __inline pdp_entry_t *
1396 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1400 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1401 return (&pdpe[pmap_pdpe_index(va)]);
1404 /* Return a pointer to the PDP slot that corresponds to a VA */
1405 static __inline pdp_entry_t *
1406 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1408 pml4_entry_t *pml4e;
1411 PG_V = pmap_valid_bit(pmap);
1412 pml4e = pmap_pml4e(pmap, va);
1413 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1415 return (pmap_pml4e_to_pdpe(pml4e, va));
1418 /* Return a pointer to the PD slot that corresponds to a VA */
1419 static __inline pd_entry_t *
1420 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1424 KASSERT((*pdpe & PG_PS) == 0,
1425 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1426 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1427 return (&pde[pmap_pde_index(va)]);
1430 /* Return a pointer to the PD slot that corresponds to a VA */
1431 static __inline pd_entry_t *
1432 pmap_pde(pmap_t pmap, vm_offset_t va)
1437 PG_V = pmap_valid_bit(pmap);
1438 pdpe = pmap_pdpe(pmap, va);
1439 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1441 KASSERT((*pdpe & PG_PS) == 0,
1442 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1443 return (pmap_pdpe_to_pde(pdpe, va));
1446 /* Return a pointer to the PT slot that corresponds to a VA */
1447 static __inline pt_entry_t *
1448 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1452 KASSERT((*pde & PG_PS) == 0,
1453 ("%s: pde %#lx is a leaf", __func__, *pde));
1454 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1455 return (&pte[pmap_pte_index(va)]);
1458 /* Return a pointer to the PT slot that corresponds to a VA */
1459 static __inline pt_entry_t *
1460 pmap_pte(pmap_t pmap, vm_offset_t va)
1465 PG_V = pmap_valid_bit(pmap);
1466 pde = pmap_pde(pmap, va);
1467 if (pde == NULL || (*pde & PG_V) == 0)
1469 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1470 return ((pt_entry_t *)pde);
1471 return (pmap_pde_to_pte(pde, va));
1474 static __inline void
1475 pmap_resident_count_adj(pmap_t pmap, int count)
1478 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1479 KASSERT(pmap->pm_stats.resident_count + count >= 0,
1480 ("pmap %p resident count underflow %ld %d", pmap,
1481 pmap->pm_stats.resident_count, count));
1482 pmap->pm_stats.resident_count += count;
1485 static __inline void
1486 pmap_pt_page_count_adj(pmap_t pmap, int count)
1488 if (pmap == kernel_pmap)
1489 counter_u64_add(kernel_pt_page_count, count);
1492 pmap_resident_count_adj(pmap, count);
1493 counter_u64_add(user_pt_page_count, count);
1497 PMAP_INLINE pt_entry_t *
1498 vtopte(vm_offset_t va)
1502 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1505 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1506 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1507 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1509 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1510 NPML4EPGSHIFT)) - 1);
1511 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1515 static __inline pd_entry_t *
1516 vtopde(vm_offset_t va)
1520 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1523 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1524 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1525 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1527 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1528 NPML4EPGSHIFT)) - 1);
1529 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1534 allocpages(vm_paddr_t *firstaddr, int n)
1539 bzero((void *)ret, n * PAGE_SIZE);
1540 *firstaddr += n * PAGE_SIZE;
1544 CTASSERT(powerof2(NDMPML4E));
1546 /* number of kernel PDP slots */
1547 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1550 nkpt_init(vm_paddr_t addr)
1557 pt_pages = howmany(addr, NBPDR);
1558 pt_pages += NKPDPE(pt_pages);
1561 * Add some slop beyond the bare minimum required for bootstrapping
1564 * This is quite important when allocating KVA for kernel modules.
1565 * The modules are required to be linked in the negative 2GB of
1566 * the address space. If we run out of KVA in this region then
1567 * pmap_growkernel() will need to allocate page table pages to map
1568 * the entire 512GB of KVA space which is an unnecessary tax on
1571 * Secondly, device memory mapped as part of setting up the low-
1572 * level console(s) is taken from KVA, starting at virtual_avail.
1573 * This is because cninit() is called after pmap_bootstrap() but
1574 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1577 pt_pages += 32; /* 64MB additional slop. */
1583 * Returns the proper write/execute permission for a physical page that is
1584 * part of the initial boot allocations.
1586 * If the page has kernel text, it is marked as read-only. If the page has
1587 * kernel read-only data, it is marked as read-only/not-executable. If the
1588 * page has only read-write data, it is marked as read-write/not-executable.
1589 * If the page is below/above the kernel range, it is marked as read-write.
1591 * This function operates on 2M pages, since we map the kernel space that
1594 static inline pt_entry_t
1595 bootaddr_rwx(vm_paddr_t pa)
1599 * The kernel is loaded at a 2MB-aligned address, and memory below that
1600 * need not be executable. The .bss section is padded to a 2MB
1601 * boundary, so memory following the kernel need not be executable
1602 * either. Preloaded kernel modules have their mapping permissions
1603 * fixed up by the linker.
1605 if (pa < trunc_2mpage(btext - KERNBASE) ||
1606 pa >= trunc_2mpage(_end - KERNBASE))
1607 return (X86_PG_RW | pg_nx);
1610 * The linker should ensure that the read-only and read-write
1611 * portions don't share the same 2M page, so this shouldn't
1612 * impact read-only data. However, in any case, any page with
1613 * read-write data needs to be read-write.
1615 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1616 return (X86_PG_RW | pg_nx);
1619 * Mark any 2M page containing kernel text as read-only. Mark
1620 * other pages with read-only data as read-only and not executable.
1621 * (It is likely a small portion of the read-only data section will
1622 * be marked as read-only, but executable. This should be acceptable
1623 * since the read-only protection will keep the data from changing.)
1624 * Note that fixups to the .text section will still work until we
1627 if (pa < round_2mpage(etext - KERNBASE))
1633 create_pagetables(vm_paddr_t *firstaddr)
1638 uint64_t DMPDkernphys;
1641 uint64_t KASANPDphys, KASANPTphys, KASANphys;
1642 vm_offset_t kasankernbase;
1643 int kasankpdpi, kasankpdi, nkasanpte;
1645 int i, j, ndm1g, nkpdpe, nkdmpde;
1647 /* Allocate page table pages for the direct map */
1648 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1649 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1651 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1652 if (ndmpdpphys > NDMPML4E) {
1654 * Each NDMPML4E allows 512 GB, so limit to that,
1655 * and then readjust ndmpdp and ndmpdpphys.
1657 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1658 Maxmem = atop(NDMPML4E * NBPML4);
1659 ndmpdpphys = NDMPML4E;
1660 ndmpdp = NDMPML4E * NPDEPG;
1662 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1664 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1666 * Calculate the number of 1G pages that will fully fit in
1669 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1672 * Allocate 2M pages for the kernel. These will be used in
1673 * place of the first one or more 1G pages from ndm1g.
1675 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1676 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1679 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1680 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1682 /* Allocate pages */
1683 KPML4phys = allocpages(firstaddr, 1);
1684 KPDPphys = allocpages(firstaddr, NKPML4E);
1686 KASANPDPphys = allocpages(firstaddr, NKASANPML4E);
1687 KASANPDphys = allocpages(firstaddr, 1);
1691 * Allocate the initial number of kernel page table pages required to
1692 * bootstrap. We defer this until after all memory-size dependent
1693 * allocations are done (e.g. direct map), so that we don't have to
1694 * build in too much slop in our estimate.
1696 * Note that when NKPML4E > 1, we have an empty page underneath
1697 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1698 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1700 nkpt_init(*firstaddr);
1701 nkpdpe = NKPDPE(nkpt);
1703 KPTphys = allocpages(firstaddr, nkpt);
1704 KPDphys = allocpages(firstaddr, nkpdpe);
1707 nkasanpte = howmany(nkpt, KASAN_SHADOW_SCALE);
1708 KASANPTphys = allocpages(firstaddr, nkasanpte);
1709 KASANphys = allocpages(firstaddr, nkasanpte * NPTEPG);
1713 * Connect the zero-filled PT pages to their PD entries. This
1714 * implicitly maps the PT pages at their correct locations within
1717 pd_p = (pd_entry_t *)KPDphys;
1718 for (i = 0; i < nkpt; i++)
1719 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1722 * Map from physical address zero to the end of loader preallocated
1723 * memory using 2MB pages. This replaces some of the PD entries
1726 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1727 /* Preset PG_M and PG_A because demotion expects it. */
1728 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1729 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1732 * Because we map the physical blocks in 2M pages, adjust firstaddr
1733 * to record the physical blocks we've actually mapped into kernel
1734 * virtual address space.
1736 if (*firstaddr < round_2mpage(KERNend))
1737 *firstaddr = round_2mpage(KERNend);
1739 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1740 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1741 for (i = 0; i < nkpdpe; i++)
1742 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1745 kasankernbase = kasan_md_addr_to_shad(KERNBASE);
1746 kasankpdpi = pmap_pdpe_index(kasankernbase);
1747 kasankpdi = pmap_pde_index(kasankernbase);
1749 pdp_p = (pdp_entry_t *)KASANPDPphys;
1750 pdp_p[kasankpdpi] = (KASANPDphys | X86_PG_RW | X86_PG_V | pg_nx);
1752 pd_p = (pd_entry_t *)KASANPDphys;
1753 for (i = 0; i < nkasanpte; i++)
1754 pd_p[i + kasankpdi] = (KASANPTphys + ptoa(i)) | X86_PG_RW |
1757 pt_p = (pt_entry_t *)KASANPTphys;
1758 for (i = 0; i < nkasanpte * NPTEPG; i++)
1759 pt_p[i] = (KASANphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
1760 X86_PG_M | X86_PG_A | pg_nx;
1764 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1765 * the end of physical memory is not aligned to a 1GB page boundary,
1766 * then the residual physical memory is mapped with 2MB pages. Later,
1767 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1768 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1769 * that are partially used.
1771 pd_p = (pd_entry_t *)DMPDphys;
1772 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1773 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1774 /* Preset PG_M and PG_A because demotion expects it. */
1775 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1776 X86_PG_M | X86_PG_A | pg_nx;
1778 pdp_p = (pdp_entry_t *)DMPDPphys;
1779 for (i = 0; i < ndm1g; i++) {
1780 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1781 /* Preset PG_M and PG_A because demotion expects it. */
1782 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1783 X86_PG_M | X86_PG_A | pg_nx;
1785 for (j = 0; i < ndmpdp; i++, j++) {
1786 pdp_p[i] = DMPDphys + ptoa(j);
1787 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1791 * Instead of using a 1G page for the memory containing the kernel,
1792 * use 2M pages with read-only and no-execute permissions. (If using 1G
1793 * pages, this will partially overwrite the PDPEs above.)
1796 pd_p = (pd_entry_t *)DMPDkernphys;
1797 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1798 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1799 X86_PG_M | X86_PG_A | pg_nx |
1800 bootaddr_rwx(i << PDRSHIFT);
1801 for (i = 0; i < nkdmpde; i++)
1802 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1806 /* And recursively map PML4 to itself in order to get PTmap */
1807 p4_p = (pml4_entry_t *)KPML4phys;
1808 p4_p[PML4PML4I] = KPML4phys;
1809 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1812 /* Connect the KASAN shadow map slots up to the PML4. */
1813 for (i = 0; i < NKASANPML4E; i++) {
1814 p4_p[KASANPML4I + i] = KASANPDPphys + ptoa(i);
1815 p4_p[KASANPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1819 /* Connect the Direct Map slots up to the PML4. */
1820 for (i = 0; i < ndmpdpphys; i++) {
1821 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1822 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1825 /* Connect the KVA slots up to the PML4 */
1826 for (i = 0; i < NKPML4E; i++) {
1827 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1828 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1831 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1835 * Bootstrap the system enough to run with virtual memory.
1837 * On amd64 this is called after mapping has already been enabled
1838 * and just syncs the pmap module with what has already been done.
1839 * [We can't call it easily with mapping off since the kernel is not
1840 * mapped with PA == VA, hence we would have to relocate every address
1841 * from the linked base (virtual) address "KERNBASE" to the actual
1842 * (physical) address starting relative to 0]
1845 pmap_bootstrap(vm_paddr_t *firstaddr)
1848 pt_entry_t *pte, *pcpu_pte;
1849 struct region_descriptor r_gdt;
1850 uint64_t cr4, pcpu_phys;
1854 KERNend = *firstaddr;
1855 res = atop(KERNend - (vm_paddr_t)kernphys);
1861 * Create an initial set of page tables to run the kernel in.
1863 create_pagetables(firstaddr);
1865 pcpu_phys = allocpages(firstaddr, MAXCPU);
1868 * Add a physical memory segment (vm_phys_seg) corresponding to the
1869 * preallocated kernel page table pages so that vm_page structures
1870 * representing these pages will be created. The vm_page structures
1871 * are required for promotion of the corresponding kernel virtual
1872 * addresses to superpage mappings.
1874 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1877 * Account for the virtual addresses mapped by create_pagetables().
1879 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1880 virtual_end = VM_MAX_KERNEL_ADDRESS;
1883 * Enable PG_G global pages, then switch to the kernel page
1884 * table from the bootstrap page table. After the switch, it
1885 * is possible to enable SMEP and SMAP since PG_U bits are
1891 load_cr3(KPML4phys);
1892 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1894 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1899 * Initialize the kernel pmap (which is statically allocated).
1900 * Count bootstrap data as being resident in case any of this data is
1901 * later unmapped (using pmap_remove()) and freed.
1903 PMAP_LOCK_INIT(kernel_pmap);
1904 kernel_pmap->pm_pmltop = kernel_pml4;
1905 kernel_pmap->pm_cr3 = KPML4phys;
1906 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1907 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1908 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1909 kernel_pmap->pm_stats.resident_count = res;
1910 kernel_pmap->pm_flags = pmap_flags;
1913 * Initialize the TLB invalidations generation number lock.
1915 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1918 * Reserve some special page table entries/VA space for temporary
1921 #define SYSMAP(c, p, v, n) \
1922 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1928 * Crashdump maps. The first page is reused as CMAP1 for the
1931 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1932 CADDR1 = crashdumpmap;
1934 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1937 for (i = 0; i < MAXCPU; i++) {
1938 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1939 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1943 * Re-initialize PCPU area for BSP after switching.
1944 * Make hardware use gdt and common_tss from the new PCPU.
1946 STAILQ_INIT(&cpuhead);
1947 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1948 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1949 amd64_bsp_pcpu_init1(&__pcpu[0]);
1950 amd64_bsp_ist_init(&__pcpu[0]);
1951 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1953 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1954 sizeof(struct user_segment_descriptor));
1955 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1956 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1957 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1958 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1959 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1961 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1962 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1963 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1964 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1967 * Initialize the PAT MSR.
1968 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1969 * side-effect, invalidates stale PG_G TLB entries that might
1970 * have been created in our pre-boot environment.
1974 /* Initialize TLB Context Id. */
1975 if (pmap_pcid_enabled) {
1976 for (i = 0; i < MAXCPU; i++) {
1977 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1978 kernel_pmap->pm_pcids[i].pm_gen = 1;
1982 * PMAP_PCID_KERN + 1 is used for initialization of
1983 * proc0 pmap. The pmap' pcid state might be used by
1984 * EFIRT entry before first context switch, so it
1985 * needs to be valid.
1987 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1988 PCPU_SET(pcid_gen, 1);
1991 * pcpu area for APs is zeroed during AP startup.
1992 * pc_pcid_next and pc_pcid_gen are initialized by AP
1993 * during pcpu setup.
1995 load_cr4(rcr4() | CR4_PCIDE);
2000 * Setup the PAT MSR.
2009 /* Bail if this CPU doesn't implement PAT. */
2010 if ((cpu_feature & CPUID_PAT) == 0)
2013 /* Set default PAT index table. */
2014 for (i = 0; i < PAT_INDEX_SIZE; i++)
2016 pat_index[PAT_WRITE_BACK] = 0;
2017 pat_index[PAT_WRITE_THROUGH] = 1;
2018 pat_index[PAT_UNCACHEABLE] = 3;
2019 pat_index[PAT_WRITE_COMBINING] = 6;
2020 pat_index[PAT_WRITE_PROTECTED] = 5;
2021 pat_index[PAT_UNCACHED] = 2;
2024 * Initialize default PAT entries.
2025 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
2026 * Program 5 and 6 as WP and WC.
2028 * Leave 4 and 7 as WB and UC. Note that a recursive page table
2029 * mapping for a 2M page uses a PAT value with the bit 3 set due
2030 * to its overload with PG_PS.
2032 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
2033 PAT_VALUE(1, PAT_WRITE_THROUGH) |
2034 PAT_VALUE(2, PAT_UNCACHED) |
2035 PAT_VALUE(3, PAT_UNCACHEABLE) |
2036 PAT_VALUE(4, PAT_WRITE_BACK) |
2037 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
2038 PAT_VALUE(6, PAT_WRITE_COMBINING) |
2039 PAT_VALUE(7, PAT_UNCACHEABLE);
2043 load_cr4(cr4 & ~CR4_PGE);
2045 /* Disable caches (CD = 1, NW = 0). */
2047 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
2049 /* Flushes caches and TLBs. */
2053 /* Update PAT and index table. */
2054 wrmsr(MSR_PAT, pat_msr);
2056 /* Flush caches and TLBs again. */
2060 /* Restore caches and PGE. */
2065 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
2066 la57_trampoline_gdt[], la57_trampoline_end[];
2069 pmap_bootstrap_la57(void *arg __unused)
2072 pml5_entry_t *v_pml5;
2073 pml4_entry_t *v_pml4;
2077 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2078 void (*la57_tramp)(uint64_t pml5);
2079 struct region_descriptor r_gdt;
2081 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2083 TUNABLE_INT_FETCH("vm.pmap.la57", &la57);
2087 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2088 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2090 m_code = vm_page_alloc_contig(NULL, 0,
2091 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2092 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2093 if ((m_code->flags & PG_ZERO) == 0)
2094 pmap_zero_page(m_code);
2095 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2096 m_pml5 = vm_page_alloc_contig(NULL, 0,
2097 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2098 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2099 if ((m_pml5->flags & PG_ZERO) == 0)
2100 pmap_zero_page(m_pml5);
2101 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2102 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2103 m_pml4 = vm_page_alloc_contig(NULL, 0,
2104 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2105 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2106 if ((m_pml4->flags & PG_ZERO) == 0)
2107 pmap_zero_page(m_pml4);
2108 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2109 m_pdp = vm_page_alloc_contig(NULL, 0,
2110 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2111 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2112 if ((m_pdp->flags & PG_ZERO) == 0)
2113 pmap_zero_page(m_pdp);
2114 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2115 m_pd = vm_page_alloc_contig(NULL, 0,
2116 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2117 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2118 if ((m_pd->flags & PG_ZERO) == 0)
2119 pmap_zero_page(m_pd);
2120 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2121 m_pt = vm_page_alloc_contig(NULL, 0,
2122 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2123 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2124 if ((m_pt->flags & PG_ZERO) == 0)
2125 pmap_zero_page(m_pt);
2126 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2129 * Map m_code 1:1, it appears below 4G in KVA due to physical
2130 * address being below 4G. Since kernel KVA is in upper half,
2131 * the pml4e should be zero and free for temporary use.
2133 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2134 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2136 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2137 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2139 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2140 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2142 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2143 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2147 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2148 * entering all existing kernel mappings into level 5 table.
2150 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2151 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2154 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2156 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2157 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2159 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2160 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2164 * Copy and call the 48->57 trampoline, hope we return there, alive.
2166 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2167 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2168 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2169 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2170 invlpg((vm_offset_t)la57_tramp);
2171 la57_tramp(KPML5phys);
2174 * gdt was necessary reset, switch back to our gdt.
2177 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2181 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2182 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2183 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2186 * Now unmap the trampoline, and free the pages.
2187 * Clear pml5 entry used for 1:1 trampoline mapping.
2189 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2190 invlpg((vm_offset_t)v_code);
2191 vm_page_free(m_code);
2192 vm_page_free(m_pdp);
2197 * Recursively map PML5 to itself in order to get PTmap and
2200 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2202 kernel_pmap->pm_cr3 = KPML5phys;
2203 kernel_pmap->pm_pmltop = v_pml5;
2204 pmap_pt_page_count_adj(kernel_pmap, 1);
2206 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2209 * Initialize a vm_page's machine-dependent fields.
2212 pmap_page_init(vm_page_t m)
2215 TAILQ_INIT(&m->md.pv_list);
2216 m->md.pat_mode = PAT_WRITE_BACK;
2219 static int pmap_allow_2m_x_ept;
2220 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2221 &pmap_allow_2m_x_ept, 0,
2222 "Allow executable superpage mappings in EPT");
2225 pmap_allow_2m_x_ept_recalculate(void)
2228 * SKL002, SKL012S. Since the EPT format is only used by
2229 * Intel CPUs, the vendor check is merely a formality.
2231 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2232 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2233 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2234 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2235 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2236 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2237 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2238 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2239 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2240 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2241 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2242 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2243 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2244 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2245 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2246 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2247 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2248 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2249 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2250 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2251 CPUID_TO_MODEL(cpu_id) == 0x85))))
2252 pmap_allow_2m_x_ept = 1;
2253 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2257 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2260 return (pmap->pm_type != PT_EPT || !executable ||
2261 !pmap_allow_2m_x_ept);
2266 pmap_init_pv_table(void)
2268 struct pmap_large_md_page *pvd;
2270 long start, end, highest, pv_npg;
2271 int domain, i, j, pages;
2274 * We strongly depend on the size being a power of two, so the assert
2275 * is overzealous. However, should the struct be resized to a
2276 * different power of two, the code below needs to be revisited.
2278 CTASSERT((sizeof(*pvd) == 64));
2281 * Calculate the size of the array.
2283 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2284 pv_npg = howmany(pmap_last_pa, NBPDR);
2285 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2287 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2288 if (pv_table == NULL)
2289 panic("%s: kva_alloc failed\n", __func__);
2292 * Iterate physical segments to allocate space for respective pages.
2296 for (i = 0; i < vm_phys_nsegs; i++) {
2297 end = vm_phys_segs[i].end / NBPDR;
2298 domain = vm_phys_segs[i].domain;
2303 start = highest + 1;
2304 pvd = &pv_table[start];
2306 pages = end - start + 1;
2307 s = round_page(pages * sizeof(*pvd));
2308 highest = start + (s / sizeof(*pvd)) - 1;
2310 for (j = 0; j < s; j += PAGE_SIZE) {
2311 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2312 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2314 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2315 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2318 for (j = 0; j < s / sizeof(*pvd); j++) {
2319 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2320 TAILQ_INIT(&pvd->pv_page.pv_list);
2321 pvd->pv_page.pv_gen = 0;
2322 pvd->pv_page.pat_mode = 0;
2323 pvd->pv_invl_gen = 0;
2327 pvd = &pv_dummy_large;
2328 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2329 TAILQ_INIT(&pvd->pv_page.pv_list);
2330 pvd->pv_page.pv_gen = 0;
2331 pvd->pv_page.pat_mode = 0;
2332 pvd->pv_invl_gen = 0;
2336 pmap_init_pv_table(void)
2342 * Initialize the pool of pv list locks.
2344 for (i = 0; i < NPV_LIST_LOCKS; i++)
2345 rw_init(&pv_list_locks[i], "pmap pv list");
2348 * Calculate the size of the pv head table for superpages.
2350 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2353 * Allocate memory for the pv head table for superpages.
2355 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2357 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2358 for (i = 0; i < pv_npg; i++)
2359 TAILQ_INIT(&pv_table[i].pv_list);
2360 TAILQ_INIT(&pv_dummy.pv_list);
2365 * Initialize the pmap module.
2366 * Called by vm_init, to initialize any structures that the pmap
2367 * system needs to map virtual memory.
2372 struct pmap_preinit_mapping *ppim;
2374 int error, i, ret, skz63;
2376 /* L1TF, reserve page @0 unconditionally */
2377 vm_page_blacklist_add(0, bootverbose);
2379 /* Detect bare-metal Skylake Server and Skylake-X. */
2380 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2381 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2383 * Skylake-X errata SKZ63. Processor May Hang When
2384 * Executing Code In an HLE Transaction Region between
2385 * 40000000H and 403FFFFFH.
2387 * Mark the pages in the range as preallocated. It
2388 * seems to be impossible to distinguish between
2389 * Skylake Server and Skylake X.
2392 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2395 printf("SKZ63: skipping 4M RAM starting "
2396 "at physical 1G\n");
2397 for (i = 0; i < atop(0x400000); i++) {
2398 ret = vm_page_blacklist_add(0x40000000 +
2400 if (!ret && bootverbose)
2401 printf("page at %#lx already used\n",
2402 0x40000000 + ptoa(i));
2408 pmap_allow_2m_x_ept_recalculate();
2411 * Initialize the vm page array entries for the kernel pmap's
2414 PMAP_LOCK(kernel_pmap);
2415 for (i = 0; i < nkpt; i++) {
2416 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2417 KASSERT(mpte >= vm_page_array &&
2418 mpte < &vm_page_array[vm_page_array_size],
2419 ("pmap_init: page table page is out of range"));
2420 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2421 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2422 mpte->ref_count = 1;
2425 * Collect the page table pages that were replaced by a 2MB
2426 * page in create_pagetables(). They are zero filled.
2428 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2429 pmap_insert_pt_page(kernel_pmap, mpte, false))
2430 panic("pmap_init: pmap_insert_pt_page failed");
2432 PMAP_UNLOCK(kernel_pmap);
2436 * If the kernel is running on a virtual machine, then it must assume
2437 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2438 * be prepared for the hypervisor changing the vendor and family that
2439 * are reported by CPUID. Consequently, the workaround for AMD Family
2440 * 10h Erratum 383 is enabled if the processor's feature set does not
2441 * include at least one feature that is only supported by older Intel
2442 * or newer AMD processors.
2444 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2445 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2446 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2448 workaround_erratum383 = 1;
2451 * Are large page mappings enabled?
2453 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2454 if (pg_ps_enabled) {
2455 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2456 ("pmap_init: can't assign to pagesizes[1]"));
2457 pagesizes[1] = NBPDR;
2458 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2459 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2460 ("pmap_init: can't assign to pagesizes[2]"));
2461 pagesizes[2] = NBPDP;
2466 * Initialize pv chunk lists.
2468 for (i = 0; i < PMAP_MEMDOM; i++) {
2469 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2470 TAILQ_INIT(&pv_chunks[i].pvc_list);
2472 pmap_init_pv_table();
2474 pmap_initialized = 1;
2475 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2476 ppim = pmap_preinit_mapping + i;
2479 /* Make the direct map consistent */
2480 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2481 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2482 ppim->sz, ppim->mode);
2486 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2487 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2490 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2491 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2492 (vmem_addr_t *)&qframe);
2494 panic("qframe allocation failed");
2497 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2498 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2499 lm_ents = LMEPML4I - LMSPML4I + 1;
2501 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2502 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2504 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2505 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2506 if (large_vmem == NULL) {
2507 printf("pmap: cannot create large map\n");
2510 for (i = 0; i < lm_ents; i++) {
2511 m = pmap_large_map_getptp_unlocked();
2513 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2514 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2520 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2521 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2522 "Maximum number of PML4 entries for use by large map (tunable). "
2523 "Each entry corresponds to 512GB of address space.");
2525 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2526 "2MB page mapping counters");
2528 static COUNTER_U64_DEFINE_EARLY(pmap_pde_demotions);
2529 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, demotions,
2530 CTLFLAG_RD, &pmap_pde_demotions, "2MB page demotions");
2532 static COUNTER_U64_DEFINE_EARLY(pmap_pde_mappings);
2533 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2534 &pmap_pde_mappings, "2MB page mappings");
2536 static COUNTER_U64_DEFINE_EARLY(pmap_pde_p_failures);
2537 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2538 &pmap_pde_p_failures, "2MB page promotion failures");
2540 static COUNTER_U64_DEFINE_EARLY(pmap_pde_promotions);
2541 SYSCTL_COUNTER_U64(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2542 &pmap_pde_promotions, "2MB page promotions");
2544 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2545 "1GB page mapping counters");
2547 static COUNTER_U64_DEFINE_EARLY(pmap_pdpe_demotions);
2548 SYSCTL_COUNTER_U64(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2549 &pmap_pdpe_demotions, "1GB page demotions");
2551 /***************************************************
2552 * Low level helper routines.....
2553 ***************************************************/
2556 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2558 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2560 switch (pmap->pm_type) {
2563 /* Verify that both PAT bits are not set at the same time */
2564 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2565 ("Invalid PAT bits in entry %#lx", entry));
2567 /* Swap the PAT bits if one of them is set */
2568 if ((entry & x86_pat_bits) != 0)
2569 entry ^= x86_pat_bits;
2573 * Nothing to do - the memory attributes are represented
2574 * the same way for regular pages and superpages.
2578 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2585 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2588 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2589 pat_index[(int)mode] >= 0);
2593 * Determine the appropriate bits to set in a PTE or PDE for a specified
2597 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2599 int cache_bits, pat_flag, pat_idx;
2601 if (!pmap_is_valid_memattr(pmap, mode))
2602 panic("Unknown caching mode %d\n", mode);
2604 switch (pmap->pm_type) {
2607 /* The PAT bit is different for PTE's and PDE's. */
2608 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2610 /* Map the caching mode to a PAT index. */
2611 pat_idx = pat_index[mode];
2613 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2616 cache_bits |= pat_flag;
2618 cache_bits |= PG_NC_PCD;
2620 cache_bits |= PG_NC_PWT;
2624 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2628 panic("unsupported pmap type %d", pmap->pm_type);
2631 return (cache_bits);
2635 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2639 switch (pmap->pm_type) {
2642 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2645 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2648 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2655 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2657 int pat_flag, pat_idx;
2660 switch (pmap->pm_type) {
2663 /* The PAT bit is different for PTE's and PDE's. */
2664 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2666 if ((pte & pat_flag) != 0)
2668 if ((pte & PG_NC_PCD) != 0)
2670 if ((pte & PG_NC_PWT) != 0)
2674 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2675 panic("EPT PTE %#lx has no PAT memory type", pte);
2676 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2680 /* See pmap_init_pat(). */
2690 pmap_ps_enabled(pmap_t pmap)
2693 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2697 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2700 switch (pmap->pm_type) {
2707 * This is a little bogus since the generation number is
2708 * supposed to be bumped up when a region of the address
2709 * space is invalidated in the page tables.
2711 * In this case the old PDE entry is valid but yet we want
2712 * to make sure that any mappings using the old entry are
2713 * invalidated in the TLB.
2715 * The reason this works as expected is because we rendezvous
2716 * "all" host cpus and force any vcpu context to exit as a
2719 atomic_add_long(&pmap->pm_eptgen, 1);
2722 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2724 pde_store(pde, newpde);
2728 * After changing the page size for the specified virtual address in the page
2729 * table, flush the corresponding entries from the processor's TLB. Only the
2730 * calling processor's TLB is affected.
2732 * The calling thread must be pinned to a processor.
2735 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2739 if (pmap_type_guest(pmap))
2742 KASSERT(pmap->pm_type == PT_X86,
2743 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2745 PG_G = pmap_global_bit(pmap);
2747 if ((newpde & PG_PS) == 0)
2748 /* Demotion: flush a specific 2MB page mapping. */
2750 else if ((newpde & PG_G) == 0)
2752 * Promotion: flush every 4KB page mapping from the TLB
2753 * because there are too many to flush individually.
2758 * Promotion: flush every 4KB page mapping from the TLB,
2759 * including any global (PG_G) mappings.
2766 * The amd64 pmap uses different approaches to TLB invalidation
2767 * depending on the kernel configuration, available hardware features,
2768 * and known hardware errata. The kernel configuration option that
2769 * has the greatest operational impact on TLB invalidation is PTI,
2770 * which is enabled automatically on affected Intel CPUs. The most
2771 * impactful hardware features are first PCID, and then INVPCID
2772 * instruction presence. PCID usage is quite different for PTI
2775 * * Kernel Page Table Isolation (PTI or KPTI) is used to mitigate
2776 * the Meltdown bug in some Intel CPUs. Under PTI, each user address
2777 * space is served by two page tables, user and kernel. The user
2778 * page table only maps user space and a kernel trampoline. The
2779 * kernel trampoline includes the entirety of the kernel text but
2780 * only the kernel data that is needed to switch from user to kernel
2781 * mode. The kernel page table maps the user and kernel address
2782 * spaces in their entirety. It is identical to the per-process
2783 * page table used in non-PTI mode.
2785 * User page tables are only used when the CPU is in user mode.
2786 * Consequently, some TLB invalidations can be postponed until the
2787 * switch from kernel to user mode. In contrast, the user
2788 * space part of the kernel page table is used for copyout(9), so
2789 * TLB invalidations on this page table cannot be similarly postponed.
2791 * The existence of a user mode page table for the given pmap is
2792 * indicated by a pm_ucr3 value that differs from PMAP_NO_CR3, in
2793 * which case pm_ucr3 contains the %cr3 register value for the user
2794 * mode page table's root.
2796 * * The pm_active bitmask indicates which CPUs currently have the
2797 * pmap active. A CPU's bit is set on context switch to the pmap, and
2798 * cleared on switching off this CPU. For the kernel page table,
2799 * the pm_active field is immutable and contains all CPUs. The
2800 * kernel page table is always logically active on every processor,
2801 * but not necessarily in use by the hardware, e.g., in PTI mode.
2803 * When requesting invalidation of virtual addresses with
2804 * pmap_invalidate_XXX() functions, the pmap sends shootdown IPIs to
2805 * all CPUs recorded as active in pm_active. Updates to and reads
2806 * from pm_active are not synchronized, and so they may race with
2807 * each other. Shootdown handlers are prepared to handle the race.
2809 * * PCID is an optional feature of the long mode x86 MMU where TLB
2810 * entries are tagged with the 'Process ID' of the address space
2811 * they belong to. This feature provides a limited namespace for
2812 * process identifiers, 12 bits, supporting 4095 simultaneous IDs
2815 * Allocation of a PCID to a pmap is done by an algorithm described
2816 * in section 15.12, "Other TLB Consistency Algorithms", of
2817 * Vahalia's book "Unix Internals". A PCID cannot be allocated for
2818 * the whole lifetime of a pmap in pmap_pinit() due to the limited
2819 * namespace. Instead, a per-CPU, per-pmap PCID is assigned when
2820 * the CPU is about to start caching TLB entries from a pmap,
2821 * i.e., on the context switch that activates the pmap on the CPU.
2823 * The PCID allocator maintains a per-CPU, per-pmap generation
2824 * count, pm_gen, which is incremented each time a new PCID is
2825 * allocated. On TLB invalidation, the generation counters for the
2826 * pmap are zeroed, which signals the context switch code that the
2827 * previously allocated PCID is no longer valid. Effectively,
2828 * zeroing any of these counters triggers a TLB shootdown for the
2829 * given CPU/address space, due to the allocation of a new PCID.
2831 * Zeroing can be performed remotely. Consequently, if a pmap is
2832 * inactive on a CPU, then a TLB shootdown for that pmap and CPU can
2833 * be initiated by an ordinary memory access to reset the target
2834 * CPU's generation count within the pmap. The CPU initiating the
2835 * TLB shootdown does not need to send an IPI to the target CPU.
2837 * * PTI + PCID. The available PCIDs are divided into two sets: PCIDs
2838 * for complete (kernel) page tables, and PCIDs for user mode page
2839 * tables. A user PCID value is obtained from the kernel PCID value
2840 * by setting the highest bit, 11, to 1 (0x800 == PMAP_PCID_USER_PT).
2842 * User space page tables are activated on return to user mode, by
2843 * loading pm_ucr3 into %cr3. If the PCPU(ucr3_load_mask) requests
2844 * clearing bit 63 of the loaded ucr3, this effectively causes
2845 * complete invalidation of the user mode TLB entries for the
2846 * current pmap. In which case, local invalidations of individual
2847 * pages in the user page table are skipped.
2849 * * Local invalidation, all modes. If the requested invalidation is
2850 * for a specific address or the total invalidation of a currently
2851 * active pmap, then the TLB is flushed using INVLPG for a kernel
2852 * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a
2853 * user space page table(s).
2855 * If the INVPCID instruction is available, it is used to flush entries
2856 * from the kernel page table.
2858 * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its
2859 * address space, all other 4095 PCIDs are used for user mode spaces
2860 * as described above. A context switch allocates a new PCID if
2861 * the recorded PCID is zero or the recorded generation does not match
2862 * the CPU's generation, effectively flushing the TLB for this address space.
2863 * Total remote invalidation is performed by zeroing pm_gen for all CPUs.
2864 * local user page: INVLPG
2865 * local kernel page: INVLPG
2866 * local user total: INVPCID(CTX)
2867 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2868 * remote user page, inactive pmap: zero pm_gen
2869 * remote user page, active pmap: zero pm_gen + IPI:INVLPG
2870 * (Both actions are required to handle the aforementioned pm_active races.)
2871 * remote kernel page: IPI:INVLPG
2872 * remote user total, inactive pmap: zero pm_gen
2873 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) or
2875 * (See note above about pm_active races.)
2876 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2878 * PTI enabled, PCID present.
2879 * local user page: INVLPG for kpt, INVPCID(ADDR) or (INVLPG for ucr3)
2881 * local kernel page: INVLPG
2882 * local user total: INVPCID(CTX) or reload %cr3 for kpt, clear PCID_SAVE
2883 * on loading UCR3 into %cr3 for upt
2884 * local kernel total: INVPCID(CTXGLOB) or invltlb_glob()
2885 * remote user page, inactive pmap: zero pm_gen
2886 * remote user page, active pmap: zero pm_gen + IPI:(INVLPG for kpt,
2887 * INVPCID(ADDR) for upt)
2888 * remote kernel page: IPI:INVLPG
2889 * remote user total, inactive pmap: zero pm_gen
2890 * remote user total, active pmap: zero pm_gen + IPI:(INVPCID(CTX) for kpt,
2891 * clear PCID_SAVE on loading UCR3 into $cr3 for upt)
2892 * remote kernel total: IPI:(INVPCID(CTXGLOB) or invltlb_glob())
2895 * local user page: INVLPG
2896 * local kernel page: INVLPG
2897 * local user total: reload %cr3
2898 * local kernel total: invltlb_glob()
2899 * remote user page, inactive pmap: -
2900 * remote user page, active pmap: IPI:INVLPG
2901 * remote kernel page: IPI:INVLPG
2902 * remote user total, inactive pmap: -
2903 * remote user total, active pmap: IPI:(reload %cr3)
2904 * remote kernel total: IPI:invltlb_glob()
2905 * Since on return to user mode, the reload of %cr3 with ucr3 causes
2906 * TLB invalidation, no specific action is required for user page table.
2908 * EPT. EPT pmaps do not map KVA, all mappings are userspace.
2914 * Interrupt the cpus that are executing in the guest context.
2915 * This will force the vcpu to exit and the cached EPT mappings
2916 * will be invalidated by the host before the next vmresume.
2918 static __inline void
2919 pmap_invalidate_ept(pmap_t pmap)
2925 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2926 ("pmap_invalidate_ept: absurd pm_active"));
2929 * The TLB mappings associated with a vcpu context are not
2930 * flushed each time a different vcpu is chosen to execute.
2932 * This is in contrast with a process's vtop mappings that
2933 * are flushed from the TLB on each context switch.
2935 * Therefore we need to do more than just a TLB shootdown on
2936 * the active cpus in 'pmap->pm_active'. To do this we keep
2937 * track of the number of invalidations performed on this pmap.
2939 * Each vcpu keeps a cache of this counter and compares it
2940 * just before a vmresume. If the counter is out-of-date an
2941 * invept will be done to flush stale mappings from the TLB.
2943 * To ensure that all vCPU threads have observed the new counter
2944 * value before returning, we use SMR. Ordering is important here:
2945 * the VMM enters an SMR read section before loading the counter
2946 * and after updating the pm_active bit set. Thus, pm_active is
2947 * a superset of active readers, and any reader that has observed
2948 * the goal has observed the new counter value.
2950 atomic_add_long(&pmap->pm_eptgen, 1);
2952 goal = smr_advance(pmap->pm_eptsmr);
2955 * Force the vcpu to exit and trap back into the hypervisor.
2957 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2958 ipi_selected(pmap->pm_active, ipinum);
2962 * Ensure that all active vCPUs will observe the new generation counter
2963 * value before executing any more guest instructions.
2965 smr_wait(pmap->pm_eptsmr, goal);
2969 pmap_invalidate_cpu_mask(pmap_t pmap)
2971 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2975 pmap_invalidate_preipi_pcid(pmap_t pmap)
2981 cpuid = PCPU_GET(cpuid);
2982 if (pmap != PCPU_GET(curpmap))
2983 cpuid = 0xffffffff; /* An impossible value */
2987 pmap->pm_pcids[i].pm_gen = 0;
2991 * The fence is between stores to pm_gen and the read of the
2992 * pm_active mask. We need to ensure that it is impossible
2993 * for us to miss the bit update in pm_active and
2994 * simultaneously observe a non-zero pm_gen in
2995 * pmap_activate_sw(), otherwise TLB update is missed.
2996 * Without the fence, IA32 allows such an outcome. Note that
2997 * pm_active is updated by a locked operation, which provides
2998 * the reciprocal fence.
3000 atomic_thread_fence_seq_cst();
3004 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
3009 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t))
3011 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
3012 pmap_invalidate_preipi_nopcid);
3016 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
3017 const bool invpcid_works1)
3019 struct invpcid_descr d;
3020 uint64_t kcr3, ucr3;
3025 * Because pm_pcid is recalculated on a context switch, we
3026 * must ensure there is no preemption, not just pinning.
3027 * Otherwise, we might use a stale value below.
3029 CRITICAL_ASSERT(curthread);
3032 * No need to do anything with user page tables invalidation
3033 * if there is no user page table, or invalidation is deferred
3034 * until the return to userspace. ucr3_load_mask is stable
3035 * because we have preemption disabled.
3037 if (pmap->pm_ucr3 == PMAP_NO_CR3 ||
3038 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3041 cpuid = PCPU_GET(cpuid);
3043 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3044 if (invpcid_works1) {
3045 d.pcid = pcid | PMAP_PCID_USER_PT;
3048 invpcid(&d, INVPCID_ADDR);
3050 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3051 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3052 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3057 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
3059 pmap_invalidate_page_pcid_cb(pmap, va, true);
3063 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
3065 pmap_invalidate_page_pcid_cb(pmap, va, false);
3069 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
3073 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t))
3075 if (pmap_pcid_enabled)
3076 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
3077 pmap_invalidate_page_pcid_noinvpcid_cb);
3078 return (pmap_invalidate_page_nopcid_cb);
3082 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
3083 vm_offset_t addr2 __unused)
3085 if (pmap == kernel_pmap) {
3087 } else if (pmap == PCPU_GET(curpmap)) {
3089 pmap_invalidate_page_cb(pmap, va);
3094 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3096 if (pmap_type_guest(pmap)) {
3097 pmap_invalidate_ept(pmap);
3101 KASSERT(pmap->pm_type == PT_X86,
3102 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
3104 pmap_invalidate_preipi(pmap);
3105 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
3106 pmap_invalidate_page_curcpu_cb);
3109 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
3110 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
3113 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3114 const bool invpcid_works1)
3116 struct invpcid_descr d;
3117 uint64_t kcr3, ucr3;
3121 CRITICAL_ASSERT(curthread);
3123 if (pmap != PCPU_GET(curpmap) ||
3124 pmap->pm_ucr3 == PMAP_NO_CR3 ||
3125 PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK)
3128 cpuid = PCPU_GET(cpuid);
3130 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3131 if (invpcid_works1) {
3132 d.pcid = pcid | PMAP_PCID_USER_PT;
3134 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
3135 invpcid(&d, INVPCID_ADDR);
3137 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3138 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3139 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3144 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
3147 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
3151 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
3154 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
3158 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
3159 vm_offset_t eva __unused)
3163 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
3166 if (pmap_pcid_enabled)
3167 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
3168 pmap_invalidate_range_pcid_noinvpcid_cb);
3169 return (pmap_invalidate_range_nopcid_cb);
3173 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3177 if (pmap == kernel_pmap) {
3178 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3180 } else if (pmap == PCPU_GET(curpmap)) {
3181 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3183 pmap_invalidate_range_cb(pmap, sva, eva);
3188 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3190 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
3191 pmap_invalidate_all(pmap);
3195 if (pmap_type_guest(pmap)) {
3196 pmap_invalidate_ept(pmap);
3200 KASSERT(pmap->pm_type == PT_X86,
3201 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3203 pmap_invalidate_preipi(pmap);
3204 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
3205 pmap_invalidate_range_curcpu_cb);
3209 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
3211 struct invpcid_descr d;
3216 if (pmap == kernel_pmap) {
3217 if (invpcid_works1) {
3218 bzero(&d, sizeof(d));
3219 invpcid(&d, INVPCID_CTXGLOB);
3223 } else if (pmap == PCPU_GET(curpmap)) {
3224 CRITICAL_ASSERT(curthread);
3225 cpuid = PCPU_GET(cpuid);
3227 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3228 if (invpcid_works1) {
3232 invpcid(&d, INVPCID_CTX);
3234 kcr3 = pmap->pm_cr3 | pcid;
3237 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3238 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3243 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
3245 pmap_invalidate_all_pcid_cb(pmap, true);
3249 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
3251 pmap_invalidate_all_pcid_cb(pmap, false);
3255 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
3257 if (pmap == kernel_pmap)
3259 else if (pmap == PCPU_GET(curpmap))
3263 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t))
3265 if (pmap_pcid_enabled)
3266 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
3267 pmap_invalidate_all_pcid_noinvpcid_cb);
3268 return (pmap_invalidate_all_nopcid_cb);
3272 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3273 vm_offset_t addr2 __unused)
3275 pmap_invalidate_all_cb(pmap);
3279 pmap_invalidate_all(pmap_t pmap)
3281 if (pmap_type_guest(pmap)) {
3282 pmap_invalidate_ept(pmap);
3286 KASSERT(pmap->pm_type == PT_X86,
3287 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3289 pmap_invalidate_preipi(pmap);
3290 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3291 pmap_invalidate_all_curcpu_cb);
3295 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3296 vm_offset_t addr2 __unused)
3302 pmap_invalidate_cache(void)
3305 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3309 cpuset_t invalidate; /* processors that invalidate their TLB */
3314 u_int store; /* processor that updates the PDE */
3318 pmap_update_pde_action(void *arg)
3320 struct pde_action *act = arg;
3322 if (act->store == PCPU_GET(cpuid))
3323 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3327 pmap_update_pde_teardown(void *arg)
3329 struct pde_action *act = arg;
3331 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3332 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3336 * Change the page size for the specified virtual address in a way that
3337 * prevents any possibility of the TLB ever having two entries that map the
3338 * same virtual address using different page sizes. This is the recommended
3339 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3340 * machine check exception for a TLB state that is improperly diagnosed as a
3344 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3346 struct pde_action act;
3347 cpuset_t active, other_cpus;
3351 cpuid = PCPU_GET(cpuid);
3352 other_cpus = all_cpus;
3353 CPU_CLR(cpuid, &other_cpus);
3354 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3357 active = pmap->pm_active;
3359 if (CPU_OVERLAP(&active, &other_cpus)) {
3361 act.invalidate = active;
3365 act.newpde = newpde;
3366 CPU_SET(cpuid, &active);
3367 smp_rendezvous_cpus(active,
3368 smp_no_rendezvous_barrier, pmap_update_pde_action,
3369 pmap_update_pde_teardown, &act);
3371 pmap_update_pde_store(pmap, pde, newpde);
3372 if (CPU_ISSET(cpuid, &active))
3373 pmap_update_pde_invalidate(pmap, va, newpde);
3379 * Normal, non-SMP, invalidation functions.
3382 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3384 struct invpcid_descr d;
3385 uint64_t kcr3, ucr3;
3388 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3392 KASSERT(pmap->pm_type == PT_X86,
3393 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3395 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3397 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3398 pmap->pm_ucr3 != PMAP_NO_CR3) {
3400 pcid = pmap->pm_pcids[0].pm_pcid;
3401 if (invpcid_works) {
3402 d.pcid = pcid | PMAP_PCID_USER_PT;
3405 invpcid(&d, INVPCID_ADDR);
3407 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3408 ucr3 = pmap->pm_ucr3 | pcid |
3409 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3410 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3414 } else if (pmap_pcid_enabled)
3415 pmap->pm_pcids[0].pm_gen = 0;
3419 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3421 struct invpcid_descr d;
3423 uint64_t kcr3, ucr3;
3425 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3429 KASSERT(pmap->pm_type == PT_X86,
3430 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3432 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3433 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3435 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3436 pmap->pm_ucr3 != PMAP_NO_CR3) {
3438 if (invpcid_works) {
3439 d.pcid = pmap->pm_pcids[0].pm_pcid |
3443 for (; d.addr < eva; d.addr += PAGE_SIZE)
3444 invpcid(&d, INVPCID_ADDR);
3446 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3447 pm_pcid | CR3_PCID_SAVE;
3448 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3449 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3450 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3454 } else if (pmap_pcid_enabled) {
3455 pmap->pm_pcids[0].pm_gen = 0;
3460 pmap_invalidate_all(pmap_t pmap)
3462 struct invpcid_descr d;
3463 uint64_t kcr3, ucr3;
3465 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3469 KASSERT(pmap->pm_type == PT_X86,
3470 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3472 if (pmap == kernel_pmap) {
3473 if (pmap_pcid_enabled && invpcid_works) {
3474 bzero(&d, sizeof(d));
3475 invpcid(&d, INVPCID_CTXGLOB);
3479 } else if (pmap == PCPU_GET(curpmap)) {
3480 if (pmap_pcid_enabled) {
3482 if (invpcid_works) {
3483 d.pcid = pmap->pm_pcids[0].pm_pcid;
3486 invpcid(&d, INVPCID_CTX);
3487 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3488 d.pcid |= PMAP_PCID_USER_PT;
3489 invpcid(&d, INVPCID_CTX);
3492 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3493 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3494 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3495 0].pm_pcid | PMAP_PCID_USER_PT;
3496 pmap_pti_pcid_invalidate(ucr3, kcr3);
3504 } else if (pmap_pcid_enabled) {
3505 pmap->pm_pcids[0].pm_gen = 0;
3510 pmap_invalidate_cache(void)
3517 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3520 pmap_update_pde_store(pmap, pde, newpde);
3521 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3522 pmap_update_pde_invalidate(pmap, va, newpde);
3524 pmap->pm_pcids[0].pm_gen = 0;
3529 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3533 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3534 * by a promotion that did not invalidate the 512 4KB page mappings
3535 * that might exist in the TLB. Consequently, at this point, the TLB
3536 * may hold both 4KB and 2MB page mappings for the address range [va,
3537 * va + NBPDR). Therefore, the entire range must be invalidated here.
3538 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3539 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3540 * single INVLPG suffices to invalidate the 2MB page mapping from the
3543 if ((pde & PG_PROMOTED) != 0)
3544 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3546 pmap_invalidate_page(pmap, va);
3549 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3550 (vm_offset_t sva, vm_offset_t eva))
3553 if ((cpu_feature & CPUID_SS) != 0)
3554 return (pmap_invalidate_cache_range_selfsnoop);
3555 if ((cpu_feature & CPUID_CLFSH) != 0)
3556 return (pmap_force_invalidate_cache_range);
3557 return (pmap_invalidate_cache_range_all);
3560 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3563 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3566 KASSERT((sva & PAGE_MASK) == 0,
3567 ("pmap_invalidate_cache_range: sva not page-aligned"));
3568 KASSERT((eva & PAGE_MASK) == 0,
3569 ("pmap_invalidate_cache_range: eva not page-aligned"));
3573 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3576 pmap_invalidate_cache_range_check_align(sva, eva);
3580 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3583 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3586 * XXX: Some CPUs fault, hang, or trash the local APIC
3587 * registers if we use CLFLUSH on the local APIC range. The
3588 * local APIC is always uncached, so we don't need to flush
3589 * for that range anyway.
3591 if (pmap_kextract(sva) == lapic_paddr)
3594 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3596 * Do per-cache line flush. Use a locked
3597 * instruction to insure that previous stores are
3598 * included in the write-back. The processor
3599 * propagates flush to other processors in the cache
3602 atomic_thread_fence_seq_cst();
3603 for (; sva < eva; sva += cpu_clflush_line_size)
3605 atomic_thread_fence_seq_cst();
3608 * Writes are ordered by CLFLUSH on Intel CPUs.
3610 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3612 for (; sva < eva; sva += cpu_clflush_line_size)
3614 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3620 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3623 pmap_invalidate_cache_range_check_align(sva, eva);
3624 pmap_invalidate_cache();
3628 * Remove the specified set of pages from the data and instruction caches.
3630 * In contrast to pmap_invalidate_cache_range(), this function does not
3631 * rely on the CPU's self-snoop feature, because it is intended for use
3632 * when moving pages into a different cache domain.
3635 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3637 vm_offset_t daddr, eva;
3641 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3642 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3643 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3644 pmap_invalidate_cache();
3647 atomic_thread_fence_seq_cst();
3648 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3650 for (i = 0; i < count; i++) {
3651 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3652 eva = daddr + PAGE_SIZE;
3653 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3661 atomic_thread_fence_seq_cst();
3662 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3668 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3671 pmap_invalidate_cache_range_check_align(sva, eva);
3673 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3674 pmap_force_invalidate_cache_range(sva, eva);
3678 /* See comment in pmap_force_invalidate_cache_range(). */
3679 if (pmap_kextract(sva) == lapic_paddr)
3682 atomic_thread_fence_seq_cst();
3683 for (; sva < eva; sva += cpu_clflush_line_size)
3685 atomic_thread_fence_seq_cst();
3689 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3693 int error, pte_bits;
3695 KASSERT((spa & PAGE_MASK) == 0,
3696 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3697 KASSERT((epa & PAGE_MASK) == 0,
3698 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3700 if (spa < dmaplimit) {
3701 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3703 if (dmaplimit >= epa)
3708 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3710 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3712 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3713 pte = vtopte(vaddr);
3714 for (; spa < epa; spa += PAGE_SIZE) {
3716 pte_store(pte, spa | pte_bits);
3718 /* XXXKIB atomic inside flush_cache_range are excessive */
3719 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3722 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3726 * Routine: pmap_extract
3728 * Extract the physical page address associated
3729 * with the given map/virtual_address pair.
3732 pmap_extract(pmap_t pmap, vm_offset_t va)
3736 pt_entry_t *pte, PG_V;
3740 PG_V = pmap_valid_bit(pmap);
3742 pdpe = pmap_pdpe(pmap, va);
3743 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3744 if ((*pdpe & PG_PS) != 0)
3745 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3747 pde = pmap_pdpe_to_pde(pdpe, va);
3748 if ((*pde & PG_V) != 0) {
3749 if ((*pde & PG_PS) != 0) {
3750 pa = (*pde & PG_PS_FRAME) |
3753 pte = pmap_pde_to_pte(pde, va);
3754 pa = (*pte & PG_FRAME) |
3765 * Routine: pmap_extract_and_hold
3767 * Atomically extract and hold the physical page
3768 * with the given pmap and virtual address pair
3769 * if that mapping permits the given protection.
3772 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3774 pdp_entry_t pdpe, *pdpep;
3775 pd_entry_t pde, *pdep;
3776 pt_entry_t pte, PG_RW, PG_V;
3780 PG_RW = pmap_rw_bit(pmap);
3781 PG_V = pmap_valid_bit(pmap);
3784 pdpep = pmap_pdpe(pmap, va);
3785 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3787 if ((pdpe & PG_PS) != 0) {
3788 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3790 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3794 pdep = pmap_pdpe_to_pde(pdpep, va);
3795 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3797 if ((pde & PG_PS) != 0) {
3798 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3800 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3804 pte = *pmap_pde_to_pte(pdep, va);
3805 if ((pte & PG_V) == 0 ||
3806 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3808 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3811 if (m != NULL && !vm_page_wire_mapped(m))
3819 pmap_kextract(vm_offset_t va)
3824 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3825 pa = DMAP_TO_PHYS(va);
3826 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3827 pa = pmap_large_map_kextract(va);
3831 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3834 * Beware of a concurrent promotion that changes the
3835 * PDE at this point! For example, vtopte() must not
3836 * be used to access the PTE because it would use the
3837 * new PDE. It is, however, safe to use the old PDE
3838 * because the page table page is preserved by the
3841 pa = *pmap_pde_to_pte(&pde, va);
3842 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3848 /***************************************************
3849 * Low level mapping routines.....
3850 ***************************************************/
3853 * Add a wired page to the kva.
3854 * Note: not SMP coherent.
3857 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3862 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3865 static __inline void
3866 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3872 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3873 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3877 * Remove a page from the kernel pagetables.
3878 * Note: not SMP coherent.
3881 pmap_kremove(vm_offset_t va)
3890 * Used to map a range of physical addresses into kernel
3891 * virtual address space.
3893 * The value passed in '*virt' is a suggested virtual address for
3894 * the mapping. Architectures which can support a direct-mapped
3895 * physical to virtual region can return the appropriate address
3896 * within that region, leaving '*virt' unchanged. Other
3897 * architectures should map the pages starting at '*virt' and
3898 * update '*virt' with the first usable address after the mapped
3902 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3904 return PHYS_TO_DMAP(start);
3908 * Add a list of wired pages to the kva
3909 * this routine is only used for temporary
3910 * kernel mappings that do not need to have
3911 * page modification or references recorded.
3912 * Note that old mappings are simply written
3913 * over. The page *must* be wired.
3914 * Note: SMP coherent. Uses a ranged shootdown IPI.
3917 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3919 pt_entry_t *endpte, oldpte, pa, *pte;
3925 endpte = pte + count;
3926 while (pte < endpte) {
3928 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3929 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3930 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3932 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3936 if (__predict_false((oldpte & X86_PG_V) != 0))
3937 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3942 * This routine tears out page mappings from the
3943 * kernel -- it is meant only for temporary mappings.
3944 * Note: SMP coherent. Uses a ranged shootdown IPI.
3947 pmap_qremove(vm_offset_t sva, int count)
3952 while (count-- > 0) {
3953 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3957 pmap_invalidate_range(kernel_pmap, sva, va);
3960 /***************************************************
3961 * Page table page management routines.....
3962 ***************************************************/
3964 * Schedule the specified unused page table page to be freed. Specifically,
3965 * add the page to the specified list of pages that will be released to the
3966 * physical memory manager after the TLB has been updated.
3968 static __inline void
3969 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3970 boolean_t set_PG_ZERO)
3974 m->flags |= PG_ZERO;
3976 m->flags &= ~PG_ZERO;
3977 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3981 * Inserts the specified page table page into the specified pmap's collection
3982 * of idle page table pages. Each of a pmap's page table pages is responsible
3983 * for mapping a distinct range of virtual addresses. The pmap's collection is
3984 * ordered by this virtual address range.
3986 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3989 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3992 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3993 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3994 return (vm_radix_insert(&pmap->pm_root, mpte));
3998 * Removes the page table page mapping the specified virtual address from the
3999 * specified pmap's collection of idle page table pages, and returns it.
4000 * Otherwise, returns NULL if there is no page table page corresponding to the
4001 * specified virtual address.
4003 static __inline vm_page_t
4004 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
4007 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4008 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
4012 * Decrements a page table page's reference count, which is used to record the
4013 * number of valid page table entries within the page. If the reference count
4014 * drops to zero, then the page table page is unmapped. Returns TRUE if the
4015 * page table page was unmapped and FALSE otherwise.
4017 static inline boolean_t
4018 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4022 if (m->ref_count == 0) {
4023 _pmap_unwire_ptp(pmap, va, m, free);
4030 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
4036 vm_page_t pdpg, pdppg, pml4pg;
4038 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4041 * unmap the page table page
4043 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
4045 MPASS(pmap_is_la57(pmap));
4046 pml5 = pmap_pml5e(pmap, va);
4048 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
4049 pml5 = pmap_pml5e_u(pmap, va);
4052 } else if (m->pindex >= NUPDE + NUPDPE) {
4054 pml4 = pmap_pml4e(pmap, va);
4056 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4057 va <= VM_MAXUSER_ADDRESS) {
4058 pml4 = pmap_pml4e_u(pmap, va);
4061 } else if (m->pindex >= NUPDE) {
4063 pdp = pmap_pdpe(pmap, va);
4067 pd = pmap_pde(pmap, va);
4070 if (m->pindex < NUPDE) {
4071 /* We just released a PT, unhold the matching PD */
4072 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
4073 pmap_unwire_ptp(pmap, va, pdpg, free);
4074 } else if (m->pindex < NUPDE + NUPDPE) {
4075 /* We just released a PD, unhold the matching PDP */
4076 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
4077 pmap_unwire_ptp(pmap, va, pdppg, free);
4078 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
4079 /* We just released a PDP, unhold the matching PML4 */
4080 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
4081 pmap_unwire_ptp(pmap, va, pml4pg, free);
4084 pmap_pt_page_count_adj(pmap, -1);
4087 * Put page on a list so that it is released after
4088 * *ALL* TLB shootdown is done
4090 pmap_add_delayed_free_list(m, free, TRUE);
4094 * After removing a page table entry, this routine is used to
4095 * conditionally free the page, and manage the reference count.
4098 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
4099 struct spglist *free)
4103 if (va >= VM_MAXUSER_ADDRESS)
4105 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
4106 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
4107 return (pmap_unwire_ptp(pmap, va, mpte, free));
4111 * Release a page table page reference after a failed attempt to create a
4115 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
4117 struct spglist free;
4120 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4122 * Although "va" was never mapped, paging-structure caches
4123 * could nonetheless have entries that refer to the freed
4124 * page table pages. Invalidate those entries.
4126 pmap_invalidate_page(pmap, va);
4127 vm_page_free_pages_toq(&free, true);
4132 pmap_pinit0(pmap_t pmap)
4138 PMAP_LOCK_INIT(pmap);
4139 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
4140 pmap->pm_pmltopu = NULL;
4141 pmap->pm_cr3 = kernel_pmap->pm_cr3;
4142 /* hack to keep pmap_pti_pcid_invalidate() alive */
4143 pmap->pm_ucr3 = PMAP_NO_CR3;
4144 pmap->pm_root.rt_root = 0;
4145 CPU_ZERO(&pmap->pm_active);
4146 TAILQ_INIT(&pmap->pm_pvchunk);
4147 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4148 pmap->pm_flags = pmap_flags;
4150 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
4151 pmap->pm_pcids[i].pm_gen = 1;
4153 pmap_activate_boot(pmap);
4158 p->p_md.md_flags |= P_MD_KPTI;
4161 pmap_thread_init_invl_gen(td);
4163 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4164 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
4165 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
4171 pmap_pinit_pml4(vm_page_t pml4pg)
4173 pml4_entry_t *pm_pml4;
4176 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
4178 /* Wire in kernel global address entries. */
4179 for (i = 0; i < NKPML4E; i++) {
4180 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
4184 for (i = 0; i < NKASANPML4E; i++) {
4185 pm_pml4[KASANPML4I + i] = (KASANPDPphys + ptoa(i)) | X86_PG_RW |
4189 for (i = 0; i < ndmpdpphys; i++) {
4190 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
4194 /* install self-referential address mapping entry(s) */
4195 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
4196 X86_PG_A | X86_PG_M;
4198 /* install large map entries if configured */
4199 for (i = 0; i < lm_ents; i++)
4200 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4204 pmap_pinit_pml5(vm_page_t pml5pg)
4206 pml5_entry_t *pm_pml5;
4208 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4211 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4212 * entering all existing kernel mappings into level 5 table.
4214 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4215 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4216 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4219 * Install self-referential address mapping entry.
4221 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4222 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4223 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4227 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4229 pml4_entry_t *pm_pml4u;
4232 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4233 for (i = 0; i < NPML4EPG; i++)
4234 pm_pml4u[i] = pti_pml4[i];
4238 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4240 pml5_entry_t *pm_pml5u;
4242 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4245 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4246 * table, entering all kernel mappings needed for usermode
4247 * into level 5 table.
4249 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4250 pmap_kextract((vm_offset_t)pti_pml4) |
4251 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4252 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4255 /* Allocate a page table page and do related bookkeeping */
4257 pmap_alloc_pt_page(pmap_t pmap, vm_pindex_t pindex, int flags)
4261 m = vm_page_alloc(NULL, pindex, flags | VM_ALLOC_NOOBJ);
4262 if (__predict_false(m == NULL))
4265 pmap_pt_page_count_adj(pmap, 1);
4267 if ((flags & VM_ALLOC_ZERO) != 0 && (m->flags & PG_ZERO) == 0)
4274 pmap_free_pt_page(pmap_t pmap, vm_page_t m, bool zerofilled)
4277 * This function assumes the page will need to be unwired,
4278 * even though the counterpart allocation in pmap_alloc_pt_page()
4279 * doesn't enforce VM_ALLOC_WIRED. However, all current uses
4280 * of pmap_free_pt_page() require unwiring. The case in which
4281 * a PT page doesn't require unwiring because its ref_count has
4282 * naturally reached 0 is handled through _pmap_unwire_ptp().
4284 vm_page_unwire_noq(m);
4286 vm_page_free_zero(m);
4290 pmap_pt_page_count_adj(pmap, -1);
4294 * Initialize a preallocated and zeroed pmap structure,
4295 * such as one in a vmspace structure.
4298 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4300 vm_page_t pmltop_pg, pmltop_pgu;
4301 vm_paddr_t pmltop_phys;
4305 * allocate the page directory page
4307 pmltop_pg = pmap_alloc_pt_page(NULL, 0, VM_ALLOC_NORMAL |
4308 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4310 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4311 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4314 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4315 pmap->pm_pcids[i].pm_gen = 0;
4317 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4318 pmap->pm_ucr3 = PMAP_NO_CR3;
4319 pmap->pm_pmltopu = NULL;
4321 pmap->pm_type = pm_type;
4324 * Do not install the host kernel mappings in the nested page
4325 * tables. These mappings are meaningless in the guest physical
4327 * Install minimal kernel mappings in PTI case.
4331 pmap->pm_cr3 = pmltop_phys;
4332 if (pmap_is_la57(pmap))
4333 pmap_pinit_pml5(pmltop_pg);
4335 pmap_pinit_pml4(pmltop_pg);
4336 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4337 pmltop_pgu = pmap_alloc_pt_page(NULL, 0,
4338 VM_ALLOC_WIRED | VM_ALLOC_NORMAL |
4340 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4341 VM_PAGE_TO_PHYS(pmltop_pgu));
4342 if (pmap_is_la57(pmap))
4343 pmap_pinit_pml5_pti(pmltop_pgu);
4345 pmap_pinit_pml4_pti(pmltop_pgu);
4346 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4348 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4349 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4350 pkru_free_range, pmap, M_NOWAIT);
4355 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4359 pmap->pm_root.rt_root = 0;
4360 CPU_ZERO(&pmap->pm_active);
4361 TAILQ_INIT(&pmap->pm_pvchunk);
4362 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4363 pmap->pm_flags = flags;
4364 pmap->pm_eptgen = 0;
4370 pmap_pinit(pmap_t pmap)
4373 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4377 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4380 struct spglist free;
4382 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4383 if (mpg->ref_count != 0)
4386 _pmap_unwire_ptp(pmap, va, mpg, &free);
4387 pmap_invalidate_page(pmap, va);
4388 vm_page_free_pages_toq(&free, true);
4391 static pml4_entry_t *
4392 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4395 vm_pindex_t pml5index;
4402 if (!pmap_is_la57(pmap))
4403 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4405 PG_V = pmap_valid_bit(pmap);
4406 pml5index = pmap_pml5e_index(va);
4407 pml5 = &pmap->pm_pmltop[pml5index];
4408 if ((*pml5 & PG_V) == 0) {
4409 if (pmap_allocpte_nosleep(pmap, pmap_pml5e_pindex(va), lockp,
4416 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4417 pml4 = &pml4[pmap_pml4e_index(va)];
4418 if ((*pml4 & PG_V) == 0) {
4419 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4420 if (allocated && !addref)
4421 pml4pg->ref_count--;
4422 else if (!allocated && addref)
4423 pml4pg->ref_count++;
4428 static pdp_entry_t *
4429 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4438 PG_V = pmap_valid_bit(pmap);
4440 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4444 if ((*pml4 & PG_V) == 0) {
4445 /* Have to allocate a new pdp, recurse */
4446 if (pmap_allocpte_nosleep(pmap, pmap_pml4e_pindex(va), lockp,
4448 if (pmap_is_la57(pmap))
4449 pmap_allocpte_free_unref(pmap, va,
4450 pmap_pml5e(pmap, va));
4457 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4458 pdp = &pdp[pmap_pdpe_index(va)];
4459 if ((*pdp & PG_V) == 0) {
4460 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4461 if (allocated && !addref)
4463 else if (!allocated && addref)
4470 * The ptepindexes, i.e. page indices, of the page table pages encountered
4471 * while translating virtual address va are defined as follows:
4472 * - for the page table page (last level),
4473 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4474 * in other words, it is just the index of the PDE that maps the page
4476 * - for the page directory page,
4477 * ptepindex = NUPDE (number of userland PD entries) +
4478 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4479 * i.e. index of PDPE is put after the last index of PDE,
4480 * - for the page directory pointer page,
4481 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4483 * i.e. index of pml4e is put after the last index of PDPE,
4484 * - for the PML4 page (if LA57 mode is enabled),
4485 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4486 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4487 * i.e. index of pml5e is put after the last index of PML4E.
4489 * Define an order on the paging entries, where all entries of the
4490 * same height are put together, then heights are put from deepest to
4491 * root. Then ptexpindex is the sequential number of the
4492 * corresponding paging entry in this order.
4494 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4495 * LA57 paging structures even in LA48 paging mode. Moreover, the
4496 * ptepindexes are calculated as if the paging structures were 5-level
4497 * regardless of the actual mode of operation.
4499 * The root page at PML4/PML5 does not participate in this indexing scheme,
4500 * since it is statically allocated by pmap_pinit() and not by pmap_allocpte().
4503 pmap_allocpte_nosleep(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4506 vm_pindex_t pml5index, pml4index;
4507 pml5_entry_t *pml5, *pml5u;
4508 pml4_entry_t *pml4, *pml4u;
4512 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4514 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4516 PG_A = pmap_accessed_bit(pmap);
4517 PG_M = pmap_modified_bit(pmap);
4518 PG_V = pmap_valid_bit(pmap);
4519 PG_RW = pmap_rw_bit(pmap);
4522 * Allocate a page table page.
4524 m = pmap_alloc_pt_page(pmap, ptepindex,
4525 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4530 * Map the pagetable page into the process address space, if
4531 * it isn't already there.
4533 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4534 MPASS(pmap_is_la57(pmap));
4536 pml5index = pmap_pml5e_index(va);
4537 pml5 = &pmap->pm_pmltop[pml5index];
4538 KASSERT((*pml5 & PG_V) == 0,
4539 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4540 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4542 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4543 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4546 pml5u = &pmap->pm_pmltopu[pml5index];
4547 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4550 } else if (ptepindex >= NUPDE + NUPDPE) {
4551 pml4index = pmap_pml4e_index(va);
4552 /* Wire up a new PDPE page */
4553 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4555 pmap_free_pt_page(pmap, m, true);
4558 KASSERT((*pml4 & PG_V) == 0,
4559 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4560 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4562 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4563 pml4index < NUPML4E) {
4565 * PTI: Make all user-space mappings in the
4566 * kernel-mode page table no-execute so that
4567 * we detect any programming errors that leave
4568 * the kernel-mode page table active on return
4571 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4574 pml4u = &pmap->pm_pmltopu[pml4index];
4575 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4578 } else if (ptepindex >= NUPDE) {
4579 /* Wire up a new PDE page */
4580 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4582 pmap_free_pt_page(pmap, m, true);
4585 KASSERT((*pdp & PG_V) == 0,
4586 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4587 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4589 /* Wire up a new PTE page */
4590 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4592 pmap_free_pt_page(pmap, m, true);
4595 if ((*pdp & PG_V) == 0) {
4596 /* Have to allocate a new pd, recurse */
4597 if (pmap_allocpte_nosleep(pmap, pmap_pdpe_pindex(va),
4598 lockp, va) == NULL) {
4599 pmap_allocpte_free_unref(pmap, va,
4600 pmap_pml4e(pmap, va));
4601 pmap_free_pt_page(pmap, m, true);
4605 /* Add reference to the pd page */
4606 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4609 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4611 /* Now we know where the page directory page is */
4612 pd = &pd[pmap_pde_index(va)];
4613 KASSERT((*pd & PG_V) == 0,
4614 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4615 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4622 * This routine is called if the desired page table page does not exist.
4624 * If page table page allocation fails, this routine may sleep before
4625 * returning NULL. It sleeps only if a lock pointer was given. Sleep
4626 * occurs right before returning to the caller. This way, we never
4627 * drop pmap lock to sleep while a page table page has ref_count == 0,
4628 * which prevents the page from being freed under us.
4631 pmap_allocpte_alloc(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4636 m = pmap_allocpte_nosleep(pmap, ptepindex, lockp, va);
4637 if (m == NULL && lockp != NULL) {
4638 RELEASE_PV_LIST_LOCK(lockp);
4640 PMAP_ASSERT_NOT_IN_DI();
4648 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4649 struct rwlock **lockp)
4651 pdp_entry_t *pdpe, PG_V;
4654 vm_pindex_t pdpindex;
4656 PG_V = pmap_valid_bit(pmap);
4659 pdpe = pmap_pdpe(pmap, va);
4660 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4661 pde = pmap_pdpe_to_pde(pdpe, va);
4662 if (va < VM_MAXUSER_ADDRESS) {
4663 /* Add a reference to the pd page. */
4664 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4668 } else if (va < VM_MAXUSER_ADDRESS) {
4669 /* Allocate a pd page. */
4670 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4671 pdpg = pmap_allocpte_alloc(pmap, NUPDE + pdpindex, lockp, va);
4678 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4679 pde = &pde[pmap_pde_index(va)];
4681 panic("pmap_alloc_pde: missing page table page for va %#lx",
4688 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4690 vm_pindex_t ptepindex;
4691 pd_entry_t *pd, PG_V;
4694 PG_V = pmap_valid_bit(pmap);
4697 * Calculate pagetable page index
4699 ptepindex = pmap_pde_pindex(va);
4702 * Get the page directory entry
4704 pd = pmap_pde(pmap, va);
4707 * This supports switching from a 2MB page to a
4710 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4711 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4713 * Invalidation of the 2MB page mapping may have caused
4714 * the deallocation of the underlying PD page.
4721 * If the page table page is mapped, we just increment the
4722 * hold count, and activate it.
4724 if (pd != NULL && (*pd & PG_V) != 0) {
4725 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4729 * Here if the pte page isn't mapped, or if it has been
4732 m = pmap_allocpte_alloc(pmap, ptepindex, lockp, va);
4733 if (m == NULL && lockp != NULL)
4739 /***************************************************
4740 * Pmap allocation/deallocation routines.
4741 ***************************************************/
4744 * Release any resources held by the given physical map.
4745 * Called when a pmap initialized by pmap_pinit is being released.
4746 * Should only be called if the map contains no valid mappings.
4749 pmap_release(pmap_t pmap)
4754 KASSERT(pmap->pm_stats.resident_count == 0,
4755 ("pmap_release: pmap %p resident count %ld != 0",
4756 pmap, pmap->pm_stats.resident_count));
4757 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4758 ("pmap_release: pmap %p has reserved page table page(s)",
4760 KASSERT(CPU_EMPTY(&pmap->pm_active),
4761 ("releasing active pmap %p", pmap));
4763 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4765 if (pmap_is_la57(pmap)) {
4766 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4767 pmap->pm_pmltop[PML5PML5I] = 0;
4769 for (i = 0; i < NKPML4E; i++) /* KVA */
4770 pmap->pm_pmltop[KPML4BASE + i] = 0;
4772 for (i = 0; i < NKASANPML4E; i++) /* KASAN shadow map */
4773 pmap->pm_pmltop[KASANPML4I + i] = 0;
4775 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4776 pmap->pm_pmltop[DMPML4I + i] = 0;
4777 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4778 for (i = 0; i < lm_ents; i++) /* Large Map */
4779 pmap->pm_pmltop[LMSPML4I + i] = 0;
4782 pmap_free_pt_page(NULL, m, true);
4784 if (pmap->pm_pmltopu != NULL) {
4785 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4787 pmap_free_pt_page(NULL, m, false);
4789 if (pmap->pm_type == PT_X86 &&
4790 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4791 rangeset_fini(&pmap->pm_pkru);
4795 kvm_size(SYSCTL_HANDLER_ARGS)
4797 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4799 return sysctl_handle_long(oidp, &ksize, 0, req);
4801 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4802 0, 0, kvm_size, "LU",
4806 kvm_free(SYSCTL_HANDLER_ARGS)
4808 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4810 return sysctl_handle_long(oidp, &kfree, 0, req);
4812 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4813 0, 0, kvm_free, "LU",
4814 "Amount of KVM free");
4817 * Allocate physical memory for the vm_page array and map it into KVA,
4818 * attempting to back the vm_pages with domain-local memory.
4821 pmap_page_array_startup(long pages)
4824 pd_entry_t *pde, newpdir;
4825 vm_offset_t va, start, end;
4830 vm_page_array_size = pages;
4832 start = VM_MIN_KERNEL_ADDRESS;
4833 end = start + pages * sizeof(struct vm_page);
4834 for (va = start; va < end; va += NBPDR) {
4835 pfn = first_page + (va - start) / sizeof(struct vm_page);
4836 domain = vm_phys_domain(ptoa(pfn));
4837 pdpe = pmap_pdpe(kernel_pmap, va);
4838 if ((*pdpe & X86_PG_V) == 0) {
4839 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4841 pagezero((void *)PHYS_TO_DMAP(pa));
4842 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4843 X86_PG_A | X86_PG_M);
4845 pde = pmap_pdpe_to_pde(pdpe, va);
4846 if ((*pde & X86_PG_V) != 0)
4847 panic("Unexpected pde");
4848 pa = vm_phys_early_alloc(domain, NBPDR);
4849 for (i = 0; i < NPDEPG; i++)
4850 dump_add_page(pa + i * PAGE_SIZE);
4851 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4852 X86_PG_M | PG_PS | pg_g | pg_nx);
4853 pde_store(pde, newpdir);
4855 vm_page_array = (vm_page_t)start;
4859 * grow the number of kernel page table entries, if needed
4862 pmap_growkernel(vm_offset_t addr)
4866 pd_entry_t *pde, newpdir;
4869 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4872 * Return if "addr" is within the range of kernel page table pages
4873 * that were preallocated during pmap bootstrap. Moreover, leave
4874 * "kernel_vm_end" and the kernel page table as they were.
4876 * The correctness of this action is based on the following
4877 * argument: vm_map_insert() allocates contiguous ranges of the
4878 * kernel virtual address space. It calls this function if a range
4879 * ends after "kernel_vm_end". If the kernel is mapped between
4880 * "kernel_vm_end" and "addr", then the range cannot begin at
4881 * "kernel_vm_end". In fact, its beginning address cannot be less
4882 * than the kernel. Thus, there is no immediate need to allocate
4883 * any new kernel page table pages between "kernel_vm_end" and
4886 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4889 addr = roundup2(addr, NBPDR);
4890 if (addr - 1 >= vm_map_max(kernel_map))
4891 addr = vm_map_max(kernel_map);
4892 if (kernel_vm_end < addr)
4893 kasan_shadow_map(kernel_vm_end, addr - kernel_vm_end);
4894 while (kernel_vm_end < addr) {
4895 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4896 if ((*pdpe & X86_PG_V) == 0) {
4897 /* We need a new PDP entry */
4898 nkpg = pmap_alloc_pt_page(kernel_pmap,
4899 kernel_vm_end >> PDPSHIFT, VM_ALLOC_WIRED |
4900 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
4902 panic("pmap_growkernel: no memory to grow kernel");
4903 paddr = VM_PAGE_TO_PHYS(nkpg);
4904 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4905 X86_PG_A | X86_PG_M);
4906 continue; /* try again */
4908 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4909 if ((*pde & X86_PG_V) != 0) {
4910 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4911 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4912 kernel_vm_end = vm_map_max(kernel_map);
4918 nkpg = pmap_alloc_pt_page(kernel_pmap,
4919 pmap_pde_pindex(kernel_vm_end), VM_ALLOC_WIRED |
4920 VM_ALLOC_INTERRUPT | VM_ALLOC_ZERO);
4922 panic("pmap_growkernel: no memory to grow kernel");
4923 paddr = VM_PAGE_TO_PHYS(nkpg);
4924 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4925 pde_store(pde, newpdir);
4927 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4928 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4929 kernel_vm_end = vm_map_max(kernel_map);
4935 /***************************************************
4936 * page management routines.
4937 ***************************************************/
4939 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4940 CTASSERT(_NPCM == 3);
4941 CTASSERT(_NPCPV == 168);
4943 static __inline struct pv_chunk *
4944 pv_to_chunk(pv_entry_t pv)
4947 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4950 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4952 #define PC_FREE0 0xfffffffffffffffful
4953 #define PC_FREE1 0xfffffffffffffffful
4954 #define PC_FREE2 0x000000fffffffffful
4956 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4960 static COUNTER_U64_DEFINE_EARLY(pc_chunk_count);
4961 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD,
4962 &pc_chunk_count, "Current number of pv entry cnunks");
4964 static COUNTER_U64_DEFINE_EARLY(pc_chunk_allocs);
4965 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD,
4966 &pc_chunk_allocs, "Total number of pv entry chunks allocated");
4968 static COUNTER_U64_DEFINE_EARLY(pc_chunk_frees);
4969 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD,
4970 &pc_chunk_frees, "Total number of pv entry chunks freed");
4972 static COUNTER_U64_DEFINE_EARLY(pc_chunk_tryfail);
4973 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD,
4975 "Number of failed attempts to get a pv entry chunk page");
4977 static COUNTER_U64_DEFINE_EARLY(pv_entry_frees);
4978 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD,
4979 &pv_entry_frees, "Total number of pv entries freed");
4981 static COUNTER_U64_DEFINE_EARLY(pv_entry_allocs);
4982 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD,
4983 &pv_entry_allocs, "Total number of pv entries allocated");
4985 static COUNTER_U64_DEFINE_EARLY(pv_entry_count);
4986 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD,
4987 &pv_entry_count, "Current number of pv entries");
4989 static COUNTER_U64_DEFINE_EARLY(pv_entry_spare);
4990 SYSCTL_COUNTER_U64(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD,
4991 &pv_entry_spare, "Current number of spare pv entries");
4995 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
5000 pmap_invalidate_all(pmap);
5001 if (pmap != locked_pmap)
5004 pmap_delayed_invl_finish();
5008 * We are in a serious low memory condition. Resort to
5009 * drastic measures to free some pages so we can allocate
5010 * another pv entry chunk.
5012 * Returns NULL if PV entries were reclaimed from the specified pmap.
5014 * We do not, however, unmap 2mpages because subsequent accesses will
5015 * allocate per-page pv entries until repromotion occurs, thereby
5016 * exacerbating the shortage of free pv entries.
5019 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
5021 struct pv_chunks_list *pvc;
5022 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
5023 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
5024 struct md_page *pvh;
5026 pmap_t next_pmap, pmap;
5027 pt_entry_t *pte, tpte;
5028 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5032 struct spglist free;
5034 int bit, field, freed;
5035 bool start_di, restart;
5037 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
5038 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
5041 PG_G = PG_A = PG_M = PG_RW = 0;
5043 bzero(&pc_marker_b, sizeof(pc_marker_b));
5044 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
5045 pc_marker = (struct pv_chunk *)&pc_marker_b;
5046 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
5049 * A delayed invalidation block should already be active if
5050 * pmap_advise() or pmap_remove() called this function by way
5051 * of pmap_demote_pde_locked().
5053 start_di = pmap_not_in_di();
5055 pvc = &pv_chunks[domain];
5056 mtx_lock(&pvc->pvc_lock);
5057 pvc->active_reclaims++;
5058 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
5059 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
5060 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
5061 SLIST_EMPTY(&free)) {
5062 next_pmap = pc->pc_pmap;
5063 if (next_pmap == NULL) {
5065 * The next chunk is a marker. However, it is
5066 * not our marker, so active_reclaims must be
5067 * > 1. Consequently, the next_chunk code
5068 * will not rotate the pv_chunks list.
5072 mtx_unlock(&pvc->pvc_lock);
5075 * A pv_chunk can only be removed from the pc_lru list
5076 * when both pc_chunks_mutex is owned and the
5077 * corresponding pmap is locked.
5079 if (pmap != next_pmap) {
5081 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
5084 /* Avoid deadlock and lock recursion. */
5085 if (pmap > locked_pmap) {
5086 RELEASE_PV_LIST_LOCK(lockp);
5089 pmap_delayed_invl_start();
5090 mtx_lock(&pvc->pvc_lock);
5092 } else if (pmap != locked_pmap) {
5093 if (PMAP_TRYLOCK(pmap)) {
5095 pmap_delayed_invl_start();
5096 mtx_lock(&pvc->pvc_lock);
5099 pmap = NULL; /* pmap is not locked */
5100 mtx_lock(&pvc->pvc_lock);
5101 pc = TAILQ_NEXT(pc_marker, pc_lru);
5103 pc->pc_pmap != next_pmap)
5107 } else if (start_di)
5108 pmap_delayed_invl_start();
5109 PG_G = pmap_global_bit(pmap);
5110 PG_A = pmap_accessed_bit(pmap);
5111 PG_M = pmap_modified_bit(pmap);
5112 PG_RW = pmap_rw_bit(pmap);
5118 * Destroy every non-wired, 4 KB page mapping in the chunk.
5121 for (field = 0; field < _NPCM; field++) {
5122 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
5123 inuse != 0; inuse &= ~(1UL << bit)) {
5125 pv = &pc->pc_pventry[field * 64 + bit];
5127 pde = pmap_pde(pmap, va);
5128 if ((*pde & PG_PS) != 0)
5130 pte = pmap_pde_to_pte(pde, va);
5131 if ((*pte & PG_W) != 0)
5133 tpte = pte_load_clear(pte);
5134 if ((tpte & PG_G) != 0)
5135 pmap_invalidate_page(pmap, va);
5136 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
5137 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5139 if ((tpte & PG_A) != 0)
5140 vm_page_aflag_set(m, PGA_REFERENCED);
5141 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5142 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5144 if (TAILQ_EMPTY(&m->md.pv_list) &&
5145 (m->flags & PG_FICTITIOUS) == 0) {
5146 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5147 if (TAILQ_EMPTY(&pvh->pv_list)) {
5148 vm_page_aflag_clear(m,
5152 pmap_delayed_invl_page(m);
5153 pc->pc_map[field] |= 1UL << bit;
5154 pmap_unuse_pt(pmap, va, *pde, &free);
5159 mtx_lock(&pvc->pvc_lock);
5162 /* Every freed mapping is for a 4 KB page. */
5163 pmap_resident_count_adj(pmap, -freed);
5164 PV_STAT(counter_u64_add(pv_entry_frees, freed));
5165 PV_STAT(counter_u64_add(pv_entry_spare, freed));
5166 PV_STAT(counter_u64_add(pv_entry_count, -freed));
5167 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5168 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
5169 pc->pc_map[2] == PC_FREE2) {
5170 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5171 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5172 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5173 /* Entire chunk is free; return it. */
5174 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5175 dump_drop_page(m_pc->phys_addr);
5176 mtx_lock(&pvc->pvc_lock);
5177 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5180 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5181 mtx_lock(&pvc->pvc_lock);
5182 /* One freed pv entry in locked_pmap is sufficient. */
5183 if (pmap == locked_pmap)
5186 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5187 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
5188 if (pvc->active_reclaims == 1 && pmap != NULL) {
5190 * Rotate the pv chunks list so that we do not
5191 * scan the same pv chunks that could not be
5192 * freed (because they contained a wired
5193 * and/or superpage mapping) on every
5194 * invocation of reclaim_pv_chunk().
5196 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
5197 MPASS(pc->pc_pmap != NULL);
5198 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5199 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5203 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
5204 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
5205 pvc->active_reclaims--;
5206 mtx_unlock(&pvc->pvc_lock);
5207 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
5208 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
5209 m_pc = SLIST_FIRST(&free);
5210 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
5211 /* Recycle a freed page table page. */
5212 m_pc->ref_count = 1;
5214 vm_page_free_pages_toq(&free, true);
5219 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
5224 domain = PCPU_GET(domain);
5225 for (i = 0; i < vm_ndomains; i++) {
5226 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
5229 domain = (domain + 1) % vm_ndomains;
5236 * free the pv_entry back to the free list
5239 free_pv_entry(pmap_t pmap, pv_entry_t pv)
5241 struct pv_chunk *pc;
5242 int idx, field, bit;
5244 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5245 PV_STAT(counter_u64_add(pv_entry_frees, 1));
5246 PV_STAT(counter_u64_add(pv_entry_spare, 1));
5247 PV_STAT(counter_u64_add(pv_entry_count, -1));
5248 pc = pv_to_chunk(pv);
5249 idx = pv - &pc->pc_pventry[0];
5252 pc->pc_map[field] |= 1ul << bit;
5253 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5254 pc->pc_map[2] != PC_FREE2) {
5255 /* 98% of the time, pc is already at the head of the list. */
5256 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5257 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5258 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5262 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5267 free_pv_chunk_dequeued(struct pv_chunk *pc)
5271 PV_STAT(counter_u64_add(pv_entry_spare, -_NPCPV));
5272 PV_STAT(counter_u64_add(pc_chunk_count, -1));
5273 PV_STAT(counter_u64_add(pc_chunk_frees, 1));
5274 counter_u64_add(pv_page_count, -1);
5275 /* entire chunk is free, return it */
5276 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5277 dump_drop_page(m->phys_addr);
5278 vm_page_unwire_noq(m);
5283 free_pv_chunk(struct pv_chunk *pc)
5285 struct pv_chunks_list *pvc;
5287 pvc = &pv_chunks[pc_to_domain(pc)];
5288 mtx_lock(&pvc->pvc_lock);
5289 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5290 mtx_unlock(&pvc->pvc_lock);
5291 free_pv_chunk_dequeued(pc);
5295 free_pv_chunk_batch(struct pv_chunklist *batch)
5297 struct pv_chunks_list *pvc;
5298 struct pv_chunk *pc, *npc;
5301 for (i = 0; i < vm_ndomains; i++) {
5302 if (TAILQ_EMPTY(&batch[i]))
5304 pvc = &pv_chunks[i];
5305 mtx_lock(&pvc->pvc_lock);
5306 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5307 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5309 mtx_unlock(&pvc->pvc_lock);
5312 for (i = 0; i < vm_ndomains; i++) {
5313 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5314 free_pv_chunk_dequeued(pc);
5320 * Returns a new PV entry, allocating a new PV chunk from the system when
5321 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5322 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5325 * The given PV list lock may be released.
5328 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5330 struct pv_chunks_list *pvc;
5333 struct pv_chunk *pc;
5336 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5337 PV_STAT(counter_u64_add(pv_entry_allocs, 1));
5339 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5341 for (field = 0; field < _NPCM; field++) {
5342 if (pc->pc_map[field]) {
5343 bit = bsfq(pc->pc_map[field]);
5347 if (field < _NPCM) {
5348 pv = &pc->pc_pventry[field * 64 + bit];
5349 pc->pc_map[field] &= ~(1ul << bit);
5350 /* If this was the last item, move it to tail */
5351 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5352 pc->pc_map[2] == 0) {
5353 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5354 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5357 PV_STAT(counter_u64_add(pv_entry_count, 1));
5358 PV_STAT(counter_u64_add(pv_entry_spare, -1));
5362 /* No free items, allocate another chunk */
5363 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5366 if (lockp == NULL) {
5367 PV_STAT(counter_u64_add(pc_chunk_tryfail, 1));
5370 m = reclaim_pv_chunk(pmap, lockp);
5374 counter_u64_add(pv_page_count, 1);
5375 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5376 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5377 dump_add_page(m->phys_addr);
5378 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5380 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5381 pc->pc_map[1] = PC_FREE1;
5382 pc->pc_map[2] = PC_FREE2;
5383 pvc = &pv_chunks[vm_page_domain(m)];
5384 mtx_lock(&pvc->pvc_lock);
5385 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5386 mtx_unlock(&pvc->pvc_lock);
5387 pv = &pc->pc_pventry[0];
5388 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5389 PV_STAT(counter_u64_add(pv_entry_count, 1));
5390 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV - 1));
5395 * Returns the number of one bits within the given PV chunk map.
5397 * The erratas for Intel processors state that "POPCNT Instruction May
5398 * Take Longer to Execute Than Expected". It is believed that the
5399 * issue is the spurious dependency on the destination register.
5400 * Provide a hint to the register rename logic that the destination
5401 * value is overwritten, by clearing it, as suggested in the
5402 * optimization manual. It should be cheap for unaffected processors
5405 * Reference numbers for erratas are
5406 * 4th Gen Core: HSD146
5407 * 5th Gen Core: BDM85
5408 * 6th Gen Core: SKL029
5411 popcnt_pc_map_pq(uint64_t *map)
5415 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5416 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5417 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5418 : "=&r" (result), "=&r" (tmp)
5419 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5424 * Ensure that the number of spare PV entries in the specified pmap meets or
5425 * exceeds the given count, "needed".
5427 * The given PV list lock may be released.
5430 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5432 struct pv_chunks_list *pvc;
5433 struct pch new_tail[PMAP_MEMDOM];
5434 struct pv_chunk *pc;
5439 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5440 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5443 * Newly allocated PV chunks must be stored in a private list until
5444 * the required number of PV chunks have been allocated. Otherwise,
5445 * reclaim_pv_chunk() could recycle one of these chunks. In
5446 * contrast, these chunks must be added to the pmap upon allocation.
5448 for (i = 0; i < PMAP_MEMDOM; i++)
5449 TAILQ_INIT(&new_tail[i]);
5452 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5454 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5455 bit_count((bitstr_t *)pc->pc_map, 0,
5456 sizeof(pc->pc_map) * NBBY, &free);
5459 free = popcnt_pc_map_pq(pc->pc_map);
5463 if (avail >= needed)
5466 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5467 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5470 m = reclaim_pv_chunk(pmap, lockp);
5475 counter_u64_add(pv_page_count, 1);
5476 PV_STAT(counter_u64_add(pc_chunk_count, 1));
5477 PV_STAT(counter_u64_add(pc_chunk_allocs, 1));
5478 dump_add_page(m->phys_addr);
5479 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5481 pc->pc_map[0] = PC_FREE0;
5482 pc->pc_map[1] = PC_FREE1;
5483 pc->pc_map[2] = PC_FREE2;
5484 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5485 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru);
5486 PV_STAT(counter_u64_add(pv_entry_spare, _NPCPV));
5489 * The reclaim might have freed a chunk from the current pmap.
5490 * If that chunk contained available entries, we need to
5491 * re-count the number of available entries.
5496 for (i = 0; i < vm_ndomains; i++) {
5497 if (TAILQ_EMPTY(&new_tail[i]))
5499 pvc = &pv_chunks[i];
5500 mtx_lock(&pvc->pvc_lock);
5501 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5502 mtx_unlock(&pvc->pvc_lock);
5507 * First find and then remove the pv entry for the specified pmap and virtual
5508 * address from the specified pv list. Returns the pv entry if found and NULL
5509 * otherwise. This operation can be performed on pv lists for either 4KB or
5510 * 2MB page mappings.
5512 static __inline pv_entry_t
5513 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5517 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5518 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5519 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5528 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5529 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5530 * entries for each of the 4KB page mappings.
5533 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5534 struct rwlock **lockp)
5536 struct md_page *pvh;
5537 struct pv_chunk *pc;
5539 vm_offset_t va_last;
5543 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5544 KASSERT((pa & PDRMASK) == 0,
5545 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5546 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5549 * Transfer the 2mpage's pv entry for this mapping to the first
5550 * page's pv list. Once this transfer begins, the pv list lock
5551 * must not be released until the last pv entry is reinstantiated.
5553 pvh = pa_to_pvh(pa);
5554 va = trunc_2mpage(va);
5555 pv = pmap_pvh_remove(pvh, pmap, va);
5556 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5557 m = PHYS_TO_VM_PAGE(pa);
5558 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5560 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5561 PV_STAT(counter_u64_add(pv_entry_allocs, NPTEPG - 1));
5562 va_last = va + NBPDR - PAGE_SIZE;
5564 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5565 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5566 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5567 for (field = 0; field < _NPCM; field++) {
5568 while (pc->pc_map[field]) {
5569 bit = bsfq(pc->pc_map[field]);
5570 pc->pc_map[field] &= ~(1ul << bit);
5571 pv = &pc->pc_pventry[field * 64 + bit];
5575 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5576 ("pmap_pv_demote_pde: page %p is not managed", m));
5577 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5583 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5584 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5587 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5588 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5589 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5591 PV_STAT(counter_u64_add(pv_entry_count, NPTEPG - 1));
5592 PV_STAT(counter_u64_add(pv_entry_spare, -(NPTEPG - 1)));
5595 #if VM_NRESERVLEVEL > 0
5597 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5598 * replace the many pv entries for the 4KB page mappings by a single pv entry
5599 * for the 2MB page mapping.
5602 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5603 struct rwlock **lockp)
5605 struct md_page *pvh;
5607 vm_offset_t va_last;
5610 KASSERT((pa & PDRMASK) == 0,
5611 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5612 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5615 * Transfer the first page's pv entry for this mapping to the 2mpage's
5616 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5617 * a transfer avoids the possibility that get_pv_entry() calls
5618 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5619 * mappings that is being promoted.
5621 m = PHYS_TO_VM_PAGE(pa);
5622 va = trunc_2mpage(va);
5623 pv = pmap_pvh_remove(&m->md, pmap, va);
5624 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5625 pvh = pa_to_pvh(pa);
5626 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5628 /* Free the remaining NPTEPG - 1 pv entries. */
5629 va_last = va + NBPDR - PAGE_SIZE;
5633 pmap_pvh_free(&m->md, pmap, va);
5634 } while (va < va_last);
5636 #endif /* VM_NRESERVLEVEL > 0 */
5639 * First find and then destroy the pv entry for the specified pmap and virtual
5640 * address. This operation can be performed on pv lists for either 4KB or 2MB
5644 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5648 pv = pmap_pvh_remove(pvh, pmap, va);
5649 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5650 free_pv_entry(pmap, pv);
5654 * Conditionally create the PV entry for a 4KB page mapping if the required
5655 * memory can be allocated without resorting to reclamation.
5658 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5659 struct rwlock **lockp)
5663 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5664 /* Pass NULL instead of the lock pointer to disable reclamation. */
5665 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5667 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5668 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5676 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5677 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5678 * false if the PV entry cannot be allocated without resorting to reclamation.
5681 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5682 struct rwlock **lockp)
5684 struct md_page *pvh;
5688 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5689 /* Pass NULL instead of the lock pointer to disable reclamation. */
5690 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5691 NULL : lockp)) == NULL)
5694 pa = pde & PG_PS_FRAME;
5695 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5696 pvh = pa_to_pvh(pa);
5697 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5703 * Fills a page table page with mappings to consecutive physical pages.
5706 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5710 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5712 newpte += PAGE_SIZE;
5717 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5718 * mapping is invalidated.
5721 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5723 struct rwlock *lock;
5727 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5734 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5738 pt_entry_t *xpte, *ypte;
5740 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5741 xpte++, newpte += PAGE_SIZE) {
5742 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5743 printf("pmap_demote_pde: xpte %zd and newpte map "
5744 "different pages: found %#lx, expected %#lx\n",
5745 xpte - firstpte, *xpte, newpte);
5746 printf("page table dump\n");
5747 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5748 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5753 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5754 ("pmap_demote_pde: firstpte and newpte map different physical"
5761 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5762 pd_entry_t oldpde, struct rwlock **lockp)
5764 struct spglist free;
5768 sva = trunc_2mpage(va);
5769 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5770 if ((oldpde & pmap_global_bit(pmap)) == 0)
5771 pmap_invalidate_pde_page(pmap, sva, oldpde);
5772 vm_page_free_pages_toq(&free, true);
5773 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5778 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5779 struct rwlock **lockp)
5781 pd_entry_t newpde, oldpde;
5782 pt_entry_t *firstpte, newpte;
5783 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5789 PG_A = pmap_accessed_bit(pmap);
5790 PG_G = pmap_global_bit(pmap);
5791 PG_M = pmap_modified_bit(pmap);
5792 PG_RW = pmap_rw_bit(pmap);
5793 PG_V = pmap_valid_bit(pmap);
5794 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5795 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5798 in_kernel = va >= VM_MAXUSER_ADDRESS;
5800 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5801 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5804 * Invalidate the 2MB page mapping and return "failure" if the
5805 * mapping was never accessed.
5807 if ((oldpde & PG_A) == 0) {
5808 KASSERT((oldpde & PG_W) == 0,
5809 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5810 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5814 mpte = pmap_remove_pt_page(pmap, va);
5816 KASSERT((oldpde & PG_W) == 0,
5817 ("pmap_demote_pde: page table page for a wired mapping"
5821 * If the page table page is missing and the mapping
5822 * is for a kernel address, the mapping must belong to
5823 * the direct map. Page table pages are preallocated
5824 * for every other part of the kernel address space,
5825 * so the direct map region is the only part of the
5826 * kernel address space that must be handled here.
5828 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5829 va < DMAP_MAX_ADDRESS),
5830 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5833 * If the 2MB page mapping belongs to the direct map
5834 * region of the kernel's address space, then the page
5835 * allocation request specifies the highest possible
5836 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5837 * priority is normal.
5839 mpte = pmap_alloc_pt_page(pmap, pmap_pde_pindex(va),
5840 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5844 * If the allocation of the new page table page fails,
5845 * invalidate the 2MB page mapping and return "failure".
5848 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5853 mpte->ref_count = NPTEPG;
5855 mptepa = VM_PAGE_TO_PHYS(mpte);
5856 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5857 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5858 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5859 ("pmap_demote_pde: oldpde is missing PG_M"));
5860 newpte = oldpde & ~PG_PS;
5861 newpte = pmap_swap_pat(pmap, newpte);
5864 * If the page table page is not leftover from an earlier promotion,
5867 if (mpte->valid == 0)
5868 pmap_fill_ptp(firstpte, newpte);
5870 pmap_demote_pde_check(firstpte, newpte);
5873 * If the mapping has changed attributes, update the page table
5876 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5877 pmap_fill_ptp(firstpte, newpte);
5880 * The spare PV entries must be reserved prior to demoting the
5881 * mapping, that is, prior to changing the PDE. Otherwise, the state
5882 * of the PDE and the PV lists will be inconsistent, which can result
5883 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5884 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5885 * PV entry for the 2MB page mapping that is being demoted.
5887 if ((oldpde & PG_MANAGED) != 0)
5888 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5891 * Demote the mapping. This pmap is locked. The old PDE has
5892 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5893 * set. Thus, there is no danger of a race with another
5894 * processor changing the setting of PG_A and/or PG_M between
5895 * the read above and the store below.
5897 if (workaround_erratum383)
5898 pmap_update_pde(pmap, va, pde, newpde);
5900 pde_store(pde, newpde);
5903 * Invalidate a stale recursive mapping of the page table page.
5906 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5909 * Demote the PV entry.
5911 if ((oldpde & PG_MANAGED) != 0)
5912 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5914 counter_u64_add(pmap_pde_demotions, 1);
5915 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5921 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5924 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5930 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5931 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5932 mpte = pmap_remove_pt_page(pmap, va);
5934 panic("pmap_remove_kernel_pde: Missing pt page.");
5936 mptepa = VM_PAGE_TO_PHYS(mpte);
5937 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5940 * If this page table page was unmapped by a promotion, then it
5941 * contains valid mappings. Zero it to invalidate those mappings.
5943 if (mpte->valid != 0)
5944 pagezero((void *)PHYS_TO_DMAP(mptepa));
5947 * Demote the mapping.
5949 if (workaround_erratum383)
5950 pmap_update_pde(pmap, va, pde, newpde);
5952 pde_store(pde, newpde);
5955 * Invalidate a stale recursive mapping of the page table page.
5957 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5961 * pmap_remove_pde: do the things to unmap a superpage in a process
5964 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5965 struct spglist *free, struct rwlock **lockp)
5967 struct md_page *pvh;
5969 vm_offset_t eva, va;
5971 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5973 PG_G = pmap_global_bit(pmap);
5974 PG_A = pmap_accessed_bit(pmap);
5975 PG_M = pmap_modified_bit(pmap);
5976 PG_RW = pmap_rw_bit(pmap);
5978 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5979 KASSERT((sva & PDRMASK) == 0,
5980 ("pmap_remove_pde: sva is not 2mpage aligned"));
5981 oldpde = pte_load_clear(pdq);
5983 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5984 if ((oldpde & PG_G) != 0)
5985 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5986 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
5987 if (oldpde & PG_MANAGED) {
5988 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5989 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5990 pmap_pvh_free(pvh, pmap, sva);
5992 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5993 va < eva; va += PAGE_SIZE, m++) {
5994 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5997 vm_page_aflag_set(m, PGA_REFERENCED);
5998 if (TAILQ_EMPTY(&m->md.pv_list) &&
5999 TAILQ_EMPTY(&pvh->pv_list))
6000 vm_page_aflag_clear(m, PGA_WRITEABLE);
6001 pmap_delayed_invl_page(m);
6004 if (pmap == kernel_pmap) {
6005 pmap_remove_kernel_pde(pmap, pdq, sva);
6007 mpte = pmap_remove_pt_page(pmap, sva);
6009 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6010 ("pmap_remove_pde: pte page not promoted"));
6011 pmap_resident_count_adj(pmap, -1);
6012 KASSERT(mpte->ref_count == NPTEPG,
6013 ("pmap_remove_pde: pte page ref count error"));
6014 mpte->ref_count = 0;
6015 pmap_add_delayed_free_list(mpte, free, FALSE);
6018 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
6022 * pmap_remove_pte: do the things to unmap a page in a process
6025 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
6026 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
6028 struct md_page *pvh;
6029 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
6032 PG_A = pmap_accessed_bit(pmap);
6033 PG_M = pmap_modified_bit(pmap);
6034 PG_RW = pmap_rw_bit(pmap);
6036 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6037 oldpte = pte_load_clear(ptq);
6039 pmap->pm_stats.wired_count -= 1;
6040 pmap_resident_count_adj(pmap, -1);
6041 if (oldpte & PG_MANAGED) {
6042 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
6043 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6046 vm_page_aflag_set(m, PGA_REFERENCED);
6047 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
6048 pmap_pvh_free(&m->md, pmap, va);
6049 if (TAILQ_EMPTY(&m->md.pv_list) &&
6050 (m->flags & PG_FICTITIOUS) == 0) {
6051 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6052 if (TAILQ_EMPTY(&pvh->pv_list))
6053 vm_page_aflag_clear(m, PGA_WRITEABLE);
6055 pmap_delayed_invl_page(m);
6057 return (pmap_unuse_pt(pmap, va, ptepde, free));
6061 * Remove a single page from a process address space
6064 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
6065 struct spglist *free)
6067 struct rwlock *lock;
6068 pt_entry_t *pte, PG_V;
6070 PG_V = pmap_valid_bit(pmap);
6071 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6072 if ((*pde & PG_V) == 0)
6074 pte = pmap_pde_to_pte(pde, va);
6075 if ((*pte & PG_V) == 0)
6078 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
6081 pmap_invalidate_page(pmap, va);
6085 * Removes the specified range of addresses from the page table page.
6088 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
6089 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
6091 pt_entry_t PG_G, *pte;
6095 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6096 PG_G = pmap_global_bit(pmap);
6099 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
6103 pmap_invalidate_range(pmap, va, sva);
6108 if ((*pte & PG_G) == 0)
6112 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
6118 pmap_invalidate_range(pmap, va, sva);
6123 * Remove the given range of addresses from the specified map.
6125 * It is assumed that the start and end are properly
6126 * rounded to the page size.
6129 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6131 struct rwlock *lock;
6133 vm_offset_t va_next;
6134 pml5_entry_t *pml5e;
6135 pml4_entry_t *pml4e;
6137 pd_entry_t ptpaddr, *pde;
6138 pt_entry_t PG_G, PG_V;
6139 struct spglist free;
6142 PG_G = pmap_global_bit(pmap);
6143 PG_V = pmap_valid_bit(pmap);
6146 * Perform an unsynchronized read. This is, however, safe.
6148 if (pmap->pm_stats.resident_count == 0)
6154 pmap_delayed_invl_start();
6156 pmap_pkru_on_remove(pmap, sva, eva);
6159 * special handling of removing one page. a very
6160 * common operation and easy to short circuit some
6163 if (sva + PAGE_SIZE == eva) {
6164 pde = pmap_pde(pmap, sva);
6165 if (pde && (*pde & PG_PS) == 0) {
6166 pmap_remove_page(pmap, sva, pde, &free);
6172 for (; sva < eva; sva = va_next) {
6173 if (pmap->pm_stats.resident_count == 0)
6176 if (pmap_is_la57(pmap)) {
6177 pml5e = pmap_pml5e(pmap, sva);
6178 if ((*pml5e & PG_V) == 0) {
6179 va_next = (sva + NBPML5) & ~PML5MASK;
6184 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
6186 pml4e = pmap_pml4e(pmap, sva);
6188 if ((*pml4e & PG_V) == 0) {
6189 va_next = (sva + NBPML4) & ~PML4MASK;
6195 va_next = (sva + NBPDP) & ~PDPMASK;
6198 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6199 if ((*pdpe & PG_V) == 0)
6201 if ((*pdpe & PG_PS) != 0) {
6202 KASSERT(va_next <= eva,
6203 ("partial update of non-transparent 1G mapping "
6204 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6205 *pdpe, sva, eva, va_next));
6206 MPASS(pmap != kernel_pmap); /* XXXKIB */
6207 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
6210 pmap_resident_count_adj(pmap, -NBPDP / PAGE_SIZE);
6211 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
6212 pmap_unwire_ptp(pmap, sva, mt, &free);
6217 * Calculate index for next page table.
6219 va_next = (sva + NBPDR) & ~PDRMASK;
6223 pde = pmap_pdpe_to_pde(pdpe, sva);
6227 * Weed out invalid mappings.
6233 * Check for large page.
6235 if ((ptpaddr & PG_PS) != 0) {
6237 * Are we removing the entire large page? If not,
6238 * demote the mapping and fall through.
6240 if (sva + NBPDR == va_next && eva >= va_next) {
6242 * The TLB entry for a PG_G mapping is
6243 * invalidated by pmap_remove_pde().
6245 if ((ptpaddr & PG_G) == 0)
6247 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6249 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6251 /* The large page mapping was destroyed. */
6258 * Limit our scan to either the end of the va represented
6259 * by the current page table page, or to the end of the
6260 * range being removed.
6265 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6272 pmap_invalidate_all(pmap);
6274 pmap_delayed_invl_finish();
6275 vm_page_free_pages_toq(&free, true);
6279 * Routine: pmap_remove_all
6281 * Removes this physical page from
6282 * all physical maps in which it resides.
6283 * Reflects back modify bits to the pager.
6286 * Original versions of this routine were very
6287 * inefficient because they iteratively called
6288 * pmap_remove (slow...)
6292 pmap_remove_all(vm_page_t m)
6294 struct md_page *pvh;
6297 struct rwlock *lock;
6298 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6301 struct spglist free;
6302 int pvh_gen, md_gen;
6304 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6305 ("pmap_remove_all: page %p is not managed", m));
6307 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6308 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6309 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6312 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6314 if (!PMAP_TRYLOCK(pmap)) {
6315 pvh_gen = pvh->pv_gen;
6319 if (pvh_gen != pvh->pv_gen) {
6325 pde = pmap_pde(pmap, va);
6326 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6329 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6331 if (!PMAP_TRYLOCK(pmap)) {
6332 pvh_gen = pvh->pv_gen;
6333 md_gen = m->md.pv_gen;
6337 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6342 PG_A = pmap_accessed_bit(pmap);
6343 PG_M = pmap_modified_bit(pmap);
6344 PG_RW = pmap_rw_bit(pmap);
6345 pmap_resident_count_adj(pmap, -1);
6346 pde = pmap_pde(pmap, pv->pv_va);
6347 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6348 " a 2mpage in page %p's pv list", m));
6349 pte = pmap_pde_to_pte(pde, pv->pv_va);
6350 tpte = pte_load_clear(pte);
6352 pmap->pm_stats.wired_count--;
6354 vm_page_aflag_set(m, PGA_REFERENCED);
6357 * Update the vm_page_t clean and reference bits.
6359 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6361 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6362 pmap_invalidate_page(pmap, pv->pv_va);
6363 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6365 free_pv_entry(pmap, pv);
6368 vm_page_aflag_clear(m, PGA_WRITEABLE);
6370 pmap_delayed_invl_wait(m);
6371 vm_page_free_pages_toq(&free, true);
6375 * pmap_protect_pde: do the things to protect a 2mpage in a process
6378 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6380 pd_entry_t newpde, oldpde;
6382 boolean_t anychanged;
6383 pt_entry_t PG_G, PG_M, PG_RW;
6385 PG_G = pmap_global_bit(pmap);
6386 PG_M = pmap_modified_bit(pmap);
6387 PG_RW = pmap_rw_bit(pmap);
6389 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6390 KASSERT((sva & PDRMASK) == 0,
6391 ("pmap_protect_pde: sva is not 2mpage aligned"));
6394 oldpde = newpde = *pde;
6395 if ((prot & VM_PROT_WRITE) == 0) {
6396 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6397 (PG_MANAGED | PG_M | PG_RW)) {
6398 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6399 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6402 newpde &= ~(PG_RW | PG_M);
6404 if ((prot & VM_PROT_EXECUTE) == 0)
6406 if (newpde != oldpde) {
6408 * As an optimization to future operations on this PDE, clear
6409 * PG_PROMOTED. The impending invalidation will remove any
6410 * lingering 4KB page mappings from the TLB.
6412 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6414 if ((oldpde & PG_G) != 0)
6415 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6419 return (anychanged);
6423 * Set the physical protection on the
6424 * specified range of this map as requested.
6427 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6430 vm_offset_t va_next;
6431 pml4_entry_t *pml4e;
6433 pd_entry_t ptpaddr, *pde;
6434 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6435 pt_entry_t obits, pbits;
6436 boolean_t anychanged;
6438 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6439 if (prot == VM_PROT_NONE) {
6440 pmap_remove(pmap, sva, eva);
6444 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6445 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6448 PG_G = pmap_global_bit(pmap);
6449 PG_M = pmap_modified_bit(pmap);
6450 PG_V = pmap_valid_bit(pmap);
6451 PG_RW = pmap_rw_bit(pmap);
6455 * Although this function delays and batches the invalidation
6456 * of stale TLB entries, it does not need to call
6457 * pmap_delayed_invl_start() and
6458 * pmap_delayed_invl_finish(), because it does not
6459 * ordinarily destroy mappings. Stale TLB entries from
6460 * protection-only changes need only be invalidated before the
6461 * pmap lock is released, because protection-only changes do
6462 * not destroy PV entries. Even operations that iterate over
6463 * a physical page's PV list of mappings, like
6464 * pmap_remove_write(), acquire the pmap lock for each
6465 * mapping. Consequently, for protection-only changes, the
6466 * pmap lock suffices to synchronize both page table and TLB
6469 * This function only destroys a mapping if pmap_demote_pde()
6470 * fails. In that case, stale TLB entries are immediately
6475 for (; sva < eva; sva = va_next) {
6476 pml4e = pmap_pml4e(pmap, sva);
6477 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6478 va_next = (sva + NBPML4) & ~PML4MASK;
6484 va_next = (sva + NBPDP) & ~PDPMASK;
6487 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6488 if ((*pdpe & PG_V) == 0)
6490 if ((*pdpe & PG_PS) != 0) {
6491 KASSERT(va_next <= eva,
6492 ("partial update of non-transparent 1G mapping "
6493 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6494 *pdpe, sva, eva, va_next));
6496 obits = pbits = *pdpe;
6497 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6498 MPASS(pmap != kernel_pmap); /* XXXKIB */
6499 if ((prot & VM_PROT_WRITE) == 0)
6500 pbits &= ~(PG_RW | PG_M);
6501 if ((prot & VM_PROT_EXECUTE) == 0)
6504 if (pbits != obits) {
6505 if (!atomic_cmpset_long(pdpe, obits, pbits))
6506 /* PG_PS cannot be cleared under us, */
6513 va_next = (sva + NBPDR) & ~PDRMASK;
6517 pde = pmap_pdpe_to_pde(pdpe, sva);
6521 * Weed out invalid mappings.
6527 * Check for large page.
6529 if ((ptpaddr & PG_PS) != 0) {
6531 * Are we protecting the entire large page? If not,
6532 * demote the mapping and fall through.
6534 if (sva + NBPDR == va_next && eva >= va_next) {
6536 * The TLB entry for a PG_G mapping is
6537 * invalidated by pmap_protect_pde().
6539 if (pmap_protect_pde(pmap, pde, sva, prot))
6542 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6544 * The large page mapping was destroyed.
6553 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6556 obits = pbits = *pte;
6557 if ((pbits & PG_V) == 0)
6560 if ((prot & VM_PROT_WRITE) == 0) {
6561 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6562 (PG_MANAGED | PG_M | PG_RW)) {
6563 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6566 pbits &= ~(PG_RW | PG_M);
6568 if ((prot & VM_PROT_EXECUTE) == 0)
6571 if (pbits != obits) {
6572 if (!atomic_cmpset_long(pte, obits, pbits))
6575 pmap_invalidate_page(pmap, sva);
6582 pmap_invalidate_all(pmap);
6586 #if VM_NRESERVLEVEL > 0
6588 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6591 if (pmap->pm_type != PT_EPT)
6593 return ((pde & EPT_PG_EXECUTE) != 0);
6597 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6598 * single page table page (PTP) to a single 2MB page mapping. For promotion
6599 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6600 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6601 * identical characteristics.
6604 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6605 struct rwlock **lockp)
6608 pt_entry_t *firstpte, oldpte, pa, *pte;
6609 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6613 PG_A = pmap_accessed_bit(pmap);
6614 PG_G = pmap_global_bit(pmap);
6615 PG_M = pmap_modified_bit(pmap);
6616 PG_V = pmap_valid_bit(pmap);
6617 PG_RW = pmap_rw_bit(pmap);
6618 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6619 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6621 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6624 * Examine the first PTE in the specified PTP. Abort if this PTE is
6625 * either invalid, unused, or does not map the first 4KB physical page
6626 * within a 2MB page.
6628 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6631 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6632 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6634 counter_u64_add(pmap_pde_p_failures, 1);
6635 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6636 " in pmap %p", va, pmap);
6639 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6641 * When PG_M is already clear, PG_RW can be cleared without
6642 * a TLB invalidation.
6644 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6650 * Examine each of the other PTEs in the specified PTP. Abort if this
6651 * PTE maps an unexpected 4KB physical page or does not have identical
6652 * characteristics to the first PTE.
6654 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6655 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6658 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6659 counter_u64_add(pmap_pde_p_failures, 1);
6660 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6661 " in pmap %p", va, pmap);
6664 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6666 * When PG_M is already clear, PG_RW can be cleared
6667 * without a TLB invalidation.
6669 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6672 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6673 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6674 (va & ~PDRMASK), pmap);
6676 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6677 counter_u64_add(pmap_pde_p_failures, 1);
6678 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6679 " in pmap %p", va, pmap);
6686 * Save the page table page in its current state until the PDE
6687 * mapping the superpage is demoted by pmap_demote_pde() or
6688 * destroyed by pmap_remove_pde().
6690 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6691 KASSERT(mpte >= vm_page_array &&
6692 mpte < &vm_page_array[vm_page_array_size],
6693 ("pmap_promote_pde: page table page is out of range"));
6694 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6695 ("pmap_promote_pde: page table page's pindex is wrong"));
6696 if (pmap_insert_pt_page(pmap, mpte, true)) {
6697 counter_u64_add(pmap_pde_p_failures, 1);
6699 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6705 * Promote the pv entries.
6707 if ((newpde & PG_MANAGED) != 0)
6708 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6711 * Propagate the PAT index to its proper position.
6713 newpde = pmap_swap_pat(pmap, newpde);
6716 * Map the superpage.
6718 if (workaround_erratum383)
6719 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6721 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6723 counter_u64_add(pmap_pde_promotions, 1);
6724 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6725 " in pmap %p", va, pmap);
6727 #endif /* VM_NRESERVLEVEL > 0 */
6730 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6734 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6736 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6737 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6738 ("psind %d unexpected", psind));
6739 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6740 ("unaligned phys address %#lx newpte %#lx psind %d",
6741 newpte & PG_FRAME, newpte, psind));
6742 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6743 ("unaligned va %#lx psind %d", va, psind));
6744 KASSERT(va < VM_MAXUSER_ADDRESS,
6745 ("kernel mode non-transparent superpage")); /* XXXKIB */
6746 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6747 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6749 PG_V = pmap_valid_bit(pmap);
6752 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6753 return (KERN_PROTECTION_FAILURE);
6755 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6756 pten |= pmap_pkru_get(pmap, va);
6758 if (psind == 2) { /* 1G */
6759 pml4e = pmap_pml4e(pmap, va);
6760 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6761 mp = pmap_allocpte_alloc(pmap, pmap_pml4e_pindex(va),
6765 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6766 pdpe = &pdpe[pmap_pdpe_index(va)];
6768 MPASS(origpte == 0);
6770 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6771 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6773 if ((origpte & PG_V) == 0) {
6774 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6779 } else /* (psind == 1) */ { /* 2M */
6780 pde = pmap_pde(pmap, va);
6782 mp = pmap_allocpte_alloc(pmap, pmap_pdpe_pindex(va),
6786 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6787 pde = &pde[pmap_pde_index(va)];
6789 MPASS(origpte == 0);
6792 if ((origpte & PG_V) == 0) {
6793 pdpe = pmap_pdpe(pmap, va);
6794 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6795 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6801 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6802 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6803 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6804 va, psind == 2 ? "1G" : "2M", origpte, pten));
6805 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6806 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6807 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6808 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6809 if ((origpte & PG_V) == 0)
6810 pmap_resident_count_adj(pmap, pagesizes[psind] / PAGE_SIZE);
6812 return (KERN_SUCCESS);
6815 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6816 return (KERN_RESOURCE_SHORTAGE);
6824 * Insert the given physical page (p) at
6825 * the specified virtual address (v) in the
6826 * target physical map with the protection requested.
6828 * If specified, the page will be wired down, meaning
6829 * that the related pte can not be reclaimed.
6831 * NB: This is the only routine which MAY NOT lazy-evaluate
6832 * or lose information. That is, this routine must actually
6833 * insert this page into the given map NOW.
6835 * When destroying both a page table and PV entry, this function
6836 * performs the TLB invalidation before releasing the PV list
6837 * lock, so we do not need pmap_delayed_invl_page() calls here.
6840 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6841 u_int flags, int8_t psind)
6843 struct rwlock *lock;
6845 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6846 pt_entry_t newpte, origpte;
6853 PG_A = pmap_accessed_bit(pmap);
6854 PG_G = pmap_global_bit(pmap);
6855 PG_M = pmap_modified_bit(pmap);
6856 PG_V = pmap_valid_bit(pmap);
6857 PG_RW = pmap_rw_bit(pmap);
6859 va = trunc_page(va);
6860 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6861 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6862 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6864 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || !VA_IS_CLEANMAP(va),
6865 ("pmap_enter: managed mapping within the clean submap"));
6866 if ((m->oflags & VPO_UNMANAGED) == 0)
6867 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6868 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6869 ("pmap_enter: flags %u has reserved bits set", flags));
6870 pa = VM_PAGE_TO_PHYS(m);
6871 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6872 if ((flags & VM_PROT_WRITE) != 0)
6874 if ((prot & VM_PROT_WRITE) != 0)
6876 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6877 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6878 if ((prot & VM_PROT_EXECUTE) == 0)
6880 if ((flags & PMAP_ENTER_WIRED) != 0)
6882 if (va < VM_MAXUSER_ADDRESS)
6884 if (pmap == kernel_pmap)
6886 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6889 * Set modified bit gratuitously for writeable mappings if
6890 * the page is unmanaged. We do not want to take a fault
6891 * to do the dirty bit accounting for these mappings.
6893 if ((m->oflags & VPO_UNMANAGED) != 0) {
6894 if ((newpte & PG_RW) != 0)
6897 newpte |= PG_MANAGED;
6901 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6902 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6903 ("managed largepage va %#lx flags %#x", va, flags));
6904 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6909 /* Assert the required virtual and physical alignment. */
6910 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6911 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6912 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6918 * In the case that a page table page is not
6919 * resident, we are creating it here.
6922 pde = pmap_pde(pmap, va);
6923 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6924 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6925 pte = pmap_pde_to_pte(pde, va);
6926 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6927 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6930 } else if (va < VM_MAXUSER_ADDRESS) {
6932 * Here if the pte page isn't mapped, or if it has been
6935 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6936 mpte = pmap_allocpte_alloc(pmap, pmap_pde_pindex(va),
6937 nosleep ? NULL : &lock, va);
6938 if (mpte == NULL && nosleep) {
6939 rv = KERN_RESOURCE_SHORTAGE;
6944 panic("pmap_enter: invalid page directory va=%#lx", va);
6948 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6949 newpte |= pmap_pkru_get(pmap, va);
6952 * Is the specified virtual address already mapped?
6954 if ((origpte & PG_V) != 0) {
6956 * Wiring change, just update stats. We don't worry about
6957 * wiring PT pages as they remain resident as long as there
6958 * are valid mappings in them. Hence, if a user page is wired,
6959 * the PT page will be also.
6961 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6962 pmap->pm_stats.wired_count++;
6963 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6964 pmap->pm_stats.wired_count--;
6967 * Remove the extra PT page reference.
6971 KASSERT(mpte->ref_count > 0,
6972 ("pmap_enter: missing reference to page table page,"
6977 * Has the physical page changed?
6979 opa = origpte & PG_FRAME;
6982 * No, might be a protection or wiring change.
6984 if ((origpte & PG_MANAGED) != 0 &&
6985 (newpte & PG_RW) != 0)
6986 vm_page_aflag_set(m, PGA_WRITEABLE);
6987 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6993 * The physical page has changed. Temporarily invalidate
6994 * the mapping. This ensures that all threads sharing the
6995 * pmap keep a consistent view of the mapping, which is
6996 * necessary for the correct handling of COW faults. It
6997 * also permits reuse of the old mapping's PV entry,
6998 * avoiding an allocation.
7000 * For consistency, handle unmanaged mappings the same way.
7002 origpte = pte_load_clear(pte);
7003 KASSERT((origpte & PG_FRAME) == opa,
7004 ("pmap_enter: unexpected pa update for %#lx", va));
7005 if ((origpte & PG_MANAGED) != 0) {
7006 om = PHYS_TO_VM_PAGE(opa);
7009 * The pmap lock is sufficient to synchronize with
7010 * concurrent calls to pmap_page_test_mappings() and
7011 * pmap_ts_referenced().
7013 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7015 if ((origpte & PG_A) != 0) {
7016 pmap_invalidate_page(pmap, va);
7017 vm_page_aflag_set(om, PGA_REFERENCED);
7019 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
7020 pv = pmap_pvh_remove(&om->md, pmap, va);
7022 ("pmap_enter: no PV entry for %#lx", va));
7023 if ((newpte & PG_MANAGED) == 0)
7024 free_pv_entry(pmap, pv);
7025 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
7026 TAILQ_EMPTY(&om->md.pv_list) &&
7027 ((om->flags & PG_FICTITIOUS) != 0 ||
7028 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
7029 vm_page_aflag_clear(om, PGA_WRITEABLE);
7032 * Since this mapping is unmanaged, assume that PG_A
7035 pmap_invalidate_page(pmap, va);
7040 * Increment the counters.
7042 if ((newpte & PG_W) != 0)
7043 pmap->pm_stats.wired_count++;
7044 pmap_resident_count_adj(pmap, 1);
7048 * Enter on the PV list if part of our managed memory.
7050 if ((newpte & PG_MANAGED) != 0) {
7052 pv = get_pv_entry(pmap, &lock);
7055 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
7056 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7058 if ((newpte & PG_RW) != 0)
7059 vm_page_aflag_set(m, PGA_WRITEABLE);
7065 if ((origpte & PG_V) != 0) {
7067 origpte = pte_load_store(pte, newpte);
7068 KASSERT((origpte & PG_FRAME) == pa,
7069 ("pmap_enter: unexpected pa update for %#lx", va));
7070 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
7072 if ((origpte & PG_MANAGED) != 0)
7076 * Although the PTE may still have PG_RW set, TLB
7077 * invalidation may nonetheless be required because
7078 * the PTE no longer has PG_M set.
7080 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
7082 * This PTE change does not require TLB invalidation.
7086 if ((origpte & PG_A) != 0)
7087 pmap_invalidate_page(pmap, va);
7089 pte_store(pte, newpte);
7093 #if VM_NRESERVLEVEL > 0
7095 * If both the page table page and the reservation are fully
7096 * populated, then attempt promotion.
7098 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
7099 pmap_ps_enabled(pmap) &&
7100 (m->flags & PG_FICTITIOUS) == 0 &&
7101 vm_reserv_level_iffullpop(m) == 0)
7102 pmap_promote_pde(pmap, pde, va, &lock);
7114 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
7115 * if successful. Returns false if (1) a page table page cannot be allocated
7116 * without sleeping, (2) a mapping already exists at the specified virtual
7117 * address, or (3) a PV entry cannot be allocated without reclaiming another
7121 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
7122 struct rwlock **lockp)
7127 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7128 PG_V = pmap_valid_bit(pmap);
7129 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
7131 if ((m->oflags & VPO_UNMANAGED) == 0)
7132 newpde |= PG_MANAGED;
7133 if ((prot & VM_PROT_EXECUTE) == 0)
7135 if (va < VM_MAXUSER_ADDRESS)
7137 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
7138 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
7143 * Returns true if every page table entry in the specified page table page is
7147 pmap_every_pte_zero(vm_paddr_t pa)
7149 pt_entry_t *pt_end, *pte;
7151 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
7152 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
7153 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
7161 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
7162 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
7163 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
7164 * a mapping already exists at the specified virtual address. Returns
7165 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
7166 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
7167 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
7169 * The parameter "m" is only used when creating a managed, writeable mapping.
7172 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
7173 vm_page_t m, struct rwlock **lockp)
7175 struct spglist free;
7176 pd_entry_t oldpde, *pde;
7177 pt_entry_t PG_G, PG_RW, PG_V;
7180 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
7181 ("pmap_enter_pde: cannot create wired user mapping"));
7182 PG_G = pmap_global_bit(pmap);
7183 PG_RW = pmap_rw_bit(pmap);
7184 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
7185 ("pmap_enter_pde: newpde is missing PG_M"));
7186 PG_V = pmap_valid_bit(pmap);
7187 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7189 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
7191 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
7192 " in pmap %p", va, pmap);
7193 return (KERN_FAILURE);
7195 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
7196 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
7197 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7198 " in pmap %p", va, pmap);
7199 return (KERN_RESOURCE_SHORTAGE);
7203 * If pkru is not same for the whole pde range, return failure
7204 * and let vm_fault() cope. Check after pde allocation, since
7207 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
7208 pmap_abort_ptp(pmap, va, pdpg);
7209 return (KERN_PROTECTION_FAILURE);
7211 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
7212 newpde &= ~X86_PG_PKU_MASK;
7213 newpde |= pmap_pkru_get(pmap, va);
7217 * If there are existing mappings, either abort or remove them.
7220 if ((oldpde & PG_V) != 0) {
7221 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
7222 ("pmap_enter_pde: pdpg's reference count is too low"));
7223 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
7224 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
7225 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
7228 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7229 " in pmap %p", va, pmap);
7230 return (KERN_FAILURE);
7232 /* Break the existing mapping(s). */
7234 if ((oldpde & PG_PS) != 0) {
7236 * The reference to the PD page that was acquired by
7237 * pmap_alloc_pde() ensures that it won't be freed.
7238 * However, if the PDE resulted from a promotion, then
7239 * a reserved PT page could be freed.
7241 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
7242 if ((oldpde & PG_G) == 0)
7243 pmap_invalidate_pde_page(pmap, va, oldpde);
7245 pmap_delayed_invl_start();
7246 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7248 pmap_invalidate_all(pmap);
7249 pmap_delayed_invl_finish();
7251 if (va < VM_MAXUSER_ADDRESS) {
7252 vm_page_free_pages_toq(&free, true);
7253 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7256 KASSERT(SLIST_EMPTY(&free),
7257 ("pmap_enter_pde: freed kernel page table page"));
7260 * Both pmap_remove_pde() and pmap_remove_ptes() will
7261 * leave the kernel page table page zero filled.
7263 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7264 if (pmap_insert_pt_page(pmap, mt, false))
7265 panic("pmap_enter_pde: trie insert failed");
7269 if ((newpde & PG_MANAGED) != 0) {
7271 * Abort this mapping if its PV entry could not be created.
7273 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7275 pmap_abort_ptp(pmap, va, pdpg);
7276 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7277 " in pmap %p", va, pmap);
7278 return (KERN_RESOURCE_SHORTAGE);
7280 if ((newpde & PG_RW) != 0) {
7281 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7282 vm_page_aflag_set(mt, PGA_WRITEABLE);
7287 * Increment counters.
7289 if ((newpde & PG_W) != 0)
7290 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7291 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7294 * Map the superpage. (This is not a promoted mapping; there will not
7295 * be any lingering 4KB page mappings in the TLB.)
7297 pde_store(pde, newpde);
7299 counter_u64_add(pmap_pde_mappings, 1);
7300 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7302 return (KERN_SUCCESS);
7306 * Maps a sequence of resident pages belonging to the same object.
7307 * The sequence begins with the given page m_start. This page is
7308 * mapped at the given virtual address start. Each subsequent page is
7309 * mapped at a virtual address that is offset from start by the same
7310 * amount as the page is offset from m_start within the object. The
7311 * last page in the sequence is the page with the largest offset from
7312 * m_start that can be mapped at a virtual address less than the given
7313 * virtual address end. Not every virtual page between start and end
7314 * is mapped; only those for which a resident page exists with the
7315 * corresponding offset from m_start are mapped.
7318 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7319 vm_page_t m_start, vm_prot_t prot)
7321 struct rwlock *lock;
7324 vm_pindex_t diff, psize;
7326 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7328 psize = atop(end - start);
7333 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7334 va = start + ptoa(diff);
7335 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7336 m->psind == 1 && pmap_ps_enabled(pmap) &&
7337 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7338 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7339 m = &m[NBPDR / PAGE_SIZE - 1];
7341 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7343 m = TAILQ_NEXT(m, listq);
7351 * this code makes some *MAJOR* assumptions:
7352 * 1. Current pmap & pmap exists.
7355 * 4. No page table pages.
7356 * but is *MUCH* faster than pmap_enter...
7360 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7362 struct rwlock *lock;
7366 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7373 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7374 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7376 pt_entry_t newpte, *pte, PG_V;
7378 KASSERT(!VA_IS_CLEANMAP(va) ||
7379 (m->oflags & VPO_UNMANAGED) != 0,
7380 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7381 PG_V = pmap_valid_bit(pmap);
7382 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7385 * In the case that a page table page is not
7386 * resident, we are creating it here.
7388 if (va < VM_MAXUSER_ADDRESS) {
7389 vm_pindex_t ptepindex;
7393 * Calculate pagetable page index
7395 ptepindex = pmap_pde_pindex(va);
7396 if (mpte && (mpte->pindex == ptepindex)) {
7400 * Get the page directory entry
7402 ptepa = pmap_pde(pmap, va);
7405 * If the page table page is mapped, we just increment
7406 * the hold count, and activate it. Otherwise, we
7407 * attempt to allocate a page table page. If this
7408 * attempt fails, we don't retry. Instead, we give up.
7410 if (ptepa && (*ptepa & PG_V) != 0) {
7413 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7417 * Pass NULL instead of the PV list lock
7418 * pointer, because we don't intend to sleep.
7420 mpte = pmap_allocpte_alloc(pmap, ptepindex,
7426 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7427 pte = &pte[pmap_pte_index(va)];
7439 * Enter on the PV list if part of our managed memory.
7441 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7442 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7444 pmap_abort_ptp(pmap, va, mpte);
7449 * Increment counters
7451 pmap_resident_count_adj(pmap, 1);
7453 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7454 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7455 if ((m->oflags & VPO_UNMANAGED) == 0)
7456 newpte |= PG_MANAGED;
7457 if ((prot & VM_PROT_EXECUTE) == 0)
7459 if (va < VM_MAXUSER_ADDRESS)
7460 newpte |= PG_U | pmap_pkru_get(pmap, va);
7461 pte_store(pte, newpte);
7466 * Make a temporary mapping for a physical address. This is only intended
7467 * to be used for panic dumps.
7470 pmap_kenter_temporary(vm_paddr_t pa, int i)
7474 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7475 pmap_kenter(va, pa);
7477 return ((void *)crashdumpmap);
7481 * This code maps large physical mmap regions into the
7482 * processor address space. Note that some shortcuts
7483 * are taken, but the code works.
7486 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7487 vm_pindex_t pindex, vm_size_t size)
7490 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7491 vm_paddr_t pa, ptepa;
7495 PG_A = pmap_accessed_bit(pmap);
7496 PG_M = pmap_modified_bit(pmap);
7497 PG_V = pmap_valid_bit(pmap);
7498 PG_RW = pmap_rw_bit(pmap);
7500 VM_OBJECT_ASSERT_WLOCKED(object);
7501 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7502 ("pmap_object_init_pt: non-device object"));
7503 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7504 if (!pmap_ps_enabled(pmap))
7506 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7508 p = vm_page_lookup(object, pindex);
7509 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7510 ("pmap_object_init_pt: invalid page %p", p));
7511 pat_mode = p->md.pat_mode;
7514 * Abort the mapping if the first page is not physically
7515 * aligned to a 2MB page boundary.
7517 ptepa = VM_PAGE_TO_PHYS(p);
7518 if (ptepa & (NBPDR - 1))
7522 * Skip the first page. Abort the mapping if the rest of
7523 * the pages are not physically contiguous or have differing
7524 * memory attributes.
7526 p = TAILQ_NEXT(p, listq);
7527 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7529 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7530 ("pmap_object_init_pt: invalid page %p", p));
7531 if (pa != VM_PAGE_TO_PHYS(p) ||
7532 pat_mode != p->md.pat_mode)
7534 p = TAILQ_NEXT(p, listq);
7538 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7539 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7540 * will not affect the termination of this loop.
7543 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7544 pa < ptepa + size; pa += NBPDR) {
7545 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7548 * The creation of mappings below is only an
7549 * optimization. If a page directory page
7550 * cannot be allocated without blocking,
7551 * continue on to the next mapping rather than
7557 if ((*pde & PG_V) == 0) {
7558 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7559 PG_U | PG_RW | PG_V);
7560 pmap_resident_count_adj(pmap, NBPDR / PAGE_SIZE);
7561 counter_u64_add(pmap_pde_mappings, 1);
7563 /* Continue on if the PDE is already valid. */
7565 KASSERT(pdpg->ref_count > 0,
7566 ("pmap_object_init_pt: missing reference "
7567 "to page directory page, va: 0x%lx", addr));
7576 * Clear the wired attribute from the mappings for the specified range of
7577 * addresses in the given pmap. Every valid mapping within that range
7578 * must have the wired attribute set. In contrast, invalid mappings
7579 * cannot have the wired attribute set, so they are ignored.
7581 * The wired attribute of the page table entry is not a hardware
7582 * feature, so there is no need to invalidate any TLB entries.
7583 * Since pmap_demote_pde() for the wired entry must never fail,
7584 * pmap_delayed_invl_start()/finish() calls around the
7585 * function are not needed.
7588 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7590 vm_offset_t va_next;
7591 pml4_entry_t *pml4e;
7594 pt_entry_t *pte, PG_V, PG_G;
7596 PG_V = pmap_valid_bit(pmap);
7597 PG_G = pmap_global_bit(pmap);
7599 for (; sva < eva; sva = va_next) {
7600 pml4e = pmap_pml4e(pmap, sva);
7601 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7602 va_next = (sva + NBPML4) & ~PML4MASK;
7608 va_next = (sva + NBPDP) & ~PDPMASK;
7611 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7612 if ((*pdpe & PG_V) == 0)
7614 if ((*pdpe & PG_PS) != 0) {
7615 KASSERT(va_next <= eva,
7616 ("partial update of non-transparent 1G mapping "
7617 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7618 *pdpe, sva, eva, va_next));
7619 MPASS(pmap != kernel_pmap); /* XXXKIB */
7620 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7621 atomic_clear_long(pdpe, PG_W);
7622 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7626 va_next = (sva + NBPDR) & ~PDRMASK;
7629 pde = pmap_pdpe_to_pde(pdpe, sva);
7630 if ((*pde & PG_V) == 0)
7632 if ((*pde & PG_PS) != 0) {
7633 if ((*pde & PG_W) == 0)
7634 panic("pmap_unwire: pde %#jx is missing PG_W",
7638 * Are we unwiring the entire large page? If not,
7639 * demote the mapping and fall through.
7641 if (sva + NBPDR == va_next && eva >= va_next) {
7642 atomic_clear_long(pde, PG_W);
7643 pmap->pm_stats.wired_count -= NBPDR /
7646 } else if (!pmap_demote_pde(pmap, pde, sva))
7647 panic("pmap_unwire: demotion failed");
7651 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7653 if ((*pte & PG_V) == 0)
7655 if ((*pte & PG_W) == 0)
7656 panic("pmap_unwire: pte %#jx is missing PG_W",
7660 * PG_W must be cleared atomically. Although the pmap
7661 * lock synchronizes access to PG_W, another processor
7662 * could be setting PG_M and/or PG_A concurrently.
7664 atomic_clear_long(pte, PG_W);
7665 pmap->pm_stats.wired_count--;
7672 * Copy the range specified by src_addr/len
7673 * from the source map to the range dst_addr/len
7674 * in the destination map.
7676 * This routine is only advisory and need not do anything.
7679 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7680 vm_offset_t src_addr)
7682 struct rwlock *lock;
7683 pml4_entry_t *pml4e;
7685 pd_entry_t *pde, srcptepaddr;
7686 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7687 vm_offset_t addr, end_addr, va_next;
7688 vm_page_t dst_pdpg, dstmpte, srcmpte;
7690 if (dst_addr != src_addr)
7693 if (dst_pmap->pm_type != src_pmap->pm_type)
7697 * EPT page table entries that require emulation of A/D bits are
7698 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7699 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7700 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7701 * implementations flag an EPT misconfiguration for exec-only
7702 * mappings we skip this function entirely for emulated pmaps.
7704 if (pmap_emulate_ad_bits(dst_pmap))
7707 end_addr = src_addr + len;
7709 if (dst_pmap < src_pmap) {
7710 PMAP_LOCK(dst_pmap);
7711 PMAP_LOCK(src_pmap);
7713 PMAP_LOCK(src_pmap);
7714 PMAP_LOCK(dst_pmap);
7717 PG_A = pmap_accessed_bit(dst_pmap);
7718 PG_M = pmap_modified_bit(dst_pmap);
7719 PG_V = pmap_valid_bit(dst_pmap);
7721 for (addr = src_addr; addr < end_addr; addr = va_next) {
7722 KASSERT(addr < UPT_MIN_ADDRESS,
7723 ("pmap_copy: invalid to pmap_copy page tables"));
7725 pml4e = pmap_pml4e(src_pmap, addr);
7726 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7727 va_next = (addr + NBPML4) & ~PML4MASK;
7733 va_next = (addr + NBPDP) & ~PDPMASK;
7736 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7737 if ((*pdpe & PG_V) == 0)
7739 if ((*pdpe & PG_PS) != 0) {
7740 KASSERT(va_next <= end_addr,
7741 ("partial update of non-transparent 1G mapping "
7742 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7743 *pdpe, addr, end_addr, va_next));
7744 MPASS((addr & PDPMASK) == 0);
7745 MPASS((*pdpe & PG_MANAGED) == 0);
7746 srcptepaddr = *pdpe;
7747 pdpe = pmap_pdpe(dst_pmap, addr);
7749 if (pmap_allocpte_alloc(dst_pmap,
7750 pmap_pml4e_pindex(addr), NULL, addr) ==
7753 pdpe = pmap_pdpe(dst_pmap, addr);
7755 pml4e = pmap_pml4e(dst_pmap, addr);
7756 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7757 dst_pdpg->ref_count++;
7760 ("1G mapping present in dst pmap "
7761 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7762 *pdpe, addr, end_addr, va_next));
7763 *pdpe = srcptepaddr & ~PG_W;
7764 pmap_resident_count_adj(dst_pmap, NBPDP / PAGE_SIZE);
7768 va_next = (addr + NBPDR) & ~PDRMASK;
7772 pde = pmap_pdpe_to_pde(pdpe, addr);
7774 if (srcptepaddr == 0)
7777 if (srcptepaddr & PG_PS) {
7778 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7780 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7783 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7784 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7785 PMAP_ENTER_NORECLAIM, &lock))) {
7786 *pde = srcptepaddr & ~PG_W;
7787 pmap_resident_count_adj(dst_pmap, NBPDR /
7789 counter_u64_add(pmap_pde_mappings, 1);
7791 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7795 srcptepaddr &= PG_FRAME;
7796 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7797 KASSERT(srcmpte->ref_count > 0,
7798 ("pmap_copy: source page table page is unused"));
7800 if (va_next > end_addr)
7803 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7804 src_pte = &src_pte[pmap_pte_index(addr)];
7806 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7810 * We only virtual copy managed pages.
7812 if ((ptetemp & PG_MANAGED) == 0)
7815 if (dstmpte != NULL) {
7816 KASSERT(dstmpte->pindex ==
7817 pmap_pde_pindex(addr),
7818 ("dstmpte pindex/addr mismatch"));
7819 dstmpte->ref_count++;
7820 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7823 dst_pte = (pt_entry_t *)
7824 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7825 dst_pte = &dst_pte[pmap_pte_index(addr)];
7826 if (*dst_pte == 0 &&
7827 pmap_try_insert_pv_entry(dst_pmap, addr,
7828 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7830 * Clear the wired, modified, and accessed
7831 * (referenced) bits during the copy.
7833 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7834 pmap_resident_count_adj(dst_pmap, 1);
7836 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7839 /* Have we copied all of the valid mappings? */
7840 if (dstmpte->ref_count >= srcmpte->ref_count)
7847 PMAP_UNLOCK(src_pmap);
7848 PMAP_UNLOCK(dst_pmap);
7852 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7856 if (dst_pmap->pm_type != src_pmap->pm_type ||
7857 dst_pmap->pm_type != PT_X86 ||
7858 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7861 if (dst_pmap < src_pmap) {
7862 PMAP_LOCK(dst_pmap);
7863 PMAP_LOCK(src_pmap);
7865 PMAP_LOCK(src_pmap);
7866 PMAP_LOCK(dst_pmap);
7868 error = pmap_pkru_copy(dst_pmap, src_pmap);
7869 /* Clean up partial copy on failure due to no memory. */
7870 if (error == ENOMEM)
7871 pmap_pkru_deassign_all(dst_pmap);
7872 PMAP_UNLOCK(src_pmap);
7873 PMAP_UNLOCK(dst_pmap);
7874 if (error != ENOMEM)
7882 * Zero the specified hardware page.
7885 pmap_zero_page(vm_page_t m)
7887 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7889 pagezero((void *)va);
7893 * Zero an an area within a single hardware page. off and size must not
7894 * cover an area beyond a single hardware page.
7897 pmap_zero_page_area(vm_page_t m, int off, int size)
7899 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7901 if (off == 0 && size == PAGE_SIZE)
7902 pagezero((void *)va);
7904 bzero((char *)va + off, size);
7908 * Copy 1 specified hardware page to another.
7911 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7913 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7914 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7916 pagecopy((void *)src, (void *)dst);
7919 int unmapped_buf_allowed = 1;
7922 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7923 vm_offset_t b_offset, int xfersize)
7927 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7931 while (xfersize > 0) {
7932 a_pg_offset = a_offset & PAGE_MASK;
7933 pages[0] = ma[a_offset >> PAGE_SHIFT];
7934 b_pg_offset = b_offset & PAGE_MASK;
7935 pages[1] = mb[b_offset >> PAGE_SHIFT];
7936 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7937 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7938 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7939 a_cp = (char *)vaddr[0] + a_pg_offset;
7940 b_cp = (char *)vaddr[1] + b_pg_offset;
7941 bcopy(a_cp, b_cp, cnt);
7942 if (__predict_false(mapped))
7943 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7951 * Returns true if the pmap's pv is one of the first
7952 * 16 pvs linked to from this page. This count may
7953 * be changed upwards or downwards in the future; it
7954 * is only necessary that true be returned for a small
7955 * subset of pmaps for proper page aging.
7958 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7960 struct md_page *pvh;
7961 struct rwlock *lock;
7966 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7967 ("pmap_page_exists_quick: page %p is not managed", m));
7969 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7971 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7972 if (PV_PMAP(pv) == pmap) {
7980 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7981 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7982 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7983 if (PV_PMAP(pv) == pmap) {
7997 * pmap_page_wired_mappings:
7999 * Return the number of managed mappings to the given physical page
8003 pmap_page_wired_mappings(vm_page_t m)
8005 struct rwlock *lock;
8006 struct md_page *pvh;
8010 int count, md_gen, pvh_gen;
8012 if ((m->oflags & VPO_UNMANAGED) != 0)
8014 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8018 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8020 if (!PMAP_TRYLOCK(pmap)) {
8021 md_gen = m->md.pv_gen;
8025 if (md_gen != m->md.pv_gen) {
8030 pte = pmap_pte(pmap, pv->pv_va);
8031 if ((*pte & PG_W) != 0)
8035 if ((m->flags & PG_FICTITIOUS) == 0) {
8036 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8037 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8039 if (!PMAP_TRYLOCK(pmap)) {
8040 md_gen = m->md.pv_gen;
8041 pvh_gen = pvh->pv_gen;
8045 if (md_gen != m->md.pv_gen ||
8046 pvh_gen != pvh->pv_gen) {
8051 pte = pmap_pde(pmap, pv->pv_va);
8052 if ((*pte & PG_W) != 0)
8062 * Returns TRUE if the given page is mapped individually or as part of
8063 * a 2mpage. Otherwise, returns FALSE.
8066 pmap_page_is_mapped(vm_page_t m)
8068 struct rwlock *lock;
8071 if ((m->oflags & VPO_UNMANAGED) != 0)
8073 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8075 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
8076 ((m->flags & PG_FICTITIOUS) == 0 &&
8077 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
8083 * Destroy all managed, non-wired mappings in the given user-space
8084 * pmap. This pmap cannot be active on any processor besides the
8087 * This function cannot be applied to the kernel pmap. Moreover, it
8088 * is not intended for general use. It is only to be used during
8089 * process termination. Consequently, it can be implemented in ways
8090 * that make it faster than pmap_remove(). First, it can more quickly
8091 * destroy mappings by iterating over the pmap's collection of PV
8092 * entries, rather than searching the page table. Second, it doesn't
8093 * have to test and clear the page table entries atomically, because
8094 * no processor is currently accessing the user address space. In
8095 * particular, a page table entry's dirty bit won't change state once
8096 * this function starts.
8098 * Although this function destroys all of the pmap's managed,
8099 * non-wired mappings, it can delay and batch the invalidation of TLB
8100 * entries without calling pmap_delayed_invl_start() and
8101 * pmap_delayed_invl_finish(). Because the pmap is not active on
8102 * any other processor, none of these TLB entries will ever be used
8103 * before their eventual invalidation. Consequently, there is no need
8104 * for either pmap_remove_all() or pmap_remove_write() to wait for
8105 * that eventual TLB invalidation.
8108 pmap_remove_pages(pmap_t pmap)
8111 pt_entry_t *pte, tpte;
8112 pt_entry_t PG_M, PG_RW, PG_V;
8113 struct spglist free;
8114 struct pv_chunklist free_chunks[PMAP_MEMDOM];
8115 vm_page_t m, mpte, mt;
8117 struct md_page *pvh;
8118 struct pv_chunk *pc, *npc;
8119 struct rwlock *lock;
8121 uint64_t inuse, bitmask;
8122 int allfree, field, freed, i, idx;
8123 boolean_t superpage;
8127 * Assert that the given pmap is only active on the current
8128 * CPU. Unfortunately, we cannot block another CPU from
8129 * activating the pmap while this function is executing.
8131 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
8134 cpuset_t other_cpus;
8136 other_cpus = all_cpus;
8138 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
8139 CPU_AND(&other_cpus, &pmap->pm_active);
8141 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
8146 PG_M = pmap_modified_bit(pmap);
8147 PG_V = pmap_valid_bit(pmap);
8148 PG_RW = pmap_rw_bit(pmap);
8150 for (i = 0; i < PMAP_MEMDOM; i++)
8151 TAILQ_INIT(&free_chunks[i]);
8154 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
8157 for (field = 0; field < _NPCM; field++) {
8158 inuse = ~pc->pc_map[field] & pc_freemask[field];
8159 while (inuse != 0) {
8161 bitmask = 1UL << bit;
8162 idx = field * 64 + bit;
8163 pv = &pc->pc_pventry[idx];
8166 pte = pmap_pdpe(pmap, pv->pv_va);
8168 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
8170 if ((tpte & (PG_PS | PG_V)) == PG_V) {
8173 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
8175 pte = &pte[pmap_pte_index(pv->pv_va)];
8179 * Keep track whether 'tpte' is a
8180 * superpage explicitly instead of
8181 * relying on PG_PS being set.
8183 * This is because PG_PS is numerically
8184 * identical to PG_PTE_PAT and thus a
8185 * regular page could be mistaken for
8191 if ((tpte & PG_V) == 0) {
8192 panic("bad pte va %lx pte %lx",
8197 * We cannot remove wired pages from a process' mapping at this time
8205 pc->pc_map[field] |= bitmask;
8208 * Because this pmap is not active on other
8209 * processors, the dirty bit cannot have
8210 * changed state since we last loaded pte.
8215 pa = tpte & PG_PS_FRAME;
8217 pa = tpte & PG_FRAME;
8219 m = PHYS_TO_VM_PAGE(pa);
8220 KASSERT(m->phys_addr == pa,
8221 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
8222 m, (uintmax_t)m->phys_addr,
8225 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
8226 m < &vm_page_array[vm_page_array_size],
8227 ("pmap_remove_pages: bad tpte %#jx",
8231 * Update the vm_page_t clean/reference bits.
8233 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8235 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8241 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
8244 pmap_resident_count_adj(pmap, -NBPDR / PAGE_SIZE);
8245 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
8246 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8248 if (TAILQ_EMPTY(&pvh->pv_list)) {
8249 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8250 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8251 TAILQ_EMPTY(&mt->md.pv_list))
8252 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8254 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8256 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8257 ("pmap_remove_pages: pte page not promoted"));
8258 pmap_resident_count_adj(pmap, -1);
8259 KASSERT(mpte->ref_count == NPTEPG,
8260 ("pmap_remove_pages: pte page reference count error"));
8261 mpte->ref_count = 0;
8262 pmap_add_delayed_free_list(mpte, &free, FALSE);
8265 pmap_resident_count_adj(pmap, -1);
8266 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8268 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8269 TAILQ_EMPTY(&m->md.pv_list) &&
8270 (m->flags & PG_FICTITIOUS) == 0) {
8271 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8272 if (TAILQ_EMPTY(&pvh->pv_list))
8273 vm_page_aflag_clear(m, PGA_WRITEABLE);
8276 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8280 PV_STAT(counter_u64_add(pv_entry_frees, freed));
8281 PV_STAT(counter_u64_add(pv_entry_spare, freed));
8282 PV_STAT(counter_u64_add(pv_entry_count, -freed));
8284 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8285 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8290 pmap_invalidate_all(pmap);
8291 pmap_pkru_deassign_all(pmap);
8292 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8294 vm_page_free_pages_toq(&free, true);
8298 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8300 struct rwlock *lock;
8302 struct md_page *pvh;
8303 pt_entry_t *pte, mask;
8304 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8306 int md_gen, pvh_gen;
8310 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8313 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8315 if (!PMAP_TRYLOCK(pmap)) {
8316 md_gen = m->md.pv_gen;
8320 if (md_gen != m->md.pv_gen) {
8325 pte = pmap_pte(pmap, pv->pv_va);
8328 PG_M = pmap_modified_bit(pmap);
8329 PG_RW = pmap_rw_bit(pmap);
8330 mask |= PG_RW | PG_M;
8333 PG_A = pmap_accessed_bit(pmap);
8334 PG_V = pmap_valid_bit(pmap);
8335 mask |= PG_V | PG_A;
8337 rv = (*pte & mask) == mask;
8342 if ((m->flags & PG_FICTITIOUS) == 0) {
8343 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8344 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8346 if (!PMAP_TRYLOCK(pmap)) {
8347 md_gen = m->md.pv_gen;
8348 pvh_gen = pvh->pv_gen;
8352 if (md_gen != m->md.pv_gen ||
8353 pvh_gen != pvh->pv_gen) {
8358 pte = pmap_pde(pmap, pv->pv_va);
8361 PG_M = pmap_modified_bit(pmap);
8362 PG_RW = pmap_rw_bit(pmap);
8363 mask |= PG_RW | PG_M;
8366 PG_A = pmap_accessed_bit(pmap);
8367 PG_V = pmap_valid_bit(pmap);
8368 mask |= PG_V | PG_A;
8370 rv = (*pte & mask) == mask;
8384 * Return whether or not the specified physical page was modified
8385 * in any physical maps.
8388 pmap_is_modified(vm_page_t m)
8391 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8392 ("pmap_is_modified: page %p is not managed", m));
8395 * If the page is not busied then this check is racy.
8397 if (!pmap_page_is_write_mapped(m))
8399 return (pmap_page_test_mappings(m, FALSE, TRUE));
8403 * pmap_is_prefaultable:
8405 * Return whether or not the specified virtual address is eligible
8409 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8412 pt_entry_t *pte, PG_V;
8415 PG_V = pmap_valid_bit(pmap);
8418 pde = pmap_pde(pmap, addr);
8419 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8420 pte = pmap_pde_to_pte(pde, addr);
8421 rv = (*pte & PG_V) == 0;
8428 * pmap_is_referenced:
8430 * Return whether or not the specified physical page was referenced
8431 * in any physical maps.
8434 pmap_is_referenced(vm_page_t m)
8437 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8438 ("pmap_is_referenced: page %p is not managed", m));
8439 return (pmap_page_test_mappings(m, TRUE, FALSE));
8443 * Clear the write and modified bits in each of the given page's mappings.
8446 pmap_remove_write(vm_page_t m)
8448 struct md_page *pvh;
8450 struct rwlock *lock;
8451 pv_entry_t next_pv, pv;
8453 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8455 int pvh_gen, md_gen;
8457 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8458 ("pmap_remove_write: page %p is not managed", m));
8460 vm_page_assert_busied(m);
8461 if (!pmap_page_is_write_mapped(m))
8464 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8465 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8466 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8469 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8471 if (!PMAP_TRYLOCK(pmap)) {
8472 pvh_gen = pvh->pv_gen;
8476 if (pvh_gen != pvh->pv_gen) {
8481 PG_RW = pmap_rw_bit(pmap);
8483 pde = pmap_pde(pmap, va);
8484 if ((*pde & PG_RW) != 0)
8485 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8486 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8487 ("inconsistent pv lock %p %p for page %p",
8488 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8491 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8493 if (!PMAP_TRYLOCK(pmap)) {
8494 pvh_gen = pvh->pv_gen;
8495 md_gen = m->md.pv_gen;
8499 if (pvh_gen != pvh->pv_gen ||
8500 md_gen != m->md.pv_gen) {
8505 PG_M = pmap_modified_bit(pmap);
8506 PG_RW = pmap_rw_bit(pmap);
8507 pde = pmap_pde(pmap, pv->pv_va);
8508 KASSERT((*pde & PG_PS) == 0,
8509 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8511 pte = pmap_pde_to_pte(pde, pv->pv_va);
8513 if (oldpte & PG_RW) {
8514 while (!atomic_fcmpset_long(pte, &oldpte, oldpte &
8517 if ((oldpte & PG_M) != 0)
8519 pmap_invalidate_page(pmap, pv->pv_va);
8524 vm_page_aflag_clear(m, PGA_WRITEABLE);
8525 pmap_delayed_invl_wait(m);
8528 static __inline boolean_t
8529 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8532 if (!pmap_emulate_ad_bits(pmap))
8535 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8538 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8539 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8540 * if the EPT_PG_WRITE bit is set.
8542 if ((pte & EPT_PG_WRITE) != 0)
8546 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8548 if ((pte & EPT_PG_EXECUTE) == 0 ||
8549 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8556 * pmap_ts_referenced:
8558 * Return a count of reference bits for a page, clearing those bits.
8559 * It is not necessary for every reference bit to be cleared, but it
8560 * is necessary that 0 only be returned when there are truly no
8561 * reference bits set.
8563 * As an optimization, update the page's dirty field if a modified bit is
8564 * found while counting reference bits. This opportunistic update can be
8565 * performed at low cost and can eliminate the need for some future calls
8566 * to pmap_is_modified(). However, since this function stops after
8567 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8568 * dirty pages. Those dirty pages will only be detected by a future call
8569 * to pmap_is_modified().
8571 * A DI block is not needed within this function, because
8572 * invalidations are performed before the PV list lock is
8576 pmap_ts_referenced(vm_page_t m)
8578 struct md_page *pvh;
8581 struct rwlock *lock;
8582 pd_entry_t oldpde, *pde;
8583 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8586 int cleared, md_gen, not_cleared, pvh_gen;
8587 struct spglist free;
8590 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8591 ("pmap_ts_referenced: page %p is not managed", m));
8594 pa = VM_PAGE_TO_PHYS(m);
8595 lock = PHYS_TO_PV_LIST_LOCK(pa);
8596 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8600 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8601 goto small_mappings;
8607 if (!PMAP_TRYLOCK(pmap)) {
8608 pvh_gen = pvh->pv_gen;
8612 if (pvh_gen != pvh->pv_gen) {
8617 PG_A = pmap_accessed_bit(pmap);
8618 PG_M = pmap_modified_bit(pmap);
8619 PG_RW = pmap_rw_bit(pmap);
8621 pde = pmap_pde(pmap, pv->pv_va);
8623 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8625 * Although "oldpde" is mapping a 2MB page, because
8626 * this function is called at a 4KB page granularity,
8627 * we only update the 4KB page under test.
8631 if ((oldpde & PG_A) != 0) {
8633 * Since this reference bit is shared by 512 4KB
8634 * pages, it should not be cleared every time it is
8635 * tested. Apply a simple "hash" function on the
8636 * physical page number, the virtual superpage number,
8637 * and the pmap address to select one 4KB page out of
8638 * the 512 on which testing the reference bit will
8639 * result in clearing that reference bit. This
8640 * function is designed to avoid the selection of the
8641 * same 4KB page for every 2MB page mapping.
8643 * On demotion, a mapping that hasn't been referenced
8644 * is simply destroyed. To avoid the possibility of a
8645 * subsequent page fault on a demoted wired mapping,
8646 * always leave its reference bit set. Moreover,
8647 * since the superpage is wired, the current state of
8648 * its reference bit won't affect page replacement.
8650 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8651 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8652 (oldpde & PG_W) == 0) {
8653 if (safe_to_clear_referenced(pmap, oldpde)) {
8654 atomic_clear_long(pde, PG_A);
8655 pmap_invalidate_page(pmap, pv->pv_va);
8657 } else if (pmap_demote_pde_locked(pmap, pde,
8658 pv->pv_va, &lock)) {
8660 * Remove the mapping to a single page
8661 * so that a subsequent access may
8662 * repromote. Since the underlying
8663 * page table page is fully populated,
8664 * this removal never frees a page
8668 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8670 pte = pmap_pde_to_pte(pde, va);
8671 pmap_remove_pte(pmap, pte, va, *pde,
8673 pmap_invalidate_page(pmap, va);
8679 * The superpage mapping was removed
8680 * entirely and therefore 'pv' is no
8688 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8689 ("inconsistent pv lock %p %p for page %p",
8690 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8695 /* Rotate the PV list if it has more than one entry. */
8696 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8697 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8698 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8701 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8703 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8705 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8712 if (!PMAP_TRYLOCK(pmap)) {
8713 pvh_gen = pvh->pv_gen;
8714 md_gen = m->md.pv_gen;
8718 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8723 PG_A = pmap_accessed_bit(pmap);
8724 PG_M = pmap_modified_bit(pmap);
8725 PG_RW = pmap_rw_bit(pmap);
8726 pde = pmap_pde(pmap, pv->pv_va);
8727 KASSERT((*pde & PG_PS) == 0,
8728 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8730 pte = pmap_pde_to_pte(pde, pv->pv_va);
8731 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8733 if ((*pte & PG_A) != 0) {
8734 if (safe_to_clear_referenced(pmap, *pte)) {
8735 atomic_clear_long(pte, PG_A);
8736 pmap_invalidate_page(pmap, pv->pv_va);
8738 } else if ((*pte & PG_W) == 0) {
8740 * Wired pages cannot be paged out so
8741 * doing accessed bit emulation for
8742 * them is wasted effort. We do the
8743 * hard work for unwired pages only.
8745 pmap_remove_pte(pmap, pte, pv->pv_va,
8746 *pde, &free, &lock);
8747 pmap_invalidate_page(pmap, pv->pv_va);
8752 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8753 ("inconsistent pv lock %p %p for page %p",
8754 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8759 /* Rotate the PV list if it has more than one entry. */
8760 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8761 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8762 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8765 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8766 not_cleared < PMAP_TS_REFERENCED_MAX);
8769 vm_page_free_pages_toq(&free, true);
8770 return (cleared + not_cleared);
8774 * Apply the given advice to the specified range of addresses within the
8775 * given pmap. Depending on the advice, clear the referenced and/or
8776 * modified flags in each mapping and set the mapped page's dirty field.
8779 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8781 struct rwlock *lock;
8782 pml4_entry_t *pml4e;
8784 pd_entry_t oldpde, *pde;
8785 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8786 vm_offset_t va, va_next;
8790 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8794 * A/D bit emulation requires an alternate code path when clearing
8795 * the modified and accessed bits below. Since this function is
8796 * advisory in nature we skip it entirely for pmaps that require
8797 * A/D bit emulation.
8799 if (pmap_emulate_ad_bits(pmap))
8802 PG_A = pmap_accessed_bit(pmap);
8803 PG_G = pmap_global_bit(pmap);
8804 PG_M = pmap_modified_bit(pmap);
8805 PG_V = pmap_valid_bit(pmap);
8806 PG_RW = pmap_rw_bit(pmap);
8808 pmap_delayed_invl_start();
8810 for (; sva < eva; sva = va_next) {
8811 pml4e = pmap_pml4e(pmap, sva);
8812 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8813 va_next = (sva + NBPML4) & ~PML4MASK;
8819 va_next = (sva + NBPDP) & ~PDPMASK;
8822 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8823 if ((*pdpe & PG_V) == 0)
8825 if ((*pdpe & PG_PS) != 0) {
8826 KASSERT(va_next <= eva,
8827 ("partial update of non-transparent 1G mapping "
8828 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8829 *pdpe, sva, eva, va_next));
8833 va_next = (sva + NBPDR) & ~PDRMASK;
8836 pde = pmap_pdpe_to_pde(pdpe, sva);
8838 if ((oldpde & PG_V) == 0)
8840 else if ((oldpde & PG_PS) != 0) {
8841 if ((oldpde & PG_MANAGED) == 0)
8844 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8849 * The large page mapping was destroyed.
8855 * Unless the page mappings are wired, remove the
8856 * mapping to a single page so that a subsequent
8857 * access may repromote. Choosing the last page
8858 * within the address range [sva, min(va_next, eva))
8859 * generally results in more repromotions. Since the
8860 * underlying page table page is fully populated, this
8861 * removal never frees a page table page.
8863 if ((oldpde & PG_W) == 0) {
8869 ("pmap_advise: no address gap"));
8870 pte = pmap_pde_to_pte(pde, va);
8871 KASSERT((*pte & PG_V) != 0,
8872 ("pmap_advise: invalid PTE"));
8873 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8883 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8885 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8887 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8888 if (advice == MADV_DONTNEED) {
8890 * Future calls to pmap_is_modified()
8891 * can be avoided by making the page
8894 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8897 atomic_clear_long(pte, PG_M | PG_A);
8898 } else if ((*pte & PG_A) != 0)
8899 atomic_clear_long(pte, PG_A);
8903 if ((*pte & PG_G) != 0) {
8910 if (va != va_next) {
8911 pmap_invalidate_range(pmap, va, sva);
8916 pmap_invalidate_range(pmap, va, sva);
8919 pmap_invalidate_all(pmap);
8921 pmap_delayed_invl_finish();
8925 * Clear the modify bits on the specified physical page.
8928 pmap_clear_modify(vm_page_t m)
8930 struct md_page *pvh;
8932 pv_entry_t next_pv, pv;
8933 pd_entry_t oldpde, *pde;
8934 pt_entry_t *pte, PG_M, PG_RW;
8935 struct rwlock *lock;
8937 int md_gen, pvh_gen;
8939 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8940 ("pmap_clear_modify: page %p is not managed", m));
8941 vm_page_assert_busied(m);
8943 if (!pmap_page_is_write_mapped(m))
8945 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8946 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8947 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8950 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8952 if (!PMAP_TRYLOCK(pmap)) {
8953 pvh_gen = pvh->pv_gen;
8957 if (pvh_gen != pvh->pv_gen) {
8962 PG_M = pmap_modified_bit(pmap);
8963 PG_RW = pmap_rw_bit(pmap);
8965 pde = pmap_pde(pmap, va);
8967 /* If oldpde has PG_RW set, then it also has PG_M set. */
8968 if ((oldpde & PG_RW) != 0 &&
8969 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8970 (oldpde & PG_W) == 0) {
8972 * Write protect the mapping to a single page so that
8973 * a subsequent write access may repromote.
8975 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8976 pte = pmap_pde_to_pte(pde, va);
8977 atomic_clear_long(pte, PG_M | PG_RW);
8979 pmap_invalidate_page(pmap, va);
8983 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8985 if (!PMAP_TRYLOCK(pmap)) {
8986 md_gen = m->md.pv_gen;
8987 pvh_gen = pvh->pv_gen;
8991 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8996 PG_M = pmap_modified_bit(pmap);
8997 PG_RW = pmap_rw_bit(pmap);
8998 pde = pmap_pde(pmap, pv->pv_va);
8999 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
9000 " a 2mpage in page %p's pv list", m));
9001 pte = pmap_pde_to_pte(pde, pv->pv_va);
9002 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
9003 atomic_clear_long(pte, PG_M);
9004 pmap_invalidate_page(pmap, pv->pv_va);
9012 * Miscellaneous support routines follow
9015 /* Adjust the properties for a leaf page table entry. */
9016 static __inline void
9017 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
9021 opte = *(u_long *)pte;
9023 npte = opte & ~mask;
9025 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
9030 * Map a set of physical memory pages into the kernel virtual
9031 * address space. Return a pointer to where it is mapped. This
9032 * routine is intended to be used for mapping device memory,
9036 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
9038 struct pmap_preinit_mapping *ppim;
9039 vm_offset_t va, offset;
9043 offset = pa & PAGE_MASK;
9044 size = round_page(offset + size);
9045 pa = trunc_page(pa);
9047 if (!pmap_initialized) {
9049 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9050 ppim = pmap_preinit_mapping + i;
9051 if (ppim->va == 0) {
9055 ppim->va = virtual_avail;
9056 virtual_avail += size;
9062 panic("%s: too many preinit mappings", __func__);
9065 * If we have a preinit mapping, re-use it.
9067 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9068 ppim = pmap_preinit_mapping + i;
9069 if (ppim->pa == pa && ppim->sz == size &&
9070 (ppim->mode == mode ||
9071 (flags & MAPDEV_SETATTR) == 0))
9072 return ((void *)(ppim->va + offset));
9075 * If the specified range of physical addresses fits within
9076 * the direct map window, use the direct map.
9078 if (pa < dmaplimit && pa + size <= dmaplimit) {
9079 va = PHYS_TO_DMAP(pa);
9080 if ((flags & MAPDEV_SETATTR) != 0) {
9081 PMAP_LOCK(kernel_pmap);
9082 i = pmap_change_props_locked(va, size,
9083 PROT_NONE, mode, flags);
9084 PMAP_UNLOCK(kernel_pmap);
9088 return ((void *)(va + offset));
9090 va = kva_alloc(size);
9092 panic("%s: Couldn't allocate KVA", __func__);
9094 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
9095 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
9096 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
9097 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9098 pmap_invalidate_cache_range(va, va + tmpsize);
9099 return ((void *)(va + offset));
9103 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
9106 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
9111 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
9114 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
9118 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
9121 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
9126 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
9129 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
9130 MAPDEV_FLUSHCACHE));
9134 pmap_unmapdev(vm_offset_t va, vm_size_t size)
9136 struct pmap_preinit_mapping *ppim;
9140 /* If we gave a direct map region in pmap_mapdev, do nothing */
9141 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
9143 offset = va & PAGE_MASK;
9144 size = round_page(offset + size);
9145 va = trunc_page(va);
9146 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
9147 ppim = pmap_preinit_mapping + i;
9148 if (ppim->va == va && ppim->sz == size) {
9149 if (pmap_initialized)
9155 if (va + size == virtual_avail)
9160 if (pmap_initialized) {
9161 pmap_qremove(va, atop(size));
9167 * Tries to demote a 1GB page mapping.
9170 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
9172 pdp_entry_t newpdpe, oldpdpe;
9173 pd_entry_t *firstpde, newpde, *pde;
9174 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
9178 PG_A = pmap_accessed_bit(pmap);
9179 PG_M = pmap_modified_bit(pmap);
9180 PG_V = pmap_valid_bit(pmap);
9181 PG_RW = pmap_rw_bit(pmap);
9183 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9185 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
9186 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
9187 pdpg = pmap_alloc_pt_page(pmap, va >> PDPSHIFT,
9188 VM_ALLOC_WIRED | VM_ALLOC_INTERRUPT);
9190 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
9191 " in pmap %p", va, pmap);
9194 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
9195 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
9196 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
9197 KASSERT((oldpdpe & PG_A) != 0,
9198 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
9199 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
9200 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
9204 * Initialize the page directory page.
9206 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
9212 * Demote the mapping.
9217 * Invalidate a stale recursive mapping of the page directory page.
9219 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
9221 counter_u64_add(pmap_pdpe_demotions, 1);
9222 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
9223 " in pmap %p", va, pmap);
9228 * Sets the memory attribute for the specified page.
9231 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
9234 m->md.pat_mode = ma;
9237 * If "m" is a normal page, update its direct mapping. This update
9238 * can be relied upon to perform any cache operations that are
9239 * required for data coherence.
9241 if ((m->flags & PG_FICTITIOUS) == 0 &&
9242 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
9244 panic("memory attribute change on the direct map failed");
9248 * Changes the specified virtual address range's memory type to that given by
9249 * the parameter "mode". The specified virtual address range must be
9250 * completely contained within either the direct map or the kernel map. If
9251 * the virtual address range is contained within the kernel map, then the
9252 * memory type for each of the corresponding ranges of the direct map is also
9253 * changed. (The corresponding ranges of the direct map are those ranges that
9254 * map the same physical pages as the specified virtual address range.) These
9255 * changes to the direct map are necessary because Intel describes the
9256 * behavior of their processors as "undefined" if two or more mappings to the
9257 * same physical page have different memory types.
9259 * Returns zero if the change completed successfully, and either EINVAL or
9260 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9261 * of the virtual address range was not mapped, and ENOMEM is returned if
9262 * there was insufficient memory available to complete the change. In the
9263 * latter case, the memory type may have been changed on some part of the
9264 * virtual address range or the direct map.
9267 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9271 PMAP_LOCK(kernel_pmap);
9272 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9274 PMAP_UNLOCK(kernel_pmap);
9279 * Changes the specified virtual address range's protections to those
9280 * specified by "prot". Like pmap_change_attr(), protections for aliases
9281 * in the direct map are updated as well. Protections on aliasing mappings may
9282 * be a subset of the requested protections; for example, mappings in the direct
9283 * map are never executable.
9286 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9290 /* Only supported within the kernel map. */
9291 if (va < VM_MIN_KERNEL_ADDRESS)
9294 PMAP_LOCK(kernel_pmap);
9295 error = pmap_change_props_locked(va, size, prot, -1,
9296 MAPDEV_ASSERTVALID);
9297 PMAP_UNLOCK(kernel_pmap);
9302 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9303 int mode, int flags)
9305 vm_offset_t base, offset, tmpva;
9306 vm_paddr_t pa_start, pa_end, pa_end1;
9308 pd_entry_t *pde, pde_bits, pde_mask;
9309 pt_entry_t *pte, pte_bits, pte_mask;
9313 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9314 base = trunc_page(va);
9315 offset = va & PAGE_MASK;
9316 size = round_page(offset + size);
9319 * Only supported on kernel virtual addresses, including the direct
9320 * map but excluding the recursive map.
9322 if (base < DMAP_MIN_ADDRESS)
9326 * Construct our flag sets and masks. "bits" is the subset of
9327 * "mask" that will be set in each modified PTE.
9329 * Mappings in the direct map are never allowed to be executable.
9331 pde_bits = pte_bits = 0;
9332 pde_mask = pte_mask = 0;
9334 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9335 pde_mask |= X86_PG_PDE_CACHE;
9336 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9337 pte_mask |= X86_PG_PTE_CACHE;
9339 if (prot != VM_PROT_NONE) {
9340 if ((prot & VM_PROT_WRITE) != 0) {
9341 pde_bits |= X86_PG_RW;
9342 pte_bits |= X86_PG_RW;
9344 if ((prot & VM_PROT_EXECUTE) == 0 ||
9345 va < VM_MIN_KERNEL_ADDRESS) {
9349 pde_mask |= X86_PG_RW | pg_nx;
9350 pte_mask |= X86_PG_RW | pg_nx;
9354 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9355 * into 4KB pages if required.
9357 for (tmpva = base; tmpva < base + size; ) {
9358 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9359 if (pdpe == NULL || *pdpe == 0) {
9360 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9361 ("%s: addr %#lx is not mapped", __func__, tmpva));
9364 if (*pdpe & PG_PS) {
9366 * If the current 1GB page already has the required
9367 * properties, then we need not demote this page. Just
9368 * increment tmpva to the next 1GB page frame.
9370 if ((*pdpe & pde_mask) == pde_bits) {
9371 tmpva = trunc_1gpage(tmpva) + NBPDP;
9376 * If the current offset aligns with a 1GB page frame
9377 * and there is at least 1GB left within the range, then
9378 * we need not break down this page into 2MB pages.
9380 if ((tmpva & PDPMASK) == 0 &&
9381 tmpva + PDPMASK < base + size) {
9385 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9388 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9390 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9391 ("%s: addr %#lx is not mapped", __func__, tmpva));
9396 * If the current 2MB page already has the required
9397 * properties, then we need not demote this page. Just
9398 * increment tmpva to the next 2MB page frame.
9400 if ((*pde & pde_mask) == pde_bits) {
9401 tmpva = trunc_2mpage(tmpva) + NBPDR;
9406 * If the current offset aligns with a 2MB page frame
9407 * and there is at least 2MB left within the range, then
9408 * we need not break down this page into 4KB pages.
9410 if ((tmpva & PDRMASK) == 0 &&
9411 tmpva + PDRMASK < base + size) {
9415 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9418 pte = pmap_pde_to_pte(pde, tmpva);
9420 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9421 ("%s: addr %#lx is not mapped", __func__, tmpva));
9429 * Ok, all the pages exist, so run through them updating their
9430 * properties if required.
9433 pa_start = pa_end = 0;
9434 for (tmpva = base; tmpva < base + size; ) {
9435 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9436 if (*pdpe & PG_PS) {
9437 if ((*pdpe & pde_mask) != pde_bits) {
9438 pmap_pte_props(pdpe, pde_bits, pde_mask);
9441 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9442 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9443 if (pa_start == pa_end) {
9444 /* Start physical address run. */
9445 pa_start = *pdpe & PG_PS_FRAME;
9446 pa_end = pa_start + NBPDP;
9447 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9450 /* Run ended, update direct map. */
9451 error = pmap_change_props_locked(
9452 PHYS_TO_DMAP(pa_start),
9453 pa_end - pa_start, prot, mode,
9457 /* Start physical address run. */
9458 pa_start = *pdpe & PG_PS_FRAME;
9459 pa_end = pa_start + NBPDP;
9462 tmpva = trunc_1gpage(tmpva) + NBPDP;
9465 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9467 if ((*pde & pde_mask) != pde_bits) {
9468 pmap_pte_props(pde, pde_bits, pde_mask);
9471 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9472 (*pde & PG_PS_FRAME) < dmaplimit) {
9473 if (pa_start == pa_end) {
9474 /* Start physical address run. */
9475 pa_start = *pde & PG_PS_FRAME;
9476 pa_end = pa_start + NBPDR;
9477 } else if (pa_end == (*pde & PG_PS_FRAME))
9480 /* Run ended, update direct map. */
9481 error = pmap_change_props_locked(
9482 PHYS_TO_DMAP(pa_start),
9483 pa_end - pa_start, prot, mode,
9487 /* Start physical address run. */
9488 pa_start = *pde & PG_PS_FRAME;
9489 pa_end = pa_start + NBPDR;
9492 tmpva = trunc_2mpage(tmpva) + NBPDR;
9494 pte = pmap_pde_to_pte(pde, tmpva);
9495 if ((*pte & pte_mask) != pte_bits) {
9496 pmap_pte_props(pte, pte_bits, pte_mask);
9499 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9500 (*pte & PG_FRAME) < dmaplimit) {
9501 if (pa_start == pa_end) {
9502 /* Start physical address run. */
9503 pa_start = *pte & PG_FRAME;
9504 pa_end = pa_start + PAGE_SIZE;
9505 } else if (pa_end == (*pte & PG_FRAME))
9506 pa_end += PAGE_SIZE;
9508 /* Run ended, update direct map. */
9509 error = pmap_change_props_locked(
9510 PHYS_TO_DMAP(pa_start),
9511 pa_end - pa_start, prot, mode,
9515 /* Start physical address run. */
9516 pa_start = *pte & PG_FRAME;
9517 pa_end = pa_start + PAGE_SIZE;
9523 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9524 pa_end1 = MIN(pa_end, dmaplimit);
9525 if (pa_start != pa_end1)
9526 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9527 pa_end1 - pa_start, prot, mode, flags);
9531 * Flush CPU caches if required to make sure any data isn't cached that
9532 * shouldn't be, etc.
9535 pmap_invalidate_range(kernel_pmap, base, tmpva);
9536 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9537 pmap_invalidate_cache_range(base, tmpva);
9543 * Demotes any mapping within the direct map region that covers more than the
9544 * specified range of physical addresses. This range's size must be a power
9545 * of two and its starting address must be a multiple of its size. Since the
9546 * demotion does not change any attributes of the mapping, a TLB invalidation
9547 * is not mandatory. The caller may, however, request a TLB invalidation.
9550 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9559 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9560 KASSERT((base & (len - 1)) == 0,
9561 ("pmap_demote_DMAP: base is not a multiple of len"));
9562 if (len < NBPDP && base < dmaplimit) {
9563 va = PHYS_TO_DMAP(base);
9565 PMAP_LOCK(kernel_pmap);
9566 pdpe = pmap_pdpe(kernel_pmap, va);
9567 if ((*pdpe & X86_PG_V) == 0)
9568 panic("pmap_demote_DMAP: invalid PDPE");
9569 if ((*pdpe & PG_PS) != 0) {
9570 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9571 panic("pmap_demote_DMAP: PDPE failed");
9575 pde = pmap_pdpe_to_pde(pdpe, va);
9576 if ((*pde & X86_PG_V) == 0)
9577 panic("pmap_demote_DMAP: invalid PDE");
9578 if ((*pde & PG_PS) != 0) {
9579 if (!pmap_demote_pde(kernel_pmap, pde, va))
9580 panic("pmap_demote_DMAP: PDE failed");
9584 if (changed && invalidate)
9585 pmap_invalidate_page(kernel_pmap, va);
9586 PMAP_UNLOCK(kernel_pmap);
9591 * Perform the pmap work for mincore(2). If the page is not both referenced and
9592 * modified by this pmap, returns its physical address so that the caller can
9593 * find other mappings.
9596 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9600 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9604 PG_A = pmap_accessed_bit(pmap);
9605 PG_M = pmap_modified_bit(pmap);
9606 PG_V = pmap_valid_bit(pmap);
9607 PG_RW = pmap_rw_bit(pmap);
9613 pdpe = pmap_pdpe(pmap, addr);
9616 if ((*pdpe & PG_V) != 0) {
9617 if ((*pdpe & PG_PS) != 0) {
9619 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9621 val = MINCORE_PSIND(2);
9623 pdep = pmap_pde(pmap, addr);
9624 if (pdep != NULL && (*pdep & PG_V) != 0) {
9625 if ((*pdep & PG_PS) != 0) {
9627 /* Compute the physical address of the 4KB page. */
9628 pa = ((pte & PG_PS_FRAME) | (addr &
9629 PDRMASK)) & PG_FRAME;
9630 val = MINCORE_PSIND(1);
9632 pte = *pmap_pde_to_pte(pdep, addr);
9633 pa = pte & PG_FRAME;
9639 if ((pte & PG_V) != 0) {
9640 val |= MINCORE_INCORE;
9641 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9642 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9643 if ((pte & PG_A) != 0)
9644 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9646 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9647 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9648 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9657 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9659 uint32_t gen, new_gen, pcid_next;
9661 CRITICAL_ASSERT(curthread);
9662 gen = PCPU_GET(pcid_gen);
9663 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9664 return (pti ? 0 : CR3_PCID_SAVE);
9665 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9666 return (CR3_PCID_SAVE);
9667 pcid_next = PCPU_GET(pcid_next);
9668 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9669 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9670 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9671 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9672 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9676 PCPU_SET(pcid_gen, new_gen);
9677 pcid_next = PMAP_PCID_KERN + 1;
9681 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9682 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9683 PCPU_SET(pcid_next, pcid_next + 1);
9688 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9692 cached = pmap_pcid_alloc(pmap, cpuid);
9693 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9694 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9695 pmap->pm_pcids[cpuid].pm_pcid));
9696 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9697 pmap == kernel_pmap,
9698 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9699 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9704 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9707 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9708 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9712 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9715 uint64_t cached, cr3, kcr3, ucr3;
9717 KASSERT((read_rflags() & PSL_I) == 0,
9718 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9720 /* See the comment in pmap_invalidate_page_pcid(). */
9721 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9722 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9723 old_pmap = PCPU_GET(curpmap);
9724 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9725 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9728 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9730 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9731 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9732 PCPU_SET(curpmap, pmap);
9733 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9734 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9737 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9738 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9740 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9741 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9743 counter_u64_add(pcid_save_cnt, 1);
9745 pmap_activate_sw_pti_post(td, pmap);
9749 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9752 uint64_t cached, cr3;
9754 KASSERT((read_rflags() & PSL_I) == 0,
9755 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9757 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9759 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9760 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9762 PCPU_SET(curpmap, pmap);
9764 counter_u64_add(pcid_save_cnt, 1);
9768 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9769 u_int cpuid __unused)
9772 load_cr3(pmap->pm_cr3);
9773 PCPU_SET(curpmap, pmap);
9777 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9778 u_int cpuid __unused)
9781 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9782 PCPU_SET(kcr3, pmap->pm_cr3);
9783 PCPU_SET(ucr3, pmap->pm_ucr3);
9784 pmap_activate_sw_pti_post(td, pmap);
9787 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9791 if (pmap_pcid_enabled && pti)
9792 return (pmap_activate_sw_pcid_pti);
9793 else if (pmap_pcid_enabled && !pti)
9794 return (pmap_activate_sw_pcid_nopti);
9795 else if (!pmap_pcid_enabled && pti)
9796 return (pmap_activate_sw_nopcid_pti);
9797 else /* if (!pmap_pcid_enabled && !pti) */
9798 return (pmap_activate_sw_nopcid_nopti);
9802 pmap_activate_sw(struct thread *td)
9804 pmap_t oldpmap, pmap;
9807 oldpmap = PCPU_GET(curpmap);
9808 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9809 if (oldpmap == pmap) {
9810 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9814 cpuid = PCPU_GET(cpuid);
9816 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9818 CPU_SET(cpuid, &pmap->pm_active);
9820 pmap_activate_sw_mode(td, pmap, cpuid);
9822 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9824 CPU_CLR(cpuid, &oldpmap->pm_active);
9829 pmap_activate(struct thread *td)
9832 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9833 * invalidate_all IPI, which checks for curpmap ==
9834 * smp_tlb_pmap. The below sequence of operations has a
9835 * window where %CR3 is loaded with the new pmap's PML4
9836 * address, but the curpmap value has not yet been updated.
9837 * This causes the invltlb IPI handler, which is called
9838 * between the updates, to execute as a NOP, which leaves
9839 * stale TLB entries.
9841 * Note that the most common use of pmap_activate_sw(), from
9842 * a context switch, is immune to this race, because
9843 * interrupts are disabled (while the thread lock is owned),
9844 * so the IPI is delayed until after curpmap is updated. Protect
9845 * other callers in a similar way, by disabling interrupts
9846 * around the %cr3 register reload and curpmap assignment.
9849 pmap_activate_sw(td);
9854 pmap_activate_boot(pmap_t pmap)
9860 * kernel_pmap must be never deactivated, and we ensure that
9861 * by never activating it at all.
9863 MPASS(pmap != kernel_pmap);
9865 cpuid = PCPU_GET(cpuid);
9867 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9869 CPU_SET(cpuid, &pmap->pm_active);
9871 PCPU_SET(curpmap, pmap);
9873 kcr3 = pmap->pm_cr3;
9874 if (pmap_pcid_enabled)
9875 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9879 PCPU_SET(kcr3, kcr3);
9880 PCPU_SET(ucr3, PMAP_NO_CR3);
9884 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9889 * Increase the starting virtual address of the given mapping if a
9890 * different alignment might result in more superpage mappings.
9893 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9894 vm_offset_t *addr, vm_size_t size)
9896 vm_offset_t superpage_offset;
9900 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9901 offset += ptoa(object->pg_color);
9902 superpage_offset = offset & PDRMASK;
9903 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9904 (*addr & PDRMASK) == superpage_offset)
9906 if ((*addr & PDRMASK) < superpage_offset)
9907 *addr = (*addr & ~PDRMASK) + superpage_offset;
9909 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9913 static unsigned long num_dirty_emulations;
9914 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9915 &num_dirty_emulations, 0, NULL);
9917 static unsigned long num_accessed_emulations;
9918 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9919 &num_accessed_emulations, 0, NULL);
9921 static unsigned long num_superpage_accessed_emulations;
9922 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9923 &num_superpage_accessed_emulations, 0, NULL);
9925 static unsigned long ad_emulation_superpage_promotions;
9926 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9927 &ad_emulation_superpage_promotions, 0, NULL);
9928 #endif /* INVARIANTS */
9931 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9934 struct rwlock *lock;
9935 #if VM_NRESERVLEVEL > 0
9939 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9941 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9942 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9944 if (!pmap_emulate_ad_bits(pmap))
9947 PG_A = pmap_accessed_bit(pmap);
9948 PG_M = pmap_modified_bit(pmap);
9949 PG_V = pmap_valid_bit(pmap);
9950 PG_RW = pmap_rw_bit(pmap);
9956 pde = pmap_pde(pmap, va);
9957 if (pde == NULL || (*pde & PG_V) == 0)
9960 if ((*pde & PG_PS) != 0) {
9961 if (ftype == VM_PROT_READ) {
9963 atomic_add_long(&num_superpage_accessed_emulations, 1);
9971 pte = pmap_pde_to_pte(pde, va);
9972 if ((*pte & PG_V) == 0)
9975 if (ftype == VM_PROT_WRITE) {
9976 if ((*pte & PG_RW) == 0)
9979 * Set the modified and accessed bits simultaneously.
9981 * Intel EPT PTEs that do software emulation of A/D bits map
9982 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9983 * An EPT misconfiguration is triggered if the PTE is writable
9984 * but not readable (WR=10). This is avoided by setting PG_A
9985 * and PG_M simultaneously.
9987 *pte |= PG_M | PG_A;
9992 #if VM_NRESERVLEVEL > 0
9993 /* try to promote the mapping */
9994 if (va < VM_MAXUSER_ADDRESS)
9995 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9999 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
10001 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
10002 pmap_ps_enabled(pmap) &&
10003 (m->flags & PG_FICTITIOUS) == 0 &&
10004 vm_reserv_level_iffullpop(m) == 0) {
10005 pmap_promote_pde(pmap, pde, va, &lock);
10007 atomic_add_long(&ad_emulation_superpage_promotions, 1);
10013 if (ftype == VM_PROT_WRITE)
10014 atomic_add_long(&num_dirty_emulations, 1);
10016 atomic_add_long(&num_accessed_emulations, 1);
10018 rv = 0; /* success */
10027 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
10029 pml4_entry_t *pml4;
10032 pt_entry_t *pte, PG_V;
10036 PG_V = pmap_valid_bit(pmap);
10039 pml4 = pmap_pml4e(pmap, va);
10042 ptr[idx++] = *pml4;
10043 if ((*pml4 & PG_V) == 0)
10046 pdp = pmap_pml4e_to_pdpe(pml4, va);
10048 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
10051 pde = pmap_pdpe_to_pde(pdp, va);
10053 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
10056 pte = pmap_pde_to_pte(pde, va);
10065 * Get the kernel virtual address of a set of physical pages. If there are
10066 * physical addresses not covered by the DMAP perform a transient mapping
10067 * that will be removed when calling pmap_unmap_io_transient.
10069 * \param page The pages the caller wishes to obtain the virtual
10070 * address on the kernel memory map.
10071 * \param vaddr On return contains the kernel virtual memory address
10072 * of the pages passed in the page parameter.
10073 * \param count Number of pages passed in.
10074 * \param can_fault TRUE if the thread using the mapped pages can take
10075 * page faults, FALSE otherwise.
10077 * \returns TRUE if the caller must call pmap_unmap_io_transient when
10078 * finished or FALSE otherwise.
10082 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10083 boolean_t can_fault)
10086 boolean_t needs_mapping;
10088 int cache_bits, error __unused, i;
10091 * Allocate any KVA space that we need, this is done in a separate
10092 * loop to prevent calling vmem_alloc while pinned.
10094 needs_mapping = FALSE;
10095 for (i = 0; i < count; i++) {
10096 paddr = VM_PAGE_TO_PHYS(page[i]);
10097 if (__predict_false(paddr >= dmaplimit)) {
10098 error = vmem_alloc(kernel_arena, PAGE_SIZE,
10099 M_BESTFIT | M_WAITOK, &vaddr[i]);
10100 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
10101 needs_mapping = TRUE;
10103 vaddr[i] = PHYS_TO_DMAP(paddr);
10107 /* Exit early if everything is covered by the DMAP */
10108 if (!needs_mapping)
10112 * NB: The sequence of updating a page table followed by accesses
10113 * to the corresponding pages used in the !DMAP case is subject to
10114 * the situation described in the "AMD64 Architecture Programmer's
10115 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
10116 * Coherency Considerations". Therefore, issuing the INVLPG right
10117 * after modifying the PTE bits is crucial.
10121 for (i = 0; i < count; i++) {
10122 paddr = VM_PAGE_TO_PHYS(page[i]);
10123 if (paddr >= dmaplimit) {
10126 * Slow path, since we can get page faults
10127 * while mappings are active don't pin the
10128 * thread to the CPU and instead add a global
10129 * mapping visible to all CPUs.
10131 pmap_qenter(vaddr[i], &page[i], 1);
10133 pte = vtopte(vaddr[i]);
10134 cache_bits = pmap_cache_bits(kernel_pmap,
10135 page[i]->md.pat_mode, 0);
10136 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
10143 return (needs_mapping);
10147 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
10148 boolean_t can_fault)
10155 for (i = 0; i < count; i++) {
10156 paddr = VM_PAGE_TO_PHYS(page[i]);
10157 if (paddr >= dmaplimit) {
10159 pmap_qremove(vaddr[i], 1);
10160 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
10166 pmap_quick_enter_page(vm_page_t m)
10170 paddr = VM_PAGE_TO_PHYS(m);
10171 if (paddr < dmaplimit)
10172 return (PHYS_TO_DMAP(paddr));
10173 mtx_lock_spin(&qframe_mtx);
10174 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
10175 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
10176 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
10181 pmap_quick_remove_page(vm_offset_t addr)
10184 if (addr != qframe)
10186 pte_store(vtopte(qframe), 0);
10188 mtx_unlock_spin(&qframe_mtx);
10192 * Pdp pages from the large map are managed differently from either
10193 * kernel or user page table pages. They are permanently allocated at
10194 * initialization time, and their reference count is permanently set to
10195 * zero. The pml4 entries pointing to those pages are copied into
10196 * each allocated pmap.
10198 * In contrast, pd and pt pages are managed like user page table
10199 * pages. They are dynamically allocated, and their reference count
10200 * represents the number of valid entries within the page.
10203 pmap_large_map_getptp_unlocked(void)
10205 return (pmap_alloc_pt_page(kernel_pmap, 0,
10206 VM_ALLOC_NORMAL | VM_ALLOC_ZERO));
10210 pmap_large_map_getptp(void)
10214 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
10215 m = pmap_large_map_getptp_unlocked();
10217 PMAP_UNLOCK(kernel_pmap);
10219 PMAP_LOCK(kernel_pmap);
10220 /* Callers retry. */
10225 static pdp_entry_t *
10226 pmap_large_map_pdpe(vm_offset_t va)
10228 vm_pindex_t pml4_idx;
10231 pml4_idx = pmap_pml4e_index(va);
10232 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
10233 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
10235 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10236 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
10237 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
10238 "LMSPML4I %#jx lm_ents %d",
10239 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10240 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
10241 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
10244 static pd_entry_t *
10245 pmap_large_map_pde(vm_offset_t va)
10252 pdpe = pmap_large_map_pdpe(va);
10254 m = pmap_large_map_getptp();
10257 mphys = VM_PAGE_TO_PHYS(m);
10258 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10260 MPASS((*pdpe & X86_PG_PS) == 0);
10261 mphys = *pdpe & PG_FRAME;
10263 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10266 static pt_entry_t *
10267 pmap_large_map_pte(vm_offset_t va)
10274 pde = pmap_large_map_pde(va);
10276 m = pmap_large_map_getptp();
10279 mphys = VM_PAGE_TO_PHYS(m);
10280 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10281 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10283 MPASS((*pde & X86_PG_PS) == 0);
10284 mphys = *pde & PG_FRAME;
10286 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10290 pmap_large_map_kextract(vm_offset_t va)
10292 pdp_entry_t *pdpe, pdp;
10293 pd_entry_t *pde, pd;
10294 pt_entry_t *pte, pt;
10296 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10297 ("not largemap range %#lx", (u_long)va));
10298 pdpe = pmap_large_map_pdpe(va);
10300 KASSERT((pdp & X86_PG_V) != 0,
10301 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10302 (u_long)pdpe, pdp));
10303 if ((pdp & X86_PG_PS) != 0) {
10304 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10305 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10306 (u_long)pdpe, pdp));
10307 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10309 pde = pmap_pdpe_to_pde(pdpe, va);
10311 KASSERT((pd & X86_PG_V) != 0,
10312 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10313 if ((pd & X86_PG_PS) != 0)
10314 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10315 pte = pmap_pde_to_pte(pde, va);
10317 KASSERT((pt & X86_PG_V) != 0,
10318 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10319 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10323 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10324 vmem_addr_t *vmem_res)
10328 * Large mappings are all but static. Consequently, there
10329 * is no point in waiting for an earlier allocation to be
10332 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10333 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10337 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10338 vm_memattr_t mattr)
10343 vm_offset_t va, inc;
10344 vmem_addr_t vmem_res;
10348 if (len == 0 || spa + len < spa)
10351 /* See if DMAP can serve. */
10352 if (spa + len <= dmaplimit) {
10353 va = PHYS_TO_DMAP(spa);
10354 *addr = (void *)va;
10355 return (pmap_change_attr(va, len, mattr));
10359 * No, allocate KVA. Fit the address with best possible
10360 * alignment for superpages. Fall back to worse align if
10364 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10365 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10366 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10368 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10370 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10373 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10378 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10379 * in the pagetable to minimize flushing. No need to
10380 * invalidate TLB, since we only update invalid entries.
10382 PMAP_LOCK(kernel_pmap);
10383 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10385 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10386 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10387 pdpe = pmap_large_map_pdpe(va);
10389 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10390 X86_PG_V | X86_PG_A | pg_nx |
10391 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10393 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10394 (va & PDRMASK) == 0) {
10395 pde = pmap_large_map_pde(va);
10397 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10398 X86_PG_V | X86_PG_A | pg_nx |
10399 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10400 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10404 pte = pmap_large_map_pte(va);
10406 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10407 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10409 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10414 PMAP_UNLOCK(kernel_pmap);
10417 *addr = (void *)vmem_res;
10422 pmap_large_unmap(void *svaa, vm_size_t len)
10424 vm_offset_t sva, va;
10426 pdp_entry_t *pdpe, pdp;
10427 pd_entry_t *pde, pd;
10430 struct spglist spgf;
10432 sva = (vm_offset_t)svaa;
10433 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10434 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10438 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10439 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10440 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10441 PMAP_LOCK(kernel_pmap);
10442 for (va = sva; va < sva + len; va += inc) {
10443 pdpe = pmap_large_map_pdpe(va);
10445 KASSERT((pdp & X86_PG_V) != 0,
10446 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10447 (u_long)pdpe, pdp));
10448 if ((pdp & X86_PG_PS) != 0) {
10449 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10450 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10451 (u_long)pdpe, pdp));
10452 KASSERT((va & PDPMASK) == 0,
10453 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10454 (u_long)pdpe, pdp));
10455 KASSERT(va + NBPDP <= sva + len,
10456 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10457 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10458 (u_long)pdpe, pdp, len));
10463 pde = pmap_pdpe_to_pde(pdpe, va);
10465 KASSERT((pd & X86_PG_V) != 0,
10466 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10468 if ((pd & X86_PG_PS) != 0) {
10469 KASSERT((va & PDRMASK) == 0,
10470 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10472 KASSERT(va + NBPDR <= sva + len,
10473 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10474 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10478 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10480 if (m->ref_count == 0) {
10482 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10486 pte = pmap_pde_to_pte(pde, va);
10487 KASSERT((*pte & X86_PG_V) != 0,
10488 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10489 (u_long)pte, *pte));
10492 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10494 if (m->ref_count == 0) {
10496 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10497 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10499 if (m->ref_count == 0) {
10501 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10505 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10506 PMAP_UNLOCK(kernel_pmap);
10507 vm_page_free_pages_toq(&spgf, false);
10508 vmem_free(large_vmem, sva, len);
10512 pmap_large_map_wb_fence_mfence(void)
10519 pmap_large_map_wb_fence_atomic(void)
10522 atomic_thread_fence_seq_cst();
10526 pmap_large_map_wb_fence_nop(void)
10530 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10533 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10534 return (pmap_large_map_wb_fence_mfence);
10535 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10536 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10537 return (pmap_large_map_wb_fence_atomic);
10539 /* clflush is strongly enough ordered */
10540 return (pmap_large_map_wb_fence_nop);
10544 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10547 for (; len > 0; len -= cpu_clflush_line_size,
10548 va += cpu_clflush_line_size)
10553 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10556 for (; len > 0; len -= cpu_clflush_line_size,
10557 va += cpu_clflush_line_size)
10562 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10565 for (; len > 0; len -= cpu_clflush_line_size,
10566 va += cpu_clflush_line_size)
10571 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10575 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10578 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10579 return (pmap_large_map_flush_range_clwb);
10580 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10581 return (pmap_large_map_flush_range_clflushopt);
10582 else if ((cpu_feature & CPUID_CLFSH) != 0)
10583 return (pmap_large_map_flush_range_clflush);
10585 return (pmap_large_map_flush_range_nop);
10589 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10591 volatile u_long *pe;
10597 for (va = sva; va < eva; va += inc) {
10599 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10600 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10602 if ((p & X86_PG_PS) != 0)
10606 pe = (volatile u_long *)pmap_large_map_pde(va);
10608 if ((p & X86_PG_PS) != 0)
10612 pe = (volatile u_long *)pmap_large_map_pte(va);
10616 seen_other = false;
10618 if ((p & X86_PG_AVAIL1) != 0) {
10620 * Spin-wait for the end of a parallel
10627 * If we saw other write-back
10628 * occuring, we cannot rely on PG_M to
10629 * indicate state of the cache. The
10630 * PG_M bit is cleared before the
10631 * flush to avoid ignoring new writes,
10632 * and writes which are relevant for
10633 * us might happen after.
10639 if ((p & X86_PG_M) != 0 || seen_other) {
10640 if (!atomic_fcmpset_long(pe, &p,
10641 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10643 * If we saw PG_M without
10644 * PG_AVAIL1, and then on the
10645 * next attempt we do not
10646 * observe either PG_M or
10647 * PG_AVAIL1, the other
10648 * write-back started after us
10649 * and finished before us. We
10650 * can rely on it doing our
10654 pmap_large_map_flush_range(va, inc);
10655 atomic_clear_long(pe, X86_PG_AVAIL1);
10664 * Write-back cache lines for the given address range.
10666 * Must be called only on the range or sub-range returned from
10667 * pmap_large_map(). Must not be called on the coalesced ranges.
10669 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10670 * instructions support.
10673 pmap_large_map_wb(void *svap, vm_size_t len)
10675 vm_offset_t eva, sva;
10677 sva = (vm_offset_t)svap;
10679 pmap_large_map_wb_fence();
10680 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10681 pmap_large_map_flush_range(sva, len);
10683 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10684 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10685 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10686 pmap_large_map_wb_large(sva, eva);
10688 pmap_large_map_wb_fence();
10692 pmap_pti_alloc_page(void)
10696 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10697 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10698 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10703 pmap_pti_free_page(vm_page_t m)
10706 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10707 if (!vm_page_unwire_noq(m))
10709 vm_page_free_zero(m);
10714 pmap_pti_init(void)
10723 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10724 VM_OBJECT_WLOCK(pti_obj);
10725 pml4_pg = pmap_pti_alloc_page();
10726 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10727 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10728 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10729 pdpe = pmap_pti_pdpe(va);
10730 pmap_pti_wire_pte(pdpe);
10732 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10733 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10734 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10735 sizeof(struct gate_descriptor) * NIDT, false);
10737 /* Doublefault stack IST 1 */
10738 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10739 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10740 /* NMI stack IST 2 */
10741 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10742 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10743 /* MC# stack IST 3 */
10744 va = __pcpu[i].pc_common_tss.tss_ist3 +
10745 sizeof(struct nmi_pcpu);
10746 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10747 /* DB# stack IST 4 */
10748 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10749 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10751 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10752 (vm_offset_t)etext, true);
10753 pti_finalized = true;
10754 VM_OBJECT_WUNLOCK(pti_obj);
10756 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10758 static pdp_entry_t *
10759 pmap_pti_pdpe(vm_offset_t va)
10761 pml4_entry_t *pml4e;
10764 vm_pindex_t pml4_idx;
10767 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10769 pml4_idx = pmap_pml4e_index(va);
10770 pml4e = &pti_pml4[pml4_idx];
10774 panic("pml4 alloc after finalization\n");
10775 m = pmap_pti_alloc_page();
10777 pmap_pti_free_page(m);
10778 mphys = *pml4e & ~PAGE_MASK;
10780 mphys = VM_PAGE_TO_PHYS(m);
10781 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10784 mphys = *pml4e & ~PAGE_MASK;
10786 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10791 pmap_pti_wire_pte(void *pte)
10795 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10796 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10801 pmap_pti_unwire_pde(void *pde, bool only_ref)
10805 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10806 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10807 MPASS(m->ref_count > 0);
10808 MPASS(only_ref || m->ref_count > 1);
10809 pmap_pti_free_page(m);
10813 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10818 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10819 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10820 MPASS(m->ref_count > 0);
10821 if (pmap_pti_free_page(m)) {
10822 pde = pmap_pti_pde(va);
10823 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10825 pmap_pti_unwire_pde(pde, false);
10829 static pd_entry_t *
10830 pmap_pti_pde(vm_offset_t va)
10835 vm_pindex_t pd_idx;
10838 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10840 pdpe = pmap_pti_pdpe(va);
10842 m = pmap_pti_alloc_page();
10844 pmap_pti_free_page(m);
10845 MPASS((*pdpe & X86_PG_PS) == 0);
10846 mphys = *pdpe & ~PAGE_MASK;
10848 mphys = VM_PAGE_TO_PHYS(m);
10849 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10852 MPASS((*pdpe & X86_PG_PS) == 0);
10853 mphys = *pdpe & ~PAGE_MASK;
10856 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10857 pd_idx = pmap_pde_index(va);
10862 static pt_entry_t *
10863 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10870 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10872 pde = pmap_pti_pde(va);
10873 if (unwire_pde != NULL) {
10874 *unwire_pde = true;
10875 pmap_pti_wire_pte(pde);
10878 m = pmap_pti_alloc_page();
10880 pmap_pti_free_page(m);
10881 MPASS((*pde & X86_PG_PS) == 0);
10882 mphys = *pde & ~(PAGE_MASK | pg_nx);
10884 mphys = VM_PAGE_TO_PHYS(m);
10885 *pde = mphys | X86_PG_RW | X86_PG_V;
10886 if (unwire_pde != NULL)
10887 *unwire_pde = false;
10890 MPASS((*pde & X86_PG_PS) == 0);
10891 mphys = *pde & ~(PAGE_MASK | pg_nx);
10894 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10895 pte += pmap_pte_index(va);
10901 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10905 pt_entry_t *pte, ptev;
10908 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10910 sva = trunc_page(sva);
10911 MPASS(sva > VM_MAXUSER_ADDRESS);
10912 eva = round_page(eva);
10914 for (; sva < eva; sva += PAGE_SIZE) {
10915 pte = pmap_pti_pte(sva, &unwire_pde);
10916 pa = pmap_kextract(sva);
10917 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10918 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10919 VM_MEMATTR_DEFAULT, FALSE);
10921 pte_store(pte, ptev);
10922 pmap_pti_wire_pte(pte);
10924 KASSERT(!pti_finalized,
10925 ("pti overlap after fin %#lx %#lx %#lx",
10927 KASSERT(*pte == ptev,
10928 ("pti non-identical pte after fin %#lx %#lx %#lx",
10932 pde = pmap_pti_pde(sva);
10933 pmap_pti_unwire_pde(pde, true);
10939 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10944 VM_OBJECT_WLOCK(pti_obj);
10945 pmap_pti_add_kva_locked(sva, eva, exec);
10946 VM_OBJECT_WUNLOCK(pti_obj);
10950 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10957 sva = rounddown2(sva, PAGE_SIZE);
10958 MPASS(sva > VM_MAXUSER_ADDRESS);
10959 eva = roundup2(eva, PAGE_SIZE);
10961 VM_OBJECT_WLOCK(pti_obj);
10962 for (va = sva; va < eva; va += PAGE_SIZE) {
10963 pte = pmap_pti_pte(va, NULL);
10964 KASSERT((*pte & X86_PG_V) != 0,
10965 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10966 (u_long)pte, *pte));
10968 pmap_pti_unwire_pte(pte, va);
10970 pmap_invalidate_range(kernel_pmap, sva, eva);
10971 VM_OBJECT_WUNLOCK(pti_obj);
10975 pkru_dup_range(void *ctx __unused, void *data)
10977 struct pmap_pkru_range *node, *new_node;
10979 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10980 if (new_node == NULL)
10983 memcpy(new_node, node, sizeof(*node));
10988 pkru_free_range(void *ctx __unused, void *node)
10991 uma_zfree(pmap_pkru_ranges_zone, node);
10995 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10998 struct pmap_pkru_range *ppr;
11001 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11002 MPASS(pmap->pm_type == PT_X86);
11003 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11004 if ((flags & AMD64_PKRU_EXCL) != 0 &&
11005 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
11007 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
11010 ppr->pkru_keyidx = keyidx;
11011 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
11012 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
11014 uma_zfree(pmap_pkru_ranges_zone, ppr);
11019 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11022 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11023 MPASS(pmap->pm_type == PT_X86);
11024 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11025 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
11029 pmap_pkru_deassign_all(pmap_t pmap)
11032 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11033 if (pmap->pm_type == PT_X86 &&
11034 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
11035 rangeset_remove_all(&pmap->pm_pkru);
11039 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11041 struct pmap_pkru_range *ppr, *prev_ppr;
11044 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11045 if (pmap->pm_type != PT_X86 ||
11046 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11047 sva >= VM_MAXUSER_ADDRESS)
11049 MPASS(eva <= VM_MAXUSER_ADDRESS);
11050 for (va = sva; va < eva; prev_ppr = ppr) {
11051 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11054 else if ((ppr == NULL) ^ (prev_ppr == NULL))
11060 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
11062 va = ppr->pkru_rs_el.re_end;
11068 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
11070 struct pmap_pkru_range *ppr;
11072 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11073 if (pmap->pm_type != PT_X86 ||
11074 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
11075 va >= VM_MAXUSER_ADDRESS)
11077 ppr = rangeset_lookup(&pmap->pm_pkru, va);
11079 return (X86_PG_PKU(ppr->pkru_keyidx));
11084 pred_pkru_on_remove(void *ctx __unused, void *r)
11086 struct pmap_pkru_range *ppr;
11089 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
11093 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11096 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11097 if (pmap->pm_type == PT_X86 &&
11098 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
11099 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
11100 pred_pkru_on_remove);
11105 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
11108 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
11109 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
11110 MPASS(dst_pmap->pm_type == PT_X86);
11111 MPASS(src_pmap->pm_type == PT_X86);
11112 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
11113 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
11115 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
11119 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11122 pml4_entry_t *pml4e;
11124 pd_entry_t newpde, ptpaddr, *pde;
11125 pt_entry_t newpte, *ptep, pte;
11126 vm_offset_t va, va_next;
11129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
11130 MPASS(pmap->pm_type == PT_X86);
11131 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
11133 for (changed = false, va = sva; va < eva; va = va_next) {
11134 pml4e = pmap_pml4e(pmap, va);
11135 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
11136 va_next = (va + NBPML4) & ~PML4MASK;
11142 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
11143 if ((*pdpe & X86_PG_V) == 0) {
11144 va_next = (va + NBPDP) & ~PDPMASK;
11150 va_next = (va + NBPDR) & ~PDRMASK;
11154 pde = pmap_pdpe_to_pde(pdpe, va);
11159 MPASS((ptpaddr & X86_PG_V) != 0);
11160 if ((ptpaddr & PG_PS) != 0) {
11161 if (va + NBPDR == va_next && eva >= va_next) {
11162 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
11163 X86_PG_PKU(keyidx);
11164 if (newpde != ptpaddr) {
11169 } else if (!pmap_demote_pde(pmap, pde, va)) {
11177 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
11178 ptep++, va += PAGE_SIZE) {
11180 if ((pte & X86_PG_V) == 0)
11182 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
11183 if (newpte != pte) {
11190 pmap_invalidate_range(pmap, sva, eva);
11194 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
11195 u_int keyidx, int flags)
11198 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
11199 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
11201 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
11203 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
11209 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
11214 sva = trunc_page(sva);
11215 eva = round_page(eva);
11216 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
11221 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
11223 pmap_pkru_update_range(pmap, sva, eva, keyidx);
11225 if (error != ENOMEM)
11233 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11237 sva = trunc_page(sva);
11238 eva = round_page(eva);
11239 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
11244 error = pmap_pkru_deassign(pmap, sva, eva);
11246 pmap_pkru_update_range(pmap, sva, eva, 0);
11248 if (error != ENOMEM)
11257 pmap_kasan_enter_alloc_4k(void)
11261 m = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
11262 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
11264 panic("%s: no memory to grow shadow map", __func__);
11265 if ((m->flags & PG_ZERO) == 0)
11271 pmap_kasan_enter_alloc_2m(void)
11275 m = vm_page_alloc_contig(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
11276 VM_ALLOC_WIRED, NPTEPG, 0, ~0ul, NBPDR, 0, VM_MEMATTR_DEFAULT);
11278 memset((void *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), 0, NBPDR);
11283 * Grow the shadow map by at least one 4KB page at the specified address. Use
11284 * 2MB pages when possible.
11287 pmap_kasan_enter(vm_offset_t va)
11294 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
11296 pdpe = pmap_pdpe(kernel_pmap, va);
11297 if ((*pdpe & X86_PG_V) == 0) {
11298 m = pmap_kasan_enter_alloc_4k();
11299 *pdpe = (pdp_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11302 pde = pmap_pdpe_to_pde(pdpe, va);
11303 if ((*pde & X86_PG_V) == 0) {
11304 m = pmap_kasan_enter_alloc_2m();
11306 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11307 X86_PG_PS | X86_PG_V | pg_nx);
11309 m = pmap_kasan_enter_alloc_4k();
11310 *pde = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW |
11314 if ((*pde & X86_PG_PS) != 0)
11316 pte = pmap_pde_to_pte(pde, va);
11317 if ((*pte & X86_PG_V) != 0)
11319 KASSERT((*pte & X86_PG_V) == 0,
11320 ("%s: shadow address %#lx is already mapped", __func__, va));
11321 m = pmap_kasan_enter_alloc_4k();
11322 *pte = (pt_entry_t)(VM_PAGE_TO_PHYS(m) | X86_PG_RW | X86_PG_V |
11323 X86_PG_M | X86_PG_A | pg_nx);
11328 * Track a range of the kernel's virtual address space that is contiguous
11329 * in various mapping attributes.
11331 struct pmap_kernel_map_range {
11340 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11346 if (eva <= range->sva)
11349 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11350 for (i = 0; i < PAT_INDEX_SIZE; i++)
11351 if (pat_index[i] == pat_idx)
11355 case PAT_WRITE_BACK:
11358 case PAT_WRITE_THROUGH:
11361 case PAT_UNCACHEABLE:
11367 case PAT_WRITE_PROTECTED:
11370 case PAT_WRITE_COMBINING:
11374 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11375 __func__, pat_idx, range->sva, eva);
11380 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11382 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11383 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11384 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11385 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11386 mode, range->pdpes, range->pdes, range->ptes);
11388 /* Reset to sentinel value. */
11389 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11390 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11391 NPDEPG - 1, NPTEPG - 1);
11395 * Determine whether the attributes specified by a page table entry match those
11396 * being tracked by the current range. This is not quite as simple as a direct
11397 * flag comparison since some PAT modes have multiple representations.
11400 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11402 pt_entry_t diff, mask;
11404 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11405 diff = (range->attrs ^ attrs) & mask;
11408 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11409 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11410 pmap_pat_index(kernel_pmap, attrs, true))
11416 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11420 memset(range, 0, sizeof(*range));
11422 range->attrs = attrs;
11426 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11427 * those of the current run, dump the address range and its attributes, and
11431 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11432 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11437 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11439 attrs |= pdpe & pg_nx;
11440 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11441 if ((pdpe & PG_PS) != 0) {
11442 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11443 } else if (pde != 0) {
11444 attrs |= pde & pg_nx;
11445 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11447 if ((pde & PG_PS) != 0) {
11448 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11449 } else if (pte != 0) {
11450 attrs |= pte & pg_nx;
11451 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11452 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11454 /* Canonicalize by always using the PDE PAT bit. */
11455 if ((attrs & X86_PG_PTE_PAT) != 0)
11456 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11459 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11460 sysctl_kmaps_dump(sb, range, va);
11461 sysctl_kmaps_reinit(range, va, attrs);
11466 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11468 struct pmap_kernel_map_range range;
11469 struct sbuf sbuf, *sb;
11470 pml4_entry_t pml4e;
11471 pdp_entry_t *pdp, pdpe;
11472 pd_entry_t *pd, pde;
11473 pt_entry_t *pt, pte;
11476 int error, i, j, k, l;
11478 error = sysctl_wire_old_buffer(req, 0);
11482 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11484 /* Sentinel value. */
11485 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11486 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11487 NPDEPG - 1, NPTEPG - 1);
11490 * Iterate over the kernel page tables without holding the kernel pmap
11491 * lock. Outside of the large map, kernel page table pages are never
11492 * freed, so at worst we will observe inconsistencies in the output.
11493 * Within the large map, ensure that PDP and PD page addresses are
11494 * valid before descending.
11496 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11499 sbuf_printf(sb, "\nRecursive map:\n");
11502 sbuf_printf(sb, "\nDirect map:\n");
11506 sbuf_printf(sb, "\nKASAN shadow map:\n");
11510 sbuf_printf(sb, "\nKernel map:\n");
11513 sbuf_printf(sb, "\nLarge map:\n");
11517 /* Convert to canonical form. */
11518 if (sva == 1ul << 47)
11522 pml4e = kernel_pml4[i];
11523 if ((pml4e & X86_PG_V) == 0) {
11524 sva = rounddown2(sva, NBPML4);
11525 sysctl_kmaps_dump(sb, &range, sva);
11529 pa = pml4e & PG_FRAME;
11530 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11532 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11534 if ((pdpe & X86_PG_V) == 0) {
11535 sva = rounddown2(sva, NBPDP);
11536 sysctl_kmaps_dump(sb, &range, sva);
11540 pa = pdpe & PG_FRAME;
11541 if ((pdpe & PG_PS) != 0) {
11542 sva = rounddown2(sva, NBPDP);
11543 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11549 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11550 vm_phys_paddr_to_vm_page(pa) == NULL) {
11552 * Page table pages for the large map may be
11553 * freed. Validate the next-level address
11554 * before descending.
11558 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11560 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11562 if ((pde & X86_PG_V) == 0) {
11563 sva = rounddown2(sva, NBPDR);
11564 sysctl_kmaps_dump(sb, &range, sva);
11568 pa = pde & PG_FRAME;
11569 if ((pde & PG_PS) != 0) {
11570 sva = rounddown2(sva, NBPDR);
11571 sysctl_kmaps_check(sb, &range, sva,
11572 pml4e, pdpe, pde, 0);
11577 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11578 vm_phys_paddr_to_vm_page(pa) == NULL) {
11580 * Page table pages for the large map
11581 * may be freed. Validate the
11582 * next-level address before descending.
11586 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11588 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11589 sva += PAGE_SIZE) {
11591 if ((pte & X86_PG_V) == 0) {
11592 sysctl_kmaps_dump(sb, &range,
11596 sysctl_kmaps_check(sb, &range, sva,
11597 pml4e, pdpe, pde, pte);
11604 error = sbuf_finish(sb);
11608 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11609 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
11610 NULL, 0, sysctl_kmaps, "A",
11611 "Dump kernel address layout");
11614 DB_SHOW_COMMAND(pte, pmap_print_pte)
11617 pml5_entry_t *pml5;
11618 pml4_entry_t *pml4;
11621 pt_entry_t *pte, PG_V;
11625 db_printf("show pte addr\n");
11628 va = (vm_offset_t)addr;
11630 if (kdb_thread != NULL)
11631 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11633 pmap = PCPU_GET(curpmap);
11635 PG_V = pmap_valid_bit(pmap);
11636 db_printf("VA 0x%016lx", va);
11638 if (pmap_is_la57(pmap)) {
11639 pml5 = pmap_pml5e(pmap, va);
11640 db_printf(" pml5e 0x%016lx", *pml5);
11641 if ((*pml5 & PG_V) == 0) {
11645 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11647 pml4 = pmap_pml4e(pmap, va);
11649 db_printf(" pml4e 0x%016lx", *pml4);
11650 if ((*pml4 & PG_V) == 0) {
11654 pdp = pmap_pml4e_to_pdpe(pml4, va);
11655 db_printf(" pdpe 0x%016lx", *pdp);
11656 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11660 pde = pmap_pdpe_to_pde(pdp, va);
11661 db_printf(" pde 0x%016lx", *pde);
11662 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11666 pte = pmap_pde_to_pte(pde, va);
11667 db_printf(" pte 0x%016lx\n", *pte);
11670 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11675 a = (vm_paddr_t)addr;
11676 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11678 db_printf("show phys2dmap addr\n");
11683 ptpages_show_page(int level, int idx, vm_page_t pg)
11685 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11686 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11690 ptpages_show_complain(int level, int idx, uint64_t pte)
11692 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11696 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11698 vm_page_t pg3, pg2, pg1;
11699 pml4_entry_t *pml4;
11704 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11705 for (i4 = 0; i4 < num_entries; i4++) {
11706 if ((pml4[i4] & PG_V) == 0)
11708 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11710 ptpages_show_complain(3, i4, pml4[i4]);
11713 ptpages_show_page(3, i4, pg3);
11714 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11715 for (i3 = 0; i3 < NPDPEPG; i3++) {
11716 if ((pdp[i3] & PG_V) == 0)
11718 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11720 ptpages_show_complain(2, i3, pdp[i3]);
11723 ptpages_show_page(2, i3, pg2);
11724 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11725 for (i2 = 0; i2 < NPDEPG; i2++) {
11726 if ((pd[i2] & PG_V) == 0)
11728 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11730 ptpages_show_complain(1, i2, pd[i2]);
11733 ptpages_show_page(1, i2, pg1);
11739 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11743 pml5_entry_t *pml5;
11748 pmap = (pmap_t)addr;
11750 pmap = PCPU_GET(curpmap);
11752 PG_V = pmap_valid_bit(pmap);
11754 if (pmap_is_la57(pmap)) {
11755 pml5 = pmap->pm_pmltop;
11756 for (i5 = 0; i5 < NUPML5E; i5++) {
11757 if ((pml5[i5] & PG_V) == 0)
11759 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11761 ptpages_show_complain(4, i5, pml5[i5]);
11764 ptpages_show_page(4, i5, pg);
11765 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11768 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11769 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);