2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmem.h>
119 #include <sys/vmmeter.h>
120 #include <sys/sched.h>
121 #include <sys/sysctl.h>
122 #include <sys/_unrhdr.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
141 #include <machine/cpu.h>
142 #include <machine/cputypes.h>
143 #include <machine/md_var.h>
144 #include <machine/pcb.h>
145 #include <machine/specialreg.h>
147 #include <machine/smp.h>
150 static __inline boolean_t
151 pmap_type_guest(pmap_t pmap)
154 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
157 static __inline boolean_t
158 pmap_emulate_ad_bits(pmap_t pmap)
161 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
164 static __inline pt_entry_t
165 pmap_valid_bit(pmap_t pmap)
169 switch (pmap->pm_type) {
175 if (pmap_emulate_ad_bits(pmap))
176 mask = EPT_PG_EMUL_V;
181 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
187 static __inline pt_entry_t
188 pmap_rw_bit(pmap_t pmap)
192 switch (pmap->pm_type) {
198 if (pmap_emulate_ad_bits(pmap))
199 mask = EPT_PG_EMUL_RW;
204 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
210 static __inline pt_entry_t
211 pmap_global_bit(pmap_t pmap)
215 switch (pmap->pm_type) {
224 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
230 static __inline pt_entry_t
231 pmap_accessed_bit(pmap_t pmap)
235 switch (pmap->pm_type) {
241 if (pmap_emulate_ad_bits(pmap))
247 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
253 static __inline pt_entry_t
254 pmap_modified_bit(pmap_t pmap)
258 switch (pmap->pm_type) {
264 if (pmap_emulate_ad_bits(pmap))
270 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
276 #if !defined(DIAGNOSTIC)
277 #ifdef __GNUC_GNU_INLINE__
278 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
280 #define PMAP_INLINE extern inline
287 #define PV_STAT(x) do { x ; } while (0)
289 #define PV_STAT(x) do { } while (0)
292 #define pa_index(pa) ((pa) >> PDRSHIFT)
293 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
295 #define NPV_LIST_LOCKS MAXCPU
297 #define PHYS_TO_PV_LIST_LOCK(pa) \
298 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
300 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
301 struct rwlock **_lockp = (lockp); \
302 struct rwlock *_new_lock; \
304 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
305 if (_new_lock != *_lockp) { \
306 if (*_lockp != NULL) \
307 rw_wunlock(*_lockp); \
308 *_lockp = _new_lock; \
313 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
314 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
316 #define RELEASE_PV_LIST_LOCK(lockp) do { \
317 struct rwlock **_lockp = (lockp); \
319 if (*_lockp != NULL) { \
320 rw_wunlock(*_lockp); \
325 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
326 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
328 struct pmap kernel_pmap_store;
330 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
331 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
334 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
335 "Number of kernel page table pages allocated on bootup");
338 vm_paddr_t dmaplimit;
339 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
342 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
344 static int pat_works = 1;
345 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
346 "Is page attribute table fully functional?");
348 static int pg_ps_enabled = 1;
349 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
350 &pg_ps_enabled, 0, "Are large page mappings enabled?");
352 #define PAT_INDEX_SIZE 8
353 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
355 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
356 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
357 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
358 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
360 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
361 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
362 static int ndmpdpphys; /* number of DMPDPphys pages */
364 static struct rwlock_padalign pvh_global_lock;
367 * Data for the pv entry allocation mechanism
369 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
370 static struct mtx pv_chunks_mutex;
371 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
372 static struct md_page *pv_table;
375 * All those kernel PT submaps that BSD is so fond of
377 pt_entry_t *CMAP1 = 0;
380 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
382 static struct unrhdr pcid_unr;
383 static struct mtx pcid_mtx;
384 int pmap_pcid_enabled = 0;
385 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
386 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
387 int invpcid_works = 0;
388 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
389 "Is the invpcid instruction available ?");
392 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
399 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
401 return (sysctl_handle_64(oidp, &res, 0, req));
403 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
404 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
405 "Count of saved TLB context on switch");
410 static caddr_t crashdumpmap;
412 static void free_pv_chunk(struct pv_chunk *pc);
413 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
414 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
415 static int popcnt_pc_map_elem(uint64_t elem);
416 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
417 static void reserve_pv_entries(pmap_t pmap, int needed,
418 struct rwlock **lockp);
419 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
420 struct rwlock **lockp);
421 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
422 struct rwlock **lockp);
423 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
424 struct rwlock **lockp);
425 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
426 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
429 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
430 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
431 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
432 vm_offset_t va, struct rwlock **lockp);
433 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
435 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
436 vm_prot_t prot, struct rwlock **lockp);
437 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
438 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
439 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
440 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
441 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
442 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
443 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
444 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
445 struct rwlock **lockp);
446 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
448 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
449 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
450 struct spglist *free, struct rwlock **lockp);
451 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
452 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
453 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
454 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
455 struct spglist *free);
456 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
457 vm_page_t m, struct rwlock **lockp);
458 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
460 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
462 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
463 struct rwlock **lockp);
464 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
465 struct rwlock **lockp);
466 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
467 struct rwlock **lockp);
469 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
470 struct spglist *free);
471 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
472 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
475 * Move the kernel virtual free pointer to the next
476 * 2MB. This is used to help improve performance
477 * by using a large (2MB) page for much of the kernel
478 * (.text, .data, .bss)
481 pmap_kmem_choose(vm_offset_t addr)
483 vm_offset_t newaddr = addr;
485 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
489 /********************/
490 /* Inline functions */
491 /********************/
493 /* Return a non-clipped PD index for a given VA */
494 static __inline vm_pindex_t
495 pmap_pde_pindex(vm_offset_t va)
497 return (va >> PDRSHIFT);
501 /* Return various clipped indexes for a given VA */
502 static __inline vm_pindex_t
503 pmap_pte_index(vm_offset_t va)
506 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
509 static __inline vm_pindex_t
510 pmap_pde_index(vm_offset_t va)
513 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
516 static __inline vm_pindex_t
517 pmap_pdpe_index(vm_offset_t va)
520 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
523 static __inline vm_pindex_t
524 pmap_pml4e_index(vm_offset_t va)
527 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
530 /* Return a pointer to the PML4 slot that corresponds to a VA */
531 static __inline pml4_entry_t *
532 pmap_pml4e(pmap_t pmap, vm_offset_t va)
535 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
538 /* Return a pointer to the PDP slot that corresponds to a VA */
539 static __inline pdp_entry_t *
540 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
544 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
545 return (&pdpe[pmap_pdpe_index(va)]);
548 /* Return a pointer to the PDP slot that corresponds to a VA */
549 static __inline pdp_entry_t *
550 pmap_pdpe(pmap_t pmap, vm_offset_t va)
555 PG_V = pmap_valid_bit(pmap);
556 pml4e = pmap_pml4e(pmap, va);
557 if ((*pml4e & PG_V) == 0)
559 return (pmap_pml4e_to_pdpe(pml4e, va));
562 /* Return a pointer to the PD slot that corresponds to a VA */
563 static __inline pd_entry_t *
564 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
568 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
569 return (&pde[pmap_pde_index(va)]);
572 /* Return a pointer to the PD slot that corresponds to a VA */
573 static __inline pd_entry_t *
574 pmap_pde(pmap_t pmap, vm_offset_t va)
579 PG_V = pmap_valid_bit(pmap);
580 pdpe = pmap_pdpe(pmap, va);
581 if (pdpe == NULL || (*pdpe & PG_V) == 0)
583 return (pmap_pdpe_to_pde(pdpe, va));
586 /* Return a pointer to the PT slot that corresponds to a VA */
587 static __inline pt_entry_t *
588 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
592 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
593 return (&pte[pmap_pte_index(va)]);
596 /* Return a pointer to the PT slot that corresponds to a VA */
597 static __inline pt_entry_t *
598 pmap_pte(pmap_t pmap, vm_offset_t va)
603 PG_V = pmap_valid_bit(pmap);
604 pde = pmap_pde(pmap, va);
605 if (pde == NULL || (*pde & PG_V) == 0)
607 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
608 return ((pt_entry_t *)pde);
609 return (pmap_pde_to_pte(pde, va));
613 pmap_resident_count_inc(pmap_t pmap, int count)
616 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
617 pmap->pm_stats.resident_count += count;
621 pmap_resident_count_dec(pmap_t pmap, int count)
624 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
625 KASSERT(pmap->pm_stats.resident_count >= count,
626 ("pmap %p resident count underflow %ld %d", pmap,
627 pmap->pm_stats.resident_count, count));
628 pmap->pm_stats.resident_count -= count;
631 PMAP_INLINE pt_entry_t *
632 vtopte(vm_offset_t va)
634 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
636 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
638 return (PTmap + ((va >> PAGE_SHIFT) & mask));
641 static __inline pd_entry_t *
642 vtopde(vm_offset_t va)
644 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
646 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
648 return (PDmap + ((va >> PDRSHIFT) & mask));
652 allocpages(vm_paddr_t *firstaddr, int n)
657 bzero((void *)ret, n * PAGE_SIZE);
658 *firstaddr += n * PAGE_SIZE;
662 CTASSERT(powerof2(NDMPML4E));
664 /* number of kernel PDP slots */
665 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
668 nkpt_init(vm_paddr_t addr)
675 pt_pages = howmany(addr, 1 << PDRSHIFT);
676 pt_pages += NKPDPE(pt_pages);
679 * Add some slop beyond the bare minimum required for bootstrapping
682 * This is quite important when allocating KVA for kernel modules.
683 * The modules are required to be linked in the negative 2GB of
684 * the address space. If we run out of KVA in this region then
685 * pmap_growkernel() will need to allocate page table pages to map
686 * the entire 512GB of KVA space which is an unnecessary tax on
689 pt_pages += 8; /* 16MB additional slop for kernel modules */
695 create_pagetables(vm_paddr_t *firstaddr)
697 int i, j, ndm1g, nkpdpe;
703 /* Allocate page table pages for the direct map */
704 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
705 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
707 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
708 if (ndmpdpphys > NDMPML4E) {
710 * Each NDMPML4E allows 512 GB, so limit to that,
711 * and then readjust ndmpdp and ndmpdpphys.
713 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
714 Maxmem = atop(NDMPML4E * NBPML4);
715 ndmpdpphys = NDMPML4E;
716 ndmpdp = NDMPML4E * NPDEPG;
718 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
720 if ((amd_feature & AMDID_PAGE1GB) != 0)
721 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
723 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
724 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
727 KPML4phys = allocpages(firstaddr, 1);
728 KPDPphys = allocpages(firstaddr, NKPML4E);
731 * Allocate the initial number of kernel page table pages required to
732 * bootstrap. We defer this until after all memory-size dependent
733 * allocations are done (e.g. direct map), so that we don't have to
734 * build in too much slop in our estimate.
736 * Note that when NKPML4E > 1, we have an empty page underneath
737 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
738 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
740 nkpt_init(*firstaddr);
741 nkpdpe = NKPDPE(nkpt);
743 KPTphys = allocpages(firstaddr, nkpt);
744 KPDphys = allocpages(firstaddr, nkpdpe);
746 /* Fill in the underlying page table pages */
747 /* Nominally read-only (but really R/W) from zero to physfree */
748 /* XXX not fully used, underneath 2M pages */
749 pt_p = (pt_entry_t *)KPTphys;
750 for (i = 0; ptoa(i) < *firstaddr; i++)
751 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
753 /* Now map the page tables at their location within PTmap */
754 pd_p = (pd_entry_t *)KPDphys;
755 for (i = 0; i < nkpt; i++)
756 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
758 /* Map from zero to end of allocations under 2M pages */
759 /* This replaces some of the KPTphys entries above */
760 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
761 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
764 /* And connect up the PD to the PDP (leaving room for L4 pages) */
765 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
766 for (i = 0; i < nkpdpe; i++)
767 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
771 * Now, set up the direct map region using 2MB and/or 1GB pages. If
772 * the end of physical memory is not aligned to a 1GB page boundary,
773 * then the residual physical memory is mapped with 2MB pages. Later,
774 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
775 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
776 * that are partially used.
778 pd_p = (pd_entry_t *)DMPDphys;
779 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
780 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
781 /* Preset PG_M and PG_A because demotion expects it. */
782 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
785 pdp_p = (pdp_entry_t *)DMPDPphys;
786 for (i = 0; i < ndm1g; i++) {
787 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
788 /* Preset PG_M and PG_A because demotion expects it. */
789 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
792 for (j = 0; i < ndmpdp; i++, j++) {
793 pdp_p[i] = DMPDphys + ptoa(j);
794 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
797 /* And recursively map PML4 to itself in order to get PTmap */
798 p4_p = (pml4_entry_t *)KPML4phys;
799 p4_p[PML4PML4I] = KPML4phys;
800 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
802 /* Connect the Direct Map slot(s) up to the PML4. */
803 for (i = 0; i < ndmpdpphys; i++) {
804 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
805 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
808 /* Connect the KVA slots up to the PML4 */
809 for (i = 0; i < NKPML4E; i++) {
810 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
811 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
816 * Bootstrap the system enough to run with virtual memory.
818 * On amd64 this is called after mapping has already been enabled
819 * and just syncs the pmap module with what has already been done.
820 * [We can't call it easily with mapping off since the kernel is not
821 * mapped with PA == VA, hence we would have to relocate every address
822 * from the linked base (virtual) address "KERNBASE" to the actual
823 * (physical) address starting relative to 0]
826 pmap_bootstrap(vm_paddr_t *firstaddr)
832 * Create an initial set of page tables to run the kernel in.
834 create_pagetables(firstaddr);
837 * Add a physical memory segment (vm_phys_seg) corresponding to the
838 * preallocated kernel page table pages so that vm_page structures
839 * representing these pages will be created. The vm_page structures
840 * are required for promotion of the corresponding kernel virtual
841 * addresses to superpage mappings.
843 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
845 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
846 virtual_avail = pmap_kmem_choose(virtual_avail);
848 virtual_end = VM_MAX_KERNEL_ADDRESS;
851 /* XXX do %cr0 as well */
852 load_cr4(rcr4() | CR4_PGE);
854 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
855 load_cr4(rcr4() | CR4_SMEP);
858 * Initialize the kernel pmap (which is statically allocated).
860 PMAP_LOCK_INIT(kernel_pmap);
861 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
862 kernel_pmap->pm_cr3 = KPML4phys;
863 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
864 CPU_FILL(&kernel_pmap->pm_save); /* always superset of pm_active */
865 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
866 kernel_pmap->pm_flags = pmap_flags;
869 * Initialize the global pv list lock.
871 rw_init(&pvh_global_lock, "pmap pv global");
874 * Reserve some special page table entries/VA space for temporary
877 #define SYSMAP(c, p, v, n) \
878 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
884 * Crashdump maps. The first page is reused as CMAP1 for the
887 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
888 CADDR1 = crashdumpmap;
892 /* Initialize the PAT MSR. */
895 /* Initialize TLB Context Id. */
896 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
897 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
898 load_cr4(rcr4() | CR4_PCIDE);
899 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
900 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
901 /* Check for INVPCID support */
902 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
904 kernel_pmap->pm_pcid = 0;
906 pmap_pcid_enabled = 0;
909 pmap_pcid_enabled = 0;
918 int pat_table[PAT_INDEX_SIZE];
923 /* Bail if this CPU doesn't implement PAT. */
924 if ((cpu_feature & CPUID_PAT) == 0)
927 /* Set default PAT index table. */
928 for (i = 0; i < PAT_INDEX_SIZE; i++)
930 pat_table[PAT_WRITE_BACK] = 0;
931 pat_table[PAT_WRITE_THROUGH] = 1;
932 pat_table[PAT_UNCACHEABLE] = 3;
933 pat_table[PAT_WRITE_COMBINING] = 3;
934 pat_table[PAT_WRITE_PROTECTED] = 3;
935 pat_table[PAT_UNCACHED] = 3;
937 /* Initialize default PAT entries. */
938 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
939 PAT_VALUE(1, PAT_WRITE_THROUGH) |
940 PAT_VALUE(2, PAT_UNCACHED) |
941 PAT_VALUE(3, PAT_UNCACHEABLE) |
942 PAT_VALUE(4, PAT_WRITE_BACK) |
943 PAT_VALUE(5, PAT_WRITE_THROUGH) |
944 PAT_VALUE(6, PAT_UNCACHED) |
945 PAT_VALUE(7, PAT_UNCACHEABLE);
949 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
950 * Program 5 and 6 as WP and WC.
951 * Leave 4 and 7 as WB and UC.
953 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
954 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
955 PAT_VALUE(6, PAT_WRITE_COMBINING);
956 pat_table[PAT_UNCACHED] = 2;
957 pat_table[PAT_WRITE_PROTECTED] = 5;
958 pat_table[PAT_WRITE_COMBINING] = 6;
961 * Just replace PAT Index 2 with WC instead of UC-.
963 pat_msr &= ~PAT_MASK(2);
964 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
965 pat_table[PAT_WRITE_COMBINING] = 2;
970 load_cr4(cr4 & ~CR4_PGE);
972 /* Disable caches (CD = 1, NW = 0). */
974 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
976 /* Flushes caches and TLBs. */
980 /* Update PAT and index table. */
981 wrmsr(MSR_PAT, pat_msr);
982 for (i = 0; i < PAT_INDEX_SIZE; i++)
983 pat_index[i] = pat_table[i];
985 /* Flush caches and TLBs again. */
989 /* Restore caches and PGE. */
995 * Initialize a vm_page's machine-dependent fields.
998 pmap_page_init(vm_page_t m)
1001 TAILQ_INIT(&m->md.pv_list);
1002 m->md.pat_mode = PAT_WRITE_BACK;
1006 * Initialize the pmap module.
1007 * Called by vm_init, to initialize any structures that the pmap
1008 * system needs to map virtual memory.
1018 * Initialize the vm page array entries for the kernel pmap's
1021 for (i = 0; i < nkpt; i++) {
1022 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1023 KASSERT(mpte >= vm_page_array &&
1024 mpte < &vm_page_array[vm_page_array_size],
1025 ("pmap_init: page table page is out of range"));
1026 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1027 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1031 * If the kernel is running on a virtual machine, then it must assume
1032 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1033 * be prepared for the hypervisor changing the vendor and family that
1034 * are reported by CPUID. Consequently, the workaround for AMD Family
1035 * 10h Erratum 383 is enabled if the processor's feature set does not
1036 * include at least one feature that is only supported by older Intel
1037 * or newer AMD processors.
1039 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1040 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1041 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1043 workaround_erratum383 = 1;
1046 * Are large page mappings enabled?
1048 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1049 if (pg_ps_enabled) {
1050 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1051 ("pmap_init: can't assign to pagesizes[1]"));
1052 pagesizes[1] = NBPDR;
1056 * Initialize the pv chunk list mutex.
1058 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1061 * Initialize the pool of pv list locks.
1063 for (i = 0; i < NPV_LIST_LOCKS; i++)
1064 rw_init(&pv_list_locks[i], "pmap pv list");
1067 * Calculate the size of the pv head table for superpages.
1069 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1072 * Allocate memory for the pv head table for superpages.
1074 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1076 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1078 for (i = 0; i < pv_npg; i++)
1079 TAILQ_INIT(&pv_table[i].pv_list);
1082 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1083 "2MB page mapping counters");
1085 static u_long pmap_pde_demotions;
1086 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1087 &pmap_pde_demotions, 0, "2MB page demotions");
1089 static u_long pmap_pde_mappings;
1090 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1091 &pmap_pde_mappings, 0, "2MB page mappings");
1093 static u_long pmap_pde_p_failures;
1094 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1095 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1097 static u_long pmap_pde_promotions;
1098 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1099 &pmap_pde_promotions, 0, "2MB page promotions");
1101 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1102 "1GB page mapping counters");
1104 static u_long pmap_pdpe_demotions;
1105 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1106 &pmap_pdpe_demotions, 0, "1GB page demotions");
1108 /***************************************************
1109 * Low level helper routines.....
1110 ***************************************************/
1113 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1115 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1117 switch (pmap->pm_type) {
1120 /* Verify that both PAT bits are not set at the same time */
1121 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1122 ("Invalid PAT bits in entry %#lx", entry));
1124 /* Swap the PAT bits if one of them is set */
1125 if ((entry & x86_pat_bits) != 0)
1126 entry ^= x86_pat_bits;
1130 * Nothing to do - the memory attributes are represented
1131 * the same way for regular pages and superpages.
1135 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1142 * Determine the appropriate bits to set in a PTE or PDE for a specified
1146 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1148 int cache_bits, pat_flag, pat_idx;
1150 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1151 panic("Unknown caching mode %d\n", mode);
1153 switch (pmap->pm_type) {
1156 /* The PAT bit is different for PTE's and PDE's. */
1157 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1159 /* Map the caching mode to a PAT index. */
1160 pat_idx = pat_index[mode];
1162 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1165 cache_bits |= pat_flag;
1167 cache_bits |= PG_NC_PCD;
1169 cache_bits |= PG_NC_PWT;
1173 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1177 panic("unsupported pmap type %d", pmap->pm_type);
1180 return (cache_bits);
1184 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1188 switch (pmap->pm_type) {
1191 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1194 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1197 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1203 static __inline boolean_t
1204 pmap_ps_enabled(pmap_t pmap)
1207 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1211 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1214 switch (pmap->pm_type) {
1221 * This is a little bogus since the generation number is
1222 * supposed to be bumped up when a region of the address
1223 * space is invalidated in the page tables.
1225 * In this case the old PDE entry is valid but yet we want
1226 * to make sure that any mappings using the old entry are
1227 * invalidated in the TLB.
1229 * The reason this works as expected is because we rendezvous
1230 * "all" host cpus and force any vcpu context to exit as a
1233 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1236 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1238 pde_store(pde, newpde);
1242 * After changing the page size for the specified virtual address in the page
1243 * table, flush the corresponding entries from the processor's TLB. Only the
1244 * calling processor's TLB is affected.
1246 * The calling thread must be pinned to a processor.
1249 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1253 if (pmap_type_guest(pmap))
1256 KASSERT(pmap->pm_type == PT_X86,
1257 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1259 PG_G = pmap_global_bit(pmap);
1261 if ((newpde & PG_PS) == 0)
1262 /* Demotion: flush a specific 2MB page mapping. */
1264 else if ((newpde & PG_G) == 0)
1266 * Promotion: flush every 4KB page mapping from the TLB
1267 * because there are too many to flush individually.
1272 * Promotion: flush every 4KB page mapping from the TLB,
1273 * including any global (PG_G) mappings.
1281 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1283 struct invpcid_descr d;
1286 if (invpcid_works) {
1287 d.pcid = pmap->pm_pcid;
1290 invpcid(&d, INVPCID_ADDR);
1296 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1298 load_cr3(cr3 | CR3_PCID_SAVE);
1303 * For SMP, these functions have to use the IPI mechanism for coherence.
1305 * N.B.: Before calling any of the following TLB invalidation functions,
1306 * the calling processor must ensure that all stores updating a non-
1307 * kernel page table are globally performed. Otherwise, another
1308 * processor could cache an old, pre-update entry without being
1309 * invalidated. This can happen one of two ways: (1) The pmap becomes
1310 * active on another processor after its pm_active field is checked by
1311 * one of the following functions but before a store updating the page
1312 * table is globally performed. (2) The pmap becomes active on another
1313 * processor before its pm_active field is checked but due to
1314 * speculative loads one of the following functions stills reads the
1315 * pmap as inactive on the other processor.
1317 * The kernel page table is exempt because its pm_active field is
1318 * immutable. The kernel page table is always active on every
1323 * Interrupt the cpus that are executing in the guest context.
1324 * This will force the vcpu to exit and the cached EPT mappings
1325 * will be invalidated by the host before the next vmresume.
1327 static __inline void
1328 pmap_invalidate_ept(pmap_t pmap)
1333 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1334 ("pmap_invalidate_ept: absurd pm_active"));
1337 * The TLB mappings associated with a vcpu context are not
1338 * flushed each time a different vcpu is chosen to execute.
1340 * This is in contrast with a process's vtop mappings that
1341 * are flushed from the TLB on each context switch.
1343 * Therefore we need to do more than just a TLB shootdown on
1344 * the active cpus in 'pmap->pm_active'. To do this we keep
1345 * track of the number of invalidations performed on this pmap.
1347 * Each vcpu keeps a cache of this counter and compares it
1348 * just before a vmresume. If the counter is out-of-date an
1349 * invept will be done to flush stale mappings from the TLB.
1351 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1354 * Force the vcpu to exit and trap back into the hypervisor.
1356 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1357 ipi_selected(pmap->pm_active, ipinum);
1362 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1364 cpuset_t other_cpus;
1367 if (pmap_type_guest(pmap)) {
1368 pmap_invalidate_ept(pmap);
1372 KASSERT(pmap->pm_type == PT_X86,
1373 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1376 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1377 if (!pmap_pcid_enabled) {
1380 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1381 if (pmap == PCPU_GET(curpmap))
1384 pmap_invalidate_page_pcid(pmap, va);
1389 smp_invlpg(pmap, va);
1391 cpuid = PCPU_GET(cpuid);
1392 other_cpus = all_cpus;
1393 CPU_CLR(cpuid, &other_cpus);
1394 if (CPU_ISSET(cpuid, &pmap->pm_active))
1396 else if (pmap_pcid_enabled) {
1397 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1398 pmap_invalidate_page_pcid(pmap, va);
1402 if (pmap_pcid_enabled)
1403 CPU_AND(&other_cpus, &pmap->pm_save);
1405 CPU_AND(&other_cpus, &pmap->pm_active);
1406 if (!CPU_EMPTY(&other_cpus))
1407 smp_masked_invlpg(other_cpus, pmap, va);
1413 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1415 struct invpcid_descr d;
1419 if (invpcid_works) {
1420 d.pcid = pmap->pm_pcid;
1422 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1424 invpcid(&d, INVPCID_ADDR);
1431 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1432 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1434 load_cr3(cr3 | CR3_PCID_SAVE);
1439 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1441 cpuset_t other_cpus;
1445 if (pmap_type_guest(pmap)) {
1446 pmap_invalidate_ept(pmap);
1450 KASSERT(pmap->pm_type == PT_X86,
1451 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1454 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1455 if (!pmap_pcid_enabled) {
1456 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1459 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1460 if (pmap == PCPU_GET(curpmap)) {
1461 for (addr = sva; addr < eva;
1465 pmap_invalidate_range_pcid(pmap,
1472 smp_invlpg_range(pmap, sva, eva);
1474 cpuid = PCPU_GET(cpuid);
1475 other_cpus = all_cpus;
1476 CPU_CLR(cpuid, &other_cpus);
1477 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1478 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1480 } else if (pmap_pcid_enabled) {
1481 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1482 pmap_invalidate_range_pcid(pmap, sva, eva);
1486 if (pmap_pcid_enabled)
1487 CPU_AND(&other_cpus, &pmap->pm_save);
1489 CPU_AND(&other_cpus, &pmap->pm_active);
1490 if (!CPU_EMPTY(&other_cpus))
1491 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1497 pmap_invalidate_all(pmap_t pmap)
1499 cpuset_t other_cpus;
1500 struct invpcid_descr d;
1504 if (pmap_type_guest(pmap)) {
1505 pmap_invalidate_ept(pmap);
1509 KASSERT(pmap->pm_type == PT_X86,
1510 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1513 cpuid = PCPU_GET(cpuid);
1514 if (pmap == kernel_pmap ||
1515 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1516 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1517 if (invpcid_works) {
1518 bzero(&d, sizeof(d));
1519 invpcid(&d, INVPCID_CTXGLOB);
1523 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1524 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1527 other_cpus = all_cpus;
1528 CPU_CLR(cpuid, &other_cpus);
1531 * This logic is duplicated in the Xinvltlb shootdown
1534 if (pmap_pcid_enabled) {
1535 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1536 if (invpcid_works) {
1537 d.pcid = pmap->pm_pcid;
1540 invpcid(&d, INVPCID_CTX);
1546 * Bit 63 is clear, pcid TLB
1547 * entries are invalidated.
1549 load_cr3(pmap->pm_cr3);
1550 load_cr3(cr3 | CR3_PCID_SAVE);
1556 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1558 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1559 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1560 if (pmap_pcid_enabled)
1561 CPU_AND(&other_cpus, &pmap->pm_save);
1563 CPU_AND(&other_cpus, &pmap->pm_active);
1564 if (!CPU_EMPTY(&other_cpus))
1565 smp_masked_invltlb(other_cpus, pmap);
1571 pmap_invalidate_cache(void)
1581 cpuset_t invalidate; /* processors that invalidate their TLB */
1586 u_int store; /* processor that updates the PDE */
1590 pmap_update_pde_action(void *arg)
1592 struct pde_action *act = arg;
1594 if (act->store == PCPU_GET(cpuid))
1595 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1599 pmap_update_pde_teardown(void *arg)
1601 struct pde_action *act = arg;
1603 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1604 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1608 * Change the page size for the specified virtual address in a way that
1609 * prevents any possibility of the TLB ever having two entries that map the
1610 * same virtual address using different page sizes. This is the recommended
1611 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1612 * machine check exception for a TLB state that is improperly diagnosed as a
1616 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1618 struct pde_action act;
1619 cpuset_t active, other_cpus;
1623 cpuid = PCPU_GET(cpuid);
1624 other_cpus = all_cpus;
1625 CPU_CLR(cpuid, &other_cpus);
1626 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1629 active = pmap->pm_active;
1630 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1632 if (CPU_OVERLAP(&active, &other_cpus)) {
1634 act.invalidate = active;
1638 act.newpde = newpde;
1639 CPU_SET(cpuid, &active);
1640 smp_rendezvous_cpus(active,
1641 smp_no_rendevous_barrier, pmap_update_pde_action,
1642 pmap_update_pde_teardown, &act);
1644 pmap_update_pde_store(pmap, pde, newpde);
1645 if (CPU_ISSET(cpuid, &active))
1646 pmap_update_pde_invalidate(pmap, va, newpde);
1652 * Normal, non-SMP, invalidation functions.
1653 * We inline these within pmap.c for speed.
1656 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1659 switch (pmap->pm_type) {
1661 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1669 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type);
1674 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1678 switch (pmap->pm_type) {
1680 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1681 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1689 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type);
1694 pmap_invalidate_all(pmap_t pmap)
1697 switch (pmap->pm_type) {
1699 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1707 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type);
1712 pmap_invalidate_cache(void)
1719 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1722 pmap_update_pde_store(pmap, pde, newpde);
1723 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1724 pmap_update_pde_invalidate(pmap, va, newpde);
1726 CPU_ZERO(&pmap->pm_save);
1730 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1733 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1737 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1739 KASSERT((sva & PAGE_MASK) == 0,
1740 ("pmap_invalidate_cache_range: sva not page-aligned"));
1741 KASSERT((eva & PAGE_MASK) == 0,
1742 ("pmap_invalidate_cache_range: eva not page-aligned"));
1745 if ((cpu_feature & CPUID_SS) != 0 && !force)
1746 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1747 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1748 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1751 * XXX: Some CPUs fault, hang, or trash the local APIC
1752 * registers if we use CLFLUSH on the local APIC
1753 * range. The local APIC is always uncached, so we
1754 * don't need to flush for that range anyway.
1756 if (pmap_kextract(sva) == lapic_paddr)
1760 * Otherwise, do per-cache line flush. Use the mfence
1761 * instruction to insure that previous stores are
1762 * included in the write-back. The processor
1763 * propagates flush to other processors in the cache
1767 for (; sva < eva; sva += cpu_clflush_line_size)
1773 * No targeted cache flush methods are supported by CPU,
1774 * or the supplied range is bigger than 2MB.
1775 * Globally invalidate cache.
1777 pmap_invalidate_cache();
1782 * Remove the specified set of pages from the data and instruction caches.
1784 * In contrast to pmap_invalidate_cache_range(), this function does not
1785 * rely on the CPU's self-snoop feature, because it is intended for use
1786 * when moving pages into a different cache domain.
1789 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1791 vm_offset_t daddr, eva;
1794 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1795 (cpu_feature & CPUID_CLFSH) == 0)
1796 pmap_invalidate_cache();
1799 for (i = 0; i < count; i++) {
1800 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1801 eva = daddr + PAGE_SIZE;
1802 for (; daddr < eva; daddr += cpu_clflush_line_size)
1810 * Routine: pmap_extract
1812 * Extract the physical page address associated
1813 * with the given map/virtual_address pair.
1816 pmap_extract(pmap_t pmap, vm_offset_t va)
1820 pt_entry_t *pte, PG_V;
1824 PG_V = pmap_valid_bit(pmap);
1826 pdpe = pmap_pdpe(pmap, va);
1827 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1828 if ((*pdpe & PG_PS) != 0)
1829 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1831 pde = pmap_pdpe_to_pde(pdpe, va);
1832 if ((*pde & PG_V) != 0) {
1833 if ((*pde & PG_PS) != 0) {
1834 pa = (*pde & PG_PS_FRAME) |
1837 pte = pmap_pde_to_pte(pde, va);
1838 pa = (*pte & PG_FRAME) |
1849 * Routine: pmap_extract_and_hold
1851 * Atomically extract and hold the physical page
1852 * with the given pmap and virtual address pair
1853 * if that mapping permits the given protection.
1856 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1858 pd_entry_t pde, *pdep;
1859 pt_entry_t pte, PG_RW, PG_V;
1865 PG_RW = pmap_rw_bit(pmap);
1866 PG_V = pmap_valid_bit(pmap);
1869 pdep = pmap_pde(pmap, va);
1870 if (pdep != NULL && (pde = *pdep)) {
1872 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1873 if (vm_page_pa_tryrelock(pmap, (pde &
1874 PG_PS_FRAME) | (va & PDRMASK), &pa))
1876 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1881 pte = *pmap_pde_to_pte(pdep, va);
1883 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1884 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1887 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1898 pmap_kextract(vm_offset_t va)
1903 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1904 pa = DMAP_TO_PHYS(va);
1908 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1911 * Beware of a concurrent promotion that changes the
1912 * PDE at this point! For example, vtopte() must not
1913 * be used to access the PTE because it would use the
1914 * new PDE. It is, however, safe to use the old PDE
1915 * because the page table page is preserved by the
1918 pa = *pmap_pde_to_pte(&pde, va);
1919 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1925 /***************************************************
1926 * Low level mapping routines.....
1927 ***************************************************/
1930 * Add a wired page to the kva.
1931 * Note: not SMP coherent.
1934 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1939 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1942 static __inline void
1943 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1949 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1950 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1954 * Remove a page from the kernel pagetables.
1955 * Note: not SMP coherent.
1958 pmap_kremove(vm_offset_t va)
1967 * Used to map a range of physical addresses into kernel
1968 * virtual address space.
1970 * The value passed in '*virt' is a suggested virtual address for
1971 * the mapping. Architectures which can support a direct-mapped
1972 * physical to virtual region can return the appropriate address
1973 * within that region, leaving '*virt' unchanged. Other
1974 * architectures should map the pages starting at '*virt' and
1975 * update '*virt' with the first usable address after the mapped
1979 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1981 return PHYS_TO_DMAP(start);
1986 * Add a list of wired pages to the kva
1987 * this routine is only used for temporary
1988 * kernel mappings that do not need to have
1989 * page modification or references recorded.
1990 * Note that old mappings are simply written
1991 * over. The page *must* be wired.
1992 * Note: SMP coherent. Uses a ranged shootdown IPI.
1995 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1997 pt_entry_t *endpte, oldpte, pa, *pte;
2003 endpte = pte + count;
2004 while (pte < endpte) {
2006 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2007 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2008 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2010 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
2014 if (__predict_false((oldpte & X86_PG_V) != 0))
2015 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2020 * This routine tears out page mappings from the
2021 * kernel -- it is meant only for temporary mappings.
2022 * Note: SMP coherent. Uses a ranged shootdown IPI.
2025 pmap_qremove(vm_offset_t sva, int count)
2030 while (count-- > 0) {
2031 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2035 pmap_invalidate_range(kernel_pmap, sva, va);
2038 /***************************************************
2039 * Page table page management routines.....
2040 ***************************************************/
2041 static __inline void
2042 pmap_free_zero_pages(struct spglist *free)
2046 while ((m = SLIST_FIRST(free)) != NULL) {
2047 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2048 /* Preserve the page's PG_ZERO setting. */
2049 vm_page_free_toq(m);
2054 * Schedule the specified unused page table page to be freed. Specifically,
2055 * add the page to the specified list of pages that will be released to the
2056 * physical memory manager after the TLB has been updated.
2058 static __inline void
2059 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2060 boolean_t set_PG_ZERO)
2064 m->flags |= PG_ZERO;
2066 m->flags &= ~PG_ZERO;
2067 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2071 * Inserts the specified page table page into the specified pmap's collection
2072 * of idle page table pages. Each of a pmap's page table pages is responsible
2073 * for mapping a distinct range of virtual addresses. The pmap's collection is
2074 * ordered by this virtual address range.
2077 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2080 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2081 return (vm_radix_insert(&pmap->pm_root, mpte));
2085 * Looks for a page table page mapping the specified virtual address in the
2086 * specified pmap's collection of idle page table pages. Returns NULL if there
2087 * is no page table page corresponding to the specified virtual address.
2089 static __inline vm_page_t
2090 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2093 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2094 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2098 * Removes the specified page table page from the specified pmap's collection
2099 * of idle page table pages. The specified page table page must be a member of
2100 * the pmap's collection.
2102 static __inline void
2103 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2106 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2107 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2111 * Decrements a page table page's wire count, which is used to record the
2112 * number of valid page table entries within the page. If the wire count
2113 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2114 * page table page was unmapped and FALSE otherwise.
2116 static inline boolean_t
2117 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2121 if (m->wire_count == 0) {
2122 _pmap_unwire_ptp(pmap, va, m, free);
2129 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2132 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2134 * unmap the page table page
2136 if (m->pindex >= (NUPDE + NUPDPE)) {
2139 pml4 = pmap_pml4e(pmap, va);
2141 } else if (m->pindex >= NUPDE) {
2144 pdp = pmap_pdpe(pmap, va);
2149 pd = pmap_pde(pmap, va);
2152 pmap_resident_count_dec(pmap, 1);
2153 if (m->pindex < NUPDE) {
2154 /* We just released a PT, unhold the matching PD */
2157 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2158 pmap_unwire_ptp(pmap, va, pdpg, free);
2160 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2161 /* We just released a PD, unhold the matching PDP */
2164 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2165 pmap_unwire_ptp(pmap, va, pdppg, free);
2169 * This is a release store so that the ordinary store unmapping
2170 * the page table page is globally performed before TLB shoot-
2173 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2176 * Put page on a list so that it is released after
2177 * *ALL* TLB shootdown is done
2179 pmap_add_delayed_free_list(m, free, TRUE);
2183 * After removing a page table entry, this routine is used to
2184 * conditionally free the page, and manage the hold/wire counts.
2187 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2188 struct spglist *free)
2192 if (va >= VM_MAXUSER_ADDRESS)
2194 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2195 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2196 return (pmap_unwire_ptp(pmap, va, mpte, free));
2200 pmap_pinit0(pmap_t pmap)
2203 PMAP_LOCK_INIT(pmap);
2204 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2205 pmap->pm_cr3 = KPML4phys;
2206 pmap->pm_root.rt_root = 0;
2207 CPU_ZERO(&pmap->pm_active);
2208 CPU_ZERO(&pmap->pm_save);
2209 PCPU_SET(curpmap, pmap);
2210 TAILQ_INIT(&pmap->pm_pvchunk);
2211 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2212 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
2213 pmap->pm_flags = pmap_flags;
2217 * Initialize a preallocated and zeroed pmap structure,
2218 * such as one in a vmspace structure.
2221 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2224 vm_paddr_t pml4phys;
2228 * allocate the page directory page
2230 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2231 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2234 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2235 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2237 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2239 if ((pml4pg->flags & PG_ZERO) == 0)
2240 pagezero(pmap->pm_pml4);
2243 * Do not install the host kernel mappings in the nested page
2244 * tables. These mappings are meaningless in the guest physical
2247 if ((pmap->pm_type = pm_type) == PT_X86) {
2248 pmap->pm_cr3 = pml4phys;
2250 /* Wire in kernel global address entries. */
2251 for (i = 0; i < NKPML4E; i++) {
2252 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2253 X86_PG_RW | X86_PG_V | PG_U;
2255 for (i = 0; i < ndmpdpphys; i++) {
2256 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2257 X86_PG_RW | X86_PG_V | PG_U;
2260 /* install self-referential address mapping entry(s) */
2261 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2262 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2264 if (pmap_pcid_enabled) {
2265 pmap->pm_pcid = alloc_unr(&pcid_unr);
2266 if (pmap->pm_pcid != -1)
2267 pmap->pm_cr3 |= pmap->pm_pcid;
2271 pmap->pm_root.rt_root = 0;
2272 CPU_ZERO(&pmap->pm_active);
2273 TAILQ_INIT(&pmap->pm_pvchunk);
2274 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2275 pmap->pm_flags = flags;
2276 pmap->pm_eptgen = 0;
2277 CPU_ZERO(&pmap->pm_save);
2283 pmap_pinit(pmap_t pmap)
2286 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2290 * This routine is called if the desired page table page does not exist.
2292 * If page table page allocation fails, this routine may sleep before
2293 * returning NULL. It sleeps only if a lock pointer was given.
2295 * Note: If a page allocation fails at page table level two or three,
2296 * one or two pages may be held during the wait, only to be released
2297 * afterwards. This conservative approach is easily argued to avoid
2301 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2303 vm_page_t m, pdppg, pdpg;
2304 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2306 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2308 PG_A = pmap_accessed_bit(pmap);
2309 PG_M = pmap_modified_bit(pmap);
2310 PG_V = pmap_valid_bit(pmap);
2311 PG_RW = pmap_rw_bit(pmap);
2314 * Allocate a page table page.
2316 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2317 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2318 if (lockp != NULL) {
2319 RELEASE_PV_LIST_LOCK(lockp);
2321 rw_runlock(&pvh_global_lock);
2323 rw_rlock(&pvh_global_lock);
2328 * Indicate the need to retry. While waiting, the page table
2329 * page may have been allocated.
2333 if ((m->flags & PG_ZERO) == 0)
2337 * Map the pagetable page into the process address space, if
2338 * it isn't already there.
2341 if (ptepindex >= (NUPDE + NUPDPE)) {
2343 vm_pindex_t pml4index;
2345 /* Wire up a new PDPE page */
2346 pml4index = ptepindex - (NUPDE + NUPDPE);
2347 pml4 = &pmap->pm_pml4[pml4index];
2348 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2350 } else if (ptepindex >= NUPDE) {
2351 vm_pindex_t pml4index;
2352 vm_pindex_t pdpindex;
2356 /* Wire up a new PDE page */
2357 pdpindex = ptepindex - NUPDE;
2358 pml4index = pdpindex >> NPML4EPGSHIFT;
2360 pml4 = &pmap->pm_pml4[pml4index];
2361 if ((*pml4 & PG_V) == 0) {
2362 /* Have to allocate a new pdp, recurse */
2363 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2366 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2367 vm_page_free_zero(m);
2371 /* Add reference to pdp page */
2372 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2373 pdppg->wire_count++;
2375 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2377 /* Now find the pdp page */
2378 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2379 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2382 vm_pindex_t pml4index;
2383 vm_pindex_t pdpindex;
2388 /* Wire up a new PTE page */
2389 pdpindex = ptepindex >> NPDPEPGSHIFT;
2390 pml4index = pdpindex >> NPML4EPGSHIFT;
2392 /* First, find the pdp and check that its valid. */
2393 pml4 = &pmap->pm_pml4[pml4index];
2394 if ((*pml4 & PG_V) == 0) {
2395 /* Have to allocate a new pd, recurse */
2396 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2399 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2400 vm_page_free_zero(m);
2403 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2404 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2406 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2407 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2408 if ((*pdp & PG_V) == 0) {
2409 /* Have to allocate a new pd, recurse */
2410 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2413 atomic_subtract_int(&vm_cnt.v_wire_count,
2415 vm_page_free_zero(m);
2419 /* Add reference to the pd page */
2420 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2424 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2426 /* Now we know where the page directory page is */
2427 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2428 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2431 pmap_resident_count_inc(pmap, 1);
2437 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2439 vm_pindex_t pdpindex, ptepindex;
2440 pdp_entry_t *pdpe, PG_V;
2443 PG_V = pmap_valid_bit(pmap);
2446 pdpe = pmap_pdpe(pmap, va);
2447 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2448 /* Add a reference to the pd page. */
2449 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2452 /* Allocate a pd page. */
2453 ptepindex = pmap_pde_pindex(va);
2454 pdpindex = ptepindex >> NPDPEPGSHIFT;
2455 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2456 if (pdpg == NULL && lockp != NULL)
2463 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2465 vm_pindex_t ptepindex;
2466 pd_entry_t *pd, PG_V;
2469 PG_V = pmap_valid_bit(pmap);
2472 * Calculate pagetable page index
2474 ptepindex = pmap_pde_pindex(va);
2477 * Get the page directory entry
2479 pd = pmap_pde(pmap, va);
2482 * This supports switching from a 2MB page to a
2485 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2486 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2488 * Invalidation of the 2MB page mapping may have caused
2489 * the deallocation of the underlying PD page.
2496 * If the page table page is mapped, we just increment the
2497 * hold count, and activate it.
2499 if (pd != NULL && (*pd & PG_V) != 0) {
2500 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2504 * Here if the pte page isn't mapped, or if it has been
2507 m = _pmap_allocpte(pmap, ptepindex, lockp);
2508 if (m == NULL && lockp != NULL)
2515 /***************************************************
2516 * Pmap allocation/deallocation routines.
2517 ***************************************************/
2520 * Release any resources held by the given physical map.
2521 * Called when a pmap initialized by pmap_pinit is being released.
2522 * Should only be called if the map contains no valid mappings.
2525 pmap_release(pmap_t pmap)
2530 KASSERT(pmap->pm_stats.resident_count == 0,
2531 ("pmap_release: pmap resident count %ld != 0",
2532 pmap->pm_stats.resident_count));
2533 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2534 ("pmap_release: pmap has reserved page table page(s)"));
2536 if (pmap_pcid_enabled) {
2538 * Invalidate any left TLB entries, to allow the reuse
2541 pmap_invalidate_all(pmap);
2544 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2546 for (i = 0; i < NKPML4E; i++) /* KVA */
2547 pmap->pm_pml4[KPML4BASE + i] = 0;
2548 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2549 pmap->pm_pml4[DMPML4I + i] = 0;
2550 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2553 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2554 vm_page_free_zero(m);
2555 if (pmap->pm_pcid != -1)
2556 free_unr(&pcid_unr, pmap->pm_pcid);
2560 kvm_size(SYSCTL_HANDLER_ARGS)
2562 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2564 return sysctl_handle_long(oidp, &ksize, 0, req);
2566 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2567 0, 0, kvm_size, "LU", "Size of KVM");
2570 kvm_free(SYSCTL_HANDLER_ARGS)
2572 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2574 return sysctl_handle_long(oidp, &kfree, 0, req);
2576 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2577 0, 0, kvm_free, "LU", "Amount of KVM free");
2580 * grow the number of kernel page table entries, if needed
2583 pmap_growkernel(vm_offset_t addr)
2587 pd_entry_t *pde, newpdir;
2590 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2593 * Return if "addr" is within the range of kernel page table pages
2594 * that were preallocated during pmap bootstrap. Moreover, leave
2595 * "kernel_vm_end" and the kernel page table as they were.
2597 * The correctness of this action is based on the following
2598 * argument: vm_map_insert() allocates contiguous ranges of the
2599 * kernel virtual address space. It calls this function if a range
2600 * ends after "kernel_vm_end". If the kernel is mapped between
2601 * "kernel_vm_end" and "addr", then the range cannot begin at
2602 * "kernel_vm_end". In fact, its beginning address cannot be less
2603 * than the kernel. Thus, there is no immediate need to allocate
2604 * any new kernel page table pages between "kernel_vm_end" and
2607 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2610 addr = roundup2(addr, NBPDR);
2611 if (addr - 1 >= kernel_map->max_offset)
2612 addr = kernel_map->max_offset;
2613 while (kernel_vm_end < addr) {
2614 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2615 if ((*pdpe & X86_PG_V) == 0) {
2616 /* We need a new PDP entry */
2617 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2618 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2619 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2621 panic("pmap_growkernel: no memory to grow kernel");
2622 if ((nkpg->flags & PG_ZERO) == 0)
2623 pmap_zero_page(nkpg);
2624 paddr = VM_PAGE_TO_PHYS(nkpg);
2625 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2626 X86_PG_A | X86_PG_M);
2627 continue; /* try again */
2629 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2630 if ((*pde & X86_PG_V) != 0) {
2631 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2632 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2633 kernel_vm_end = kernel_map->max_offset;
2639 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2640 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2643 panic("pmap_growkernel: no memory to grow kernel");
2644 if ((nkpg->flags & PG_ZERO) == 0)
2645 pmap_zero_page(nkpg);
2646 paddr = VM_PAGE_TO_PHYS(nkpg);
2647 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2648 pde_store(pde, newpdir);
2650 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2651 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2652 kernel_vm_end = kernel_map->max_offset;
2659 /***************************************************
2660 * page management routines.
2661 ***************************************************/
2663 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2664 CTASSERT(_NPCM == 3);
2665 CTASSERT(_NPCPV == 168);
2667 static __inline struct pv_chunk *
2668 pv_to_chunk(pv_entry_t pv)
2671 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2674 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2676 #define PC_FREE0 0xfffffffffffffffful
2677 #define PC_FREE1 0xfffffffffffffffful
2678 #define PC_FREE2 0x000000fffffffffful
2680 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2683 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2685 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2686 "Current number of pv entry chunks");
2687 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2688 "Current number of pv entry chunks allocated");
2689 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2690 "Current number of pv entry chunks frees");
2691 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2692 "Number of times tried to get a chunk page but failed.");
2694 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2695 static int pv_entry_spare;
2697 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2698 "Current number of pv entry frees");
2699 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2700 "Current number of pv entry allocs");
2701 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2702 "Current number of pv entries");
2703 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2704 "Current number of spare pv entries");
2708 * We are in a serious low memory condition. Resort to
2709 * drastic measures to free some pages so we can allocate
2710 * another pv entry chunk.
2712 * Returns NULL if PV entries were reclaimed from the specified pmap.
2714 * We do not, however, unmap 2mpages because subsequent accesses will
2715 * allocate per-page pv entries until repromotion occurs, thereby
2716 * exacerbating the shortage of free pv entries.
2719 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2721 struct pch new_tail;
2722 struct pv_chunk *pc;
2723 struct md_page *pvh;
2726 pt_entry_t *pte, tpte;
2727 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2731 struct spglist free;
2733 int bit, field, freed;
2735 rw_assert(&pvh_global_lock, RA_LOCKED);
2736 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2737 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2740 PG_G = PG_A = PG_M = PG_RW = 0;
2742 TAILQ_INIT(&new_tail);
2743 mtx_lock(&pv_chunks_mutex);
2744 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2745 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2746 mtx_unlock(&pv_chunks_mutex);
2747 if (pmap != pc->pc_pmap) {
2749 pmap_invalidate_all(pmap);
2750 if (pmap != locked_pmap)
2754 /* Avoid deadlock and lock recursion. */
2755 if (pmap > locked_pmap) {
2756 RELEASE_PV_LIST_LOCK(lockp);
2758 } else if (pmap != locked_pmap &&
2759 !PMAP_TRYLOCK(pmap)) {
2761 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2762 mtx_lock(&pv_chunks_mutex);
2765 PG_G = pmap_global_bit(pmap);
2766 PG_A = pmap_accessed_bit(pmap);
2767 PG_M = pmap_modified_bit(pmap);
2768 PG_RW = pmap_rw_bit(pmap);
2772 * Destroy every non-wired, 4 KB page mapping in the chunk.
2775 for (field = 0; field < _NPCM; field++) {
2776 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2777 inuse != 0; inuse &= ~(1UL << bit)) {
2779 pv = &pc->pc_pventry[field * 64 + bit];
2781 pde = pmap_pde(pmap, va);
2782 if ((*pde & PG_PS) != 0)
2784 pte = pmap_pde_to_pte(pde, va);
2785 if ((*pte & PG_W) != 0)
2787 tpte = pte_load_clear(pte);
2788 if ((tpte & PG_G) != 0)
2789 pmap_invalidate_page(pmap, va);
2790 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2791 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2793 if ((tpte & PG_A) != 0)
2794 vm_page_aflag_set(m, PGA_REFERENCED);
2795 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2796 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2798 if (TAILQ_EMPTY(&m->md.pv_list) &&
2799 (m->flags & PG_FICTITIOUS) == 0) {
2800 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2801 if (TAILQ_EMPTY(&pvh->pv_list)) {
2802 vm_page_aflag_clear(m,
2806 pc->pc_map[field] |= 1UL << bit;
2807 pmap_unuse_pt(pmap, va, *pde, &free);
2812 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2813 mtx_lock(&pv_chunks_mutex);
2816 /* Every freed mapping is for a 4 KB page. */
2817 pmap_resident_count_dec(pmap, freed);
2818 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2819 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2820 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2821 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2822 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2823 pc->pc_map[2] == PC_FREE2) {
2824 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2825 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2826 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2827 /* Entire chunk is free; return it. */
2828 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2829 dump_drop_page(m_pc->phys_addr);
2830 mtx_lock(&pv_chunks_mutex);
2833 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2834 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2835 mtx_lock(&pv_chunks_mutex);
2836 /* One freed pv entry in locked_pmap is sufficient. */
2837 if (pmap == locked_pmap)
2840 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2841 mtx_unlock(&pv_chunks_mutex);
2843 pmap_invalidate_all(pmap);
2844 if (pmap != locked_pmap)
2847 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2848 m_pc = SLIST_FIRST(&free);
2849 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2850 /* Recycle a freed page table page. */
2851 m_pc->wire_count = 1;
2852 atomic_add_int(&vm_cnt.v_wire_count, 1);
2854 pmap_free_zero_pages(&free);
2859 * free the pv_entry back to the free list
2862 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2864 struct pv_chunk *pc;
2865 int idx, field, bit;
2867 rw_assert(&pvh_global_lock, RA_LOCKED);
2868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2869 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2870 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2871 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2872 pc = pv_to_chunk(pv);
2873 idx = pv - &pc->pc_pventry[0];
2876 pc->pc_map[field] |= 1ul << bit;
2877 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2878 pc->pc_map[2] != PC_FREE2) {
2879 /* 98% of the time, pc is already at the head of the list. */
2880 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2881 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2882 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2886 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2891 free_pv_chunk(struct pv_chunk *pc)
2895 mtx_lock(&pv_chunks_mutex);
2896 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2897 mtx_unlock(&pv_chunks_mutex);
2898 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2899 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2900 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2901 /* entire chunk is free, return it */
2902 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2903 dump_drop_page(m->phys_addr);
2904 vm_page_unwire(m, PQ_INACTIVE);
2909 * Returns a new PV entry, allocating a new PV chunk from the system when
2910 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2911 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2914 * The given PV list lock may be released.
2917 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2921 struct pv_chunk *pc;
2924 rw_assert(&pvh_global_lock, RA_LOCKED);
2925 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2926 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2928 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2930 for (field = 0; field < _NPCM; field++) {
2931 if (pc->pc_map[field]) {
2932 bit = bsfq(pc->pc_map[field]);
2936 if (field < _NPCM) {
2937 pv = &pc->pc_pventry[field * 64 + bit];
2938 pc->pc_map[field] &= ~(1ul << bit);
2939 /* If this was the last item, move it to tail */
2940 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2941 pc->pc_map[2] == 0) {
2942 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2943 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2946 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2947 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2951 /* No free items, allocate another chunk */
2952 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2955 if (lockp == NULL) {
2956 PV_STAT(pc_chunk_tryfail++);
2959 m = reclaim_pv_chunk(pmap, lockp);
2963 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2964 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2965 dump_add_page(m->phys_addr);
2966 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2968 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2969 pc->pc_map[1] = PC_FREE1;
2970 pc->pc_map[2] = PC_FREE2;
2971 mtx_lock(&pv_chunks_mutex);
2972 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2973 mtx_unlock(&pv_chunks_mutex);
2974 pv = &pc->pc_pventry[0];
2975 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2976 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2977 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2982 * Returns the number of one bits within the given PV chunk map element.
2985 popcnt_pc_map_elem(uint64_t elem)
2990 * This simple method of counting the one bits performs well because
2991 * the given element typically contains more zero bits than one bits.
2994 for (; elem != 0; elem &= elem - 1)
3000 * Ensure that the number of spare PV entries in the specified pmap meets or
3001 * exceeds the given count, "needed".
3003 * The given PV list lock may be released.
3006 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3008 struct pch new_tail;
3009 struct pv_chunk *pc;
3013 rw_assert(&pvh_global_lock, RA_LOCKED);
3014 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3015 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3018 * Newly allocated PV chunks must be stored in a private list until
3019 * the required number of PV chunks have been allocated. Otherwise,
3020 * reclaim_pv_chunk() could recycle one of these chunks. In
3021 * contrast, these chunks must be added to the pmap upon allocation.
3023 TAILQ_INIT(&new_tail);
3026 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3027 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
3028 free = popcnt_pc_map_elem(pc->pc_map[0]);
3029 free += popcnt_pc_map_elem(pc->pc_map[1]);
3030 free += popcnt_pc_map_elem(pc->pc_map[2]);
3032 free = popcntq(pc->pc_map[0]);
3033 free += popcntq(pc->pc_map[1]);
3034 free += popcntq(pc->pc_map[2]);
3039 if (avail >= needed)
3042 for (; avail < needed; avail += _NPCPV) {
3043 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3046 m = reclaim_pv_chunk(pmap, lockp);
3050 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3051 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3052 dump_add_page(m->phys_addr);
3053 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3055 pc->pc_map[0] = PC_FREE0;
3056 pc->pc_map[1] = PC_FREE1;
3057 pc->pc_map[2] = PC_FREE2;
3058 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3059 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3060 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3062 if (!TAILQ_EMPTY(&new_tail)) {
3063 mtx_lock(&pv_chunks_mutex);
3064 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3065 mtx_unlock(&pv_chunks_mutex);
3070 * First find and then remove the pv entry for the specified pmap and virtual
3071 * address from the specified pv list. Returns the pv entry if found and NULL
3072 * otherwise. This operation can be performed on pv lists for either 4KB or
3073 * 2MB page mappings.
3075 static __inline pv_entry_t
3076 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3080 rw_assert(&pvh_global_lock, RA_LOCKED);
3081 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3082 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3083 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3092 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3093 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3094 * entries for each of the 4KB page mappings.
3097 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3098 struct rwlock **lockp)
3100 struct md_page *pvh;
3101 struct pv_chunk *pc;
3103 vm_offset_t va_last;
3107 rw_assert(&pvh_global_lock, RA_LOCKED);
3108 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3109 KASSERT((pa & PDRMASK) == 0,
3110 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3111 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3114 * Transfer the 2mpage's pv entry for this mapping to the first
3115 * page's pv list. Once this transfer begins, the pv list lock
3116 * must not be released until the last pv entry is reinstantiated.
3118 pvh = pa_to_pvh(pa);
3119 va = trunc_2mpage(va);
3120 pv = pmap_pvh_remove(pvh, pmap, va);
3121 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3122 m = PHYS_TO_VM_PAGE(pa);
3123 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3125 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3126 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3127 va_last = va + NBPDR - PAGE_SIZE;
3129 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3130 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3131 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3132 for (field = 0; field < _NPCM; field++) {
3133 while (pc->pc_map[field]) {
3134 bit = bsfq(pc->pc_map[field]);
3135 pc->pc_map[field] &= ~(1ul << bit);
3136 pv = &pc->pc_pventry[field * 64 + bit];
3140 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3141 ("pmap_pv_demote_pde: page %p is not managed", m));
3142 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3148 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3149 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3152 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3153 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3154 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3156 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3157 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3161 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3162 * replace the many pv entries for the 4KB page mappings by a single pv entry
3163 * for the 2MB page mapping.
3166 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3167 struct rwlock **lockp)
3169 struct md_page *pvh;
3171 vm_offset_t va_last;
3174 rw_assert(&pvh_global_lock, RA_LOCKED);
3175 KASSERT((pa & PDRMASK) == 0,
3176 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3177 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3180 * Transfer the first page's pv entry for this mapping to the 2mpage's
3181 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3182 * a transfer avoids the possibility that get_pv_entry() calls
3183 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3184 * mappings that is being promoted.
3186 m = PHYS_TO_VM_PAGE(pa);
3187 va = trunc_2mpage(va);
3188 pv = pmap_pvh_remove(&m->md, pmap, va);
3189 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3190 pvh = pa_to_pvh(pa);
3191 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3193 /* Free the remaining NPTEPG - 1 pv entries. */
3194 va_last = va + NBPDR - PAGE_SIZE;
3198 pmap_pvh_free(&m->md, pmap, va);
3199 } while (va < va_last);
3203 * First find and then destroy the pv entry for the specified pmap and virtual
3204 * address. This operation can be performed on pv lists for either 4KB or 2MB
3208 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3212 pv = pmap_pvh_remove(pvh, pmap, va);
3213 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3214 free_pv_entry(pmap, pv);
3218 * Conditionally create the PV entry for a 4KB page mapping if the required
3219 * memory can be allocated without resorting to reclamation.
3222 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3223 struct rwlock **lockp)
3227 rw_assert(&pvh_global_lock, RA_LOCKED);
3228 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3229 /* Pass NULL instead of the lock pointer to disable reclamation. */
3230 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3232 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3233 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3241 * Conditionally create the PV entry for a 2MB page mapping if the required
3242 * memory can be allocated without resorting to reclamation.
3245 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3246 struct rwlock **lockp)
3248 struct md_page *pvh;
3251 rw_assert(&pvh_global_lock, RA_LOCKED);
3252 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3253 /* Pass NULL instead of the lock pointer to disable reclamation. */
3254 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3256 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3257 pvh = pa_to_pvh(pa);
3258 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3266 * Fills a page table page with mappings to consecutive physical pages.
3269 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3273 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3275 newpte += PAGE_SIZE;
3280 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3281 * mapping is invalidated.
3284 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3286 struct rwlock *lock;
3290 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3297 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3298 struct rwlock **lockp)
3300 pd_entry_t newpde, oldpde;
3301 pt_entry_t *firstpte, newpte;
3302 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3305 struct spglist free;
3308 PG_G = pmap_global_bit(pmap);
3309 PG_A = pmap_accessed_bit(pmap);
3310 PG_M = pmap_modified_bit(pmap);
3311 PG_RW = pmap_rw_bit(pmap);
3312 PG_V = pmap_valid_bit(pmap);
3313 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3315 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3317 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3318 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3319 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3321 pmap_remove_pt_page(pmap, mpte);
3323 KASSERT((oldpde & PG_W) == 0,
3324 ("pmap_demote_pde: page table page for a wired mapping"
3328 * Invalidate the 2MB page mapping and return "failure" if the
3329 * mapping was never accessed or the allocation of the new
3330 * page table page fails. If the 2MB page mapping belongs to
3331 * the direct map region of the kernel's address space, then
3332 * the page allocation request specifies the highest possible
3333 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3334 * normal. Page table pages are preallocated for every other
3335 * part of the kernel address space, so the direct map region
3336 * is the only part of the kernel address space that must be
3339 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3340 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3341 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3342 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3344 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3346 pmap_invalidate_page(pmap, trunc_2mpage(va));
3347 pmap_free_zero_pages(&free);
3348 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3349 " in pmap %p", va, pmap);
3352 if (va < VM_MAXUSER_ADDRESS)
3353 pmap_resident_count_inc(pmap, 1);
3355 mptepa = VM_PAGE_TO_PHYS(mpte);
3356 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3357 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3358 KASSERT((oldpde & PG_A) != 0,
3359 ("pmap_demote_pde: oldpde is missing PG_A"));
3360 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3361 ("pmap_demote_pde: oldpde is missing PG_M"));
3362 newpte = oldpde & ~PG_PS;
3363 newpte = pmap_swap_pat(pmap, newpte);
3366 * If the page table page is new, initialize it.
3368 if (mpte->wire_count == 1) {
3369 mpte->wire_count = NPTEPG;
3370 pmap_fill_ptp(firstpte, newpte);
3372 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3373 ("pmap_demote_pde: firstpte and newpte map different physical"
3377 * If the mapping has changed attributes, update the page table
3380 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3381 pmap_fill_ptp(firstpte, newpte);
3384 * The spare PV entries must be reserved prior to demoting the
3385 * mapping, that is, prior to changing the PDE. Otherwise, the state
3386 * of the PDE and the PV lists will be inconsistent, which can result
3387 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3388 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3389 * PV entry for the 2MB page mapping that is being demoted.
3391 if ((oldpde & PG_MANAGED) != 0)
3392 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3395 * Demote the mapping. This pmap is locked. The old PDE has
3396 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3397 * set. Thus, there is no danger of a race with another
3398 * processor changing the setting of PG_A and/or PG_M between
3399 * the read above and the store below.
3401 if (workaround_erratum383)
3402 pmap_update_pde(pmap, va, pde, newpde);
3404 pde_store(pde, newpde);
3407 * Invalidate a stale recursive mapping of the page table page.
3409 if (va >= VM_MAXUSER_ADDRESS)
3410 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3413 * Demote the PV entry.
3415 if ((oldpde & PG_MANAGED) != 0)
3416 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3418 atomic_add_long(&pmap_pde_demotions, 1);
3419 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3420 " in pmap %p", va, pmap);
3425 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3428 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3434 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3435 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3436 mpte = pmap_lookup_pt_page(pmap, va);
3438 panic("pmap_remove_kernel_pde: Missing pt page.");
3440 pmap_remove_pt_page(pmap, mpte);
3441 mptepa = VM_PAGE_TO_PHYS(mpte);
3442 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3445 * Initialize the page table page.
3447 pagezero((void *)PHYS_TO_DMAP(mptepa));
3450 * Demote the mapping.
3452 if (workaround_erratum383)
3453 pmap_update_pde(pmap, va, pde, newpde);
3455 pde_store(pde, newpde);
3458 * Invalidate a stale recursive mapping of the page table page.
3460 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3464 * pmap_remove_pde: do the things to unmap a superpage in a process
3467 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3468 struct spglist *free, struct rwlock **lockp)
3470 struct md_page *pvh;
3472 vm_offset_t eva, va;
3474 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3476 PG_G = pmap_global_bit(pmap);
3477 PG_A = pmap_accessed_bit(pmap);
3478 PG_M = pmap_modified_bit(pmap);
3479 PG_RW = pmap_rw_bit(pmap);
3481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3482 KASSERT((sva & PDRMASK) == 0,
3483 ("pmap_remove_pde: sva is not 2mpage aligned"));
3484 oldpde = pte_load_clear(pdq);
3486 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3489 * Machines that don't support invlpg, also don't support
3493 pmap_invalidate_page(kernel_pmap, sva);
3494 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3495 if (oldpde & PG_MANAGED) {
3496 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3497 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3498 pmap_pvh_free(pvh, pmap, sva);
3500 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3501 va < eva; va += PAGE_SIZE, m++) {
3502 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3505 vm_page_aflag_set(m, PGA_REFERENCED);
3506 if (TAILQ_EMPTY(&m->md.pv_list) &&
3507 TAILQ_EMPTY(&pvh->pv_list))
3508 vm_page_aflag_clear(m, PGA_WRITEABLE);
3511 if (pmap == kernel_pmap) {
3512 pmap_remove_kernel_pde(pmap, pdq, sva);
3514 mpte = pmap_lookup_pt_page(pmap, sva);
3516 pmap_remove_pt_page(pmap, mpte);
3517 pmap_resident_count_dec(pmap, 1);
3518 KASSERT(mpte->wire_count == NPTEPG,
3519 ("pmap_remove_pde: pte page wire count error"));
3520 mpte->wire_count = 0;
3521 pmap_add_delayed_free_list(mpte, free, FALSE);
3522 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
3525 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3529 * pmap_remove_pte: do the things to unmap a page in a process
3532 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3533 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3535 struct md_page *pvh;
3536 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3539 PG_A = pmap_accessed_bit(pmap);
3540 PG_M = pmap_modified_bit(pmap);
3541 PG_RW = pmap_rw_bit(pmap);
3543 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3544 oldpte = pte_load_clear(ptq);
3546 pmap->pm_stats.wired_count -= 1;
3547 pmap_resident_count_dec(pmap, 1);
3548 if (oldpte & PG_MANAGED) {
3549 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3550 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3553 vm_page_aflag_set(m, PGA_REFERENCED);
3554 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3555 pmap_pvh_free(&m->md, pmap, va);
3556 if (TAILQ_EMPTY(&m->md.pv_list) &&
3557 (m->flags & PG_FICTITIOUS) == 0) {
3558 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3559 if (TAILQ_EMPTY(&pvh->pv_list))
3560 vm_page_aflag_clear(m, PGA_WRITEABLE);
3563 return (pmap_unuse_pt(pmap, va, ptepde, free));
3567 * Remove a single page from a process address space
3570 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3571 struct spglist *free)
3573 struct rwlock *lock;
3574 pt_entry_t *pte, PG_V;
3576 PG_V = pmap_valid_bit(pmap);
3577 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3578 if ((*pde & PG_V) == 0)
3580 pte = pmap_pde_to_pte(pde, va);
3581 if ((*pte & PG_V) == 0)
3584 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3587 pmap_invalidate_page(pmap, va);
3591 * Remove the given range of addresses from the specified map.
3593 * It is assumed that the start and end are properly
3594 * rounded to the page size.
3597 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3599 struct rwlock *lock;
3600 vm_offset_t va, va_next;
3601 pml4_entry_t *pml4e;
3603 pd_entry_t ptpaddr, *pde;
3604 pt_entry_t *pte, PG_G, PG_V;
3605 struct spglist free;
3608 PG_G = pmap_global_bit(pmap);
3609 PG_V = pmap_valid_bit(pmap);
3612 * Perform an unsynchronized read. This is, however, safe.
3614 if (pmap->pm_stats.resident_count == 0)
3620 rw_rlock(&pvh_global_lock);
3624 * special handling of removing one page. a very
3625 * common operation and easy to short circuit some
3628 if (sva + PAGE_SIZE == eva) {
3629 pde = pmap_pde(pmap, sva);
3630 if (pde && (*pde & PG_PS) == 0) {
3631 pmap_remove_page(pmap, sva, pde, &free);
3637 for (; sva < eva; sva = va_next) {
3639 if (pmap->pm_stats.resident_count == 0)
3642 pml4e = pmap_pml4e(pmap, sva);
3643 if ((*pml4e & PG_V) == 0) {
3644 va_next = (sva + NBPML4) & ~PML4MASK;
3650 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3651 if ((*pdpe & PG_V) == 0) {
3652 va_next = (sva + NBPDP) & ~PDPMASK;
3659 * Calculate index for next page table.
3661 va_next = (sva + NBPDR) & ~PDRMASK;
3665 pde = pmap_pdpe_to_pde(pdpe, sva);
3669 * Weed out invalid mappings.
3675 * Check for large page.
3677 if ((ptpaddr & PG_PS) != 0) {
3679 * Are we removing the entire large page? If not,
3680 * demote the mapping and fall through.
3682 if (sva + NBPDR == va_next && eva >= va_next) {
3684 * The TLB entry for a PG_G mapping is
3685 * invalidated by pmap_remove_pde().
3687 if ((ptpaddr & PG_G) == 0)
3689 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3691 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3693 /* The large page mapping was destroyed. */
3700 * Limit our scan to either the end of the va represented
3701 * by the current page table page, or to the end of the
3702 * range being removed.
3708 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3711 if (va != va_next) {
3712 pmap_invalidate_range(pmap, va, sva);
3717 if ((*pte & PG_G) == 0)
3719 else if (va == va_next)
3721 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3728 pmap_invalidate_range(pmap, va, sva);
3734 pmap_invalidate_all(pmap);
3735 rw_runlock(&pvh_global_lock);
3737 pmap_free_zero_pages(&free);
3741 * Routine: pmap_remove_all
3743 * Removes this physical page from
3744 * all physical maps in which it resides.
3745 * Reflects back modify bits to the pager.
3748 * Original versions of this routine were very
3749 * inefficient because they iteratively called
3750 * pmap_remove (slow...)
3754 pmap_remove_all(vm_page_t m)
3756 struct md_page *pvh;
3759 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3762 struct spglist free;
3764 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3765 ("pmap_remove_all: page %p is not managed", m));
3767 rw_wlock(&pvh_global_lock);
3768 if ((m->flags & PG_FICTITIOUS) != 0)
3769 goto small_mappings;
3770 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3771 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3775 pde = pmap_pde(pmap, va);
3776 (void)pmap_demote_pde(pmap, pde, va);
3780 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3783 PG_A = pmap_accessed_bit(pmap);
3784 PG_M = pmap_modified_bit(pmap);
3785 PG_RW = pmap_rw_bit(pmap);
3786 pmap_resident_count_dec(pmap, 1);
3787 pde = pmap_pde(pmap, pv->pv_va);
3788 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3789 " a 2mpage in page %p's pv list", m));
3790 pte = pmap_pde_to_pte(pde, pv->pv_va);
3791 tpte = pte_load_clear(pte);
3793 pmap->pm_stats.wired_count--;
3795 vm_page_aflag_set(m, PGA_REFERENCED);
3798 * Update the vm_page_t clean and reference bits.
3800 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3802 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3803 pmap_invalidate_page(pmap, pv->pv_va);
3804 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3806 free_pv_entry(pmap, pv);
3809 vm_page_aflag_clear(m, PGA_WRITEABLE);
3810 rw_wunlock(&pvh_global_lock);
3811 pmap_free_zero_pages(&free);
3815 * pmap_protect_pde: do the things to protect a 2mpage in a process
3818 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3820 pd_entry_t newpde, oldpde;
3821 vm_offset_t eva, va;
3823 boolean_t anychanged;
3824 pt_entry_t PG_G, PG_M, PG_RW;
3826 PG_G = pmap_global_bit(pmap);
3827 PG_M = pmap_modified_bit(pmap);
3828 PG_RW = pmap_rw_bit(pmap);
3830 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3831 KASSERT((sva & PDRMASK) == 0,
3832 ("pmap_protect_pde: sva is not 2mpage aligned"));
3835 oldpde = newpde = *pde;
3836 if (oldpde & PG_MANAGED) {
3838 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3839 va < eva; va += PAGE_SIZE, m++)
3840 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3843 if ((prot & VM_PROT_WRITE) == 0)
3844 newpde &= ~(PG_RW | PG_M);
3845 if ((prot & VM_PROT_EXECUTE) == 0)
3847 if (newpde != oldpde) {
3848 if (!atomic_cmpset_long(pde, oldpde, newpde))
3851 pmap_invalidate_page(pmap, sva);
3855 return (anychanged);
3859 * Set the physical protection on the
3860 * specified range of this map as requested.
3863 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3865 vm_offset_t va_next;
3866 pml4_entry_t *pml4e;
3868 pd_entry_t ptpaddr, *pde;
3869 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3870 boolean_t anychanged, pv_lists_locked;
3872 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3873 if (prot == VM_PROT_NONE) {
3874 pmap_remove(pmap, sva, eva);
3878 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3879 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3882 PG_G = pmap_global_bit(pmap);
3883 PG_M = pmap_modified_bit(pmap);
3884 PG_V = pmap_valid_bit(pmap);
3885 PG_RW = pmap_rw_bit(pmap);
3886 pv_lists_locked = FALSE;
3891 for (; sva < eva; sva = va_next) {
3893 pml4e = pmap_pml4e(pmap, sva);
3894 if ((*pml4e & PG_V) == 0) {
3895 va_next = (sva + NBPML4) & ~PML4MASK;
3901 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3902 if ((*pdpe & PG_V) == 0) {
3903 va_next = (sva + NBPDP) & ~PDPMASK;
3909 va_next = (sva + NBPDR) & ~PDRMASK;
3913 pde = pmap_pdpe_to_pde(pdpe, sva);
3917 * Weed out invalid mappings.
3923 * Check for large page.
3925 if ((ptpaddr & PG_PS) != 0) {
3927 * Are we protecting the entire large page? If not,
3928 * demote the mapping and fall through.
3930 if (sva + NBPDR == va_next && eva >= va_next) {
3932 * The TLB entry for a PG_G mapping is
3933 * invalidated by pmap_protect_pde().
3935 if (pmap_protect_pde(pmap, pde, sva, prot))
3939 if (!pv_lists_locked) {
3940 pv_lists_locked = TRUE;
3941 if (!rw_try_rlock(&pvh_global_lock)) {
3943 pmap_invalidate_all(
3946 rw_rlock(&pvh_global_lock);
3950 if (!pmap_demote_pde(pmap, pde, sva)) {
3952 * The large page mapping was
3963 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3965 pt_entry_t obits, pbits;
3969 obits = pbits = *pte;
3970 if ((pbits & PG_V) == 0)
3973 if ((prot & VM_PROT_WRITE) == 0) {
3974 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3975 (PG_MANAGED | PG_M | PG_RW)) {
3976 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3979 pbits &= ~(PG_RW | PG_M);
3981 if ((prot & VM_PROT_EXECUTE) == 0)
3984 if (pbits != obits) {
3985 if (!atomic_cmpset_long(pte, obits, pbits))
3988 pmap_invalidate_page(pmap, sva);
3995 pmap_invalidate_all(pmap);
3996 if (pv_lists_locked)
3997 rw_runlock(&pvh_global_lock);
4002 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4003 * single page table page (PTP) to a single 2MB page mapping. For promotion
4004 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4005 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4006 * identical characteristics.
4009 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4010 struct rwlock **lockp)
4013 pt_entry_t *firstpte, oldpte, pa, *pte;
4014 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4015 vm_offset_t oldpteva;
4019 PG_A = pmap_accessed_bit(pmap);
4020 PG_G = pmap_global_bit(pmap);
4021 PG_M = pmap_modified_bit(pmap);
4022 PG_V = pmap_valid_bit(pmap);
4023 PG_RW = pmap_rw_bit(pmap);
4024 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4026 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4029 * Examine the first PTE in the specified PTP. Abort if this PTE is
4030 * either invalid, unused, or does not map the first 4KB physical page
4031 * within a 2MB page.
4033 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4036 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4037 atomic_add_long(&pmap_pde_p_failures, 1);
4038 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4039 " in pmap %p", va, pmap);
4042 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4044 * When PG_M is already clear, PG_RW can be cleared without
4045 * a TLB invalidation.
4047 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4053 * Examine each of the other PTEs in the specified PTP. Abort if this
4054 * PTE maps an unexpected 4KB physical page or does not have identical
4055 * characteristics to the first PTE.
4057 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4058 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4061 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4062 atomic_add_long(&pmap_pde_p_failures, 1);
4063 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4064 " in pmap %p", va, pmap);
4067 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4069 * When PG_M is already clear, PG_RW can be cleared
4070 * without a TLB invalidation.
4072 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4075 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
4077 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4078 " in pmap %p", oldpteva, pmap);
4080 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4081 atomic_add_long(&pmap_pde_p_failures, 1);
4082 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4083 " in pmap %p", va, pmap);
4090 * Save the page table page in its current state until the PDE
4091 * mapping the superpage is demoted by pmap_demote_pde() or
4092 * destroyed by pmap_remove_pde().
4094 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4095 KASSERT(mpte >= vm_page_array &&
4096 mpte < &vm_page_array[vm_page_array_size],
4097 ("pmap_promote_pde: page table page is out of range"));
4098 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4099 ("pmap_promote_pde: page table page's pindex is wrong"));
4100 if (pmap_insert_pt_page(pmap, mpte)) {
4101 atomic_add_long(&pmap_pde_p_failures, 1);
4103 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4109 * Promote the pv entries.
4111 if ((newpde & PG_MANAGED) != 0)
4112 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4115 * Propagate the PAT index to its proper position.
4117 newpde = pmap_swap_pat(pmap, newpde);
4120 * Map the superpage.
4122 if (workaround_erratum383)
4123 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4125 pde_store(pde, PG_PS | newpde);
4127 atomic_add_long(&pmap_pde_promotions, 1);
4128 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4129 " in pmap %p", va, pmap);
4133 * Insert the given physical page (p) at
4134 * the specified virtual address (v) in the
4135 * target physical map with the protection requested.
4137 * If specified, the page will be wired down, meaning
4138 * that the related pte can not be reclaimed.
4140 * NB: This is the only routine which MAY NOT lazy-evaluate
4141 * or lose information. That is, this routine must actually
4142 * insert this page into the given map NOW.
4145 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4146 u_int flags, int8_t psind __unused)
4148 struct rwlock *lock;
4150 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4151 pt_entry_t newpte, origpte;
4157 PG_A = pmap_accessed_bit(pmap);
4158 PG_G = pmap_global_bit(pmap);
4159 PG_M = pmap_modified_bit(pmap);
4160 PG_V = pmap_valid_bit(pmap);
4161 PG_RW = pmap_rw_bit(pmap);
4163 va = trunc_page(va);
4164 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4165 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4166 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4168 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4169 va >= kmi.clean_eva,
4170 ("pmap_enter: managed mapping within the clean submap"));
4171 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4172 VM_OBJECT_ASSERT_LOCKED(m->object);
4173 pa = VM_PAGE_TO_PHYS(m);
4174 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4175 if ((flags & VM_PROT_WRITE) != 0)
4177 if ((prot & VM_PROT_WRITE) != 0)
4179 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4180 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4181 if ((prot & VM_PROT_EXECUTE) == 0)
4183 if ((flags & PMAP_ENTER_WIRED) != 0)
4185 if (va < VM_MAXUSER_ADDRESS)
4187 if (pmap == kernel_pmap)
4189 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4192 * Set modified bit gratuitously for writeable mappings if
4193 * the page is unmanaged. We do not want to take a fault
4194 * to do the dirty bit accounting for these mappings.
4196 if ((m->oflags & VPO_UNMANAGED) != 0) {
4197 if ((newpte & PG_RW) != 0)
4204 rw_rlock(&pvh_global_lock);
4208 * In the case that a page table page is not
4209 * resident, we are creating it here.
4212 pde = pmap_pde(pmap, va);
4213 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4214 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4215 pte = pmap_pde_to_pte(pde, va);
4216 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4217 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4220 } else if (va < VM_MAXUSER_ADDRESS) {
4222 * Here if the pte page isn't mapped, or if it has been
4225 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4226 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4227 nosleep ? NULL : &lock);
4228 if (mpte == NULL && nosleep) {
4231 rw_runlock(&pvh_global_lock);
4233 return (KERN_RESOURCE_SHORTAGE);
4237 panic("pmap_enter: invalid page directory va=%#lx", va);
4242 * Is the specified virtual address already mapped?
4244 if ((origpte & PG_V) != 0) {
4246 * Wiring change, just update stats. We don't worry about
4247 * wiring PT pages as they remain resident as long as there
4248 * are valid mappings in them. Hence, if a user page is wired,
4249 * the PT page will be also.
4251 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4252 pmap->pm_stats.wired_count++;
4253 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4254 pmap->pm_stats.wired_count--;
4257 * Remove the extra PT page reference.
4261 KASSERT(mpte->wire_count > 0,
4262 ("pmap_enter: missing reference to page table page,"
4267 * Has the physical page changed?
4269 opa = origpte & PG_FRAME;
4272 * No, might be a protection or wiring change.
4274 if ((origpte & PG_MANAGED) != 0) {
4275 newpte |= PG_MANAGED;
4276 if ((newpte & PG_RW) != 0)
4277 vm_page_aflag_set(m, PGA_WRITEABLE);
4279 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4285 * Increment the counters.
4287 if ((newpte & PG_W) != 0)
4288 pmap->pm_stats.wired_count++;
4289 pmap_resident_count_inc(pmap, 1);
4293 * Enter on the PV list if part of our managed memory.
4295 if ((m->oflags & VPO_UNMANAGED) == 0) {
4296 newpte |= PG_MANAGED;
4297 pv = get_pv_entry(pmap, &lock);
4299 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4300 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4302 if ((newpte & PG_RW) != 0)
4303 vm_page_aflag_set(m, PGA_WRITEABLE);
4309 if ((origpte & PG_V) != 0) {
4311 origpte = pte_load_store(pte, newpte);
4312 opa = origpte & PG_FRAME;
4314 if ((origpte & PG_MANAGED) != 0) {
4315 om = PHYS_TO_VM_PAGE(opa);
4316 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4319 if ((origpte & PG_A) != 0)
4320 vm_page_aflag_set(om, PGA_REFERENCED);
4321 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4322 pmap_pvh_free(&om->md, pmap, va);
4323 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4324 TAILQ_EMPTY(&om->md.pv_list) &&
4325 ((om->flags & PG_FICTITIOUS) != 0 ||
4326 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4327 vm_page_aflag_clear(om, PGA_WRITEABLE);
4329 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4330 PG_RW)) == (PG_M | PG_RW)) {
4331 if ((origpte & PG_MANAGED) != 0)
4335 * Although the PTE may still have PG_RW set, TLB
4336 * invalidation may nonetheless be required because
4337 * the PTE no longer has PG_M set.
4339 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4341 * This PTE change does not require TLB invalidation.
4345 if ((origpte & PG_A) != 0)
4346 pmap_invalidate_page(pmap, va);
4348 pte_store(pte, newpte);
4353 * If both the page table page and the reservation are fully
4354 * populated, then attempt promotion.
4356 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4357 pmap_ps_enabled(pmap) &&
4358 (m->flags & PG_FICTITIOUS) == 0 &&
4359 vm_reserv_level_iffullpop(m) == 0)
4360 pmap_promote_pde(pmap, pde, va, &lock);
4364 rw_runlock(&pvh_global_lock);
4366 return (KERN_SUCCESS);
4370 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4371 * otherwise. Fails if (1) a page table page cannot be allocated without
4372 * blocking, (2) a mapping already exists at the specified virtual address, or
4373 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4376 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4377 struct rwlock **lockp)
4379 pd_entry_t *pde, newpde;
4382 struct spglist free;
4384 PG_V = pmap_valid_bit(pmap);
4385 rw_assert(&pvh_global_lock, RA_LOCKED);
4386 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4388 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4389 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4390 " in pmap %p", va, pmap);
4393 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4394 pde = &pde[pmap_pde_index(va)];
4395 if ((*pde & PG_V) != 0) {
4396 KASSERT(mpde->wire_count > 1,
4397 ("pmap_enter_pde: mpde's wire count is too low"));
4399 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4400 " in pmap %p", va, pmap);
4403 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4405 if ((m->oflags & VPO_UNMANAGED) == 0) {
4406 newpde |= PG_MANAGED;
4409 * Abort this mapping if its PV entry could not be created.
4411 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4414 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4415 pmap_invalidate_page(pmap, va);
4416 pmap_free_zero_pages(&free);
4418 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4419 " in pmap %p", va, pmap);
4423 if ((prot & VM_PROT_EXECUTE) == 0)
4425 if (va < VM_MAXUSER_ADDRESS)
4429 * Increment counters.
4431 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4434 * Map the superpage.
4436 pde_store(pde, newpde);
4438 atomic_add_long(&pmap_pde_mappings, 1);
4439 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4440 " in pmap %p", va, pmap);
4445 * Maps a sequence of resident pages belonging to the same object.
4446 * The sequence begins with the given page m_start. This page is
4447 * mapped at the given virtual address start. Each subsequent page is
4448 * mapped at a virtual address that is offset from start by the same
4449 * amount as the page is offset from m_start within the object. The
4450 * last page in the sequence is the page with the largest offset from
4451 * m_start that can be mapped at a virtual address less than the given
4452 * virtual address end. Not every virtual page between start and end
4453 * is mapped; only those for which a resident page exists with the
4454 * corresponding offset from m_start are mapped.
4457 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4458 vm_page_t m_start, vm_prot_t prot)
4460 struct rwlock *lock;
4463 vm_pindex_t diff, psize;
4465 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4467 psize = atop(end - start);
4471 rw_rlock(&pvh_global_lock);
4473 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4474 va = start + ptoa(diff);
4475 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4476 m->psind == 1 && pmap_ps_enabled(pmap) &&
4477 pmap_enter_pde(pmap, va, m, prot, &lock))
4478 m = &m[NBPDR / PAGE_SIZE - 1];
4480 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4482 m = TAILQ_NEXT(m, listq);
4486 rw_runlock(&pvh_global_lock);
4491 * this code makes some *MAJOR* assumptions:
4492 * 1. Current pmap & pmap exists.
4495 * 4. No page table pages.
4496 * but is *MUCH* faster than pmap_enter...
4500 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4502 struct rwlock *lock;
4505 rw_rlock(&pvh_global_lock);
4507 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4510 rw_runlock(&pvh_global_lock);
4515 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4516 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4518 struct spglist free;
4519 pt_entry_t *pte, PG_V;
4522 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4523 (m->oflags & VPO_UNMANAGED) != 0,
4524 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4525 PG_V = pmap_valid_bit(pmap);
4526 rw_assert(&pvh_global_lock, RA_LOCKED);
4527 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4530 * In the case that a page table page is not
4531 * resident, we are creating it here.
4533 if (va < VM_MAXUSER_ADDRESS) {
4534 vm_pindex_t ptepindex;
4538 * Calculate pagetable page index
4540 ptepindex = pmap_pde_pindex(va);
4541 if (mpte && (mpte->pindex == ptepindex)) {
4545 * Get the page directory entry
4547 ptepa = pmap_pde(pmap, va);
4550 * If the page table page is mapped, we just increment
4551 * the hold count, and activate it. Otherwise, we
4552 * attempt to allocate a page table page. If this
4553 * attempt fails, we don't retry. Instead, we give up.
4555 if (ptepa && (*ptepa & PG_V) != 0) {
4558 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4562 * Pass NULL instead of the PV list lock
4563 * pointer, because we don't intend to sleep.
4565 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4570 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4571 pte = &pte[pmap_pte_index(va)];
4585 * Enter on the PV list if part of our managed memory.
4587 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4588 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4591 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4592 pmap_invalidate_page(pmap, va);
4593 pmap_free_zero_pages(&free);
4601 * Increment counters
4603 pmap_resident_count_inc(pmap, 1);
4605 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4606 if ((prot & VM_PROT_EXECUTE) == 0)
4610 * Now validate mapping with RO protection
4612 if ((m->oflags & VPO_UNMANAGED) != 0)
4613 pte_store(pte, pa | PG_V | PG_U);
4615 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4620 * Make a temporary mapping for a physical address. This is only intended
4621 * to be used for panic dumps.
4624 pmap_kenter_temporary(vm_paddr_t pa, int i)
4628 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4629 pmap_kenter(va, pa);
4631 return ((void *)crashdumpmap);
4635 * This code maps large physical mmap regions into the
4636 * processor address space. Note that some shortcuts
4637 * are taken, but the code works.
4640 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4641 vm_pindex_t pindex, vm_size_t size)
4644 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4645 vm_paddr_t pa, ptepa;
4649 PG_A = pmap_accessed_bit(pmap);
4650 PG_M = pmap_modified_bit(pmap);
4651 PG_V = pmap_valid_bit(pmap);
4652 PG_RW = pmap_rw_bit(pmap);
4654 VM_OBJECT_ASSERT_WLOCKED(object);
4655 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4656 ("pmap_object_init_pt: non-device object"));
4657 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4658 if (!pmap_ps_enabled(pmap))
4660 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4662 p = vm_page_lookup(object, pindex);
4663 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4664 ("pmap_object_init_pt: invalid page %p", p));
4665 pat_mode = p->md.pat_mode;
4668 * Abort the mapping if the first page is not physically
4669 * aligned to a 2MB page boundary.
4671 ptepa = VM_PAGE_TO_PHYS(p);
4672 if (ptepa & (NBPDR - 1))
4676 * Skip the first page. Abort the mapping if the rest of
4677 * the pages are not physically contiguous or have differing
4678 * memory attributes.
4680 p = TAILQ_NEXT(p, listq);
4681 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4683 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4684 ("pmap_object_init_pt: invalid page %p", p));
4685 if (pa != VM_PAGE_TO_PHYS(p) ||
4686 pat_mode != p->md.pat_mode)
4688 p = TAILQ_NEXT(p, listq);
4692 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4693 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4694 * will not affect the termination of this loop.
4697 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4698 pa < ptepa + size; pa += NBPDR) {
4699 pdpg = pmap_allocpde(pmap, addr, NULL);
4702 * The creation of mappings below is only an
4703 * optimization. If a page directory page
4704 * cannot be allocated without blocking,
4705 * continue on to the next mapping rather than
4711 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4712 pde = &pde[pmap_pde_index(addr)];
4713 if ((*pde & PG_V) == 0) {
4714 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4715 PG_U | PG_RW | PG_V);
4716 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4717 atomic_add_long(&pmap_pde_mappings, 1);
4719 /* Continue on if the PDE is already valid. */
4721 KASSERT(pdpg->wire_count > 0,
4722 ("pmap_object_init_pt: missing reference "
4723 "to page directory page, va: 0x%lx", addr));
4732 * Clear the wired attribute from the mappings for the specified range of
4733 * addresses in the given pmap. Every valid mapping within that range
4734 * must have the wired attribute set. In contrast, invalid mappings
4735 * cannot have the wired attribute set, so they are ignored.
4737 * The wired attribute of the page table entry is not a hardware feature,
4738 * so there is no need to invalidate any TLB entries.
4741 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4743 vm_offset_t va_next;
4744 pml4_entry_t *pml4e;
4747 pt_entry_t *pte, PG_V;
4748 boolean_t pv_lists_locked;
4750 PG_V = pmap_valid_bit(pmap);
4751 pv_lists_locked = FALSE;
4754 for (; sva < eva; sva = va_next) {
4755 pml4e = pmap_pml4e(pmap, sva);
4756 if ((*pml4e & PG_V) == 0) {
4757 va_next = (sva + NBPML4) & ~PML4MASK;
4762 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4763 if ((*pdpe & PG_V) == 0) {
4764 va_next = (sva + NBPDP) & ~PDPMASK;
4769 va_next = (sva + NBPDR) & ~PDRMASK;
4772 pde = pmap_pdpe_to_pde(pdpe, sva);
4773 if ((*pde & PG_V) == 0)
4775 if ((*pde & PG_PS) != 0) {
4776 if ((*pde & PG_W) == 0)
4777 panic("pmap_unwire: pde %#jx is missing PG_W",
4781 * Are we unwiring the entire large page? If not,
4782 * demote the mapping and fall through.
4784 if (sva + NBPDR == va_next && eva >= va_next) {
4785 atomic_clear_long(pde, PG_W);
4786 pmap->pm_stats.wired_count -= NBPDR /
4790 if (!pv_lists_locked) {
4791 pv_lists_locked = TRUE;
4792 if (!rw_try_rlock(&pvh_global_lock)) {
4794 rw_rlock(&pvh_global_lock);
4799 if (!pmap_demote_pde(pmap, pde, sva))
4800 panic("pmap_unwire: demotion failed");
4805 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4807 if ((*pte & PG_V) == 0)
4809 if ((*pte & PG_W) == 0)
4810 panic("pmap_unwire: pte %#jx is missing PG_W",
4814 * PG_W must be cleared atomically. Although the pmap
4815 * lock synchronizes access to PG_W, another processor
4816 * could be setting PG_M and/or PG_A concurrently.
4818 atomic_clear_long(pte, PG_W);
4819 pmap->pm_stats.wired_count--;
4822 if (pv_lists_locked)
4823 rw_runlock(&pvh_global_lock);
4828 * Copy the range specified by src_addr/len
4829 * from the source map to the range dst_addr/len
4830 * in the destination map.
4832 * This routine is only advisory and need not do anything.
4836 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4837 vm_offset_t src_addr)
4839 struct rwlock *lock;
4840 struct spglist free;
4842 vm_offset_t end_addr = src_addr + len;
4843 vm_offset_t va_next;
4844 pt_entry_t PG_A, PG_M, PG_V;
4846 if (dst_addr != src_addr)
4849 if (dst_pmap->pm_type != src_pmap->pm_type)
4853 * EPT page table entries that require emulation of A/D bits are
4854 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4855 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4856 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4857 * implementations flag an EPT misconfiguration for exec-only
4858 * mappings we skip this function entirely for emulated pmaps.
4860 if (pmap_emulate_ad_bits(dst_pmap))
4864 rw_rlock(&pvh_global_lock);
4865 if (dst_pmap < src_pmap) {
4866 PMAP_LOCK(dst_pmap);
4867 PMAP_LOCK(src_pmap);
4869 PMAP_LOCK(src_pmap);
4870 PMAP_LOCK(dst_pmap);
4873 PG_A = pmap_accessed_bit(dst_pmap);
4874 PG_M = pmap_modified_bit(dst_pmap);
4875 PG_V = pmap_valid_bit(dst_pmap);
4877 for (addr = src_addr; addr < end_addr; addr = va_next) {
4878 pt_entry_t *src_pte, *dst_pte;
4879 vm_page_t dstmpde, dstmpte, srcmpte;
4880 pml4_entry_t *pml4e;
4882 pd_entry_t srcptepaddr, *pde;
4884 KASSERT(addr < UPT_MIN_ADDRESS,
4885 ("pmap_copy: invalid to pmap_copy page tables"));
4887 pml4e = pmap_pml4e(src_pmap, addr);
4888 if ((*pml4e & PG_V) == 0) {
4889 va_next = (addr + NBPML4) & ~PML4MASK;
4895 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4896 if ((*pdpe & PG_V) == 0) {
4897 va_next = (addr + NBPDP) & ~PDPMASK;
4903 va_next = (addr + NBPDR) & ~PDRMASK;
4907 pde = pmap_pdpe_to_pde(pdpe, addr);
4909 if (srcptepaddr == 0)
4912 if (srcptepaddr & PG_PS) {
4913 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4915 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4916 if (dstmpde == NULL)
4918 pde = (pd_entry_t *)
4919 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4920 pde = &pde[pmap_pde_index(addr)];
4921 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4922 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4923 PG_PS_FRAME, &lock))) {
4924 *pde = srcptepaddr & ~PG_W;
4925 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4927 dstmpde->wire_count--;
4931 srcptepaddr &= PG_FRAME;
4932 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4933 KASSERT(srcmpte->wire_count > 0,
4934 ("pmap_copy: source page table page is unused"));
4936 if (va_next > end_addr)
4939 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4940 src_pte = &src_pte[pmap_pte_index(addr)];
4942 while (addr < va_next) {
4946 * we only virtual copy managed pages
4948 if ((ptetemp & PG_MANAGED) != 0) {
4949 if (dstmpte != NULL &&
4950 dstmpte->pindex == pmap_pde_pindex(addr))
4951 dstmpte->wire_count++;
4952 else if ((dstmpte = pmap_allocpte(dst_pmap,
4953 addr, NULL)) == NULL)
4955 dst_pte = (pt_entry_t *)
4956 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4957 dst_pte = &dst_pte[pmap_pte_index(addr)];
4958 if (*dst_pte == 0 &&
4959 pmap_try_insert_pv_entry(dst_pmap, addr,
4960 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4963 * Clear the wired, modified, and
4964 * accessed (referenced) bits
4967 *dst_pte = ptetemp & ~(PG_W | PG_M |
4969 pmap_resident_count_inc(dst_pmap, 1);
4972 if (pmap_unwire_ptp(dst_pmap, addr,
4974 pmap_invalidate_page(dst_pmap,
4976 pmap_free_zero_pages(&free);
4980 if (dstmpte->wire_count >= srcmpte->wire_count)
4990 rw_runlock(&pvh_global_lock);
4991 PMAP_UNLOCK(src_pmap);
4992 PMAP_UNLOCK(dst_pmap);
4996 * pmap_zero_page zeros the specified hardware page by mapping
4997 * the page into KVM and using bzero to clear its contents.
5000 pmap_zero_page(vm_page_t m)
5002 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5004 pagezero((void *)va);
5008 * pmap_zero_page_area zeros the specified hardware page by mapping
5009 * the page into KVM and using bzero to clear its contents.
5011 * off and size may not cover an area beyond a single hardware page.
5014 pmap_zero_page_area(vm_page_t m, int off, int size)
5016 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5018 if (off == 0 && size == PAGE_SIZE)
5019 pagezero((void *)va);
5021 bzero((char *)va + off, size);
5025 * pmap_zero_page_idle zeros the specified hardware page by mapping
5026 * the page into KVM and using bzero to clear its contents. This
5027 * is intended to be called from the vm_pagezero process only and
5031 pmap_zero_page_idle(vm_page_t m)
5033 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5035 pagezero((void *)va);
5039 * pmap_copy_page copies the specified (machine independent)
5040 * page by mapping the page into virtual memory and using
5041 * bcopy to copy the page, one machine dependent page at a
5045 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5047 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5048 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5050 pagecopy((void *)src, (void *)dst);
5053 int unmapped_buf_allowed = 1;
5056 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5057 vm_offset_t b_offset, int xfersize)
5061 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5065 while (xfersize > 0) {
5066 a_pg_offset = a_offset & PAGE_MASK;
5067 pages[0] = ma[a_offset >> PAGE_SHIFT];
5068 b_pg_offset = b_offset & PAGE_MASK;
5069 pages[1] = mb[b_offset >> PAGE_SHIFT];
5070 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5071 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5072 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5073 a_cp = (char *)vaddr[0] + a_pg_offset;
5074 b_cp = (char *)vaddr[1] + b_pg_offset;
5075 bcopy(a_cp, b_cp, cnt);
5076 if (__predict_false(mapped))
5077 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5085 * Returns true if the pmap's pv is one of the first
5086 * 16 pvs linked to from this page. This count may
5087 * be changed upwards or downwards in the future; it
5088 * is only necessary that true be returned for a small
5089 * subset of pmaps for proper page aging.
5092 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5094 struct md_page *pvh;
5095 struct rwlock *lock;
5100 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5101 ("pmap_page_exists_quick: page %p is not managed", m));
5103 rw_rlock(&pvh_global_lock);
5104 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5106 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5107 if (PV_PMAP(pv) == pmap) {
5115 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5116 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5117 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5118 if (PV_PMAP(pv) == pmap) {
5128 rw_runlock(&pvh_global_lock);
5133 * pmap_page_wired_mappings:
5135 * Return the number of managed mappings to the given physical page
5139 pmap_page_wired_mappings(vm_page_t m)
5141 struct rwlock *lock;
5142 struct md_page *pvh;
5146 int count, md_gen, pvh_gen;
5148 if ((m->oflags & VPO_UNMANAGED) != 0)
5150 rw_rlock(&pvh_global_lock);
5151 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5155 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5157 if (!PMAP_TRYLOCK(pmap)) {
5158 md_gen = m->md.pv_gen;
5162 if (md_gen != m->md.pv_gen) {
5167 pte = pmap_pte(pmap, pv->pv_va);
5168 if ((*pte & PG_W) != 0)
5172 if ((m->flags & PG_FICTITIOUS) == 0) {
5173 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5174 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5176 if (!PMAP_TRYLOCK(pmap)) {
5177 md_gen = m->md.pv_gen;
5178 pvh_gen = pvh->pv_gen;
5182 if (md_gen != m->md.pv_gen ||
5183 pvh_gen != pvh->pv_gen) {
5188 pte = pmap_pde(pmap, pv->pv_va);
5189 if ((*pte & PG_W) != 0)
5195 rw_runlock(&pvh_global_lock);
5200 * Returns TRUE if the given page is mapped individually or as part of
5201 * a 2mpage. Otherwise, returns FALSE.
5204 pmap_page_is_mapped(vm_page_t m)
5206 struct rwlock *lock;
5209 if ((m->oflags & VPO_UNMANAGED) != 0)
5211 rw_rlock(&pvh_global_lock);
5212 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5214 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5215 ((m->flags & PG_FICTITIOUS) == 0 &&
5216 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5218 rw_runlock(&pvh_global_lock);
5223 * Destroy all managed, non-wired mappings in the given user-space
5224 * pmap. This pmap cannot be active on any processor besides the
5227 * This function cannot be applied to the kernel pmap. Moreover, it
5228 * is not intended for general use. It is only to be used during
5229 * process termination. Consequently, it can be implemented in ways
5230 * that make it faster than pmap_remove(). First, it can more quickly
5231 * destroy mappings by iterating over the pmap's collection of PV
5232 * entries, rather than searching the page table. Second, it doesn't
5233 * have to test and clear the page table entries atomically, because
5234 * no processor is currently accessing the user address space. In
5235 * particular, a page table entry's dirty bit won't change state once
5236 * this function starts.
5239 pmap_remove_pages(pmap_t pmap)
5242 pt_entry_t *pte, tpte;
5243 pt_entry_t PG_M, PG_RW, PG_V;
5244 struct spglist free;
5245 vm_page_t m, mpte, mt;
5247 struct md_page *pvh;
5248 struct pv_chunk *pc, *npc;
5249 struct rwlock *lock;
5251 uint64_t inuse, bitmask;
5252 int allfree, field, freed, idx;
5253 boolean_t superpage;
5257 * Assert that the given pmap is only active on the current
5258 * CPU. Unfortunately, we cannot block another CPU from
5259 * activating the pmap while this function is executing.
5261 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5264 cpuset_t other_cpus;
5266 other_cpus = all_cpus;
5268 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5269 CPU_AND(&other_cpus, &pmap->pm_active);
5271 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5276 PG_M = pmap_modified_bit(pmap);
5277 PG_V = pmap_valid_bit(pmap);
5278 PG_RW = pmap_rw_bit(pmap);
5281 rw_rlock(&pvh_global_lock);
5283 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5286 for (field = 0; field < _NPCM; field++) {
5287 inuse = ~pc->pc_map[field] & pc_freemask[field];
5288 while (inuse != 0) {
5290 bitmask = 1UL << bit;
5291 idx = field * 64 + bit;
5292 pv = &pc->pc_pventry[idx];
5295 pte = pmap_pdpe(pmap, pv->pv_va);
5297 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5299 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5302 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5304 pte = &pte[pmap_pte_index(pv->pv_va)];
5308 * Keep track whether 'tpte' is a
5309 * superpage explicitly instead of
5310 * relying on PG_PS being set.
5312 * This is because PG_PS is numerically
5313 * identical to PG_PTE_PAT and thus a
5314 * regular page could be mistaken for
5320 if ((tpte & PG_V) == 0) {
5321 panic("bad pte va %lx pte %lx",
5326 * We cannot remove wired pages from a process' mapping at this time
5334 pa = tpte & PG_PS_FRAME;
5336 pa = tpte & PG_FRAME;
5338 m = PHYS_TO_VM_PAGE(pa);
5339 KASSERT(m->phys_addr == pa,
5340 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5341 m, (uintmax_t)m->phys_addr,
5344 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5345 m < &vm_page_array[vm_page_array_size],
5346 ("pmap_remove_pages: bad tpte %#jx",
5352 * Update the vm_page_t clean/reference bits.
5354 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5356 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5362 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5365 pc->pc_map[field] |= bitmask;
5367 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5368 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5369 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5371 if (TAILQ_EMPTY(&pvh->pv_list)) {
5372 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5373 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5374 TAILQ_EMPTY(&mt->md.pv_list))
5375 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5377 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5379 pmap_remove_pt_page(pmap, mpte);
5380 pmap_resident_count_dec(pmap, 1);
5381 KASSERT(mpte->wire_count == NPTEPG,
5382 ("pmap_remove_pages: pte page wire count error"));
5383 mpte->wire_count = 0;
5384 pmap_add_delayed_free_list(mpte, &free, FALSE);
5385 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
5388 pmap_resident_count_dec(pmap, 1);
5389 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5391 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5392 TAILQ_EMPTY(&m->md.pv_list) &&
5393 (m->flags & PG_FICTITIOUS) == 0) {
5394 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5395 if (TAILQ_EMPTY(&pvh->pv_list))
5396 vm_page_aflag_clear(m, PGA_WRITEABLE);
5399 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5403 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5404 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5405 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5407 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5413 pmap_invalidate_all(pmap);
5414 rw_runlock(&pvh_global_lock);
5416 pmap_free_zero_pages(&free);
5420 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5422 struct rwlock *lock;
5424 struct md_page *pvh;
5425 pt_entry_t *pte, mask;
5426 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5428 int md_gen, pvh_gen;
5432 rw_rlock(&pvh_global_lock);
5433 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5436 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5438 if (!PMAP_TRYLOCK(pmap)) {
5439 md_gen = m->md.pv_gen;
5443 if (md_gen != m->md.pv_gen) {
5448 pte = pmap_pte(pmap, pv->pv_va);
5451 PG_M = pmap_modified_bit(pmap);
5452 PG_RW = pmap_rw_bit(pmap);
5453 mask |= PG_RW | PG_M;
5456 PG_A = pmap_accessed_bit(pmap);
5457 PG_V = pmap_valid_bit(pmap);
5458 mask |= PG_V | PG_A;
5460 rv = (*pte & mask) == mask;
5465 if ((m->flags & PG_FICTITIOUS) == 0) {
5466 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5467 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5469 if (!PMAP_TRYLOCK(pmap)) {
5470 md_gen = m->md.pv_gen;
5471 pvh_gen = pvh->pv_gen;
5475 if (md_gen != m->md.pv_gen ||
5476 pvh_gen != pvh->pv_gen) {
5481 pte = pmap_pde(pmap, pv->pv_va);
5484 PG_M = pmap_modified_bit(pmap);
5485 PG_RW = pmap_rw_bit(pmap);
5486 mask |= PG_RW | PG_M;
5489 PG_A = pmap_accessed_bit(pmap);
5490 PG_V = pmap_valid_bit(pmap);
5491 mask |= PG_V | PG_A;
5493 rv = (*pte & mask) == mask;
5501 rw_runlock(&pvh_global_lock);
5508 * Return whether or not the specified physical page was modified
5509 * in any physical maps.
5512 pmap_is_modified(vm_page_t m)
5515 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5516 ("pmap_is_modified: page %p is not managed", m));
5519 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5520 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5521 * is clear, no PTEs can have PG_M set.
5523 VM_OBJECT_ASSERT_WLOCKED(m->object);
5524 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5526 return (pmap_page_test_mappings(m, FALSE, TRUE));
5530 * pmap_is_prefaultable:
5532 * Return whether or not the specified virtual address is eligible
5536 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5539 pt_entry_t *pte, PG_V;
5542 PG_V = pmap_valid_bit(pmap);
5545 pde = pmap_pde(pmap, addr);
5546 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5547 pte = pmap_pde_to_pte(pde, addr);
5548 rv = (*pte & PG_V) == 0;
5555 * pmap_is_referenced:
5557 * Return whether or not the specified physical page was referenced
5558 * in any physical maps.
5561 pmap_is_referenced(vm_page_t m)
5564 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5565 ("pmap_is_referenced: page %p is not managed", m));
5566 return (pmap_page_test_mappings(m, TRUE, FALSE));
5570 * Clear the write and modified bits in each of the given page's mappings.
5573 pmap_remove_write(vm_page_t m)
5575 struct md_page *pvh;
5577 struct rwlock *lock;
5578 pv_entry_t next_pv, pv;
5580 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5582 int pvh_gen, md_gen;
5584 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5585 ("pmap_remove_write: page %p is not managed", m));
5588 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5589 * set by another thread while the object is locked. Thus,
5590 * if PGA_WRITEABLE is clear, no page table entries need updating.
5592 VM_OBJECT_ASSERT_WLOCKED(m->object);
5593 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5595 rw_rlock(&pvh_global_lock);
5596 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5597 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5600 if ((m->flags & PG_FICTITIOUS) != 0)
5601 goto small_mappings;
5602 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5604 if (!PMAP_TRYLOCK(pmap)) {
5605 pvh_gen = pvh->pv_gen;
5609 if (pvh_gen != pvh->pv_gen) {
5615 PG_RW = pmap_rw_bit(pmap);
5617 pde = pmap_pde(pmap, va);
5618 if ((*pde & PG_RW) != 0)
5619 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5620 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5621 ("inconsistent pv lock %p %p for page %p",
5622 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5626 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5628 if (!PMAP_TRYLOCK(pmap)) {
5629 pvh_gen = pvh->pv_gen;
5630 md_gen = m->md.pv_gen;
5634 if (pvh_gen != pvh->pv_gen ||
5635 md_gen != m->md.pv_gen) {
5641 PG_M = pmap_modified_bit(pmap);
5642 PG_RW = pmap_rw_bit(pmap);
5643 pde = pmap_pde(pmap, pv->pv_va);
5644 KASSERT((*pde & PG_PS) == 0,
5645 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5647 pte = pmap_pde_to_pte(pde, pv->pv_va);
5650 if (oldpte & PG_RW) {
5651 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5654 if ((oldpte & PG_M) != 0)
5656 pmap_invalidate_page(pmap, pv->pv_va);
5661 vm_page_aflag_clear(m, PGA_WRITEABLE);
5662 rw_runlock(&pvh_global_lock);
5665 static __inline boolean_t
5666 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5669 if (!pmap_emulate_ad_bits(pmap))
5672 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5675 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
5676 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5677 * if the EPT_PG_WRITE bit is set.
5679 if ((pte & EPT_PG_WRITE) != 0)
5683 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5685 if ((pte & EPT_PG_EXECUTE) == 0 ||
5686 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5692 #define PMAP_TS_REFERENCED_MAX 5
5695 * pmap_ts_referenced:
5697 * Return a count of reference bits for a page, clearing those bits.
5698 * It is not necessary for every reference bit to be cleared, but it
5699 * is necessary that 0 only be returned when there are truly no
5700 * reference bits set.
5702 * XXX: The exact number of bits to check and clear is a matter that
5703 * should be tested and standardized at some point in the future for
5704 * optimal aging of shared pages.
5707 pmap_ts_referenced(vm_page_t m)
5709 struct md_page *pvh;
5712 struct rwlock *lock;
5713 pd_entry_t oldpde, *pde;
5714 pt_entry_t *pte, PG_A;
5717 int cleared, md_gen, not_cleared, pvh_gen;
5718 struct spglist free;
5721 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5722 ("pmap_ts_referenced: page %p is not managed", m));
5725 pa = VM_PAGE_TO_PHYS(m);
5726 lock = PHYS_TO_PV_LIST_LOCK(pa);
5727 pvh = pa_to_pvh(pa);
5728 rw_rlock(&pvh_global_lock);
5732 if ((m->flags & PG_FICTITIOUS) != 0 ||
5733 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5734 goto small_mappings;
5740 if (!PMAP_TRYLOCK(pmap)) {
5741 pvh_gen = pvh->pv_gen;
5745 if (pvh_gen != pvh->pv_gen) {
5750 PG_A = pmap_accessed_bit(pmap);
5752 pde = pmap_pde(pmap, pv->pv_va);
5754 if ((*pde & PG_A) != 0) {
5756 * Since this reference bit is shared by 512 4KB
5757 * pages, it should not be cleared every time it is
5758 * tested. Apply a simple "hash" function on the
5759 * physical page number, the virtual superpage number,
5760 * and the pmap address to select one 4KB page out of
5761 * the 512 on which testing the reference bit will
5762 * result in clearing that reference bit. This
5763 * function is designed to avoid the selection of the
5764 * same 4KB page for every 2MB page mapping.
5766 * On demotion, a mapping that hasn't been referenced
5767 * is simply destroyed. To avoid the possibility of a
5768 * subsequent page fault on a demoted wired mapping,
5769 * always leave its reference bit set. Moreover,
5770 * since the superpage is wired, the current state of
5771 * its reference bit won't affect page replacement.
5773 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5774 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5775 (*pde & PG_W) == 0) {
5776 if (safe_to_clear_referenced(pmap, oldpde)) {
5777 atomic_clear_long(pde, PG_A);
5778 pmap_invalidate_page(pmap, pv->pv_va);
5780 } else if (pmap_demote_pde_locked(pmap, pde,
5781 pv->pv_va, &lock)) {
5783 * Remove the mapping to a single page
5784 * so that a subsequent access may
5785 * repromote. Since the underlying
5786 * page table page is fully populated,
5787 * this removal never frees a page
5791 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5793 pte = pmap_pde_to_pte(pde, va);
5794 pmap_remove_pte(pmap, pte, va, *pde,
5796 pmap_invalidate_page(pmap, va);
5802 * The superpage mapping was removed
5803 * entirely and therefore 'pv' is no
5811 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5812 ("inconsistent pv lock %p %p for page %p",
5813 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5818 /* Rotate the PV list if it has more than one entry. */
5819 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5820 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5821 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5824 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5826 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5828 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5835 if (!PMAP_TRYLOCK(pmap)) {
5836 pvh_gen = pvh->pv_gen;
5837 md_gen = m->md.pv_gen;
5841 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5846 PG_A = pmap_accessed_bit(pmap);
5847 pde = pmap_pde(pmap, pv->pv_va);
5848 KASSERT((*pde & PG_PS) == 0,
5849 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5851 pte = pmap_pde_to_pte(pde, pv->pv_va);
5852 if ((*pte & PG_A) != 0) {
5853 if (safe_to_clear_referenced(pmap, *pte)) {
5854 atomic_clear_long(pte, PG_A);
5855 pmap_invalidate_page(pmap, pv->pv_va);
5857 } else if ((*pte & PG_W) == 0) {
5859 * Wired pages cannot be paged out so
5860 * doing accessed bit emulation for
5861 * them is wasted effort. We do the
5862 * hard work for unwired pages only.
5864 pmap_remove_pte(pmap, pte, pv->pv_va,
5865 *pde, &free, &lock);
5866 pmap_invalidate_page(pmap, pv->pv_va);
5871 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5872 ("inconsistent pv lock %p %p for page %p",
5873 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5878 /* Rotate the PV list if it has more than one entry. */
5879 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5880 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5881 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5884 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5885 not_cleared < PMAP_TS_REFERENCED_MAX);
5888 rw_runlock(&pvh_global_lock);
5889 pmap_free_zero_pages(&free);
5890 return (cleared + not_cleared);
5894 * Apply the given advice to the specified range of addresses within the
5895 * given pmap. Depending on the advice, clear the referenced and/or
5896 * modified flags in each mapping and set the mapped page's dirty field.
5899 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5901 struct rwlock *lock;
5902 pml4_entry_t *pml4e;
5904 pd_entry_t oldpde, *pde;
5905 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5906 vm_offset_t va_next;
5908 boolean_t anychanged, pv_lists_locked;
5910 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5914 * A/D bit emulation requires an alternate code path when clearing
5915 * the modified and accessed bits below. Since this function is
5916 * advisory in nature we skip it entirely for pmaps that require
5917 * A/D bit emulation.
5919 if (pmap_emulate_ad_bits(pmap))
5922 PG_A = pmap_accessed_bit(pmap);
5923 PG_G = pmap_global_bit(pmap);
5924 PG_M = pmap_modified_bit(pmap);
5925 PG_V = pmap_valid_bit(pmap);
5926 PG_RW = pmap_rw_bit(pmap);
5928 pv_lists_locked = FALSE;
5932 for (; sva < eva; sva = va_next) {
5933 pml4e = pmap_pml4e(pmap, sva);
5934 if ((*pml4e & PG_V) == 0) {
5935 va_next = (sva + NBPML4) & ~PML4MASK;
5940 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5941 if ((*pdpe & PG_V) == 0) {
5942 va_next = (sva + NBPDP) & ~PDPMASK;
5947 va_next = (sva + NBPDR) & ~PDRMASK;
5950 pde = pmap_pdpe_to_pde(pdpe, sva);
5952 if ((oldpde & PG_V) == 0)
5954 else if ((oldpde & PG_PS) != 0) {
5955 if ((oldpde & PG_MANAGED) == 0)
5957 if (!pv_lists_locked) {
5958 pv_lists_locked = TRUE;
5959 if (!rw_try_rlock(&pvh_global_lock)) {
5961 pmap_invalidate_all(pmap);
5963 rw_rlock(&pvh_global_lock);
5968 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5973 * The large page mapping was destroyed.
5979 * Unless the page mappings are wired, remove the
5980 * mapping to a single page so that a subsequent
5981 * access may repromote. Since the underlying page
5982 * table page is fully populated, this removal never
5983 * frees a page table page.
5985 if ((oldpde & PG_W) == 0) {
5986 pte = pmap_pde_to_pte(pde, sva);
5987 KASSERT((*pte & PG_V) != 0,
5988 ("pmap_advise: invalid PTE"));
5989 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
5998 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6000 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
6003 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6004 if (advice == MADV_DONTNEED) {
6006 * Future calls to pmap_is_modified()
6007 * can be avoided by making the page
6010 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6013 atomic_clear_long(pte, PG_M | PG_A);
6014 } else if ((*pte & PG_A) != 0)
6015 atomic_clear_long(pte, PG_A);
6018 if ((*pte & PG_G) != 0)
6019 pmap_invalidate_page(pmap, sva);
6025 pmap_invalidate_all(pmap);
6026 if (pv_lists_locked)
6027 rw_runlock(&pvh_global_lock);
6032 * Clear the modify bits on the specified physical page.
6035 pmap_clear_modify(vm_page_t m)
6037 struct md_page *pvh;
6039 pv_entry_t next_pv, pv;
6040 pd_entry_t oldpde, *pde;
6041 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6042 struct rwlock *lock;
6044 int md_gen, pvh_gen;
6046 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6047 ("pmap_clear_modify: page %p is not managed", m));
6048 VM_OBJECT_ASSERT_WLOCKED(m->object);
6049 KASSERT(!vm_page_xbusied(m),
6050 ("pmap_clear_modify: page %p is exclusive busied", m));
6053 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6054 * If the object containing the page is locked and the page is not
6055 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6057 if ((m->aflags & PGA_WRITEABLE) == 0)
6059 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6060 rw_rlock(&pvh_global_lock);
6061 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6064 if ((m->flags & PG_FICTITIOUS) != 0)
6065 goto small_mappings;
6066 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6068 if (!PMAP_TRYLOCK(pmap)) {
6069 pvh_gen = pvh->pv_gen;
6073 if (pvh_gen != pvh->pv_gen) {
6078 PG_M = pmap_modified_bit(pmap);
6079 PG_V = pmap_valid_bit(pmap);
6080 PG_RW = pmap_rw_bit(pmap);
6082 pde = pmap_pde(pmap, va);
6084 if ((oldpde & PG_RW) != 0) {
6085 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6086 if ((oldpde & PG_W) == 0) {
6088 * Write protect the mapping to a
6089 * single page so that a subsequent
6090 * write access may repromote.
6092 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6094 pte = pmap_pde_to_pte(pde, va);
6096 if ((oldpte & PG_V) != 0) {
6097 while (!atomic_cmpset_long(pte,
6099 oldpte & ~(PG_M | PG_RW)))
6102 pmap_invalidate_page(pmap, va);
6110 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6112 if (!PMAP_TRYLOCK(pmap)) {
6113 md_gen = m->md.pv_gen;
6114 pvh_gen = pvh->pv_gen;
6118 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6123 PG_M = pmap_modified_bit(pmap);
6124 PG_RW = pmap_rw_bit(pmap);
6125 pde = pmap_pde(pmap, pv->pv_va);
6126 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6127 " a 2mpage in page %p's pv list", m));
6128 pte = pmap_pde_to_pte(pde, pv->pv_va);
6129 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6130 atomic_clear_long(pte, PG_M);
6131 pmap_invalidate_page(pmap, pv->pv_va);
6136 rw_runlock(&pvh_global_lock);
6140 * Miscellaneous support routines follow
6143 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6144 static __inline void
6145 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6150 * The cache mode bits are all in the low 32-bits of the
6151 * PTE, so we can just spin on updating the low 32-bits.
6154 opte = *(u_int *)pte;
6155 npte = opte & ~mask;
6157 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6160 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6161 static __inline void
6162 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6167 * The cache mode bits are all in the low 32-bits of the
6168 * PDE, so we can just spin on updating the low 32-bits.
6171 opde = *(u_int *)pde;
6172 npde = opde & ~mask;
6174 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6178 * Map a set of physical memory pages into the kernel virtual
6179 * address space. Return a pointer to where it is mapped. This
6180 * routine is intended to be used for mapping device memory,
6184 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6186 vm_offset_t va, offset;
6190 * If the specified range of physical addresses fits within the direct
6191 * map window, use the direct map.
6193 if (pa < dmaplimit && pa + size < dmaplimit) {
6194 va = PHYS_TO_DMAP(pa);
6195 if (!pmap_change_attr(va, size, mode))
6196 return ((void *)va);
6198 offset = pa & PAGE_MASK;
6199 size = round_page(offset + size);
6200 va = kva_alloc(size);
6202 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
6203 pa = trunc_page(pa);
6204 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6205 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6206 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6207 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6208 return ((void *)(va + offset));
6212 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6215 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6219 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6222 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6226 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6228 vm_offset_t base, offset;
6230 /* If we gave a direct map region in pmap_mapdev, do nothing */
6231 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6233 base = trunc_page(va);
6234 offset = va & PAGE_MASK;
6235 size = round_page(offset + size);
6236 kva_free(base, size);
6240 * Tries to demote a 1GB page mapping.
6243 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6245 pdp_entry_t newpdpe, oldpdpe;
6246 pd_entry_t *firstpde, newpde, *pde;
6247 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6251 PG_A = pmap_accessed_bit(pmap);
6252 PG_M = pmap_modified_bit(pmap);
6253 PG_V = pmap_valid_bit(pmap);
6254 PG_RW = pmap_rw_bit(pmap);
6256 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6258 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6259 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6260 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6261 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6262 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6263 " in pmap %p", va, pmap);
6266 mpdepa = VM_PAGE_TO_PHYS(mpde);
6267 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6268 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6269 KASSERT((oldpdpe & PG_A) != 0,
6270 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6271 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6272 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6276 * Initialize the page directory page.
6278 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6284 * Demote the mapping.
6289 * Invalidate a stale recursive mapping of the page directory page.
6291 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6293 pmap_pdpe_demotions++;
6294 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6295 " in pmap %p", va, pmap);
6300 * Sets the memory attribute for the specified page.
6303 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6306 m->md.pat_mode = ma;
6309 * If "m" is a normal page, update its direct mapping. This update
6310 * can be relied upon to perform any cache operations that are
6311 * required for data coherence.
6313 if ((m->flags & PG_FICTITIOUS) == 0 &&
6314 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6316 panic("memory attribute change on the direct map failed");
6320 * Changes the specified virtual address range's memory type to that given by
6321 * the parameter "mode". The specified virtual address range must be
6322 * completely contained within either the direct map or the kernel map. If
6323 * the virtual address range is contained within the kernel map, then the
6324 * memory type for each of the corresponding ranges of the direct map is also
6325 * changed. (The corresponding ranges of the direct map are those ranges that
6326 * map the same physical pages as the specified virtual address range.) These
6327 * changes to the direct map are necessary because Intel describes the
6328 * behavior of their processors as "undefined" if two or more mappings to the
6329 * same physical page have different memory types.
6331 * Returns zero if the change completed successfully, and either EINVAL or
6332 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6333 * of the virtual address range was not mapped, and ENOMEM is returned if
6334 * there was insufficient memory available to complete the change. In the
6335 * latter case, the memory type may have been changed on some part of the
6336 * virtual address range or the direct map.
6339 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6343 PMAP_LOCK(kernel_pmap);
6344 error = pmap_change_attr_locked(va, size, mode);
6345 PMAP_UNLOCK(kernel_pmap);
6350 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6352 vm_offset_t base, offset, tmpva;
6353 vm_paddr_t pa_start, pa_end;
6357 int cache_bits_pte, cache_bits_pde, error;
6360 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6361 base = trunc_page(va);
6362 offset = va & PAGE_MASK;
6363 size = round_page(offset + size);
6366 * Only supported on kernel virtual addresses, including the direct
6367 * map but excluding the recursive map.
6369 if (base < DMAP_MIN_ADDRESS)
6372 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6373 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6377 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6378 * into 4KB pages if required.
6380 for (tmpva = base; tmpva < base + size; ) {
6381 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6384 if (*pdpe & PG_PS) {
6386 * If the current 1GB page already has the required
6387 * memory type, then we need not demote this page. Just
6388 * increment tmpva to the next 1GB page frame.
6390 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6391 tmpva = trunc_1gpage(tmpva) + NBPDP;
6396 * If the current offset aligns with a 1GB page frame
6397 * and there is at least 1GB left within the range, then
6398 * we need not break down this page into 2MB pages.
6400 if ((tmpva & PDPMASK) == 0 &&
6401 tmpva + PDPMASK < base + size) {
6405 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6408 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6413 * If the current 2MB page already has the required
6414 * memory type, then we need not demote this page. Just
6415 * increment tmpva to the next 2MB page frame.
6417 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6418 tmpva = trunc_2mpage(tmpva) + NBPDR;
6423 * If the current offset aligns with a 2MB page frame
6424 * and there is at least 2MB left within the range, then
6425 * we need not break down this page into 4KB pages.
6427 if ((tmpva & PDRMASK) == 0 &&
6428 tmpva + PDRMASK < base + size) {
6432 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6435 pte = pmap_pde_to_pte(pde, tmpva);
6443 * Ok, all the pages exist, so run through them updating their
6444 * cache mode if required.
6446 pa_start = pa_end = 0;
6447 for (tmpva = base; tmpva < base + size; ) {
6448 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6449 if (*pdpe & PG_PS) {
6450 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6451 pmap_pde_attr(pdpe, cache_bits_pde,
6455 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6456 if (pa_start == pa_end) {
6457 /* Start physical address run. */
6458 pa_start = *pdpe & PG_PS_FRAME;
6459 pa_end = pa_start + NBPDP;
6460 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6463 /* Run ended, update direct map. */
6464 error = pmap_change_attr_locked(
6465 PHYS_TO_DMAP(pa_start),
6466 pa_end - pa_start, mode);
6469 /* Start physical address run. */
6470 pa_start = *pdpe & PG_PS_FRAME;
6471 pa_end = pa_start + NBPDP;
6474 tmpva = trunc_1gpage(tmpva) + NBPDP;
6477 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6479 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6480 pmap_pde_attr(pde, cache_bits_pde,
6484 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6485 if (pa_start == pa_end) {
6486 /* Start physical address run. */
6487 pa_start = *pde & PG_PS_FRAME;
6488 pa_end = pa_start + NBPDR;
6489 } else if (pa_end == (*pde & PG_PS_FRAME))
6492 /* Run ended, update direct map. */
6493 error = pmap_change_attr_locked(
6494 PHYS_TO_DMAP(pa_start),
6495 pa_end - pa_start, mode);
6498 /* Start physical address run. */
6499 pa_start = *pde & PG_PS_FRAME;
6500 pa_end = pa_start + NBPDR;
6503 tmpva = trunc_2mpage(tmpva) + NBPDR;
6505 pte = pmap_pde_to_pte(pde, tmpva);
6506 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6507 pmap_pte_attr(pte, cache_bits_pte,
6511 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6512 if (pa_start == pa_end) {
6513 /* Start physical address run. */
6514 pa_start = *pte & PG_FRAME;
6515 pa_end = pa_start + PAGE_SIZE;
6516 } else if (pa_end == (*pte & PG_FRAME))
6517 pa_end += PAGE_SIZE;
6519 /* Run ended, update direct map. */
6520 error = pmap_change_attr_locked(
6521 PHYS_TO_DMAP(pa_start),
6522 pa_end - pa_start, mode);
6525 /* Start physical address run. */
6526 pa_start = *pte & PG_FRAME;
6527 pa_end = pa_start + PAGE_SIZE;
6533 if (error == 0 && pa_start != pa_end)
6534 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6535 pa_end - pa_start, mode);
6538 * Flush CPU caches if required to make sure any data isn't cached that
6539 * shouldn't be, etc.
6542 pmap_invalidate_range(kernel_pmap, base, tmpva);
6543 pmap_invalidate_cache_range(base, tmpva, FALSE);
6549 * Demotes any mapping within the direct map region that covers more than the
6550 * specified range of physical addresses. This range's size must be a power
6551 * of two and its starting address must be a multiple of its size. Since the
6552 * demotion does not change any attributes of the mapping, a TLB invalidation
6553 * is not mandatory. The caller may, however, request a TLB invalidation.
6556 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6565 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6566 KASSERT((base & (len - 1)) == 0,
6567 ("pmap_demote_DMAP: base is not a multiple of len"));
6568 if (len < NBPDP && base < dmaplimit) {
6569 va = PHYS_TO_DMAP(base);
6571 PMAP_LOCK(kernel_pmap);
6572 pdpe = pmap_pdpe(kernel_pmap, va);
6573 if ((*pdpe & X86_PG_V) == 0)
6574 panic("pmap_demote_DMAP: invalid PDPE");
6575 if ((*pdpe & PG_PS) != 0) {
6576 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6577 panic("pmap_demote_DMAP: PDPE failed");
6581 pde = pmap_pdpe_to_pde(pdpe, va);
6582 if ((*pde & X86_PG_V) == 0)
6583 panic("pmap_demote_DMAP: invalid PDE");
6584 if ((*pde & PG_PS) != 0) {
6585 if (!pmap_demote_pde(kernel_pmap, pde, va))
6586 panic("pmap_demote_DMAP: PDE failed");
6590 if (changed && invalidate)
6591 pmap_invalidate_page(kernel_pmap, va);
6592 PMAP_UNLOCK(kernel_pmap);
6597 * perform the pmap work for mincore
6600 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6603 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6607 PG_A = pmap_accessed_bit(pmap);
6608 PG_M = pmap_modified_bit(pmap);
6609 PG_V = pmap_valid_bit(pmap);
6610 PG_RW = pmap_rw_bit(pmap);
6614 pdep = pmap_pde(pmap, addr);
6615 if (pdep != NULL && (*pdep & PG_V)) {
6616 if (*pdep & PG_PS) {
6618 /* Compute the physical address of the 4KB page. */
6619 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6621 val = MINCORE_SUPER;
6623 pte = *pmap_pde_to_pte(pdep, addr);
6624 pa = pte & PG_FRAME;
6632 if ((pte & PG_V) != 0) {
6633 val |= MINCORE_INCORE;
6634 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6635 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6636 if ((pte & PG_A) != 0)
6637 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6639 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6640 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6641 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6642 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6643 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6646 PA_UNLOCK_COND(*locked_pa);
6652 pmap_activate(struct thread *td)
6654 pmap_t pmap, oldpmap;
6658 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6659 oldpmap = PCPU_GET(curpmap);
6660 cpuid = PCPU_GET(cpuid);
6662 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6663 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6664 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
6666 CPU_CLR(cpuid, &oldpmap->pm_active);
6667 CPU_SET(cpuid, &pmap->pm_active);
6668 CPU_SET(cpuid, &pmap->pm_save);
6670 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
6671 load_cr3(pmap->pm_cr3);
6672 PCPU_SET(curpmap, pmap);
6677 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6682 * Increase the starting virtual address of the given mapping if a
6683 * different alignment might result in more superpage mappings.
6686 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6687 vm_offset_t *addr, vm_size_t size)
6689 vm_offset_t superpage_offset;
6693 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6694 offset += ptoa(object->pg_color);
6695 superpage_offset = offset & PDRMASK;
6696 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6697 (*addr & PDRMASK) == superpage_offset)
6699 if ((*addr & PDRMASK) < superpage_offset)
6700 *addr = (*addr & ~PDRMASK) + superpage_offset;
6702 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6706 static unsigned long num_dirty_emulations;
6707 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6708 &num_dirty_emulations, 0, NULL);
6710 static unsigned long num_accessed_emulations;
6711 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6712 &num_accessed_emulations, 0, NULL);
6714 static unsigned long num_superpage_accessed_emulations;
6715 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6716 &num_superpage_accessed_emulations, 0, NULL);
6718 static unsigned long ad_emulation_superpage_promotions;
6719 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6720 &ad_emulation_superpage_promotions, 0, NULL);
6721 #endif /* INVARIANTS */
6724 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6727 struct rwlock *lock;
6730 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6731 boolean_t pv_lists_locked;
6733 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6734 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6736 if (!pmap_emulate_ad_bits(pmap))
6739 PG_A = pmap_accessed_bit(pmap);
6740 PG_M = pmap_modified_bit(pmap);
6741 PG_V = pmap_valid_bit(pmap);
6742 PG_RW = pmap_rw_bit(pmap);
6746 pv_lists_locked = FALSE;
6750 pde = pmap_pde(pmap, va);
6751 if (pde == NULL || (*pde & PG_V) == 0)
6754 if ((*pde & PG_PS) != 0) {
6755 if (ftype == VM_PROT_READ) {
6757 atomic_add_long(&num_superpage_accessed_emulations, 1);
6765 pte = pmap_pde_to_pte(pde, va);
6766 if ((*pte & PG_V) == 0)
6769 if (ftype == VM_PROT_WRITE) {
6770 if ((*pte & PG_RW) == 0)
6773 * Set the modified and accessed bits simultaneously.
6775 * Intel EPT PTEs that do software emulation of A/D bits map
6776 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
6777 * An EPT misconfiguration is triggered if the PTE is writable
6778 * but not readable (WR=10). This is avoided by setting PG_A
6779 * and PG_M simultaneously.
6781 *pte |= PG_M | PG_A;
6786 /* try to promote the mapping */
6787 if (va < VM_MAXUSER_ADDRESS)
6788 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6792 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6794 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6795 pmap_ps_enabled(pmap) &&
6796 (m->flags & PG_FICTITIOUS) == 0 &&
6797 vm_reserv_level_iffullpop(m) == 0) {
6798 if (!pv_lists_locked) {
6799 pv_lists_locked = TRUE;
6800 if (!rw_try_rlock(&pvh_global_lock)) {
6802 rw_rlock(&pvh_global_lock);
6806 pmap_promote_pde(pmap, pde, va, &lock);
6808 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6812 if (ftype == VM_PROT_WRITE)
6813 atomic_add_long(&num_dirty_emulations, 1);
6815 atomic_add_long(&num_accessed_emulations, 1);
6817 rv = 0; /* success */
6821 if (pv_lists_locked)
6822 rw_runlock(&pvh_global_lock);
6828 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6833 pt_entry_t *pte, PG_V;
6837 PG_V = pmap_valid_bit(pmap);
6840 pml4 = pmap_pml4e(pmap, va);
6842 if ((*pml4 & PG_V) == 0)
6845 pdp = pmap_pml4e_to_pdpe(pml4, va);
6847 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6850 pde = pmap_pdpe_to_pde(pdp, va);
6852 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6855 pte = pmap_pde_to_pte(pde, va);
6864 * Get the kernel virtual address of a set of physical pages. If there are
6865 * physical addresses not covered by the DMAP perform a transient mapping
6866 * that will be removed when calling pmap_unmap_io_transient.
6868 * \param page The pages the caller wishes to obtain the virtual
6869 * address on the kernel memory map.
6870 * \param vaddr On return contains the kernel virtual memory address
6871 * of the pages passed in the page parameter.
6872 * \param count Number of pages passed in.
6873 * \param can_fault TRUE if the thread using the mapped pages can take
6874 * page faults, FALSE otherwise.
6876 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6877 * finished or FALSE otherwise.
6881 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6882 boolean_t can_fault)
6885 boolean_t needs_mapping;
6887 int cache_bits, error, i;
6890 * Allocate any KVA space that we need, this is done in a separate
6891 * loop to prevent calling vmem_alloc while pinned.
6893 needs_mapping = FALSE;
6894 for (i = 0; i < count; i++) {
6895 paddr = VM_PAGE_TO_PHYS(page[i]);
6896 if (__predict_false(paddr >= dmaplimit)) {
6897 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6898 M_BESTFIT | M_WAITOK, &vaddr[i]);
6899 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6900 needs_mapping = TRUE;
6902 vaddr[i] = PHYS_TO_DMAP(paddr);
6906 /* Exit early if everything is covered by the DMAP */
6911 * NB: The sequence of updating a page table followed by accesses
6912 * to the corresponding pages used in the !DMAP case is subject to
6913 * the situation described in the "AMD64 Architecture Programmer's
6914 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
6915 * Coherency Considerations". Therefore, issuing the INVLPG right
6916 * after modifying the PTE bits is crucial.
6920 for (i = 0; i < count; i++) {
6921 paddr = VM_PAGE_TO_PHYS(page[i]);
6922 if (paddr >= dmaplimit) {
6925 * Slow path, since we can get page faults
6926 * while mappings are active don't pin the
6927 * thread to the CPU and instead add a global
6928 * mapping visible to all CPUs.
6930 pmap_qenter(vaddr[i], &page[i], 1);
6932 pte = vtopte(vaddr[i]);
6933 cache_bits = pmap_cache_bits(kernel_pmap,
6934 page[i]->md.pat_mode, 0);
6935 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
6942 return (needs_mapping);
6946 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6947 boolean_t can_fault)
6954 for (i = 0; i < count; i++) {
6955 paddr = VM_PAGE_TO_PHYS(page[i]);
6956 if (paddr >= dmaplimit) {
6958 pmap_qremove(vaddr[i], 1);
6959 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
6964 #include "opt_ddb.h"
6966 #include <ddb/ddb.h>
6968 DB_SHOW_COMMAND(pte, pmap_print_pte)
6974 pt_entry_t *pte, PG_V;
6978 va = (vm_offset_t)addr;
6979 pmap = PCPU_GET(curpmap); /* XXX */
6981 db_printf("show pte addr\n");
6984 PG_V = pmap_valid_bit(pmap);
6985 pml4 = pmap_pml4e(pmap, va);
6986 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
6987 if ((*pml4 & PG_V) == 0) {
6991 pdp = pmap_pml4e_to_pdpe(pml4, va);
6992 db_printf(" pdpe %#016lx", *pdp);
6993 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
6997 pde = pmap_pdpe_to_pde(pdp, va);
6998 db_printf(" pde %#016lx", *pde);
6999 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
7003 pte = pmap_pde_to_pte(pde, va);
7004 db_printf(" pte %#016lx\n", *pte);
7007 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
7012 a = (vm_paddr_t)addr;
7013 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
7015 db_printf("show phys2dmap addr\n");