2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2018 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
110 #include "opt_pmap.h"
113 #include <sys/param.h>
114 #include <sys/bitstring.h>
116 #include <sys/systm.h>
117 #include <sys/kernel.h>
119 #include <sys/lock.h>
120 #include <sys/malloc.h>
121 #include <sys/mman.h>
122 #include <sys/mutex.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
126 #include <sys/turnstile.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/intr_machdep.h>
148 #include <x86/apicvar.h>
149 #include <x86/ifunc.h>
150 #include <machine/cpu.h>
151 #include <machine/cputypes.h>
152 #include <machine/md_var.h>
153 #include <machine/pcb.h>
154 #include <machine/specialreg.h>
156 #include <machine/smp.h>
158 #include <machine/tss.h>
160 static __inline boolean_t
161 pmap_type_guest(pmap_t pmap)
164 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
167 static __inline boolean_t
168 pmap_emulate_ad_bits(pmap_t pmap)
171 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
174 static __inline pt_entry_t
175 pmap_valid_bit(pmap_t pmap)
179 switch (pmap->pm_type) {
185 if (pmap_emulate_ad_bits(pmap))
186 mask = EPT_PG_EMUL_V;
191 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
197 static __inline pt_entry_t
198 pmap_rw_bit(pmap_t pmap)
202 switch (pmap->pm_type) {
208 if (pmap_emulate_ad_bits(pmap))
209 mask = EPT_PG_EMUL_RW;
214 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
220 static pt_entry_t pg_g;
222 static __inline pt_entry_t
223 pmap_global_bit(pmap_t pmap)
227 switch (pmap->pm_type) {
236 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
242 static __inline pt_entry_t
243 pmap_accessed_bit(pmap_t pmap)
247 switch (pmap->pm_type) {
253 if (pmap_emulate_ad_bits(pmap))
259 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
265 static __inline pt_entry_t
266 pmap_modified_bit(pmap_t pmap)
270 switch (pmap->pm_type) {
276 if (pmap_emulate_ad_bits(pmap))
282 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
288 #if !defined(DIAGNOSTIC)
289 #ifdef __GNUC_GNU_INLINE__
290 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
292 #define PMAP_INLINE extern inline
299 #define PV_STAT(x) do { x ; } while (0)
301 #define PV_STAT(x) do { } while (0)
304 #define pa_index(pa) ((pa) >> PDRSHIFT)
305 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
307 #define NPV_LIST_LOCKS MAXCPU
309 #define PHYS_TO_PV_LIST_LOCK(pa) \
310 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
312 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
313 struct rwlock **_lockp = (lockp); \
314 struct rwlock *_new_lock; \
316 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
317 if (_new_lock != *_lockp) { \
318 if (*_lockp != NULL) \
319 rw_wunlock(*_lockp); \
320 *_lockp = _new_lock; \
325 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
326 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
328 #define RELEASE_PV_LIST_LOCK(lockp) do { \
329 struct rwlock **_lockp = (lockp); \
331 if (*_lockp != NULL) { \
332 rw_wunlock(*_lockp); \
337 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
338 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
340 struct pmap kernel_pmap_store;
342 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
343 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
346 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
347 "Number of kernel page table pages allocated on bootup");
350 vm_paddr_t dmaplimit;
351 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
354 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
356 static int pat_works = 1;
357 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
358 "Is page attribute table fully functional?");
360 static int pg_ps_enabled = 1;
361 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
362 &pg_ps_enabled, 0, "Are large page mappings enabled?");
364 #define PAT_INDEX_SIZE 8
365 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
367 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
368 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
369 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
370 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
372 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
373 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
374 static int ndmpdpphys; /* number of DMPDPphys pages */
376 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
379 * pmap_mapdev support pre initialization (i.e. console)
381 #define PMAP_PREINIT_MAPPING_COUNT 8
382 static struct pmap_preinit_mapping {
387 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
388 static int pmap_initialized;
391 * Data for the pv entry allocation mechanism.
392 * Updates to pv_invl_gen are protected by the pv_list_locks[]
393 * elements, but reads are not.
395 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
396 static struct mtx __exclusive_cache_line pv_chunks_mutex;
397 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
398 static u_long pv_invl_gen[NPV_LIST_LOCKS];
399 static struct md_page *pv_table;
400 static struct md_page pv_dummy;
403 * All those kernel PT submaps that BSD is so fond of
405 pt_entry_t *CMAP1 = NULL;
407 static vm_offset_t qframe = 0;
408 static struct mtx qframe_mtx;
410 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
412 int pmap_pcid_enabled = 1;
413 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
414 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
415 int invpcid_works = 0;
416 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
417 "Is the invpcid instruction available ?");
419 int __read_frequently pti = 0;
420 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
422 "Page Table Isolation enabled");
423 static vm_object_t pti_obj;
424 static pml4_entry_t *pti_pml4;
425 static vm_pindex_t pti_pg_idx;
426 static bool pti_finalized;
429 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
436 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
438 return (sysctl_handle_64(oidp, &res, 0, req));
440 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
441 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
442 "Count of saved TLB context on switch");
444 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
445 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
446 static struct mtx invl_gen_mtx;
447 static u_long pmap_invl_gen = 0;
448 /* Fake lock object to satisfy turnstiles interface. */
449 static struct lock_object invl_gen_ts = {
457 return (curthread->td_md.md_invl_gen.gen == 0);
460 #define PMAP_ASSERT_NOT_IN_DI() \
461 KASSERT(pmap_not_in_di(), ("DI already started"))
464 * Start a new Delayed Invalidation (DI) block of code, executed by
465 * the current thread. Within a DI block, the current thread may
466 * destroy both the page table and PV list entries for a mapping and
467 * then release the corresponding PV list lock before ensuring that
468 * the mapping is flushed from the TLBs of any processors with the
472 pmap_delayed_invl_started(void)
474 struct pmap_invl_gen *invl_gen;
477 invl_gen = &curthread->td_md.md_invl_gen;
478 PMAP_ASSERT_NOT_IN_DI();
479 mtx_lock(&invl_gen_mtx);
480 if (LIST_EMPTY(&pmap_invl_gen_tracker))
481 currgen = pmap_invl_gen;
483 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
484 invl_gen->gen = currgen + 1;
485 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
486 mtx_unlock(&invl_gen_mtx);
490 * Finish the DI block, previously started by the current thread. All
491 * required TLB flushes for the pages marked by
492 * pmap_delayed_invl_page() must be finished before this function is
495 * This function works by bumping the global DI generation number to
496 * the generation number of the current thread's DI, unless there is a
497 * pending DI that started earlier. In the latter case, bumping the
498 * global DI generation number would incorrectly signal that the
499 * earlier DI had finished. Instead, this function bumps the earlier
500 * DI's generation number to match the generation number of the
501 * current thread's DI.
504 pmap_delayed_invl_finished(void)
506 struct pmap_invl_gen *invl_gen, *next;
507 struct turnstile *ts;
509 invl_gen = &curthread->td_md.md_invl_gen;
510 KASSERT(invl_gen->gen != 0, ("missed invl_started"));
511 mtx_lock(&invl_gen_mtx);
512 next = LIST_NEXT(invl_gen, link);
514 turnstile_chain_lock(&invl_gen_ts);
515 ts = turnstile_lookup(&invl_gen_ts);
516 pmap_invl_gen = invl_gen->gen;
518 turnstile_broadcast(ts, TS_SHARED_QUEUE);
519 turnstile_unpend(ts);
521 turnstile_chain_unlock(&invl_gen_ts);
523 next->gen = invl_gen->gen;
525 LIST_REMOVE(invl_gen, link);
526 mtx_unlock(&invl_gen_mtx);
531 static long invl_wait;
532 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
533 "Number of times DI invalidation blocked pmap_remove_all/write");
537 pmap_delayed_invl_genp(vm_page_t m)
540 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
544 * Ensure that all currently executing DI blocks, that need to flush
545 * TLB for the given page m, actually flushed the TLB at the time the
546 * function returned. If the page m has an empty PV list and we call
547 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
548 * valid mapping for the page m in either its page table or TLB.
550 * This function works by blocking until the global DI generation
551 * number catches up with the generation number associated with the
552 * given page m and its PV list. Since this function's callers
553 * typically own an object lock and sometimes own a page lock, it
554 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
558 pmap_delayed_invl_wait(vm_page_t m)
560 struct turnstile *ts;
563 bool accounted = false;
566 m_gen = pmap_delayed_invl_genp(m);
567 while (*m_gen > pmap_invl_gen) {
570 atomic_add_long(&invl_wait, 1);
574 ts = turnstile_trywait(&invl_gen_ts);
575 if (*m_gen > pmap_invl_gen)
576 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
578 turnstile_cancel(ts);
583 * Mark the page m's PV list as participating in the current thread's
584 * DI block. Any threads concurrently using m's PV list to remove or
585 * restrict all mappings to m will wait for the current thread's DI
586 * block to complete before proceeding.
588 * The function works by setting the DI generation number for m's PV
589 * list to at least the DI generation number of the current thread.
590 * This forces a caller of pmap_delayed_invl_wait() to block until
591 * current thread calls pmap_delayed_invl_finished().
594 pmap_delayed_invl_page(vm_page_t m)
598 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
599 gen = curthread->td_md.md_invl_gen.gen;
602 m_gen = pmap_delayed_invl_genp(m);
610 static caddr_t crashdumpmap;
613 * Internal flags for pmap_enter()'s helper functions.
615 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
616 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
618 static void free_pv_chunk(struct pv_chunk *pc);
619 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
620 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
621 static int popcnt_pc_map_pq(uint64_t *map);
622 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
623 static void reserve_pv_entries(pmap_t pmap, int needed,
624 struct rwlock **lockp);
625 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
626 struct rwlock **lockp);
627 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
628 u_int flags, struct rwlock **lockp);
629 #if VM_NRESERVLEVEL > 0
630 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
631 struct rwlock **lockp);
633 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
634 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
637 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
638 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
639 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
640 vm_offset_t va, struct rwlock **lockp);
641 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
643 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
644 vm_prot_t prot, struct rwlock **lockp);
645 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
646 u_int flags, vm_page_t m, struct rwlock **lockp);
647 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
648 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
649 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
650 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
651 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
653 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
654 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
655 #if VM_NRESERVLEVEL > 0
656 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
657 struct rwlock **lockp);
659 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
661 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
662 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
664 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
665 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
666 static void pmap_pti_wire_pte(void *pte);
667 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
668 struct spglist *free, struct rwlock **lockp);
669 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
670 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
671 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
672 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
673 struct spglist *free);
674 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
675 pd_entry_t *pde, struct spglist *free,
676 struct rwlock **lockp);
677 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
678 vm_page_t m, struct rwlock **lockp);
679 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
681 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
683 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
684 struct rwlock **lockp);
685 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
686 struct rwlock **lockp);
687 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
688 struct rwlock **lockp);
690 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
691 struct spglist *free);
692 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
694 /********************/
695 /* Inline functions */
696 /********************/
698 /* Return a non-clipped PD index for a given VA */
699 static __inline vm_pindex_t
700 pmap_pde_pindex(vm_offset_t va)
702 return (va >> PDRSHIFT);
706 /* Return a pointer to the PML4 slot that corresponds to a VA */
707 static __inline pml4_entry_t *
708 pmap_pml4e(pmap_t pmap, vm_offset_t va)
711 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
714 /* Return a pointer to the PDP slot that corresponds to a VA */
715 static __inline pdp_entry_t *
716 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
720 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
721 return (&pdpe[pmap_pdpe_index(va)]);
724 /* Return a pointer to the PDP slot that corresponds to a VA */
725 static __inline pdp_entry_t *
726 pmap_pdpe(pmap_t pmap, vm_offset_t va)
731 PG_V = pmap_valid_bit(pmap);
732 pml4e = pmap_pml4e(pmap, va);
733 if ((*pml4e & PG_V) == 0)
735 return (pmap_pml4e_to_pdpe(pml4e, va));
738 /* Return a pointer to the PD slot that corresponds to a VA */
739 static __inline pd_entry_t *
740 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
744 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
745 return (&pde[pmap_pde_index(va)]);
748 /* Return a pointer to the PD slot that corresponds to a VA */
749 static __inline pd_entry_t *
750 pmap_pde(pmap_t pmap, vm_offset_t va)
755 PG_V = pmap_valid_bit(pmap);
756 pdpe = pmap_pdpe(pmap, va);
757 if (pdpe == NULL || (*pdpe & PG_V) == 0)
759 return (pmap_pdpe_to_pde(pdpe, va));
762 /* Return a pointer to the PT slot that corresponds to a VA */
763 static __inline pt_entry_t *
764 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
768 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
769 return (&pte[pmap_pte_index(va)]);
772 /* Return a pointer to the PT slot that corresponds to a VA */
773 static __inline pt_entry_t *
774 pmap_pte(pmap_t pmap, vm_offset_t va)
779 PG_V = pmap_valid_bit(pmap);
780 pde = pmap_pde(pmap, va);
781 if (pde == NULL || (*pde & PG_V) == 0)
783 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
784 return ((pt_entry_t *)pde);
785 return (pmap_pde_to_pte(pde, va));
789 pmap_resident_count_inc(pmap_t pmap, int count)
792 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
793 pmap->pm_stats.resident_count += count;
797 pmap_resident_count_dec(pmap_t pmap, int count)
800 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
801 KASSERT(pmap->pm_stats.resident_count >= count,
802 ("pmap %p resident count underflow %ld %d", pmap,
803 pmap->pm_stats.resident_count, count));
804 pmap->pm_stats.resident_count -= count;
807 PMAP_INLINE pt_entry_t *
808 vtopte(vm_offset_t va)
810 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
812 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
814 return (PTmap + ((va >> PAGE_SHIFT) & mask));
817 static __inline pd_entry_t *
818 vtopde(vm_offset_t va)
820 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
822 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
824 return (PDmap + ((va >> PDRSHIFT) & mask));
828 allocpages(vm_paddr_t *firstaddr, int n)
833 bzero((void *)ret, n * PAGE_SIZE);
834 *firstaddr += n * PAGE_SIZE;
838 CTASSERT(powerof2(NDMPML4E));
840 /* number of kernel PDP slots */
841 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
844 nkpt_init(vm_paddr_t addr)
851 pt_pages = howmany(addr, 1 << PDRSHIFT);
852 pt_pages += NKPDPE(pt_pages);
855 * Add some slop beyond the bare minimum required for bootstrapping
858 * This is quite important when allocating KVA for kernel modules.
859 * The modules are required to be linked in the negative 2GB of
860 * the address space. If we run out of KVA in this region then
861 * pmap_growkernel() will need to allocate page table pages to map
862 * the entire 512GB of KVA space which is an unnecessary tax on
865 * Secondly, device memory mapped as part of setting up the low-
866 * level console(s) is taken from KVA, starting at virtual_avail.
867 * This is because cninit() is called after pmap_bootstrap() but
868 * before vm_init() and pmap_init(). 20MB for a frame buffer is
871 pt_pages += 32; /* 64MB additional slop. */
877 * Returns the proper write/execute permission for a physical page that is
878 * part of the initial boot allocations.
880 * If the page has kernel text, it is marked as read-only. If the page has
881 * kernel read-only data, it is marked as read-only/not-executable. If the
882 * page has only read-write data, it is marked as read-write/not-executable.
883 * If the page is below/above the kernel range, it is marked as read-write.
885 * This function operates on 2M pages, since we map the kernel space that
888 * Note that this doesn't currently provide any protection for modules.
890 static inline pt_entry_t
891 bootaddr_rwx(vm_paddr_t pa)
895 * Everything in the same 2M page as the start of the kernel
896 * should be static. On the other hand, things in the same 2M
897 * page as the end of the kernel could be read-write/executable,
898 * as the kernel image is not guaranteed to end on a 2M boundary.
900 if (pa < trunc_2mpage(btext - KERNBASE) ||
901 pa >= trunc_2mpage(_end - KERNBASE))
904 * The linker should ensure that the read-only and read-write
905 * portions don't share the same 2M page, so this shouldn't
906 * impact read-only data. However, in any case, any page with
907 * read-write data needs to be read-write.
909 if (pa >= trunc_2mpage(brwsection - KERNBASE))
910 return (X86_PG_RW | pg_nx);
912 * Mark any 2M page containing kernel text as read-only. Mark
913 * other pages with read-only data as read-only and not executable.
914 * (It is likely a small portion of the read-only data section will
915 * be marked as read-only, but executable. This should be acceptable
916 * since the read-only protection will keep the data from changing.)
917 * Note that fixups to the .text section will still work until we
920 if (pa < round_2mpage(etext - KERNBASE))
926 create_pagetables(vm_paddr_t *firstaddr)
928 int i, j, ndm1g, nkpdpe, nkdmpde;
933 uint64_t DMPDkernphys;
935 /* Allocate page table pages for the direct map */
936 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
937 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
939 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
940 if (ndmpdpphys > NDMPML4E) {
942 * Each NDMPML4E allows 512 GB, so limit to that,
943 * and then readjust ndmpdp and ndmpdpphys.
945 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
946 Maxmem = atop(NDMPML4E * NBPML4);
947 ndmpdpphys = NDMPML4E;
948 ndmpdp = NDMPML4E * NPDEPG;
950 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
952 if ((amd_feature & AMDID_PAGE1GB) != 0) {
954 * Calculate the number of 1G pages that will fully fit in
957 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
960 * Allocate 2M pages for the kernel. These will be used in
961 * place of the first one or more 1G pages from ndm1g.
963 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
964 DMPDkernphys = allocpages(firstaddr, nkdmpde);
967 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
968 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
971 KPML4phys = allocpages(firstaddr, 1);
972 KPDPphys = allocpages(firstaddr, NKPML4E);
975 * Allocate the initial number of kernel page table pages required to
976 * bootstrap. We defer this until after all memory-size dependent
977 * allocations are done (e.g. direct map), so that we don't have to
978 * build in too much slop in our estimate.
980 * Note that when NKPML4E > 1, we have an empty page underneath
981 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
982 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
984 nkpt_init(*firstaddr);
985 nkpdpe = NKPDPE(nkpt);
987 KPTphys = allocpages(firstaddr, nkpt);
988 KPDphys = allocpages(firstaddr, nkpdpe);
990 /* Fill in the underlying page table pages */
991 /* XXX not fully used, underneath 2M pages */
992 pt_p = (pt_entry_t *)KPTphys;
993 for (i = 0; ptoa(i) < *firstaddr; i++)
994 pt_p[i] = ptoa(i) | X86_PG_V | pg_g | bootaddr_rwx(ptoa(i));
996 /* Now map the page tables at their location within PTmap */
997 pd_p = (pd_entry_t *)KPDphys;
998 for (i = 0; i < nkpt; i++)
999 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1001 /* Map from zero to end of allocations under 2M pages */
1002 /* This replaces some of the KPTphys entries above */
1003 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
1004 /* Preset PG_M and PG_A because demotion expects it. */
1005 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1006 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1009 * Because we map the physical blocks in 2M pages, adjust firstaddr
1010 * to record the physical blocks we've actually mapped into kernel
1011 * virtual address space.
1013 *firstaddr = round_2mpage(*firstaddr);
1015 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1016 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1017 for (i = 0; i < nkpdpe; i++)
1018 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1021 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1022 * the end of physical memory is not aligned to a 1GB page boundary,
1023 * then the residual physical memory is mapped with 2MB pages. Later,
1024 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1025 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1026 * that are partially used.
1028 pd_p = (pd_entry_t *)DMPDphys;
1029 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1030 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1031 /* Preset PG_M and PG_A because demotion expects it. */
1032 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1033 X86_PG_M | X86_PG_A | pg_nx;
1035 pdp_p = (pdp_entry_t *)DMPDPphys;
1036 for (i = 0; i < ndm1g; i++) {
1037 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1038 /* Preset PG_M and PG_A because demotion expects it. */
1039 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1040 X86_PG_M | X86_PG_A | pg_nx;
1042 for (j = 0; i < ndmpdp; i++, j++) {
1043 pdp_p[i] = DMPDphys + ptoa(j);
1044 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1048 * Instead of using a 1G page for the memory containing the kernel,
1049 * use 2M pages with appropriate permissions. (If using 1G pages,
1050 * this will partially overwrite the PDPEs above.)
1053 pd_p = (pd_entry_t *)DMPDkernphys;
1054 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1055 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1056 X86_PG_M | X86_PG_A | pg_nx |
1057 bootaddr_rwx(i << PDRSHIFT);
1058 for (i = 0; i < nkdmpde; i++)
1059 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1063 /* And recursively map PML4 to itself in order to get PTmap */
1064 p4_p = (pml4_entry_t *)KPML4phys;
1065 p4_p[PML4PML4I] = KPML4phys;
1066 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1068 /* Connect the Direct Map slot(s) up to the PML4. */
1069 for (i = 0; i < ndmpdpphys; i++) {
1070 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1071 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1074 /* Connect the KVA slots up to the PML4 */
1075 for (i = 0; i < NKPML4E; i++) {
1076 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1077 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1082 * Bootstrap the system enough to run with virtual memory.
1084 * On amd64 this is called after mapping has already been enabled
1085 * and just syncs the pmap module with what has already been done.
1086 * [We can't call it easily with mapping off since the kernel is not
1087 * mapped with PA == VA, hence we would have to relocate every address
1088 * from the linked base (virtual) address "KERNBASE" to the actual
1089 * (physical) address starting relative to 0]
1092 pmap_bootstrap(vm_paddr_t *firstaddr)
1099 KERNend = *firstaddr;
1105 * Create an initial set of page tables to run the kernel in.
1107 create_pagetables(firstaddr);
1110 * Add a physical memory segment (vm_phys_seg) corresponding to the
1111 * preallocated kernel page table pages so that vm_page structures
1112 * representing these pages will be created. The vm_page structures
1113 * are required for promotion of the corresponding kernel virtual
1114 * addresses to superpage mappings.
1116 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1118 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
1120 virtual_end = VM_MAX_KERNEL_ADDRESS;
1124 * Enable PG_G global pages, then switch to the kernel page
1125 * table from the bootstrap page table. After the switch, it
1126 * is possible to enable SMEP and SMAP since PG_U bits are
1132 load_cr3(KPML4phys);
1133 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1135 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1140 * Initialize the kernel pmap (which is statically allocated).
1142 PMAP_LOCK_INIT(kernel_pmap);
1143 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1144 kernel_pmap->pm_cr3 = KPML4phys;
1145 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1146 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1147 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1148 kernel_pmap->pm_flags = pmap_flags;
1151 * Initialize the TLB invalidations generation number lock.
1153 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1156 * Reserve some special page table entries/VA space for temporary
1159 #define SYSMAP(c, p, v, n) \
1160 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1166 * Crashdump maps. The first page is reused as CMAP1 for the
1169 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1170 CADDR1 = crashdumpmap;
1175 * Initialize the PAT MSR.
1176 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1177 * side-effect, invalidates stale PG_G TLB entries that might
1178 * have been created in our pre-boot environment.
1182 /* Initialize TLB Context Id. */
1183 if (pmap_pcid_enabled) {
1184 for (i = 0; i < MAXCPU; i++) {
1185 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1186 kernel_pmap->pm_pcids[i].pm_gen = 1;
1190 * PMAP_PCID_KERN + 1 is used for initialization of
1191 * proc0 pmap. The pmap' pcid state might be used by
1192 * EFIRT entry before first context switch, so it
1193 * needs to be valid.
1195 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1196 PCPU_SET(pcid_gen, 1);
1199 * pcpu area for APs is zeroed during AP startup.
1200 * pc_pcid_next and pc_pcid_gen are initialized by AP
1201 * during pcpu setup.
1203 load_cr4(rcr4() | CR4_PCIDE);
1208 * Setup the PAT MSR.
1213 int pat_table[PAT_INDEX_SIZE];
1218 /* Bail if this CPU doesn't implement PAT. */
1219 if ((cpu_feature & CPUID_PAT) == 0)
1222 /* Set default PAT index table. */
1223 for (i = 0; i < PAT_INDEX_SIZE; i++)
1225 pat_table[PAT_WRITE_BACK] = 0;
1226 pat_table[PAT_WRITE_THROUGH] = 1;
1227 pat_table[PAT_UNCACHEABLE] = 3;
1228 pat_table[PAT_WRITE_COMBINING] = 3;
1229 pat_table[PAT_WRITE_PROTECTED] = 3;
1230 pat_table[PAT_UNCACHED] = 3;
1232 /* Initialize default PAT entries. */
1233 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1234 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1235 PAT_VALUE(2, PAT_UNCACHED) |
1236 PAT_VALUE(3, PAT_UNCACHEABLE) |
1237 PAT_VALUE(4, PAT_WRITE_BACK) |
1238 PAT_VALUE(5, PAT_WRITE_THROUGH) |
1239 PAT_VALUE(6, PAT_UNCACHED) |
1240 PAT_VALUE(7, PAT_UNCACHEABLE);
1244 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1245 * Program 5 and 6 as WP and WC.
1246 * Leave 4 and 7 as WB and UC.
1248 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
1249 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1250 PAT_VALUE(6, PAT_WRITE_COMBINING);
1251 pat_table[PAT_UNCACHED] = 2;
1252 pat_table[PAT_WRITE_PROTECTED] = 5;
1253 pat_table[PAT_WRITE_COMBINING] = 6;
1256 * Just replace PAT Index 2 with WC instead of UC-.
1258 pat_msr &= ~PAT_MASK(2);
1259 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
1260 pat_table[PAT_WRITE_COMBINING] = 2;
1265 load_cr4(cr4 & ~CR4_PGE);
1267 /* Disable caches (CD = 1, NW = 0). */
1269 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1271 /* Flushes caches and TLBs. */
1275 /* Update PAT and index table. */
1276 wrmsr(MSR_PAT, pat_msr);
1277 for (i = 0; i < PAT_INDEX_SIZE; i++)
1278 pat_index[i] = pat_table[i];
1280 /* Flush caches and TLBs again. */
1284 /* Restore caches and PGE. */
1290 * Initialize a vm_page's machine-dependent fields.
1293 pmap_page_init(vm_page_t m)
1296 TAILQ_INIT(&m->md.pv_list);
1297 m->md.pat_mode = PAT_WRITE_BACK;
1301 * Initialize the pmap module.
1302 * Called by vm_init, to initialize any structures that the pmap
1303 * system needs to map virtual memory.
1308 struct pmap_preinit_mapping *ppim;
1311 int error, i, pv_npg, ret, skz63;
1313 /* L1TF, reserve page @0 unconditionally */
1314 vm_page_blacklist_add(0, bootverbose);
1316 /* Detect bare-metal Skylake Server and Skylake-X. */
1317 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1318 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1320 * Skylake-X errata SKZ63. Processor May Hang When
1321 * Executing Code In an HLE Transaction Region between
1322 * 40000000H and 403FFFFFH.
1324 * Mark the pages in the range as preallocated. It
1325 * seems to be impossible to distinguish between
1326 * Skylake Server and Skylake X.
1329 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1332 printf("SKZ63: skipping 4M RAM starting "
1333 "at physical 1G\n");
1334 for (i = 0; i < atop(0x400000); i++) {
1335 ret = vm_page_blacklist_add(0x40000000 +
1337 if (!ret && bootverbose)
1338 printf("page at %#lx already used\n",
1339 0x40000000 + ptoa(i));
1345 * Initialize the vm page array entries for the kernel pmap's
1348 PMAP_LOCK(kernel_pmap);
1349 for (i = 0; i < nkpt; i++) {
1350 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1351 KASSERT(mpte >= vm_page_array &&
1352 mpte < &vm_page_array[vm_page_array_size],
1353 ("pmap_init: page table page is out of range"));
1354 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1355 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1356 mpte->wire_count = 1;
1357 if (i << PDRSHIFT < KERNend &&
1358 pmap_insert_pt_page(kernel_pmap, mpte))
1359 panic("pmap_init: pmap_insert_pt_page failed");
1361 PMAP_UNLOCK(kernel_pmap);
1365 * If the kernel is running on a virtual machine, then it must assume
1366 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1367 * be prepared for the hypervisor changing the vendor and family that
1368 * are reported by CPUID. Consequently, the workaround for AMD Family
1369 * 10h Erratum 383 is enabled if the processor's feature set does not
1370 * include at least one feature that is only supported by older Intel
1371 * or newer AMD processors.
1373 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1374 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1375 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1377 workaround_erratum383 = 1;
1380 * Are large page mappings enabled?
1382 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1383 if (pg_ps_enabled) {
1384 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1385 ("pmap_init: can't assign to pagesizes[1]"));
1386 pagesizes[1] = NBPDR;
1390 * Initialize the pv chunk list mutex.
1392 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1395 * Initialize the pool of pv list locks.
1397 for (i = 0; i < NPV_LIST_LOCKS; i++)
1398 rw_init(&pv_list_locks[i], "pmap pv list");
1401 * Calculate the size of the pv head table for superpages.
1403 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1406 * Allocate memory for the pv head table for superpages.
1408 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1410 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1411 for (i = 0; i < pv_npg; i++)
1412 TAILQ_INIT(&pv_table[i].pv_list);
1413 TAILQ_INIT(&pv_dummy.pv_list);
1415 pmap_initialized = 1;
1416 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1417 ppim = pmap_preinit_mapping + i;
1420 /* Make the direct map consistent */
1421 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1422 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1423 ppim->sz, ppim->mode);
1427 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1428 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1431 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1432 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1433 (vmem_addr_t *)&qframe);
1435 panic("qframe allocation failed");
1438 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1439 "2MB page mapping counters");
1441 static u_long pmap_pde_demotions;
1442 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1443 &pmap_pde_demotions, 0, "2MB page demotions");
1445 static u_long pmap_pde_mappings;
1446 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1447 &pmap_pde_mappings, 0, "2MB page mappings");
1449 static u_long pmap_pde_p_failures;
1450 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1451 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1453 static u_long pmap_pde_promotions;
1454 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1455 &pmap_pde_promotions, 0, "2MB page promotions");
1457 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1458 "1GB page mapping counters");
1460 static u_long pmap_pdpe_demotions;
1461 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1462 &pmap_pdpe_demotions, 0, "1GB page demotions");
1464 /***************************************************
1465 * Low level helper routines.....
1466 ***************************************************/
1469 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1471 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1473 switch (pmap->pm_type) {
1476 /* Verify that both PAT bits are not set at the same time */
1477 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1478 ("Invalid PAT bits in entry %#lx", entry));
1480 /* Swap the PAT bits if one of them is set */
1481 if ((entry & x86_pat_bits) != 0)
1482 entry ^= x86_pat_bits;
1486 * Nothing to do - the memory attributes are represented
1487 * the same way for regular pages and superpages.
1491 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1498 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
1501 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1502 pat_index[(int)mode] >= 0);
1506 * Determine the appropriate bits to set in a PTE or PDE for a specified
1510 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1512 int cache_bits, pat_flag, pat_idx;
1514 if (!pmap_is_valid_memattr(pmap, mode))
1515 panic("Unknown caching mode %d\n", mode);
1517 switch (pmap->pm_type) {
1520 /* The PAT bit is different for PTE's and PDE's. */
1521 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1523 /* Map the caching mode to a PAT index. */
1524 pat_idx = pat_index[mode];
1526 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1529 cache_bits |= pat_flag;
1531 cache_bits |= PG_NC_PCD;
1533 cache_bits |= PG_NC_PWT;
1537 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1541 panic("unsupported pmap type %d", pmap->pm_type);
1544 return (cache_bits);
1548 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1552 switch (pmap->pm_type) {
1555 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1558 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1561 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1568 pmap_ps_enabled(pmap_t pmap)
1571 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1575 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1578 switch (pmap->pm_type) {
1585 * This is a little bogus since the generation number is
1586 * supposed to be bumped up when a region of the address
1587 * space is invalidated in the page tables.
1589 * In this case the old PDE entry is valid but yet we want
1590 * to make sure that any mappings using the old entry are
1591 * invalidated in the TLB.
1593 * The reason this works as expected is because we rendezvous
1594 * "all" host cpus and force any vcpu context to exit as a
1597 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1600 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1602 pde_store(pde, newpde);
1606 * After changing the page size for the specified virtual address in the page
1607 * table, flush the corresponding entries from the processor's TLB. Only the
1608 * calling processor's TLB is affected.
1610 * The calling thread must be pinned to a processor.
1613 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1617 if (pmap_type_guest(pmap))
1620 KASSERT(pmap->pm_type == PT_X86,
1621 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1623 PG_G = pmap_global_bit(pmap);
1625 if ((newpde & PG_PS) == 0)
1626 /* Demotion: flush a specific 2MB page mapping. */
1628 else if ((newpde & PG_G) == 0)
1630 * Promotion: flush every 4KB page mapping from the TLB
1631 * because there are too many to flush individually.
1636 * Promotion: flush every 4KB page mapping from the TLB,
1637 * including any global (PG_G) mappings.
1645 * For SMP, these functions have to use the IPI mechanism for coherence.
1647 * N.B.: Before calling any of the following TLB invalidation functions,
1648 * the calling processor must ensure that all stores updating a non-
1649 * kernel page table are globally performed. Otherwise, another
1650 * processor could cache an old, pre-update entry without being
1651 * invalidated. This can happen one of two ways: (1) The pmap becomes
1652 * active on another processor after its pm_active field is checked by
1653 * one of the following functions but before a store updating the page
1654 * table is globally performed. (2) The pmap becomes active on another
1655 * processor before its pm_active field is checked but due to
1656 * speculative loads one of the following functions stills reads the
1657 * pmap as inactive on the other processor.
1659 * The kernel page table is exempt because its pm_active field is
1660 * immutable. The kernel page table is always active on every
1665 * Interrupt the cpus that are executing in the guest context.
1666 * This will force the vcpu to exit and the cached EPT mappings
1667 * will be invalidated by the host before the next vmresume.
1669 static __inline void
1670 pmap_invalidate_ept(pmap_t pmap)
1675 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1676 ("pmap_invalidate_ept: absurd pm_active"));
1679 * The TLB mappings associated with a vcpu context are not
1680 * flushed each time a different vcpu is chosen to execute.
1682 * This is in contrast with a process's vtop mappings that
1683 * are flushed from the TLB on each context switch.
1685 * Therefore we need to do more than just a TLB shootdown on
1686 * the active cpus in 'pmap->pm_active'. To do this we keep
1687 * track of the number of invalidations performed on this pmap.
1689 * Each vcpu keeps a cache of this counter and compares it
1690 * just before a vmresume. If the counter is out-of-date an
1691 * invept will be done to flush stale mappings from the TLB.
1693 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1696 * Force the vcpu to exit and trap back into the hypervisor.
1698 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1699 ipi_selected(pmap->pm_active, ipinum);
1704 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1707 struct invpcid_descr d;
1708 uint64_t kcr3, ucr3;
1712 if (pmap_type_guest(pmap)) {
1713 pmap_invalidate_ept(pmap);
1717 KASSERT(pmap->pm_type == PT_X86,
1718 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1721 if (pmap == kernel_pmap) {
1725 cpuid = PCPU_GET(cpuid);
1726 if (pmap == PCPU_GET(curpmap)) {
1728 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1730 * Disable context switching. pm_pcid
1731 * is recalculated on switch, which
1732 * might make us use wrong pcid below.
1735 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1737 if (invpcid_works) {
1738 d.pcid = pcid | PMAP_PCID_USER_PT;
1741 invpcid(&d, INVPCID_ADDR);
1743 kcr3 = pmap->pm_cr3 | pcid |
1745 ucr3 = pmap->pm_ucr3 | pcid |
1746 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1747 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
1751 } else if (pmap_pcid_enabled)
1752 pmap->pm_pcids[cpuid].pm_gen = 0;
1753 if (pmap_pcid_enabled) {
1756 pmap->pm_pcids[i].pm_gen = 0;
1760 * The fence is between stores to pm_gen and the read of
1761 * the pm_active mask. We need to ensure that it is
1762 * impossible for us to miss the bit update in pm_active
1763 * and simultaneously observe a non-zero pm_gen in
1764 * pmap_activate_sw(), otherwise TLB update is missed.
1765 * Without the fence, IA32 allows such an outcome.
1766 * Note that pm_active is updated by a locked operation,
1767 * which provides the reciprocal fence.
1769 atomic_thread_fence_seq_cst();
1771 mask = &pmap->pm_active;
1773 smp_masked_invlpg(*mask, va, pmap);
1777 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1778 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1781 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1784 struct invpcid_descr d;
1786 uint64_t kcr3, ucr3;
1790 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1791 pmap_invalidate_all(pmap);
1795 if (pmap_type_guest(pmap)) {
1796 pmap_invalidate_ept(pmap);
1800 KASSERT(pmap->pm_type == PT_X86,
1801 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1804 cpuid = PCPU_GET(cpuid);
1805 if (pmap == kernel_pmap) {
1806 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1810 if (pmap == PCPU_GET(curpmap)) {
1811 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1813 if (pmap_pcid_enabled && pmap->pm_ucr3 != PMAP_NO_CR3) {
1815 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1816 if (invpcid_works) {
1817 d.pcid = pcid | PMAP_PCID_USER_PT;
1820 for (; d.addr < eva; d.addr +=
1822 invpcid(&d, INVPCID_ADDR);
1824 kcr3 = pmap->pm_cr3 | pcid |
1826 ucr3 = pmap->pm_ucr3 | pcid |
1827 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
1828 pmap_pti_pcid_invlrng(ucr3, kcr3, sva,
1833 } else if (pmap_pcid_enabled) {
1834 pmap->pm_pcids[cpuid].pm_gen = 0;
1836 if (pmap_pcid_enabled) {
1839 pmap->pm_pcids[i].pm_gen = 0;
1841 /* See the comment in pmap_invalidate_page(). */
1842 atomic_thread_fence_seq_cst();
1844 mask = &pmap->pm_active;
1846 smp_masked_invlpg_range(*mask, sva, eva, pmap);
1851 pmap_invalidate_all(pmap_t pmap)
1854 struct invpcid_descr d;
1855 uint64_t kcr3, ucr3;
1859 if (pmap_type_guest(pmap)) {
1860 pmap_invalidate_ept(pmap);
1864 KASSERT(pmap->pm_type == PT_X86,
1865 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1868 if (pmap == kernel_pmap) {
1869 if (pmap_pcid_enabled && invpcid_works) {
1870 bzero(&d, sizeof(d));
1871 invpcid(&d, INVPCID_CTXGLOB);
1877 cpuid = PCPU_GET(cpuid);
1878 if (pmap == PCPU_GET(curpmap)) {
1879 if (pmap_pcid_enabled) {
1881 pcid = pmap->pm_pcids[cpuid].pm_pcid;
1882 if (invpcid_works) {
1886 invpcid(&d, INVPCID_CTX);
1887 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
1888 d.pcid |= PMAP_PCID_USER_PT;
1889 invpcid(&d, INVPCID_CTX);
1892 kcr3 = pmap->pm_cr3 | pcid;
1893 ucr3 = pmap->pm_ucr3;
1894 if (ucr3 != PMAP_NO_CR3) {
1895 ucr3 |= pcid | PMAP_PCID_USER_PT;
1896 pmap_pti_pcid_invalidate(ucr3,
1906 } else if (pmap_pcid_enabled) {
1907 pmap->pm_pcids[cpuid].pm_gen = 0;
1909 if (pmap_pcid_enabled) {
1912 pmap->pm_pcids[i].pm_gen = 0;
1914 /* See the comment in pmap_invalidate_page(). */
1915 atomic_thread_fence_seq_cst();
1917 mask = &pmap->pm_active;
1919 smp_masked_invltlb(*mask, pmap);
1924 pmap_invalidate_cache(void)
1934 cpuset_t invalidate; /* processors that invalidate their TLB */
1939 u_int store; /* processor that updates the PDE */
1943 pmap_update_pde_action(void *arg)
1945 struct pde_action *act = arg;
1947 if (act->store == PCPU_GET(cpuid))
1948 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1952 pmap_update_pde_teardown(void *arg)
1954 struct pde_action *act = arg;
1956 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1957 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1961 * Change the page size for the specified virtual address in a way that
1962 * prevents any possibility of the TLB ever having two entries that map the
1963 * same virtual address using different page sizes. This is the recommended
1964 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1965 * machine check exception for a TLB state that is improperly diagnosed as a
1969 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1971 struct pde_action act;
1972 cpuset_t active, other_cpus;
1976 cpuid = PCPU_GET(cpuid);
1977 other_cpus = all_cpus;
1978 CPU_CLR(cpuid, &other_cpus);
1979 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1982 active = pmap->pm_active;
1984 if (CPU_OVERLAP(&active, &other_cpus)) {
1986 act.invalidate = active;
1990 act.newpde = newpde;
1991 CPU_SET(cpuid, &active);
1992 smp_rendezvous_cpus(active,
1993 smp_no_rendezvous_barrier, pmap_update_pde_action,
1994 pmap_update_pde_teardown, &act);
1996 pmap_update_pde_store(pmap, pde, newpde);
1997 if (CPU_ISSET(cpuid, &active))
1998 pmap_update_pde_invalidate(pmap, va, newpde);
2004 * Normal, non-SMP, invalidation functions.
2007 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2009 struct invpcid_descr d;
2010 uint64_t kcr3, ucr3;
2013 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2017 KASSERT(pmap->pm_type == PT_X86,
2018 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2020 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2022 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2023 pmap->pm_ucr3 != PMAP_NO_CR3) {
2025 pcid = pmap->pm_pcids[0].pm_pcid;
2026 if (invpcid_works) {
2027 d.pcid = pcid | PMAP_PCID_USER_PT;
2030 invpcid(&d, INVPCID_ADDR);
2032 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2033 ucr3 = pmap->pm_ucr3 | pcid |
2034 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2035 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2039 } else if (pmap_pcid_enabled)
2040 pmap->pm_pcids[0].pm_gen = 0;
2044 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2046 struct invpcid_descr d;
2048 uint64_t kcr3, ucr3;
2050 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2054 KASSERT(pmap->pm_type == PT_X86,
2055 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2057 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2058 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2060 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2061 pmap->pm_ucr3 != PMAP_NO_CR3) {
2063 if (invpcid_works) {
2064 d.pcid = pmap->pm_pcids[0].pm_pcid |
2068 for (; d.addr < eva; d.addr += PAGE_SIZE)
2069 invpcid(&d, INVPCID_ADDR);
2071 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2072 pm_pcid | CR3_PCID_SAVE;
2073 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2074 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2075 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2079 } else if (pmap_pcid_enabled) {
2080 pmap->pm_pcids[0].pm_gen = 0;
2085 pmap_invalidate_all(pmap_t pmap)
2087 struct invpcid_descr d;
2088 uint64_t kcr3, ucr3;
2090 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2094 KASSERT(pmap->pm_type == PT_X86,
2095 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2097 if (pmap == kernel_pmap) {
2098 if (pmap_pcid_enabled && invpcid_works) {
2099 bzero(&d, sizeof(d));
2100 invpcid(&d, INVPCID_CTXGLOB);
2104 } else if (pmap == PCPU_GET(curpmap)) {
2105 if (pmap_pcid_enabled) {
2107 if (invpcid_works) {
2108 d.pcid = pmap->pm_pcids[0].pm_pcid;
2111 invpcid(&d, INVPCID_CTX);
2112 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2113 d.pcid |= PMAP_PCID_USER_PT;
2114 invpcid(&d, INVPCID_CTX);
2117 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2118 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2119 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2120 0].pm_pcid | PMAP_PCID_USER_PT;
2121 pmap_pti_pcid_invalidate(ucr3, kcr3);
2129 } else if (pmap_pcid_enabled) {
2130 pmap->pm_pcids[0].pm_gen = 0;
2135 pmap_invalidate_cache(void)
2142 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2145 pmap_update_pde_store(pmap, pde, newpde);
2146 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2147 pmap_update_pde_invalidate(pmap, va, newpde);
2149 pmap->pm_pcids[0].pm_gen = 0;
2154 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2158 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2159 * by a promotion that did not invalidate the 512 4KB page mappings
2160 * that might exist in the TLB. Consequently, at this point, the TLB
2161 * may hold both 4KB and 2MB page mappings for the address range [va,
2162 * va + NBPDR). Therefore, the entire range must be invalidated here.
2163 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2164 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2165 * single INVLPG suffices to invalidate the 2MB page mapping from the
2168 if ((pde & PG_PROMOTED) != 0)
2169 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2171 pmap_invalidate_page(pmap, va);
2174 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2177 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
2181 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2183 KASSERT((sva & PAGE_MASK) == 0,
2184 ("pmap_invalidate_cache_range: sva not page-aligned"));
2185 KASSERT((eva & PAGE_MASK) == 0,
2186 ("pmap_invalidate_cache_range: eva not page-aligned"));
2189 if ((cpu_feature & CPUID_SS) != 0 && !force)
2190 ; /* If "Self Snoop" is supported and allowed, do nothing. */
2191 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
2192 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2194 * XXX: Some CPUs fault, hang, or trash the local APIC
2195 * registers if we use CLFLUSH on the local APIC
2196 * range. The local APIC is always uncached, so we
2197 * don't need to flush for that range anyway.
2199 if (pmap_kextract(sva) == lapic_paddr)
2203 * Otherwise, do per-cache line flush. Use the sfence
2204 * instruction to insure that previous stores are
2205 * included in the write-back. The processor
2206 * propagates flush to other processors in the cache
2210 for (; sva < eva; sva += cpu_clflush_line_size)
2213 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
2214 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
2215 if (pmap_kextract(sva) == lapic_paddr)
2218 * Writes are ordered by CLFLUSH on Intel CPUs.
2220 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2222 for (; sva < eva; sva += cpu_clflush_line_size)
2224 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2229 * No targeted cache flush methods are supported by CPU,
2230 * or the supplied range is bigger than 2MB.
2231 * Globally invalidate cache.
2233 pmap_invalidate_cache();
2238 * Remove the specified set of pages from the data and instruction caches.
2240 * In contrast to pmap_invalidate_cache_range(), this function does not
2241 * rely on the CPU's self-snoop feature, because it is intended for use
2242 * when moving pages into a different cache domain.
2245 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2247 vm_offset_t daddr, eva;
2251 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2252 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2253 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2254 pmap_invalidate_cache();
2258 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2260 for (i = 0; i < count; i++) {
2261 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2262 eva = daddr + PAGE_SIZE;
2263 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2272 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2278 * Routine: pmap_extract
2280 * Extract the physical page address associated
2281 * with the given map/virtual_address pair.
2284 pmap_extract(pmap_t pmap, vm_offset_t va)
2288 pt_entry_t *pte, PG_V;
2292 PG_V = pmap_valid_bit(pmap);
2294 pdpe = pmap_pdpe(pmap, va);
2295 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2296 if ((*pdpe & PG_PS) != 0)
2297 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
2299 pde = pmap_pdpe_to_pde(pdpe, va);
2300 if ((*pde & PG_V) != 0) {
2301 if ((*pde & PG_PS) != 0) {
2302 pa = (*pde & PG_PS_FRAME) |
2305 pte = pmap_pde_to_pte(pde, va);
2306 pa = (*pte & PG_FRAME) |
2317 * Routine: pmap_extract_and_hold
2319 * Atomically extract and hold the physical page
2320 * with the given pmap and virtual address pair
2321 * if that mapping permits the given protection.
2324 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
2326 pd_entry_t pde, *pdep;
2327 pt_entry_t pte, PG_RW, PG_V;
2333 PG_RW = pmap_rw_bit(pmap);
2334 PG_V = pmap_valid_bit(pmap);
2337 pdep = pmap_pde(pmap, va);
2338 if (pdep != NULL && (pde = *pdep)) {
2340 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
2341 if (vm_page_pa_tryrelock(pmap, (pde &
2342 PG_PS_FRAME) | (va & PDRMASK), &pa))
2344 m = PHYS_TO_VM_PAGE(pa);
2347 pte = *pmap_pde_to_pte(pdep, va);
2349 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
2350 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
2353 m = PHYS_TO_VM_PAGE(pa);
2365 pmap_kextract(vm_offset_t va)
2370 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
2371 pa = DMAP_TO_PHYS(va);
2375 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
2378 * Beware of a concurrent promotion that changes the
2379 * PDE at this point! For example, vtopte() must not
2380 * be used to access the PTE because it would use the
2381 * new PDE. It is, however, safe to use the old PDE
2382 * because the page table page is preserved by the
2385 pa = *pmap_pde_to_pte(&pde, va);
2386 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
2392 /***************************************************
2393 * Low level mapping routines.....
2394 ***************************************************/
2397 * Add a wired page to the kva.
2398 * Note: not SMP coherent.
2401 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2406 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
2409 static __inline void
2410 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
2416 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
2417 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
2421 * Remove a page from the kernel pagetables.
2422 * Note: not SMP coherent.
2425 pmap_kremove(vm_offset_t va)
2434 * Used to map a range of physical addresses into kernel
2435 * virtual address space.
2437 * The value passed in '*virt' is a suggested virtual address for
2438 * the mapping. Architectures which can support a direct-mapped
2439 * physical to virtual region can return the appropriate address
2440 * within that region, leaving '*virt' unchanged. Other
2441 * architectures should map the pages starting at '*virt' and
2442 * update '*virt' with the first usable address after the mapped
2446 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
2448 return PHYS_TO_DMAP(start);
2453 * Add a list of wired pages to the kva
2454 * this routine is only used for temporary
2455 * kernel mappings that do not need to have
2456 * page modification or references recorded.
2457 * Note that old mappings are simply written
2458 * over. The page *must* be wired.
2459 * Note: SMP coherent. Uses a ranged shootdown IPI.
2462 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2464 pt_entry_t *endpte, oldpte, pa, *pte;
2470 endpte = pte + count;
2471 while (pte < endpte) {
2473 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2474 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2475 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2477 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
2481 if (__predict_false((oldpte & X86_PG_V) != 0))
2482 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2487 * This routine tears out page mappings from the
2488 * kernel -- it is meant only for temporary mappings.
2489 * Note: SMP coherent. Uses a ranged shootdown IPI.
2492 pmap_qremove(vm_offset_t sva, int count)
2497 while (count-- > 0) {
2498 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2502 pmap_invalidate_range(kernel_pmap, sva, va);
2505 /***************************************************
2506 * Page table page management routines.....
2507 ***************************************************/
2509 * Schedule the specified unused page table page to be freed. Specifically,
2510 * add the page to the specified list of pages that will be released to the
2511 * physical memory manager after the TLB has been updated.
2513 static __inline void
2514 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2515 boolean_t set_PG_ZERO)
2519 m->flags |= PG_ZERO;
2521 m->flags &= ~PG_ZERO;
2522 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2526 * Inserts the specified page table page into the specified pmap's collection
2527 * of idle page table pages. Each of a pmap's page table pages is responsible
2528 * for mapping a distinct range of virtual addresses. The pmap's collection is
2529 * ordered by this virtual address range.
2532 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2535 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2536 return (vm_radix_insert(&pmap->pm_root, mpte));
2540 * Removes the page table page mapping the specified virtual address from the
2541 * specified pmap's collection of idle page table pages, and returns it.
2542 * Otherwise, returns NULL if there is no page table page corresponding to the
2543 * specified virtual address.
2545 static __inline vm_page_t
2546 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2550 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
2554 * Decrements a page table page's wire count, which is used to record the
2555 * number of valid page table entries within the page. If the wire count
2556 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2557 * page table page was unmapped and FALSE otherwise.
2559 static inline boolean_t
2560 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2564 if (m->wire_count == 0) {
2565 _pmap_unwire_ptp(pmap, va, m, free);
2572 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2575 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2577 * unmap the page table page
2579 if (m->pindex >= (NUPDE + NUPDPE)) {
2582 pml4 = pmap_pml4e(pmap, va);
2584 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
2585 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
2588 } else if (m->pindex >= NUPDE) {
2591 pdp = pmap_pdpe(pmap, va);
2596 pd = pmap_pde(pmap, va);
2599 pmap_resident_count_dec(pmap, 1);
2600 if (m->pindex < NUPDE) {
2601 /* We just released a PT, unhold the matching PD */
2604 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2605 pmap_unwire_ptp(pmap, va, pdpg, free);
2607 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2608 /* We just released a PD, unhold the matching PDP */
2611 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2612 pmap_unwire_ptp(pmap, va, pdppg, free);
2616 * Put page on a list so that it is released after
2617 * *ALL* TLB shootdown is done
2619 pmap_add_delayed_free_list(m, free, TRUE);
2623 * After removing a page table entry, this routine is used to
2624 * conditionally free the page, and manage the hold/wire counts.
2627 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2628 struct spglist *free)
2632 if (va >= VM_MAXUSER_ADDRESS)
2634 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2635 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2636 return (pmap_unwire_ptp(pmap, va, mpte, free));
2640 pmap_pinit0(pmap_t pmap)
2644 PMAP_LOCK_INIT(pmap);
2645 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2646 pmap->pm_pml4u = NULL;
2647 pmap->pm_cr3 = KPML4phys;
2648 /* hack to keep pmap_pti_pcid_invalidate() alive */
2649 pmap->pm_ucr3 = PMAP_NO_CR3;
2650 pmap->pm_root.rt_root = 0;
2651 CPU_ZERO(&pmap->pm_active);
2652 TAILQ_INIT(&pmap->pm_pvchunk);
2653 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2654 pmap->pm_flags = pmap_flags;
2656 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
2657 pmap->pm_pcids[i].pm_gen = 1;
2659 pmap_activate_boot(pmap);
2663 pmap_pinit_pml4(vm_page_t pml4pg)
2665 pml4_entry_t *pm_pml4;
2668 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2670 /* Wire in kernel global address entries. */
2671 for (i = 0; i < NKPML4E; i++) {
2672 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
2675 for (i = 0; i < ndmpdpphys; i++) {
2676 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
2680 /* install self-referential address mapping entry(s) */
2681 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
2682 X86_PG_A | X86_PG_M;
2686 pmap_pinit_pml4_pti(vm_page_t pml4pg)
2688 pml4_entry_t *pm_pml4;
2691 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
2692 for (i = 0; i < NPML4EPG; i++)
2693 pm_pml4[i] = pti_pml4[i];
2697 * Initialize a preallocated and zeroed pmap structure,
2698 * such as one in a vmspace structure.
2701 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2703 vm_page_t pml4pg, pml4pgu;
2704 vm_paddr_t pml4phys;
2708 * allocate the page directory page
2710 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2711 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2713 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2714 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2716 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2717 pmap->pm_pcids[i].pm_gen = 0;
2719 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
2720 pmap->pm_ucr3 = PMAP_NO_CR3;
2721 pmap->pm_pml4u = NULL;
2723 pmap->pm_type = pm_type;
2724 if ((pml4pg->flags & PG_ZERO) == 0)
2725 pagezero(pmap->pm_pml4);
2728 * Do not install the host kernel mappings in the nested page
2729 * tables. These mappings are meaningless in the guest physical
2731 * Install minimal kernel mappings in PTI case.
2733 if (pm_type == PT_X86) {
2734 pmap->pm_cr3 = pml4phys;
2735 pmap_pinit_pml4(pml4pg);
2737 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2738 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
2739 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
2740 VM_PAGE_TO_PHYS(pml4pgu));
2741 pmap_pinit_pml4_pti(pml4pgu);
2742 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
2746 pmap->pm_root.rt_root = 0;
2747 CPU_ZERO(&pmap->pm_active);
2748 TAILQ_INIT(&pmap->pm_pvchunk);
2749 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2750 pmap->pm_flags = flags;
2751 pmap->pm_eptgen = 0;
2757 pmap_pinit(pmap_t pmap)
2760 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2764 * This routine is called if the desired page table page does not exist.
2766 * If page table page allocation fails, this routine may sleep before
2767 * returning NULL. It sleeps only if a lock pointer was given.
2769 * Note: If a page allocation fails at page table level two or three,
2770 * one or two pages may be held during the wait, only to be released
2771 * afterwards. This conservative approach is easily argued to avoid
2775 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2777 vm_page_t m, pdppg, pdpg;
2778 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2780 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2782 PG_A = pmap_accessed_bit(pmap);
2783 PG_M = pmap_modified_bit(pmap);
2784 PG_V = pmap_valid_bit(pmap);
2785 PG_RW = pmap_rw_bit(pmap);
2788 * Allocate a page table page.
2790 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2791 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2792 if (lockp != NULL) {
2793 RELEASE_PV_LIST_LOCK(lockp);
2795 PMAP_ASSERT_NOT_IN_DI();
2801 * Indicate the need to retry. While waiting, the page table
2802 * page may have been allocated.
2806 if ((m->flags & PG_ZERO) == 0)
2810 * Map the pagetable page into the process address space, if
2811 * it isn't already there.
2814 if (ptepindex >= (NUPDE + NUPDPE)) {
2815 pml4_entry_t *pml4, *pml4u;
2816 vm_pindex_t pml4index;
2818 /* Wire up a new PDPE page */
2819 pml4index = ptepindex - (NUPDE + NUPDPE);
2820 pml4 = &pmap->pm_pml4[pml4index];
2821 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2822 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
2824 * PTI: Make all user-space mappings in the
2825 * kernel-mode page table no-execute so that
2826 * we detect any programming errors that leave
2827 * the kernel-mode page table active on return
2830 if (pmap->pm_ucr3 != PMAP_NO_CR3)
2833 pml4u = &pmap->pm_pml4u[pml4index];
2834 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
2838 } else if (ptepindex >= NUPDE) {
2839 vm_pindex_t pml4index;
2840 vm_pindex_t pdpindex;
2844 /* Wire up a new PDE page */
2845 pdpindex = ptepindex - NUPDE;
2846 pml4index = pdpindex >> NPML4EPGSHIFT;
2848 pml4 = &pmap->pm_pml4[pml4index];
2849 if ((*pml4 & PG_V) == 0) {
2850 /* Have to allocate a new pdp, recurse */
2851 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2853 vm_page_unwire_noq(m);
2854 vm_page_free_zero(m);
2858 /* Add reference to pdp page */
2859 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2860 pdppg->wire_count++;
2862 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2864 /* Now find the pdp page */
2865 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2866 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2869 vm_pindex_t pml4index;
2870 vm_pindex_t pdpindex;
2875 /* Wire up a new PTE page */
2876 pdpindex = ptepindex >> NPDPEPGSHIFT;
2877 pml4index = pdpindex >> NPML4EPGSHIFT;
2879 /* First, find the pdp and check that its valid. */
2880 pml4 = &pmap->pm_pml4[pml4index];
2881 if ((*pml4 & PG_V) == 0) {
2882 /* Have to allocate a new pd, recurse */
2883 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2885 vm_page_unwire_noq(m);
2886 vm_page_free_zero(m);
2889 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2890 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2892 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2893 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2894 if ((*pdp & PG_V) == 0) {
2895 /* Have to allocate a new pd, recurse */
2896 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2898 vm_page_unwire_noq(m);
2899 vm_page_free_zero(m);
2903 /* Add reference to the pd page */
2904 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2908 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2910 /* Now we know where the page directory page is */
2911 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2912 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2915 pmap_resident_count_inc(pmap, 1);
2921 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2923 vm_pindex_t pdpindex, ptepindex;
2924 pdp_entry_t *pdpe, PG_V;
2927 PG_V = pmap_valid_bit(pmap);
2930 pdpe = pmap_pdpe(pmap, va);
2931 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2932 /* Add a reference to the pd page. */
2933 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2936 /* Allocate a pd page. */
2937 ptepindex = pmap_pde_pindex(va);
2938 pdpindex = ptepindex >> NPDPEPGSHIFT;
2939 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2940 if (pdpg == NULL && lockp != NULL)
2947 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2949 vm_pindex_t ptepindex;
2950 pd_entry_t *pd, PG_V;
2953 PG_V = pmap_valid_bit(pmap);
2956 * Calculate pagetable page index
2958 ptepindex = pmap_pde_pindex(va);
2961 * Get the page directory entry
2963 pd = pmap_pde(pmap, va);
2966 * This supports switching from a 2MB page to a
2969 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2970 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2972 * Invalidation of the 2MB page mapping may have caused
2973 * the deallocation of the underlying PD page.
2980 * If the page table page is mapped, we just increment the
2981 * hold count, and activate it.
2983 if (pd != NULL && (*pd & PG_V) != 0) {
2984 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2988 * Here if the pte page isn't mapped, or if it has been
2991 m = _pmap_allocpte(pmap, ptepindex, lockp);
2992 if (m == NULL && lockp != NULL)
2999 /***************************************************
3000 * Pmap allocation/deallocation routines.
3001 ***************************************************/
3004 * Release any resources held by the given physical map.
3005 * Called when a pmap initialized by pmap_pinit is being released.
3006 * Should only be called if the map contains no valid mappings.
3009 pmap_release(pmap_t pmap)
3014 KASSERT(pmap->pm_stats.resident_count == 0,
3015 ("pmap_release: pmap resident count %ld != 0",
3016 pmap->pm_stats.resident_count));
3017 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3018 ("pmap_release: pmap has reserved page table page(s)"));
3019 KASSERT(CPU_EMPTY(&pmap->pm_active),
3020 ("releasing active pmap %p", pmap));
3022 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3024 for (i = 0; i < NKPML4E; i++) /* KVA */
3025 pmap->pm_pml4[KPML4BASE + i] = 0;
3026 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3027 pmap->pm_pml4[DMPML4I + i] = 0;
3028 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3030 vm_page_unwire_noq(m);
3031 vm_page_free_zero(m);
3033 if (pmap->pm_pml4u != NULL) {
3034 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3035 vm_page_unwire_noq(m);
3041 kvm_size(SYSCTL_HANDLER_ARGS)
3043 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3045 return sysctl_handle_long(oidp, &ksize, 0, req);
3047 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3048 0, 0, kvm_size, "LU", "Size of KVM");
3051 kvm_free(SYSCTL_HANDLER_ARGS)
3053 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3055 return sysctl_handle_long(oidp, &kfree, 0, req);
3057 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3058 0, 0, kvm_free, "LU", "Amount of KVM free");
3061 * grow the number of kernel page table entries, if needed
3064 pmap_growkernel(vm_offset_t addr)
3068 pd_entry_t *pde, newpdir;
3071 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3074 * Return if "addr" is within the range of kernel page table pages
3075 * that were preallocated during pmap bootstrap. Moreover, leave
3076 * "kernel_vm_end" and the kernel page table as they were.
3078 * The correctness of this action is based on the following
3079 * argument: vm_map_insert() allocates contiguous ranges of the
3080 * kernel virtual address space. It calls this function if a range
3081 * ends after "kernel_vm_end". If the kernel is mapped between
3082 * "kernel_vm_end" and "addr", then the range cannot begin at
3083 * "kernel_vm_end". In fact, its beginning address cannot be less
3084 * than the kernel. Thus, there is no immediate need to allocate
3085 * any new kernel page table pages between "kernel_vm_end" and
3088 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3091 addr = roundup2(addr, NBPDR);
3092 if (addr - 1 >= vm_map_max(kernel_map))
3093 addr = vm_map_max(kernel_map);
3094 while (kernel_vm_end < addr) {
3095 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3096 if ((*pdpe & X86_PG_V) == 0) {
3097 /* We need a new PDP entry */
3098 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3099 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3100 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3102 panic("pmap_growkernel: no memory to grow kernel");
3103 if ((nkpg->flags & PG_ZERO) == 0)
3104 pmap_zero_page(nkpg);
3105 paddr = VM_PAGE_TO_PHYS(nkpg);
3106 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3107 X86_PG_A | X86_PG_M);
3108 continue; /* try again */
3110 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3111 if ((*pde & X86_PG_V) != 0) {
3112 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3113 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3114 kernel_vm_end = vm_map_max(kernel_map);
3120 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3121 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3124 panic("pmap_growkernel: no memory to grow kernel");
3125 if ((nkpg->flags & PG_ZERO) == 0)
3126 pmap_zero_page(nkpg);
3127 paddr = VM_PAGE_TO_PHYS(nkpg);
3128 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3129 pde_store(pde, newpdir);
3131 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3132 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3133 kernel_vm_end = vm_map_max(kernel_map);
3140 /***************************************************
3141 * page management routines.
3142 ***************************************************/
3144 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3145 CTASSERT(_NPCM == 3);
3146 CTASSERT(_NPCPV == 168);
3148 static __inline struct pv_chunk *
3149 pv_to_chunk(pv_entry_t pv)
3152 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3155 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3157 #define PC_FREE0 0xfffffffffffffffful
3158 #define PC_FREE1 0xfffffffffffffffful
3159 #define PC_FREE2 0x000000fffffffffful
3161 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3164 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3166 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3167 "Current number of pv entry chunks");
3168 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3169 "Current number of pv entry chunks allocated");
3170 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3171 "Current number of pv entry chunks frees");
3172 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3173 "Number of times tried to get a chunk page but failed.");
3175 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3176 static int pv_entry_spare;
3178 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3179 "Current number of pv entry frees");
3180 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3181 "Current number of pv entry allocs");
3182 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3183 "Current number of pv entries");
3184 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3185 "Current number of spare pv entries");
3189 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3194 pmap_invalidate_all(pmap);
3195 if (pmap != locked_pmap)
3198 pmap_delayed_invl_finished();
3202 * We are in a serious low memory condition. Resort to
3203 * drastic measures to free some pages so we can allocate
3204 * another pv entry chunk.
3206 * Returns NULL if PV entries were reclaimed from the specified pmap.
3208 * We do not, however, unmap 2mpages because subsequent accesses will
3209 * allocate per-page pv entries until repromotion occurs, thereby
3210 * exacerbating the shortage of free pv entries.
3213 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3215 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3216 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3217 struct md_page *pvh;
3219 pmap_t next_pmap, pmap;
3220 pt_entry_t *pte, tpte;
3221 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3225 struct spglist free;
3227 int bit, field, freed;
3229 static int active_reclaims = 0;
3231 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
3232 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
3235 PG_G = PG_A = PG_M = PG_RW = 0;
3237 bzero(&pc_marker_b, sizeof(pc_marker_b));
3238 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
3239 pc_marker = (struct pv_chunk *)&pc_marker_b;
3240 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
3243 * A delayed invalidation block should already be active if
3244 * pmap_advise() or pmap_remove() called this function by way
3245 * of pmap_demote_pde_locked().
3247 start_di = pmap_not_in_di();
3249 mtx_lock(&pv_chunks_mutex);
3251 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
3252 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
3253 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
3254 SLIST_EMPTY(&free)) {
3255 next_pmap = pc->pc_pmap;
3256 if (next_pmap == NULL) {
3258 * The next chunk is a marker. However, it is
3259 * not our marker, so active_reclaims must be
3260 * > 1. Consequently, the next_chunk code
3261 * will not rotate the pv_chunks list.
3265 mtx_unlock(&pv_chunks_mutex);
3268 * A pv_chunk can only be removed from the pc_lru list
3269 * when both pc_chunks_mutex is owned and the
3270 * corresponding pmap is locked.
3272 if (pmap != next_pmap) {
3273 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
3276 /* Avoid deadlock and lock recursion. */
3277 if (pmap > locked_pmap) {
3278 RELEASE_PV_LIST_LOCK(lockp);
3281 pmap_delayed_invl_started();
3282 mtx_lock(&pv_chunks_mutex);
3284 } else if (pmap != locked_pmap) {
3285 if (PMAP_TRYLOCK(pmap)) {
3287 pmap_delayed_invl_started();
3288 mtx_lock(&pv_chunks_mutex);
3291 pmap = NULL; /* pmap is not locked */
3292 mtx_lock(&pv_chunks_mutex);
3293 pc = TAILQ_NEXT(pc_marker, pc_lru);
3295 pc->pc_pmap != next_pmap)
3299 } else if (start_di)
3300 pmap_delayed_invl_started();
3301 PG_G = pmap_global_bit(pmap);
3302 PG_A = pmap_accessed_bit(pmap);
3303 PG_M = pmap_modified_bit(pmap);
3304 PG_RW = pmap_rw_bit(pmap);
3308 * Destroy every non-wired, 4 KB page mapping in the chunk.
3311 for (field = 0; field < _NPCM; field++) {
3312 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
3313 inuse != 0; inuse &= ~(1UL << bit)) {
3315 pv = &pc->pc_pventry[field * 64 + bit];
3317 pde = pmap_pde(pmap, va);
3318 if ((*pde & PG_PS) != 0)
3320 pte = pmap_pde_to_pte(pde, va);
3321 if ((*pte & PG_W) != 0)
3323 tpte = pte_load_clear(pte);
3324 if ((tpte & PG_G) != 0)
3325 pmap_invalidate_page(pmap, va);
3326 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
3327 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3329 if ((tpte & PG_A) != 0)
3330 vm_page_aflag_set(m, PGA_REFERENCED);
3331 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3332 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3334 if (TAILQ_EMPTY(&m->md.pv_list) &&
3335 (m->flags & PG_FICTITIOUS) == 0) {
3336 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3337 if (TAILQ_EMPTY(&pvh->pv_list)) {
3338 vm_page_aflag_clear(m,
3342 pmap_delayed_invl_page(m);
3343 pc->pc_map[field] |= 1UL << bit;
3344 pmap_unuse_pt(pmap, va, *pde, &free);
3349 mtx_lock(&pv_chunks_mutex);
3352 /* Every freed mapping is for a 4 KB page. */
3353 pmap_resident_count_dec(pmap, freed);
3354 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3355 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3356 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3357 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3358 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
3359 pc->pc_map[2] == PC_FREE2) {
3360 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3361 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3362 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3363 /* Entire chunk is free; return it. */
3364 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3365 dump_drop_page(m_pc->phys_addr);
3366 mtx_lock(&pv_chunks_mutex);
3367 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3370 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3371 mtx_lock(&pv_chunks_mutex);
3372 /* One freed pv entry in locked_pmap is sufficient. */
3373 if (pmap == locked_pmap)
3376 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3377 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
3378 if (active_reclaims == 1 && pmap != NULL) {
3380 * Rotate the pv chunks list so that we do not
3381 * scan the same pv chunks that could not be
3382 * freed (because they contained a wired
3383 * and/or superpage mapping) on every
3384 * invocation of reclaim_pv_chunk().
3386 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
3387 MPASS(pc->pc_pmap != NULL);
3388 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3389 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3393 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
3394 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
3396 mtx_unlock(&pv_chunks_mutex);
3397 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
3398 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
3399 m_pc = SLIST_FIRST(&free);
3400 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
3401 /* Recycle a freed page table page. */
3402 m_pc->wire_count = 1;
3404 vm_page_free_pages_toq(&free, true);
3409 * free the pv_entry back to the free list
3412 free_pv_entry(pmap_t pmap, pv_entry_t pv)
3414 struct pv_chunk *pc;
3415 int idx, field, bit;
3417 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3418 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
3419 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
3420 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
3421 pc = pv_to_chunk(pv);
3422 idx = pv - &pc->pc_pventry[0];
3425 pc->pc_map[field] |= 1ul << bit;
3426 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
3427 pc->pc_map[2] != PC_FREE2) {
3428 /* 98% of the time, pc is already at the head of the list. */
3429 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
3430 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3431 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3435 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3440 free_pv_chunk(struct pv_chunk *pc)
3444 mtx_lock(&pv_chunks_mutex);
3445 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
3446 mtx_unlock(&pv_chunks_mutex);
3447 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
3448 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
3449 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
3450 /* entire chunk is free, return it */
3451 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
3452 dump_drop_page(m->phys_addr);
3453 vm_page_unwire(m, PQ_NONE);
3458 * Returns a new PV entry, allocating a new PV chunk from the system when
3459 * needed. If this PV chunk allocation fails and a PV list lock pointer was
3460 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
3463 * The given PV list lock may be released.
3466 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
3470 struct pv_chunk *pc;
3473 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3474 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
3476 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3478 for (field = 0; field < _NPCM; field++) {
3479 if (pc->pc_map[field]) {
3480 bit = bsfq(pc->pc_map[field]);
3484 if (field < _NPCM) {
3485 pv = &pc->pc_pventry[field * 64 + bit];
3486 pc->pc_map[field] &= ~(1ul << bit);
3487 /* If this was the last item, move it to tail */
3488 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
3489 pc->pc_map[2] == 0) {
3490 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3491 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
3494 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3495 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
3499 /* No free items, allocate another chunk */
3500 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3503 if (lockp == NULL) {
3504 PV_STAT(pc_chunk_tryfail++);
3507 m = reclaim_pv_chunk(pmap, lockp);
3511 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3512 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3513 dump_add_page(m->phys_addr);
3514 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3516 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
3517 pc->pc_map[1] = PC_FREE1;
3518 pc->pc_map[2] = PC_FREE2;
3519 mtx_lock(&pv_chunks_mutex);
3520 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
3521 mtx_unlock(&pv_chunks_mutex);
3522 pv = &pc->pc_pventry[0];
3523 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3524 PV_STAT(atomic_add_long(&pv_entry_count, 1));
3525 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
3530 * Returns the number of one bits within the given PV chunk map.
3532 * The erratas for Intel processors state that "POPCNT Instruction May
3533 * Take Longer to Execute Than Expected". It is believed that the
3534 * issue is the spurious dependency on the destination register.
3535 * Provide a hint to the register rename logic that the destination
3536 * value is overwritten, by clearing it, as suggested in the
3537 * optimization manual. It should be cheap for unaffected processors
3540 * Reference numbers for erratas are
3541 * 4th Gen Core: HSD146
3542 * 5th Gen Core: BDM85
3543 * 6th Gen Core: SKL029
3546 popcnt_pc_map_pq(uint64_t *map)
3550 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
3551 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
3552 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
3553 : "=&r" (result), "=&r" (tmp)
3554 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
3559 * Ensure that the number of spare PV entries in the specified pmap meets or
3560 * exceeds the given count, "needed".
3562 * The given PV list lock may be released.
3565 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3567 struct pch new_tail;
3568 struct pv_chunk *pc;
3573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3574 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3577 * Newly allocated PV chunks must be stored in a private list until
3578 * the required number of PV chunks have been allocated. Otherwise,
3579 * reclaim_pv_chunk() could recycle one of these chunks. In
3580 * contrast, these chunks must be added to the pmap upon allocation.
3582 TAILQ_INIT(&new_tail);
3585 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3587 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
3588 bit_count((bitstr_t *)pc->pc_map, 0,
3589 sizeof(pc->pc_map) * NBBY, &free);
3592 free = popcnt_pc_map_pq(pc->pc_map);
3596 if (avail >= needed)
3599 for (reclaimed = false; avail < needed; avail += _NPCPV) {
3600 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3603 m = reclaim_pv_chunk(pmap, lockp);
3608 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3609 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3610 dump_add_page(m->phys_addr);
3611 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3613 pc->pc_map[0] = PC_FREE0;
3614 pc->pc_map[1] = PC_FREE1;
3615 pc->pc_map[2] = PC_FREE2;
3616 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3617 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3618 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3621 * The reclaim might have freed a chunk from the current pmap.
3622 * If that chunk contained available entries, we need to
3623 * re-count the number of available entries.
3628 if (!TAILQ_EMPTY(&new_tail)) {
3629 mtx_lock(&pv_chunks_mutex);
3630 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3631 mtx_unlock(&pv_chunks_mutex);
3636 * First find and then remove the pv entry for the specified pmap and virtual
3637 * address from the specified pv list. Returns the pv entry if found and NULL
3638 * otherwise. This operation can be performed on pv lists for either 4KB or
3639 * 2MB page mappings.
3641 static __inline pv_entry_t
3642 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3646 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3647 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3648 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3657 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3658 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3659 * entries for each of the 4KB page mappings.
3662 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3663 struct rwlock **lockp)
3665 struct md_page *pvh;
3666 struct pv_chunk *pc;
3668 vm_offset_t va_last;
3672 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3673 KASSERT((pa & PDRMASK) == 0,
3674 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3675 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3678 * Transfer the 2mpage's pv entry for this mapping to the first
3679 * page's pv list. Once this transfer begins, the pv list lock
3680 * must not be released until the last pv entry is reinstantiated.
3682 pvh = pa_to_pvh(pa);
3683 va = trunc_2mpage(va);
3684 pv = pmap_pvh_remove(pvh, pmap, va);
3685 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3686 m = PHYS_TO_VM_PAGE(pa);
3687 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3689 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3690 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3691 va_last = va + NBPDR - PAGE_SIZE;
3693 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3694 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3695 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3696 for (field = 0; field < _NPCM; field++) {
3697 while (pc->pc_map[field]) {
3698 bit = bsfq(pc->pc_map[field]);
3699 pc->pc_map[field] &= ~(1ul << bit);
3700 pv = &pc->pc_pventry[field * 64 + bit];
3704 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3705 ("pmap_pv_demote_pde: page %p is not managed", m));
3706 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3712 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3713 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3716 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3717 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3718 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3720 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3721 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3724 #if VM_NRESERVLEVEL > 0
3726 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3727 * replace the many pv entries for the 4KB page mappings by a single pv entry
3728 * for the 2MB page mapping.
3731 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3732 struct rwlock **lockp)
3734 struct md_page *pvh;
3736 vm_offset_t va_last;
3739 KASSERT((pa & PDRMASK) == 0,
3740 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3741 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3744 * Transfer the first page's pv entry for this mapping to the 2mpage's
3745 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3746 * a transfer avoids the possibility that get_pv_entry() calls
3747 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3748 * mappings that is being promoted.
3750 m = PHYS_TO_VM_PAGE(pa);
3751 va = trunc_2mpage(va);
3752 pv = pmap_pvh_remove(&m->md, pmap, va);
3753 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3754 pvh = pa_to_pvh(pa);
3755 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3757 /* Free the remaining NPTEPG - 1 pv entries. */
3758 va_last = va + NBPDR - PAGE_SIZE;
3762 pmap_pvh_free(&m->md, pmap, va);
3763 } while (va < va_last);
3765 #endif /* VM_NRESERVLEVEL > 0 */
3768 * First find and then destroy the pv entry for the specified pmap and virtual
3769 * address. This operation can be performed on pv lists for either 4KB or 2MB
3773 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3777 pv = pmap_pvh_remove(pvh, pmap, va);
3778 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3779 free_pv_entry(pmap, pv);
3783 * Conditionally create the PV entry for a 4KB page mapping if the required
3784 * memory can be allocated without resorting to reclamation.
3787 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3788 struct rwlock **lockp)
3792 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3793 /* Pass NULL instead of the lock pointer to disable reclamation. */
3794 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3796 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3797 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3805 * Create the PV entry for a 2MB page mapping. Always returns true unless the
3806 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
3807 * false if the PV entry cannot be allocated without resorting to reclamation.
3810 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
3811 struct rwlock **lockp)
3813 struct md_page *pvh;
3817 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3818 /* Pass NULL instead of the lock pointer to disable reclamation. */
3819 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
3820 NULL : lockp)) == NULL)
3823 pa = pde & PG_PS_FRAME;
3824 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3825 pvh = pa_to_pvh(pa);
3826 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3832 * Fills a page table page with mappings to consecutive physical pages.
3835 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3839 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3841 newpte += PAGE_SIZE;
3846 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3847 * mapping is invalidated.
3850 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3852 struct rwlock *lock;
3856 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3863 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3864 struct rwlock **lockp)
3866 pd_entry_t newpde, oldpde;
3867 pt_entry_t *firstpte, newpte;
3868 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3871 struct spglist free;
3875 PG_G = pmap_global_bit(pmap);
3876 PG_A = pmap_accessed_bit(pmap);
3877 PG_M = pmap_modified_bit(pmap);
3878 PG_RW = pmap_rw_bit(pmap);
3879 PG_V = pmap_valid_bit(pmap);
3880 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3882 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3884 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3885 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3886 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
3888 KASSERT((oldpde & PG_W) == 0,
3889 ("pmap_demote_pde: page table page for a wired mapping"
3893 * Invalidate the 2MB page mapping and return "failure" if the
3894 * mapping was never accessed or the allocation of the new
3895 * page table page fails. If the 2MB page mapping belongs to
3896 * the direct map region of the kernel's address space, then
3897 * the page allocation request specifies the highest possible
3898 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3899 * normal. Page table pages are preallocated for every other
3900 * part of the kernel address space, so the direct map region
3901 * is the only part of the kernel address space that must be
3904 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3905 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3906 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3907 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3909 sva = trunc_2mpage(va);
3910 pmap_remove_pde(pmap, pde, sva, &free, lockp);
3911 if ((oldpde & PG_G) == 0)
3912 pmap_invalidate_pde_page(pmap, sva, oldpde);
3913 vm_page_free_pages_toq(&free, true);
3914 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3915 " in pmap %p", va, pmap);
3918 if (va < VM_MAXUSER_ADDRESS)
3919 pmap_resident_count_inc(pmap, 1);
3921 mptepa = VM_PAGE_TO_PHYS(mpte);
3922 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3923 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3924 KASSERT((oldpde & PG_A) != 0,
3925 ("pmap_demote_pde: oldpde is missing PG_A"));
3926 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3927 ("pmap_demote_pde: oldpde is missing PG_M"));
3928 newpte = oldpde & ~PG_PS;
3929 newpte = pmap_swap_pat(pmap, newpte);
3932 * If the page table page is new, initialize it.
3934 if (mpte->wire_count == 1) {
3935 mpte->wire_count = NPTEPG;
3936 pmap_fill_ptp(firstpte, newpte);
3938 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3939 ("pmap_demote_pde: firstpte and newpte map different physical"
3943 * If the mapping has changed attributes, update the page table
3946 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3947 pmap_fill_ptp(firstpte, newpte);
3950 * The spare PV entries must be reserved prior to demoting the
3951 * mapping, that is, prior to changing the PDE. Otherwise, the state
3952 * of the PDE and the PV lists will be inconsistent, which can result
3953 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3954 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3955 * PV entry for the 2MB page mapping that is being demoted.
3957 if ((oldpde & PG_MANAGED) != 0)
3958 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3961 * Demote the mapping. This pmap is locked. The old PDE has
3962 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3963 * set. Thus, there is no danger of a race with another
3964 * processor changing the setting of PG_A and/or PG_M between
3965 * the read above and the store below.
3967 if (workaround_erratum383)
3968 pmap_update_pde(pmap, va, pde, newpde);
3970 pde_store(pde, newpde);
3973 * Invalidate a stale recursive mapping of the page table page.
3975 if (va >= VM_MAXUSER_ADDRESS)
3976 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3979 * Demote the PV entry.
3981 if ((oldpde & PG_MANAGED) != 0)
3982 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3984 atomic_add_long(&pmap_pde_demotions, 1);
3985 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3986 " in pmap %p", va, pmap);
3991 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3994 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4000 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4001 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4002 mpte = pmap_remove_pt_page(pmap, va);
4004 panic("pmap_remove_kernel_pde: Missing pt page.");
4006 mptepa = VM_PAGE_TO_PHYS(mpte);
4007 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4010 * Initialize the page table page.
4012 pagezero((void *)PHYS_TO_DMAP(mptepa));
4015 * Demote the mapping.
4017 if (workaround_erratum383)
4018 pmap_update_pde(pmap, va, pde, newpde);
4020 pde_store(pde, newpde);
4023 * Invalidate a stale recursive mapping of the page table page.
4025 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4029 * pmap_remove_pde: do the things to unmap a superpage in a process
4032 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4033 struct spglist *free, struct rwlock **lockp)
4035 struct md_page *pvh;
4037 vm_offset_t eva, va;
4039 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4041 PG_G = pmap_global_bit(pmap);
4042 PG_A = pmap_accessed_bit(pmap);
4043 PG_M = pmap_modified_bit(pmap);
4044 PG_RW = pmap_rw_bit(pmap);
4046 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4047 KASSERT((sva & PDRMASK) == 0,
4048 ("pmap_remove_pde: sva is not 2mpage aligned"));
4049 oldpde = pte_load_clear(pdq);
4051 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4052 if ((oldpde & PG_G) != 0)
4053 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4054 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4055 if (oldpde & PG_MANAGED) {
4056 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4057 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4058 pmap_pvh_free(pvh, pmap, sva);
4060 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4061 va < eva; va += PAGE_SIZE, m++) {
4062 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4065 vm_page_aflag_set(m, PGA_REFERENCED);
4066 if (TAILQ_EMPTY(&m->md.pv_list) &&
4067 TAILQ_EMPTY(&pvh->pv_list))
4068 vm_page_aflag_clear(m, PGA_WRITEABLE);
4069 pmap_delayed_invl_page(m);
4072 if (pmap == kernel_pmap) {
4073 pmap_remove_kernel_pde(pmap, pdq, sva);
4075 mpte = pmap_remove_pt_page(pmap, sva);
4077 pmap_resident_count_dec(pmap, 1);
4078 KASSERT(mpte->wire_count == NPTEPG,
4079 ("pmap_remove_pde: pte page wire count error"));
4080 mpte->wire_count = 0;
4081 pmap_add_delayed_free_list(mpte, free, FALSE);
4084 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4088 * pmap_remove_pte: do the things to unmap a page in a process
4091 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4092 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4094 struct md_page *pvh;
4095 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4098 PG_A = pmap_accessed_bit(pmap);
4099 PG_M = pmap_modified_bit(pmap);
4100 PG_RW = pmap_rw_bit(pmap);
4102 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4103 oldpte = pte_load_clear(ptq);
4105 pmap->pm_stats.wired_count -= 1;
4106 pmap_resident_count_dec(pmap, 1);
4107 if (oldpte & PG_MANAGED) {
4108 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4109 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4112 vm_page_aflag_set(m, PGA_REFERENCED);
4113 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4114 pmap_pvh_free(&m->md, pmap, va);
4115 if (TAILQ_EMPTY(&m->md.pv_list) &&
4116 (m->flags & PG_FICTITIOUS) == 0) {
4117 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4118 if (TAILQ_EMPTY(&pvh->pv_list))
4119 vm_page_aflag_clear(m, PGA_WRITEABLE);
4121 pmap_delayed_invl_page(m);
4123 return (pmap_unuse_pt(pmap, va, ptepde, free));
4127 * Remove a single page from a process address space
4130 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4131 struct spglist *free)
4133 struct rwlock *lock;
4134 pt_entry_t *pte, PG_V;
4136 PG_V = pmap_valid_bit(pmap);
4137 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4138 if ((*pde & PG_V) == 0)
4140 pte = pmap_pde_to_pte(pde, va);
4141 if ((*pte & PG_V) == 0)
4144 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4147 pmap_invalidate_page(pmap, va);
4151 * Removes the specified range of addresses from the page table page.
4154 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4155 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4157 pt_entry_t PG_G, *pte;
4161 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4162 PG_G = pmap_global_bit(pmap);
4165 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
4169 pmap_invalidate_range(pmap, va, sva);
4174 if ((*pte & PG_G) == 0)
4178 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
4184 pmap_invalidate_range(pmap, va, sva);
4189 * Remove the given range of addresses from the specified map.
4191 * It is assumed that the start and end are properly
4192 * rounded to the page size.
4195 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4197 struct rwlock *lock;
4198 vm_offset_t va_next;
4199 pml4_entry_t *pml4e;
4201 pd_entry_t ptpaddr, *pde;
4202 pt_entry_t PG_G, PG_V;
4203 struct spglist free;
4206 PG_G = pmap_global_bit(pmap);
4207 PG_V = pmap_valid_bit(pmap);
4210 * Perform an unsynchronized read. This is, however, safe.
4212 if (pmap->pm_stats.resident_count == 0)
4218 pmap_delayed_invl_started();
4222 * special handling of removing one page. a very
4223 * common operation and easy to short circuit some
4226 if (sva + PAGE_SIZE == eva) {
4227 pde = pmap_pde(pmap, sva);
4228 if (pde && (*pde & PG_PS) == 0) {
4229 pmap_remove_page(pmap, sva, pde, &free);
4235 for (; sva < eva; sva = va_next) {
4237 if (pmap->pm_stats.resident_count == 0)
4240 pml4e = pmap_pml4e(pmap, sva);
4241 if ((*pml4e & PG_V) == 0) {
4242 va_next = (sva + NBPML4) & ~PML4MASK;
4248 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4249 if ((*pdpe & PG_V) == 0) {
4250 va_next = (sva + NBPDP) & ~PDPMASK;
4257 * Calculate index for next page table.
4259 va_next = (sva + NBPDR) & ~PDRMASK;
4263 pde = pmap_pdpe_to_pde(pdpe, sva);
4267 * Weed out invalid mappings.
4273 * Check for large page.
4275 if ((ptpaddr & PG_PS) != 0) {
4277 * Are we removing the entire large page? If not,
4278 * demote the mapping and fall through.
4280 if (sva + NBPDR == va_next && eva >= va_next) {
4282 * The TLB entry for a PG_G mapping is
4283 * invalidated by pmap_remove_pde().
4285 if ((ptpaddr & PG_G) == 0)
4287 pmap_remove_pde(pmap, pde, sva, &free, &lock);
4289 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
4291 /* The large page mapping was destroyed. */
4298 * Limit our scan to either the end of the va represented
4299 * by the current page table page, or to the end of the
4300 * range being removed.
4305 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
4312 pmap_invalidate_all(pmap);
4314 pmap_delayed_invl_finished();
4315 vm_page_free_pages_toq(&free, true);
4319 * Routine: pmap_remove_all
4321 * Removes this physical page from
4322 * all physical maps in which it resides.
4323 * Reflects back modify bits to the pager.
4326 * Original versions of this routine were very
4327 * inefficient because they iteratively called
4328 * pmap_remove (slow...)
4332 pmap_remove_all(vm_page_t m)
4334 struct md_page *pvh;
4337 struct rwlock *lock;
4338 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
4341 struct spglist free;
4342 int pvh_gen, md_gen;
4344 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4345 ("pmap_remove_all: page %p is not managed", m));
4347 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4348 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4349 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4352 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
4354 if (!PMAP_TRYLOCK(pmap)) {
4355 pvh_gen = pvh->pv_gen;
4359 if (pvh_gen != pvh->pv_gen) {
4366 pde = pmap_pde(pmap, va);
4367 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
4370 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4372 if (!PMAP_TRYLOCK(pmap)) {
4373 pvh_gen = pvh->pv_gen;
4374 md_gen = m->md.pv_gen;
4378 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4384 PG_A = pmap_accessed_bit(pmap);
4385 PG_M = pmap_modified_bit(pmap);
4386 PG_RW = pmap_rw_bit(pmap);
4387 pmap_resident_count_dec(pmap, 1);
4388 pde = pmap_pde(pmap, pv->pv_va);
4389 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
4390 " a 2mpage in page %p's pv list", m));
4391 pte = pmap_pde_to_pte(pde, pv->pv_va);
4392 tpte = pte_load_clear(pte);
4394 pmap->pm_stats.wired_count--;
4396 vm_page_aflag_set(m, PGA_REFERENCED);
4399 * Update the vm_page_t clean and reference bits.
4401 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4403 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
4404 pmap_invalidate_page(pmap, pv->pv_va);
4405 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4407 free_pv_entry(pmap, pv);
4410 vm_page_aflag_clear(m, PGA_WRITEABLE);
4412 pmap_delayed_invl_wait(m);
4413 vm_page_free_pages_toq(&free, true);
4417 * pmap_protect_pde: do the things to protect a 2mpage in a process
4420 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
4422 pd_entry_t newpde, oldpde;
4423 vm_offset_t eva, va;
4425 boolean_t anychanged;
4426 pt_entry_t PG_G, PG_M, PG_RW;
4428 PG_G = pmap_global_bit(pmap);
4429 PG_M = pmap_modified_bit(pmap);
4430 PG_RW = pmap_rw_bit(pmap);
4432 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4433 KASSERT((sva & PDRMASK) == 0,
4434 ("pmap_protect_pde: sva is not 2mpage aligned"));
4437 oldpde = newpde = *pde;
4438 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
4439 (PG_MANAGED | PG_M | PG_RW)) {
4441 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4442 va < eva; va += PAGE_SIZE, m++)
4445 if ((prot & VM_PROT_WRITE) == 0)
4446 newpde &= ~(PG_RW | PG_M);
4447 if ((prot & VM_PROT_EXECUTE) == 0)
4449 if (newpde != oldpde) {
4451 * As an optimization to future operations on this PDE, clear
4452 * PG_PROMOTED. The impending invalidation will remove any
4453 * lingering 4KB page mappings from the TLB.
4455 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
4457 if ((oldpde & PG_G) != 0)
4458 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4462 return (anychanged);
4466 * Set the physical protection on the
4467 * specified range of this map as requested.
4470 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
4472 vm_offset_t va_next;
4473 pml4_entry_t *pml4e;
4475 pd_entry_t ptpaddr, *pde;
4476 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
4477 boolean_t anychanged;
4479 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
4480 if (prot == VM_PROT_NONE) {
4481 pmap_remove(pmap, sva, eva);
4485 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
4486 (VM_PROT_WRITE|VM_PROT_EXECUTE))
4489 PG_G = pmap_global_bit(pmap);
4490 PG_M = pmap_modified_bit(pmap);
4491 PG_V = pmap_valid_bit(pmap);
4492 PG_RW = pmap_rw_bit(pmap);
4496 * Although this function delays and batches the invalidation
4497 * of stale TLB entries, it does not need to call
4498 * pmap_delayed_invl_started() and
4499 * pmap_delayed_invl_finished(), because it does not
4500 * ordinarily destroy mappings. Stale TLB entries from
4501 * protection-only changes need only be invalidated before the
4502 * pmap lock is released, because protection-only changes do
4503 * not destroy PV entries. Even operations that iterate over
4504 * a physical page's PV list of mappings, like
4505 * pmap_remove_write(), acquire the pmap lock for each
4506 * mapping. Consequently, for protection-only changes, the
4507 * pmap lock suffices to synchronize both page table and TLB
4510 * This function only destroys a mapping if pmap_demote_pde()
4511 * fails. In that case, stale TLB entries are immediately
4516 for (; sva < eva; sva = va_next) {
4518 pml4e = pmap_pml4e(pmap, sva);
4519 if ((*pml4e & PG_V) == 0) {
4520 va_next = (sva + NBPML4) & ~PML4MASK;
4526 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4527 if ((*pdpe & PG_V) == 0) {
4528 va_next = (sva + NBPDP) & ~PDPMASK;
4534 va_next = (sva + NBPDR) & ~PDRMASK;
4538 pde = pmap_pdpe_to_pde(pdpe, sva);
4542 * Weed out invalid mappings.
4548 * Check for large page.
4550 if ((ptpaddr & PG_PS) != 0) {
4552 * Are we protecting the entire large page? If not,
4553 * demote the mapping and fall through.
4555 if (sva + NBPDR == va_next && eva >= va_next) {
4557 * The TLB entry for a PG_G mapping is
4558 * invalidated by pmap_protect_pde().
4560 if (pmap_protect_pde(pmap, pde, sva, prot))
4563 } else if (!pmap_demote_pde(pmap, pde, sva)) {
4565 * The large page mapping was destroyed.
4574 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4576 pt_entry_t obits, pbits;
4580 obits = pbits = *pte;
4581 if ((pbits & PG_V) == 0)
4584 if ((prot & VM_PROT_WRITE) == 0) {
4585 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
4586 (PG_MANAGED | PG_M | PG_RW)) {
4587 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
4590 pbits &= ~(PG_RW | PG_M);
4592 if ((prot & VM_PROT_EXECUTE) == 0)
4595 if (pbits != obits) {
4596 if (!atomic_cmpset_long(pte, obits, pbits))
4599 pmap_invalidate_page(pmap, sva);
4606 pmap_invalidate_all(pmap);
4610 #if VM_NRESERVLEVEL > 0
4612 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4613 * single page table page (PTP) to a single 2MB page mapping. For promotion
4614 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4615 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4616 * identical characteristics.
4619 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4620 struct rwlock **lockp)
4623 pt_entry_t *firstpte, oldpte, pa, *pte;
4624 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4628 PG_A = pmap_accessed_bit(pmap);
4629 PG_G = pmap_global_bit(pmap);
4630 PG_M = pmap_modified_bit(pmap);
4631 PG_V = pmap_valid_bit(pmap);
4632 PG_RW = pmap_rw_bit(pmap);
4633 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4635 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4638 * Examine the first PTE in the specified PTP. Abort if this PTE is
4639 * either invalid, unused, or does not map the first 4KB physical page
4640 * within a 2MB page.
4642 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4645 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4646 atomic_add_long(&pmap_pde_p_failures, 1);
4647 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4648 " in pmap %p", va, pmap);
4651 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4653 * When PG_M is already clear, PG_RW can be cleared without
4654 * a TLB invalidation.
4656 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4662 * Examine each of the other PTEs in the specified PTP. Abort if this
4663 * PTE maps an unexpected 4KB physical page or does not have identical
4664 * characteristics to the first PTE.
4666 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4667 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4670 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4671 atomic_add_long(&pmap_pde_p_failures, 1);
4672 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4673 " in pmap %p", va, pmap);
4676 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4678 * When PG_M is already clear, PG_RW can be cleared
4679 * without a TLB invalidation.
4681 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4684 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4685 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4686 (va & ~PDRMASK), pmap);
4688 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4689 atomic_add_long(&pmap_pde_p_failures, 1);
4690 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4691 " in pmap %p", va, pmap);
4698 * Save the page table page in its current state until the PDE
4699 * mapping the superpage is demoted by pmap_demote_pde() or
4700 * destroyed by pmap_remove_pde().
4702 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4703 KASSERT(mpte >= vm_page_array &&
4704 mpte < &vm_page_array[vm_page_array_size],
4705 ("pmap_promote_pde: page table page is out of range"));
4706 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4707 ("pmap_promote_pde: page table page's pindex is wrong"));
4708 if (pmap_insert_pt_page(pmap, mpte)) {
4709 atomic_add_long(&pmap_pde_p_failures, 1);
4711 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4717 * Promote the pv entries.
4719 if ((newpde & PG_MANAGED) != 0)
4720 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4723 * Propagate the PAT index to its proper position.
4725 newpde = pmap_swap_pat(pmap, newpde);
4728 * Map the superpage.
4730 if (workaround_erratum383)
4731 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4733 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
4735 atomic_add_long(&pmap_pde_promotions, 1);
4736 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4737 " in pmap %p", va, pmap);
4739 #endif /* VM_NRESERVLEVEL > 0 */
4742 * Insert the given physical page (p) at
4743 * the specified virtual address (v) in the
4744 * target physical map with the protection requested.
4746 * If specified, the page will be wired down, meaning
4747 * that the related pte can not be reclaimed.
4749 * NB: This is the only routine which MAY NOT lazy-evaluate
4750 * or lose information. That is, this routine must actually
4751 * insert this page into the given map NOW.
4753 * When destroying both a page table and PV entry, this function
4754 * performs the TLB invalidation before releasing the PV list
4755 * lock, so we do not need pmap_delayed_invl_page() calls here.
4758 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4759 u_int flags, int8_t psind)
4761 struct rwlock *lock;
4763 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4764 pt_entry_t newpte, origpte;
4771 PG_A = pmap_accessed_bit(pmap);
4772 PG_G = pmap_global_bit(pmap);
4773 PG_M = pmap_modified_bit(pmap);
4774 PG_V = pmap_valid_bit(pmap);
4775 PG_RW = pmap_rw_bit(pmap);
4777 va = trunc_page(va);
4778 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4779 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4780 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4782 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4783 va >= kmi.clean_eva,
4784 ("pmap_enter: managed mapping within the clean submap"));
4785 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4786 VM_OBJECT_ASSERT_LOCKED(m->object);
4787 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
4788 ("pmap_enter: flags %u has reserved bits set", flags));
4789 pa = VM_PAGE_TO_PHYS(m);
4790 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4791 if ((flags & VM_PROT_WRITE) != 0)
4793 if ((prot & VM_PROT_WRITE) != 0)
4795 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4796 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4797 if ((prot & VM_PROT_EXECUTE) == 0)
4799 if ((flags & PMAP_ENTER_WIRED) != 0)
4801 if (va < VM_MAXUSER_ADDRESS)
4803 if (pmap == kernel_pmap)
4805 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
4808 * Set modified bit gratuitously for writeable mappings if
4809 * the page is unmanaged. We do not want to take a fault
4810 * to do the dirty bit accounting for these mappings.
4812 if ((m->oflags & VPO_UNMANAGED) != 0) {
4813 if ((newpte & PG_RW) != 0)
4816 newpte |= PG_MANAGED;
4821 /* Assert the required virtual and physical alignment. */
4822 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
4823 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
4824 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
4830 * In the case that a page table page is not
4831 * resident, we are creating it here.
4834 pde = pmap_pde(pmap, va);
4835 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4836 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4837 pte = pmap_pde_to_pte(pde, va);
4838 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4839 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4842 } else if (va < VM_MAXUSER_ADDRESS) {
4844 * Here if the pte page isn't mapped, or if it has been
4847 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4848 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4849 nosleep ? NULL : &lock);
4850 if (mpte == NULL && nosleep) {
4851 rv = KERN_RESOURCE_SHORTAGE;
4856 panic("pmap_enter: invalid page directory va=%#lx", va);
4862 * Is the specified virtual address already mapped?
4864 if ((origpte & PG_V) != 0) {
4866 * Wiring change, just update stats. We don't worry about
4867 * wiring PT pages as they remain resident as long as there
4868 * are valid mappings in them. Hence, if a user page is wired,
4869 * the PT page will be also.
4871 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4872 pmap->pm_stats.wired_count++;
4873 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4874 pmap->pm_stats.wired_count--;
4877 * Remove the extra PT page reference.
4881 KASSERT(mpte->wire_count > 0,
4882 ("pmap_enter: missing reference to page table page,"
4887 * Has the physical page changed?
4889 opa = origpte & PG_FRAME;
4892 * No, might be a protection or wiring change.
4894 if ((origpte & PG_MANAGED) != 0 &&
4895 (newpte & PG_RW) != 0)
4896 vm_page_aflag_set(m, PGA_WRITEABLE);
4897 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4903 * The physical page has changed. Temporarily invalidate
4904 * the mapping. This ensures that all threads sharing the
4905 * pmap keep a consistent view of the mapping, which is
4906 * necessary for the correct handling of COW faults. It
4907 * also permits reuse of the old mapping's PV entry,
4908 * avoiding an allocation.
4910 * For consistency, handle unmanaged mappings the same way.
4912 origpte = pte_load_clear(pte);
4913 KASSERT((origpte & PG_FRAME) == opa,
4914 ("pmap_enter: unexpected pa update for %#lx", va));
4915 if ((origpte & PG_MANAGED) != 0) {
4916 om = PHYS_TO_VM_PAGE(opa);
4919 * The pmap lock is sufficient to synchronize with
4920 * concurrent calls to pmap_page_test_mappings() and
4921 * pmap_ts_referenced().
4923 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4925 if ((origpte & PG_A) != 0)
4926 vm_page_aflag_set(om, PGA_REFERENCED);
4927 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4928 pv = pmap_pvh_remove(&om->md, pmap, va);
4929 if ((newpte & PG_MANAGED) == 0)
4930 free_pv_entry(pmap, pv);
4931 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4932 TAILQ_EMPTY(&om->md.pv_list) &&
4933 ((om->flags & PG_FICTITIOUS) != 0 ||
4934 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4935 vm_page_aflag_clear(om, PGA_WRITEABLE);
4937 if ((origpte & PG_A) != 0)
4938 pmap_invalidate_page(pmap, va);
4942 * Increment the counters.
4944 if ((newpte & PG_W) != 0)
4945 pmap->pm_stats.wired_count++;
4946 pmap_resident_count_inc(pmap, 1);
4950 * Enter on the PV list if part of our managed memory.
4952 if ((newpte & PG_MANAGED) != 0) {
4954 pv = get_pv_entry(pmap, &lock);
4957 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4958 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4960 if ((newpte & PG_RW) != 0)
4961 vm_page_aflag_set(m, PGA_WRITEABLE);
4967 if ((origpte & PG_V) != 0) {
4969 origpte = pte_load_store(pte, newpte);
4970 KASSERT((origpte & PG_FRAME) == pa,
4971 ("pmap_enter: unexpected pa update for %#lx", va));
4972 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
4974 if ((origpte & PG_MANAGED) != 0)
4978 * Although the PTE may still have PG_RW set, TLB
4979 * invalidation may nonetheless be required because
4980 * the PTE no longer has PG_M set.
4982 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4984 * This PTE change does not require TLB invalidation.
4988 if ((origpte & PG_A) != 0)
4989 pmap_invalidate_page(pmap, va);
4991 pte_store(pte, newpte);
4995 #if VM_NRESERVLEVEL > 0
4997 * If both the page table page and the reservation are fully
4998 * populated, then attempt promotion.
5000 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5001 pmap_ps_enabled(pmap) &&
5002 (m->flags & PG_FICTITIOUS) == 0 &&
5003 vm_reserv_level_iffullpop(m) == 0)
5004 pmap_promote_pde(pmap, pde, va, &lock);
5016 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5017 * if successful. Returns false if (1) a page table page cannot be allocated
5018 * without sleeping, (2) a mapping already exists at the specified virtual
5019 * address, or (3) a PV entry cannot be allocated without reclaiming another
5023 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5024 struct rwlock **lockp)
5029 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5030 PG_V = pmap_valid_bit(pmap);
5031 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5033 if ((m->oflags & VPO_UNMANAGED) == 0)
5034 newpde |= PG_MANAGED;
5035 if ((prot & VM_PROT_EXECUTE) == 0)
5037 if (va < VM_MAXUSER_ADDRESS)
5039 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5040 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5045 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5046 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5047 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5048 * a mapping already exists at the specified virtual address. Returns
5049 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5050 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5051 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5053 * The parameter "m" is only used when creating a managed, writeable mapping.
5056 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5057 vm_page_t m, struct rwlock **lockp)
5059 struct spglist free;
5060 pd_entry_t oldpde, *pde;
5061 pt_entry_t PG_G, PG_RW, PG_V;
5064 PG_G = pmap_global_bit(pmap);
5065 PG_RW = pmap_rw_bit(pmap);
5066 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5067 ("pmap_enter_pde: newpde is missing PG_M"));
5068 PG_V = pmap_valid_bit(pmap);
5069 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5071 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5072 NULL : lockp)) == NULL) {
5073 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5074 " in pmap %p", va, pmap);
5075 return (KERN_RESOURCE_SHORTAGE);
5077 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5078 pde = &pde[pmap_pde_index(va)];
5080 if ((oldpde & PG_V) != 0) {
5081 KASSERT(pdpg->wire_count > 1,
5082 ("pmap_enter_pde: pdpg's wire count is too low"));
5083 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5085 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5086 " in pmap %p", va, pmap);
5087 return (KERN_FAILURE);
5089 /* Break the existing mapping(s). */
5091 if ((oldpde & PG_PS) != 0) {
5093 * The reference to the PD page that was acquired by
5094 * pmap_allocpde() ensures that it won't be freed.
5095 * However, if the PDE resulted from a promotion, then
5096 * a reserved PT page could be freed.
5098 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5099 if ((oldpde & PG_G) == 0)
5100 pmap_invalidate_pde_page(pmap, va, oldpde);
5102 pmap_delayed_invl_started();
5103 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5105 pmap_invalidate_all(pmap);
5106 pmap_delayed_invl_finished();
5108 vm_page_free_pages_toq(&free, true);
5109 if (va >= VM_MAXUSER_ADDRESS) {
5110 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5111 if (pmap_insert_pt_page(pmap, mt)) {
5113 * XXX Currently, this can't happen because
5114 * we do not perform pmap_enter(psind == 1)
5115 * on the kernel pmap.
5117 panic("pmap_enter_pde: trie insert failed");
5120 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
5123 if ((newpde & PG_MANAGED) != 0) {
5125 * Abort this mapping if its PV entry could not be created.
5127 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
5129 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5131 * Although "va" is not mapped, paging-
5132 * structure caches could nonetheless have
5133 * entries that refer to the freed page table
5134 * pages. Invalidate those entries.
5136 pmap_invalidate_page(pmap, va);
5137 vm_page_free_pages_toq(&free, true);
5139 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5140 " in pmap %p", va, pmap);
5141 return (KERN_RESOURCE_SHORTAGE);
5143 if ((newpde & PG_RW) != 0) {
5144 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5145 vm_page_aflag_set(mt, PGA_WRITEABLE);
5150 * Increment counters.
5152 if ((newpde & PG_W) != 0)
5153 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
5154 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5157 * Map the superpage. (This is not a promoted mapping; there will not
5158 * be any lingering 4KB page mappings in the TLB.)
5160 pde_store(pde, newpde);
5162 atomic_add_long(&pmap_pde_mappings, 1);
5163 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
5164 " in pmap %p", va, pmap);
5165 return (KERN_SUCCESS);
5169 * Maps a sequence of resident pages belonging to the same object.
5170 * The sequence begins with the given page m_start. This page is
5171 * mapped at the given virtual address start. Each subsequent page is
5172 * mapped at a virtual address that is offset from start by the same
5173 * amount as the page is offset from m_start within the object. The
5174 * last page in the sequence is the page with the largest offset from
5175 * m_start that can be mapped at a virtual address less than the given
5176 * virtual address end. Not every virtual page between start and end
5177 * is mapped; only those for which a resident page exists with the
5178 * corresponding offset from m_start are mapped.
5181 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
5182 vm_page_t m_start, vm_prot_t prot)
5184 struct rwlock *lock;
5187 vm_pindex_t diff, psize;
5189 VM_OBJECT_ASSERT_LOCKED(m_start->object);
5191 psize = atop(end - start);
5196 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
5197 va = start + ptoa(diff);
5198 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
5199 m->psind == 1 && pmap_ps_enabled(pmap) &&
5200 pmap_enter_2mpage(pmap, va, m, prot, &lock))
5201 m = &m[NBPDR / PAGE_SIZE - 1];
5203 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
5205 m = TAILQ_NEXT(m, listq);
5213 * this code makes some *MAJOR* assumptions:
5214 * 1. Current pmap & pmap exists.
5217 * 4. No page table pages.
5218 * but is *MUCH* faster than pmap_enter...
5222 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
5224 struct rwlock *lock;
5228 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
5235 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
5236 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
5238 struct spglist free;
5239 pt_entry_t *pte, PG_V;
5242 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
5243 (m->oflags & VPO_UNMANAGED) != 0,
5244 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
5245 PG_V = pmap_valid_bit(pmap);
5246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5249 * In the case that a page table page is not
5250 * resident, we are creating it here.
5252 if (va < VM_MAXUSER_ADDRESS) {
5253 vm_pindex_t ptepindex;
5257 * Calculate pagetable page index
5259 ptepindex = pmap_pde_pindex(va);
5260 if (mpte && (mpte->pindex == ptepindex)) {
5264 * Get the page directory entry
5266 ptepa = pmap_pde(pmap, va);
5269 * If the page table page is mapped, we just increment
5270 * the hold count, and activate it. Otherwise, we
5271 * attempt to allocate a page table page. If this
5272 * attempt fails, we don't retry. Instead, we give up.
5274 if (ptepa && (*ptepa & PG_V) != 0) {
5277 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
5281 * Pass NULL instead of the PV list lock
5282 * pointer, because we don't intend to sleep.
5284 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
5289 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
5290 pte = &pte[pmap_pte_index(va)];
5304 * Enter on the PV list if part of our managed memory.
5306 if ((m->oflags & VPO_UNMANAGED) == 0 &&
5307 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
5310 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
5312 * Although "va" is not mapped, paging-
5313 * structure caches could nonetheless have
5314 * entries that refer to the freed page table
5315 * pages. Invalidate those entries.
5317 pmap_invalidate_page(pmap, va);
5318 vm_page_free_pages_toq(&free, true);
5326 * Increment counters
5328 pmap_resident_count_inc(pmap, 1);
5330 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
5331 if ((prot & VM_PROT_EXECUTE) == 0)
5335 * Now validate mapping with RO protection
5337 if ((m->oflags & VPO_UNMANAGED) != 0)
5338 pte_store(pte, pa | PG_V | PG_U);
5340 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
5345 * Make a temporary mapping for a physical address. This is only intended
5346 * to be used for panic dumps.
5349 pmap_kenter_temporary(vm_paddr_t pa, int i)
5353 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
5354 pmap_kenter(va, pa);
5356 return ((void *)crashdumpmap);
5360 * This code maps large physical mmap regions into the
5361 * processor address space. Note that some shortcuts
5362 * are taken, but the code works.
5365 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
5366 vm_pindex_t pindex, vm_size_t size)
5369 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5370 vm_paddr_t pa, ptepa;
5374 PG_A = pmap_accessed_bit(pmap);
5375 PG_M = pmap_modified_bit(pmap);
5376 PG_V = pmap_valid_bit(pmap);
5377 PG_RW = pmap_rw_bit(pmap);
5379 VM_OBJECT_ASSERT_WLOCKED(object);
5380 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
5381 ("pmap_object_init_pt: non-device object"));
5382 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
5383 if (!pmap_ps_enabled(pmap))
5385 if (!vm_object_populate(object, pindex, pindex + atop(size)))
5387 p = vm_page_lookup(object, pindex);
5388 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5389 ("pmap_object_init_pt: invalid page %p", p));
5390 pat_mode = p->md.pat_mode;
5393 * Abort the mapping if the first page is not physically
5394 * aligned to a 2MB page boundary.
5396 ptepa = VM_PAGE_TO_PHYS(p);
5397 if (ptepa & (NBPDR - 1))
5401 * Skip the first page. Abort the mapping if the rest of
5402 * the pages are not physically contiguous or have differing
5403 * memory attributes.
5405 p = TAILQ_NEXT(p, listq);
5406 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
5408 KASSERT(p->valid == VM_PAGE_BITS_ALL,
5409 ("pmap_object_init_pt: invalid page %p", p));
5410 if (pa != VM_PAGE_TO_PHYS(p) ||
5411 pat_mode != p->md.pat_mode)
5413 p = TAILQ_NEXT(p, listq);
5417 * Map using 2MB pages. Since "ptepa" is 2M aligned and
5418 * "size" is a multiple of 2M, adding the PAT setting to "pa"
5419 * will not affect the termination of this loop.
5422 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
5423 pa < ptepa + size; pa += NBPDR) {
5424 pdpg = pmap_allocpde(pmap, addr, NULL);
5427 * The creation of mappings below is only an
5428 * optimization. If a page directory page
5429 * cannot be allocated without blocking,
5430 * continue on to the next mapping rather than
5436 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5437 pde = &pde[pmap_pde_index(addr)];
5438 if ((*pde & PG_V) == 0) {
5439 pde_store(pde, pa | PG_PS | PG_M | PG_A |
5440 PG_U | PG_RW | PG_V);
5441 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
5442 atomic_add_long(&pmap_pde_mappings, 1);
5444 /* Continue on if the PDE is already valid. */
5446 KASSERT(pdpg->wire_count > 0,
5447 ("pmap_object_init_pt: missing reference "
5448 "to page directory page, va: 0x%lx", addr));
5457 * Clear the wired attribute from the mappings for the specified range of
5458 * addresses in the given pmap. Every valid mapping within that range
5459 * must have the wired attribute set. In contrast, invalid mappings
5460 * cannot have the wired attribute set, so they are ignored.
5462 * The wired attribute of the page table entry is not a hardware
5463 * feature, so there is no need to invalidate any TLB entries.
5464 * Since pmap_demote_pde() for the wired entry must never fail,
5465 * pmap_delayed_invl_started()/finished() calls around the
5466 * function are not needed.
5469 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5471 vm_offset_t va_next;
5472 pml4_entry_t *pml4e;
5475 pt_entry_t *pte, PG_V;
5477 PG_V = pmap_valid_bit(pmap);
5479 for (; sva < eva; sva = va_next) {
5480 pml4e = pmap_pml4e(pmap, sva);
5481 if ((*pml4e & PG_V) == 0) {
5482 va_next = (sva + NBPML4) & ~PML4MASK;
5487 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5488 if ((*pdpe & PG_V) == 0) {
5489 va_next = (sva + NBPDP) & ~PDPMASK;
5494 va_next = (sva + NBPDR) & ~PDRMASK;
5497 pde = pmap_pdpe_to_pde(pdpe, sva);
5498 if ((*pde & PG_V) == 0)
5500 if ((*pde & PG_PS) != 0) {
5501 if ((*pde & PG_W) == 0)
5502 panic("pmap_unwire: pde %#jx is missing PG_W",
5506 * Are we unwiring the entire large page? If not,
5507 * demote the mapping and fall through.
5509 if (sva + NBPDR == va_next && eva >= va_next) {
5510 atomic_clear_long(pde, PG_W);
5511 pmap->pm_stats.wired_count -= NBPDR /
5514 } else if (!pmap_demote_pde(pmap, pde, sva))
5515 panic("pmap_unwire: demotion failed");
5519 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5521 if ((*pte & PG_V) == 0)
5523 if ((*pte & PG_W) == 0)
5524 panic("pmap_unwire: pte %#jx is missing PG_W",
5528 * PG_W must be cleared atomically. Although the pmap
5529 * lock synchronizes access to PG_W, another processor
5530 * could be setting PG_M and/or PG_A concurrently.
5532 atomic_clear_long(pte, PG_W);
5533 pmap->pm_stats.wired_count--;
5540 * Copy the range specified by src_addr/len
5541 * from the source map to the range dst_addr/len
5542 * in the destination map.
5544 * This routine is only advisory and need not do anything.
5548 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
5549 vm_offset_t src_addr)
5551 struct rwlock *lock;
5552 struct spglist free;
5554 vm_offset_t end_addr = src_addr + len;
5555 vm_offset_t va_next;
5556 vm_page_t dst_pdpg, dstmpte, srcmpte;
5557 pt_entry_t PG_A, PG_M, PG_V;
5559 if (dst_addr != src_addr)
5562 if (dst_pmap->pm_type != src_pmap->pm_type)
5566 * EPT page table entries that require emulation of A/D bits are
5567 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
5568 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
5569 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
5570 * implementations flag an EPT misconfiguration for exec-only
5571 * mappings we skip this function entirely for emulated pmaps.
5573 if (pmap_emulate_ad_bits(dst_pmap))
5577 if (dst_pmap < src_pmap) {
5578 PMAP_LOCK(dst_pmap);
5579 PMAP_LOCK(src_pmap);
5581 PMAP_LOCK(src_pmap);
5582 PMAP_LOCK(dst_pmap);
5585 PG_A = pmap_accessed_bit(dst_pmap);
5586 PG_M = pmap_modified_bit(dst_pmap);
5587 PG_V = pmap_valid_bit(dst_pmap);
5589 for (addr = src_addr; addr < end_addr; addr = va_next) {
5590 pt_entry_t *src_pte, *dst_pte;
5591 pml4_entry_t *pml4e;
5593 pd_entry_t srcptepaddr, *pde;
5595 KASSERT(addr < UPT_MIN_ADDRESS,
5596 ("pmap_copy: invalid to pmap_copy page tables"));
5598 pml4e = pmap_pml4e(src_pmap, addr);
5599 if ((*pml4e & PG_V) == 0) {
5600 va_next = (addr + NBPML4) & ~PML4MASK;
5606 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
5607 if ((*pdpe & PG_V) == 0) {
5608 va_next = (addr + NBPDP) & ~PDPMASK;
5614 va_next = (addr + NBPDR) & ~PDRMASK;
5618 pde = pmap_pdpe_to_pde(pdpe, addr);
5620 if (srcptepaddr == 0)
5623 if (srcptepaddr & PG_PS) {
5624 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
5626 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
5627 if (dst_pdpg == NULL)
5629 pde = (pd_entry_t *)
5630 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
5631 pde = &pde[pmap_pde_index(addr)];
5632 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
5633 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
5634 PMAP_ENTER_NORECLAIM, &lock))) {
5635 *pde = srcptepaddr & ~PG_W;
5636 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
5637 atomic_add_long(&pmap_pde_mappings, 1);
5639 dst_pdpg->wire_count--;
5643 srcptepaddr &= PG_FRAME;
5644 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
5645 KASSERT(srcmpte->wire_count > 0,
5646 ("pmap_copy: source page table page is unused"));
5648 if (va_next > end_addr)
5651 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
5652 src_pte = &src_pte[pmap_pte_index(addr)];
5654 while (addr < va_next) {
5658 * we only virtual copy managed pages
5660 if ((ptetemp & PG_MANAGED) != 0) {
5661 if (dstmpte != NULL &&
5662 dstmpte->pindex == pmap_pde_pindex(addr))
5663 dstmpte->wire_count++;
5664 else if ((dstmpte = pmap_allocpte(dst_pmap,
5665 addr, NULL)) == NULL)
5667 dst_pte = (pt_entry_t *)
5668 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
5669 dst_pte = &dst_pte[pmap_pte_index(addr)];
5670 if (*dst_pte == 0 &&
5671 pmap_try_insert_pv_entry(dst_pmap, addr,
5672 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
5675 * Clear the wired, modified, and
5676 * accessed (referenced) bits
5679 *dst_pte = ptetemp & ~(PG_W | PG_M |
5681 pmap_resident_count_inc(dst_pmap, 1);
5684 if (pmap_unwire_ptp(dst_pmap, addr,
5687 * Although "addr" is not
5688 * mapped, paging-structure
5689 * caches could nonetheless
5690 * have entries that refer to
5691 * the freed page table pages.
5692 * Invalidate those entries.
5694 pmap_invalidate_page(dst_pmap,
5696 vm_page_free_pages_toq(&free,
5701 if (dstmpte->wire_count >= srcmpte->wire_count)
5711 PMAP_UNLOCK(src_pmap);
5712 PMAP_UNLOCK(dst_pmap);
5716 * Zero the specified hardware page.
5719 pmap_zero_page(vm_page_t m)
5721 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5723 pagezero((void *)va);
5727 * Zero an an area within a single hardware page. off and size must not
5728 * cover an area beyond a single hardware page.
5731 pmap_zero_page_area(vm_page_t m, int off, int size)
5733 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5735 if (off == 0 && size == PAGE_SIZE)
5736 pagezero((void *)va);
5738 bzero((char *)va + off, size);
5742 * Copy 1 specified hardware page to another.
5745 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5747 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5748 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5750 pagecopy((void *)src, (void *)dst);
5753 int unmapped_buf_allowed = 1;
5756 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5757 vm_offset_t b_offset, int xfersize)
5761 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5765 while (xfersize > 0) {
5766 a_pg_offset = a_offset & PAGE_MASK;
5767 pages[0] = ma[a_offset >> PAGE_SHIFT];
5768 b_pg_offset = b_offset & PAGE_MASK;
5769 pages[1] = mb[b_offset >> PAGE_SHIFT];
5770 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5771 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5772 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5773 a_cp = (char *)vaddr[0] + a_pg_offset;
5774 b_cp = (char *)vaddr[1] + b_pg_offset;
5775 bcopy(a_cp, b_cp, cnt);
5776 if (__predict_false(mapped))
5777 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5785 * Returns true if the pmap's pv is one of the first
5786 * 16 pvs linked to from this page. This count may
5787 * be changed upwards or downwards in the future; it
5788 * is only necessary that true be returned for a small
5789 * subset of pmaps for proper page aging.
5792 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5794 struct md_page *pvh;
5795 struct rwlock *lock;
5800 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5801 ("pmap_page_exists_quick: page %p is not managed", m));
5803 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5805 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5806 if (PV_PMAP(pv) == pmap) {
5814 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5815 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5816 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5817 if (PV_PMAP(pv) == pmap) {
5831 * pmap_page_wired_mappings:
5833 * Return the number of managed mappings to the given physical page
5837 pmap_page_wired_mappings(vm_page_t m)
5839 struct rwlock *lock;
5840 struct md_page *pvh;
5844 int count, md_gen, pvh_gen;
5846 if ((m->oflags & VPO_UNMANAGED) != 0)
5848 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5852 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5854 if (!PMAP_TRYLOCK(pmap)) {
5855 md_gen = m->md.pv_gen;
5859 if (md_gen != m->md.pv_gen) {
5864 pte = pmap_pte(pmap, pv->pv_va);
5865 if ((*pte & PG_W) != 0)
5869 if ((m->flags & PG_FICTITIOUS) == 0) {
5870 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5871 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5873 if (!PMAP_TRYLOCK(pmap)) {
5874 md_gen = m->md.pv_gen;
5875 pvh_gen = pvh->pv_gen;
5879 if (md_gen != m->md.pv_gen ||
5880 pvh_gen != pvh->pv_gen) {
5885 pte = pmap_pde(pmap, pv->pv_va);
5886 if ((*pte & PG_W) != 0)
5896 * Returns TRUE if the given page is mapped individually or as part of
5897 * a 2mpage. Otherwise, returns FALSE.
5900 pmap_page_is_mapped(vm_page_t m)
5902 struct rwlock *lock;
5905 if ((m->oflags & VPO_UNMANAGED) != 0)
5907 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5909 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5910 ((m->flags & PG_FICTITIOUS) == 0 &&
5911 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5917 * Destroy all managed, non-wired mappings in the given user-space
5918 * pmap. This pmap cannot be active on any processor besides the
5921 * This function cannot be applied to the kernel pmap. Moreover, it
5922 * is not intended for general use. It is only to be used during
5923 * process termination. Consequently, it can be implemented in ways
5924 * that make it faster than pmap_remove(). First, it can more quickly
5925 * destroy mappings by iterating over the pmap's collection of PV
5926 * entries, rather than searching the page table. Second, it doesn't
5927 * have to test and clear the page table entries atomically, because
5928 * no processor is currently accessing the user address space. In
5929 * particular, a page table entry's dirty bit won't change state once
5930 * this function starts.
5932 * Although this function destroys all of the pmap's managed,
5933 * non-wired mappings, it can delay and batch the invalidation of TLB
5934 * entries without calling pmap_delayed_invl_started() and
5935 * pmap_delayed_invl_finished(). Because the pmap is not active on
5936 * any other processor, none of these TLB entries will ever be used
5937 * before their eventual invalidation. Consequently, there is no need
5938 * for either pmap_remove_all() or pmap_remove_write() to wait for
5939 * that eventual TLB invalidation.
5942 pmap_remove_pages(pmap_t pmap)
5945 pt_entry_t *pte, tpte;
5946 pt_entry_t PG_M, PG_RW, PG_V;
5947 struct spglist free;
5948 vm_page_t m, mpte, mt;
5950 struct md_page *pvh;
5951 struct pv_chunk *pc, *npc;
5952 struct rwlock *lock;
5954 uint64_t inuse, bitmask;
5955 int allfree, field, freed, idx;
5956 boolean_t superpage;
5960 * Assert that the given pmap is only active on the current
5961 * CPU. Unfortunately, we cannot block another CPU from
5962 * activating the pmap while this function is executing.
5964 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5967 cpuset_t other_cpus;
5969 other_cpus = all_cpus;
5971 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5972 CPU_AND(&other_cpus, &pmap->pm_active);
5974 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5979 PG_M = pmap_modified_bit(pmap);
5980 PG_V = pmap_valid_bit(pmap);
5981 PG_RW = pmap_rw_bit(pmap);
5985 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5988 for (field = 0; field < _NPCM; field++) {
5989 inuse = ~pc->pc_map[field] & pc_freemask[field];
5990 while (inuse != 0) {
5992 bitmask = 1UL << bit;
5993 idx = field * 64 + bit;
5994 pv = &pc->pc_pventry[idx];
5997 pte = pmap_pdpe(pmap, pv->pv_va);
5999 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6001 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6004 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6006 pte = &pte[pmap_pte_index(pv->pv_va)];
6010 * Keep track whether 'tpte' is a
6011 * superpage explicitly instead of
6012 * relying on PG_PS being set.
6014 * This is because PG_PS is numerically
6015 * identical to PG_PTE_PAT and thus a
6016 * regular page could be mistaken for
6022 if ((tpte & PG_V) == 0) {
6023 panic("bad pte va %lx pte %lx",
6028 * We cannot remove wired pages from a process' mapping at this time
6036 pa = tpte & PG_PS_FRAME;
6038 pa = tpte & PG_FRAME;
6040 m = PHYS_TO_VM_PAGE(pa);
6041 KASSERT(m->phys_addr == pa,
6042 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6043 m, (uintmax_t)m->phys_addr,
6046 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6047 m < &vm_page_array[vm_page_array_size],
6048 ("pmap_remove_pages: bad tpte %#jx",
6054 * Update the vm_page_t clean/reference bits.
6056 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6058 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6064 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6067 pc->pc_map[field] |= bitmask;
6069 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6070 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6071 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6073 if (TAILQ_EMPTY(&pvh->pv_list)) {
6074 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6075 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6076 TAILQ_EMPTY(&mt->md.pv_list))
6077 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6079 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6081 pmap_resident_count_dec(pmap, 1);
6082 KASSERT(mpte->wire_count == NPTEPG,
6083 ("pmap_remove_pages: pte page wire count error"));
6084 mpte->wire_count = 0;
6085 pmap_add_delayed_free_list(mpte, &free, FALSE);
6088 pmap_resident_count_dec(pmap, 1);
6089 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6091 if ((m->aflags & PGA_WRITEABLE) != 0 &&
6092 TAILQ_EMPTY(&m->md.pv_list) &&
6093 (m->flags & PG_FICTITIOUS) == 0) {
6094 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6095 if (TAILQ_EMPTY(&pvh->pv_list))
6096 vm_page_aflag_clear(m, PGA_WRITEABLE);
6099 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
6103 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
6104 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
6105 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
6107 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
6113 pmap_invalidate_all(pmap);
6115 vm_page_free_pages_toq(&free, true);
6119 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
6121 struct rwlock *lock;
6123 struct md_page *pvh;
6124 pt_entry_t *pte, mask;
6125 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6127 int md_gen, pvh_gen;
6131 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6134 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6136 if (!PMAP_TRYLOCK(pmap)) {
6137 md_gen = m->md.pv_gen;
6141 if (md_gen != m->md.pv_gen) {
6146 pte = pmap_pte(pmap, pv->pv_va);
6149 PG_M = pmap_modified_bit(pmap);
6150 PG_RW = pmap_rw_bit(pmap);
6151 mask |= PG_RW | PG_M;
6154 PG_A = pmap_accessed_bit(pmap);
6155 PG_V = pmap_valid_bit(pmap);
6156 mask |= PG_V | PG_A;
6158 rv = (*pte & mask) == mask;
6163 if ((m->flags & PG_FICTITIOUS) == 0) {
6164 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6165 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6167 if (!PMAP_TRYLOCK(pmap)) {
6168 md_gen = m->md.pv_gen;
6169 pvh_gen = pvh->pv_gen;
6173 if (md_gen != m->md.pv_gen ||
6174 pvh_gen != pvh->pv_gen) {
6179 pte = pmap_pde(pmap, pv->pv_va);
6182 PG_M = pmap_modified_bit(pmap);
6183 PG_RW = pmap_rw_bit(pmap);
6184 mask |= PG_RW | PG_M;
6187 PG_A = pmap_accessed_bit(pmap);
6188 PG_V = pmap_valid_bit(pmap);
6189 mask |= PG_V | PG_A;
6191 rv = (*pte & mask) == mask;
6205 * Return whether or not the specified physical page was modified
6206 * in any physical maps.
6209 pmap_is_modified(vm_page_t m)
6212 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6213 ("pmap_is_modified: page %p is not managed", m));
6216 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6217 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
6218 * is clear, no PTEs can have PG_M set.
6220 VM_OBJECT_ASSERT_WLOCKED(m->object);
6221 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6223 return (pmap_page_test_mappings(m, FALSE, TRUE));
6227 * pmap_is_prefaultable:
6229 * Return whether or not the specified virtual address is eligible
6233 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
6236 pt_entry_t *pte, PG_V;
6239 PG_V = pmap_valid_bit(pmap);
6242 pde = pmap_pde(pmap, addr);
6243 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
6244 pte = pmap_pde_to_pte(pde, addr);
6245 rv = (*pte & PG_V) == 0;
6252 * pmap_is_referenced:
6254 * Return whether or not the specified physical page was referenced
6255 * in any physical maps.
6258 pmap_is_referenced(vm_page_t m)
6261 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6262 ("pmap_is_referenced: page %p is not managed", m));
6263 return (pmap_page_test_mappings(m, TRUE, FALSE));
6267 * Clear the write and modified bits in each of the given page's mappings.
6270 pmap_remove_write(vm_page_t m)
6272 struct md_page *pvh;
6274 struct rwlock *lock;
6275 pv_entry_t next_pv, pv;
6277 pt_entry_t oldpte, *pte, PG_M, PG_RW;
6279 int pvh_gen, md_gen;
6281 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6282 ("pmap_remove_write: page %p is not managed", m));
6285 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
6286 * set by another thread while the object is locked. Thus,
6287 * if PGA_WRITEABLE is clear, no page table entries need updating.
6289 VM_OBJECT_ASSERT_WLOCKED(m->object);
6290 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
6292 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6293 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6294 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6297 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6299 if (!PMAP_TRYLOCK(pmap)) {
6300 pvh_gen = pvh->pv_gen;
6304 if (pvh_gen != pvh->pv_gen) {
6310 PG_RW = pmap_rw_bit(pmap);
6312 pde = pmap_pde(pmap, va);
6313 if ((*pde & PG_RW) != 0)
6314 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6315 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6316 ("inconsistent pv lock %p %p for page %p",
6317 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6320 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6322 if (!PMAP_TRYLOCK(pmap)) {
6323 pvh_gen = pvh->pv_gen;
6324 md_gen = m->md.pv_gen;
6328 if (pvh_gen != pvh->pv_gen ||
6329 md_gen != m->md.pv_gen) {
6335 PG_M = pmap_modified_bit(pmap);
6336 PG_RW = pmap_rw_bit(pmap);
6337 pde = pmap_pde(pmap, pv->pv_va);
6338 KASSERT((*pde & PG_PS) == 0,
6339 ("pmap_remove_write: found a 2mpage in page %p's pv list",
6341 pte = pmap_pde_to_pte(pde, pv->pv_va);
6344 if (oldpte & PG_RW) {
6345 if (!atomic_cmpset_long(pte, oldpte, oldpte &
6348 if ((oldpte & PG_M) != 0)
6350 pmap_invalidate_page(pmap, pv->pv_va);
6355 vm_page_aflag_clear(m, PGA_WRITEABLE);
6356 pmap_delayed_invl_wait(m);
6359 static __inline boolean_t
6360 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
6363 if (!pmap_emulate_ad_bits(pmap))
6366 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
6369 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
6370 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
6371 * if the EPT_PG_WRITE bit is set.
6373 if ((pte & EPT_PG_WRITE) != 0)
6377 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
6379 if ((pte & EPT_PG_EXECUTE) == 0 ||
6380 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
6387 * pmap_ts_referenced:
6389 * Return a count of reference bits for a page, clearing those bits.
6390 * It is not necessary for every reference bit to be cleared, but it
6391 * is necessary that 0 only be returned when there are truly no
6392 * reference bits set.
6394 * As an optimization, update the page's dirty field if a modified bit is
6395 * found while counting reference bits. This opportunistic update can be
6396 * performed at low cost and can eliminate the need for some future calls
6397 * to pmap_is_modified(). However, since this function stops after
6398 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
6399 * dirty pages. Those dirty pages will only be detected by a future call
6400 * to pmap_is_modified().
6402 * A DI block is not needed within this function, because
6403 * invalidations are performed before the PV list lock is
6407 pmap_ts_referenced(vm_page_t m)
6409 struct md_page *pvh;
6412 struct rwlock *lock;
6413 pd_entry_t oldpde, *pde;
6414 pt_entry_t *pte, PG_A, PG_M, PG_RW;
6417 int cleared, md_gen, not_cleared, pvh_gen;
6418 struct spglist free;
6421 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6422 ("pmap_ts_referenced: page %p is not managed", m));
6425 pa = VM_PAGE_TO_PHYS(m);
6426 lock = PHYS_TO_PV_LIST_LOCK(pa);
6427 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
6431 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
6432 goto small_mappings;
6438 if (!PMAP_TRYLOCK(pmap)) {
6439 pvh_gen = pvh->pv_gen;
6443 if (pvh_gen != pvh->pv_gen) {
6448 PG_A = pmap_accessed_bit(pmap);
6449 PG_M = pmap_modified_bit(pmap);
6450 PG_RW = pmap_rw_bit(pmap);
6452 pde = pmap_pde(pmap, pv->pv_va);
6454 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6456 * Although "oldpde" is mapping a 2MB page, because
6457 * this function is called at a 4KB page granularity,
6458 * we only update the 4KB page under test.
6462 if ((oldpde & PG_A) != 0) {
6464 * Since this reference bit is shared by 512 4KB
6465 * pages, it should not be cleared every time it is
6466 * tested. Apply a simple "hash" function on the
6467 * physical page number, the virtual superpage number,
6468 * and the pmap address to select one 4KB page out of
6469 * the 512 on which testing the reference bit will
6470 * result in clearing that reference bit. This
6471 * function is designed to avoid the selection of the
6472 * same 4KB page for every 2MB page mapping.
6474 * On demotion, a mapping that hasn't been referenced
6475 * is simply destroyed. To avoid the possibility of a
6476 * subsequent page fault on a demoted wired mapping,
6477 * always leave its reference bit set. Moreover,
6478 * since the superpage is wired, the current state of
6479 * its reference bit won't affect page replacement.
6481 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
6482 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
6483 (oldpde & PG_W) == 0) {
6484 if (safe_to_clear_referenced(pmap, oldpde)) {
6485 atomic_clear_long(pde, PG_A);
6486 pmap_invalidate_page(pmap, pv->pv_va);
6488 } else if (pmap_demote_pde_locked(pmap, pde,
6489 pv->pv_va, &lock)) {
6491 * Remove the mapping to a single page
6492 * so that a subsequent access may
6493 * repromote. Since the underlying
6494 * page table page is fully populated,
6495 * this removal never frees a page
6499 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6501 pte = pmap_pde_to_pte(pde, va);
6502 pmap_remove_pte(pmap, pte, va, *pde,
6504 pmap_invalidate_page(pmap, va);
6510 * The superpage mapping was removed
6511 * entirely and therefore 'pv' is no
6519 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6520 ("inconsistent pv lock %p %p for page %p",
6521 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6526 /* Rotate the PV list if it has more than one entry. */
6527 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6528 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6529 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
6532 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
6534 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
6536 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
6543 if (!PMAP_TRYLOCK(pmap)) {
6544 pvh_gen = pvh->pv_gen;
6545 md_gen = m->md.pv_gen;
6549 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6554 PG_A = pmap_accessed_bit(pmap);
6555 PG_M = pmap_modified_bit(pmap);
6556 PG_RW = pmap_rw_bit(pmap);
6557 pde = pmap_pde(pmap, pv->pv_va);
6558 KASSERT((*pde & PG_PS) == 0,
6559 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
6561 pte = pmap_pde_to_pte(pde, pv->pv_va);
6562 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6564 if ((*pte & PG_A) != 0) {
6565 if (safe_to_clear_referenced(pmap, *pte)) {
6566 atomic_clear_long(pte, PG_A);
6567 pmap_invalidate_page(pmap, pv->pv_va);
6569 } else if ((*pte & PG_W) == 0) {
6571 * Wired pages cannot be paged out so
6572 * doing accessed bit emulation for
6573 * them is wasted effort. We do the
6574 * hard work for unwired pages only.
6576 pmap_remove_pte(pmap, pte, pv->pv_va,
6577 *pde, &free, &lock);
6578 pmap_invalidate_page(pmap, pv->pv_va);
6583 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
6584 ("inconsistent pv lock %p %p for page %p",
6585 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
6590 /* Rotate the PV list if it has more than one entry. */
6591 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
6592 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6593 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6596 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
6597 not_cleared < PMAP_TS_REFERENCED_MAX);
6600 vm_page_free_pages_toq(&free, true);
6601 return (cleared + not_cleared);
6605 * Apply the given advice to the specified range of addresses within the
6606 * given pmap. Depending on the advice, clear the referenced and/or
6607 * modified flags in each mapping and set the mapped page's dirty field.
6610 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
6612 struct rwlock *lock;
6613 pml4_entry_t *pml4e;
6615 pd_entry_t oldpde, *pde;
6616 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
6617 vm_offset_t va, va_next;
6619 boolean_t anychanged;
6621 if (advice != MADV_DONTNEED && advice != MADV_FREE)
6625 * A/D bit emulation requires an alternate code path when clearing
6626 * the modified and accessed bits below. Since this function is
6627 * advisory in nature we skip it entirely for pmaps that require
6628 * A/D bit emulation.
6630 if (pmap_emulate_ad_bits(pmap))
6633 PG_A = pmap_accessed_bit(pmap);
6634 PG_G = pmap_global_bit(pmap);
6635 PG_M = pmap_modified_bit(pmap);
6636 PG_V = pmap_valid_bit(pmap);
6637 PG_RW = pmap_rw_bit(pmap);
6639 pmap_delayed_invl_started();
6641 for (; sva < eva; sva = va_next) {
6642 pml4e = pmap_pml4e(pmap, sva);
6643 if ((*pml4e & PG_V) == 0) {
6644 va_next = (sva + NBPML4) & ~PML4MASK;
6649 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6650 if ((*pdpe & PG_V) == 0) {
6651 va_next = (sva + NBPDP) & ~PDPMASK;
6656 va_next = (sva + NBPDR) & ~PDRMASK;
6659 pde = pmap_pdpe_to_pde(pdpe, sva);
6661 if ((oldpde & PG_V) == 0)
6663 else if ((oldpde & PG_PS) != 0) {
6664 if ((oldpde & PG_MANAGED) == 0)
6667 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6672 * The large page mapping was destroyed.
6678 * Unless the page mappings are wired, remove the
6679 * mapping to a single page so that a subsequent
6680 * access may repromote. Since the underlying page
6681 * table page is fully populated, this removal never
6682 * frees a page table page.
6684 if ((oldpde & PG_W) == 0) {
6685 pte = pmap_pde_to_pte(pde, sva);
6686 KASSERT((*pte & PG_V) != 0,
6687 ("pmap_advise: invalid PTE"));
6688 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6698 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6700 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
6702 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6703 if (advice == MADV_DONTNEED) {
6705 * Future calls to pmap_is_modified()
6706 * can be avoided by making the page
6709 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6712 atomic_clear_long(pte, PG_M | PG_A);
6713 } else if ((*pte & PG_A) != 0)
6714 atomic_clear_long(pte, PG_A);
6718 if ((*pte & PG_G) != 0) {
6725 if (va != va_next) {
6726 pmap_invalidate_range(pmap, va, sva);
6731 pmap_invalidate_range(pmap, va, sva);
6734 pmap_invalidate_all(pmap);
6736 pmap_delayed_invl_finished();
6740 * Clear the modify bits on the specified physical page.
6743 pmap_clear_modify(vm_page_t m)
6745 struct md_page *pvh;
6747 pv_entry_t next_pv, pv;
6748 pd_entry_t oldpde, *pde;
6749 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6750 struct rwlock *lock;
6752 int md_gen, pvh_gen;
6754 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6755 ("pmap_clear_modify: page %p is not managed", m));
6756 VM_OBJECT_ASSERT_WLOCKED(m->object);
6757 KASSERT(!vm_page_xbusied(m),
6758 ("pmap_clear_modify: page %p is exclusive busied", m));
6761 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6762 * If the object containing the page is locked and the page is not
6763 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6765 if ((m->aflags & PGA_WRITEABLE) == 0)
6767 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6768 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6769 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6772 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6774 if (!PMAP_TRYLOCK(pmap)) {
6775 pvh_gen = pvh->pv_gen;
6779 if (pvh_gen != pvh->pv_gen) {
6784 PG_M = pmap_modified_bit(pmap);
6785 PG_V = pmap_valid_bit(pmap);
6786 PG_RW = pmap_rw_bit(pmap);
6788 pde = pmap_pde(pmap, va);
6790 if ((oldpde & PG_RW) != 0) {
6791 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6792 if ((oldpde & PG_W) == 0) {
6794 * Write protect the mapping to a
6795 * single page so that a subsequent
6796 * write access may repromote.
6798 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6800 pte = pmap_pde_to_pte(pde, va);
6802 if ((oldpte & PG_V) != 0) {
6803 while (!atomic_cmpset_long(pte,
6805 oldpte & ~(PG_M | PG_RW)))
6808 pmap_invalidate_page(pmap, va);
6815 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6817 if (!PMAP_TRYLOCK(pmap)) {
6818 md_gen = m->md.pv_gen;
6819 pvh_gen = pvh->pv_gen;
6823 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6828 PG_M = pmap_modified_bit(pmap);
6829 PG_RW = pmap_rw_bit(pmap);
6830 pde = pmap_pde(pmap, pv->pv_va);
6831 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6832 " a 2mpage in page %p's pv list", m));
6833 pte = pmap_pde_to_pte(pde, pv->pv_va);
6834 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6835 atomic_clear_long(pte, PG_M);
6836 pmap_invalidate_page(pmap, pv->pv_va);
6844 * Miscellaneous support routines follow
6847 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6848 static __inline void
6849 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6854 * The cache mode bits are all in the low 32-bits of the
6855 * PTE, so we can just spin on updating the low 32-bits.
6858 opte = *(u_int *)pte;
6859 npte = opte & ~mask;
6861 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6864 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6865 static __inline void
6866 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6871 * The cache mode bits are all in the low 32-bits of the
6872 * PDE, so we can just spin on updating the low 32-bits.
6875 opde = *(u_int *)pde;
6876 npde = opde & ~mask;
6878 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6882 * Map a set of physical memory pages into the kernel virtual
6883 * address space. Return a pointer to where it is mapped. This
6884 * routine is intended to be used for mapping device memory,
6888 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6890 struct pmap_preinit_mapping *ppim;
6891 vm_offset_t va, offset;
6895 offset = pa & PAGE_MASK;
6896 size = round_page(offset + size);
6897 pa = trunc_page(pa);
6899 if (!pmap_initialized) {
6901 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6902 ppim = pmap_preinit_mapping + i;
6903 if (ppim->va == 0) {
6907 ppim->va = virtual_avail;
6908 virtual_avail += size;
6914 panic("%s: too many preinit mappings", __func__);
6917 * If we have a preinit mapping, re-use it.
6919 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6920 ppim = pmap_preinit_mapping + i;
6921 if (ppim->pa == pa && ppim->sz == size &&
6923 return ((void *)(ppim->va + offset));
6926 * If the specified range of physical addresses fits within
6927 * the direct map window, use the direct map.
6929 if (pa < dmaplimit && pa + size < dmaplimit) {
6930 va = PHYS_TO_DMAP(pa);
6931 if (!pmap_change_attr(va, size, mode))
6932 return ((void *)(va + offset));
6934 va = kva_alloc(size);
6936 panic("%s: Couldn't allocate KVA", __func__);
6938 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6939 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6940 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6941 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6942 return ((void *)(va + offset));
6946 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6949 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6953 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6956 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6960 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6962 struct pmap_preinit_mapping *ppim;
6966 /* If we gave a direct map region in pmap_mapdev, do nothing */
6967 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6969 offset = va & PAGE_MASK;
6970 size = round_page(offset + size);
6971 va = trunc_page(va);
6972 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6973 ppim = pmap_preinit_mapping + i;
6974 if (ppim->va == va && ppim->sz == size) {
6975 if (pmap_initialized)
6981 if (va + size == virtual_avail)
6986 if (pmap_initialized)
6991 * Tries to demote a 1GB page mapping.
6994 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6996 pdp_entry_t newpdpe, oldpdpe;
6997 pd_entry_t *firstpde, newpde, *pde;
6998 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7002 PG_A = pmap_accessed_bit(pmap);
7003 PG_M = pmap_modified_bit(pmap);
7004 PG_V = pmap_valid_bit(pmap);
7005 PG_RW = pmap_rw_bit(pmap);
7007 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7009 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7010 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7011 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7012 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7013 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7014 " in pmap %p", va, pmap);
7017 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7018 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7019 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7020 KASSERT((oldpdpe & PG_A) != 0,
7021 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7022 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7023 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7027 * Initialize the page directory page.
7029 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7035 * Demote the mapping.
7040 * Invalidate a stale recursive mapping of the page directory page.
7042 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7044 pmap_pdpe_demotions++;
7045 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7046 " in pmap %p", va, pmap);
7051 * Sets the memory attribute for the specified page.
7054 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
7057 m->md.pat_mode = ma;
7060 * If "m" is a normal page, update its direct mapping. This update
7061 * can be relied upon to perform any cache operations that are
7062 * required for data coherence.
7064 if ((m->flags & PG_FICTITIOUS) == 0 &&
7065 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
7067 panic("memory attribute change on the direct map failed");
7071 * Changes the specified virtual address range's memory type to that given by
7072 * the parameter "mode". The specified virtual address range must be
7073 * completely contained within either the direct map or the kernel map. If
7074 * the virtual address range is contained within the kernel map, then the
7075 * memory type for each of the corresponding ranges of the direct map is also
7076 * changed. (The corresponding ranges of the direct map are those ranges that
7077 * map the same physical pages as the specified virtual address range.) These
7078 * changes to the direct map are necessary because Intel describes the
7079 * behavior of their processors as "undefined" if two or more mappings to the
7080 * same physical page have different memory types.
7082 * Returns zero if the change completed successfully, and either EINVAL or
7083 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
7084 * of the virtual address range was not mapped, and ENOMEM is returned if
7085 * there was insufficient memory available to complete the change. In the
7086 * latter case, the memory type may have been changed on some part of the
7087 * virtual address range or the direct map.
7090 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
7094 PMAP_LOCK(kernel_pmap);
7095 error = pmap_change_attr_locked(va, size, mode);
7096 PMAP_UNLOCK(kernel_pmap);
7101 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
7103 vm_offset_t base, offset, tmpva;
7104 vm_paddr_t pa_start, pa_end, pa_end1;
7108 int cache_bits_pte, cache_bits_pde, error;
7111 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
7112 base = trunc_page(va);
7113 offset = va & PAGE_MASK;
7114 size = round_page(offset + size);
7117 * Only supported on kernel virtual addresses, including the direct
7118 * map but excluding the recursive map.
7120 if (base < DMAP_MIN_ADDRESS)
7123 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
7124 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
7128 * Pages that aren't mapped aren't supported. Also break down 2MB pages
7129 * into 4KB pages if required.
7131 for (tmpva = base; tmpva < base + size; ) {
7132 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7133 if (pdpe == NULL || *pdpe == 0)
7135 if (*pdpe & PG_PS) {
7137 * If the current 1GB page already has the required
7138 * memory type, then we need not demote this page. Just
7139 * increment tmpva to the next 1GB page frame.
7141 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
7142 tmpva = trunc_1gpage(tmpva) + NBPDP;
7147 * If the current offset aligns with a 1GB page frame
7148 * and there is at least 1GB left within the range, then
7149 * we need not break down this page into 2MB pages.
7151 if ((tmpva & PDPMASK) == 0 &&
7152 tmpva + PDPMASK < base + size) {
7156 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
7159 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7164 * If the current 2MB page already has the required
7165 * memory type, then we need not demote this page. Just
7166 * increment tmpva to the next 2MB page frame.
7168 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
7169 tmpva = trunc_2mpage(tmpva) + NBPDR;
7174 * If the current offset aligns with a 2MB page frame
7175 * and there is at least 2MB left within the range, then
7176 * we need not break down this page into 4KB pages.
7178 if ((tmpva & PDRMASK) == 0 &&
7179 tmpva + PDRMASK < base + size) {
7183 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
7186 pte = pmap_pde_to_pte(pde, tmpva);
7194 * Ok, all the pages exist, so run through them updating their
7195 * cache mode if required.
7197 pa_start = pa_end = 0;
7198 for (tmpva = base; tmpva < base + size; ) {
7199 pdpe = pmap_pdpe(kernel_pmap, tmpva);
7200 if (*pdpe & PG_PS) {
7201 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
7202 pmap_pde_attr(pdpe, cache_bits_pde,
7206 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7207 (*pdpe & PG_PS_FRAME) < dmaplimit) {
7208 if (pa_start == pa_end) {
7209 /* Start physical address run. */
7210 pa_start = *pdpe & PG_PS_FRAME;
7211 pa_end = pa_start + NBPDP;
7212 } else if (pa_end == (*pdpe & PG_PS_FRAME))
7215 /* Run ended, update direct map. */
7216 error = pmap_change_attr_locked(
7217 PHYS_TO_DMAP(pa_start),
7218 pa_end - pa_start, mode);
7221 /* Start physical address run. */
7222 pa_start = *pdpe & PG_PS_FRAME;
7223 pa_end = pa_start + NBPDP;
7226 tmpva = trunc_1gpage(tmpva) + NBPDP;
7229 pde = pmap_pdpe_to_pde(pdpe, tmpva);
7231 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
7232 pmap_pde_attr(pde, cache_bits_pde,
7236 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7237 (*pde & PG_PS_FRAME) < dmaplimit) {
7238 if (pa_start == pa_end) {
7239 /* Start physical address run. */
7240 pa_start = *pde & PG_PS_FRAME;
7241 pa_end = pa_start + NBPDR;
7242 } else if (pa_end == (*pde & PG_PS_FRAME))
7245 /* Run ended, update direct map. */
7246 error = pmap_change_attr_locked(
7247 PHYS_TO_DMAP(pa_start),
7248 pa_end - pa_start, mode);
7251 /* Start physical address run. */
7252 pa_start = *pde & PG_PS_FRAME;
7253 pa_end = pa_start + NBPDR;
7256 tmpva = trunc_2mpage(tmpva) + NBPDR;
7258 pte = pmap_pde_to_pte(pde, tmpva);
7259 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
7260 pmap_pte_attr(pte, cache_bits_pte,
7264 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
7265 (*pte & PG_FRAME) < dmaplimit) {
7266 if (pa_start == pa_end) {
7267 /* Start physical address run. */
7268 pa_start = *pte & PG_FRAME;
7269 pa_end = pa_start + PAGE_SIZE;
7270 } else if (pa_end == (*pte & PG_FRAME))
7271 pa_end += PAGE_SIZE;
7273 /* Run ended, update direct map. */
7274 error = pmap_change_attr_locked(
7275 PHYS_TO_DMAP(pa_start),
7276 pa_end - pa_start, mode);
7279 /* Start physical address run. */
7280 pa_start = *pte & PG_FRAME;
7281 pa_end = pa_start + PAGE_SIZE;
7287 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
7288 pa_end1 = MIN(pa_end, dmaplimit);
7289 if (pa_start != pa_end1)
7290 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
7291 pa_end1 - pa_start, mode);
7295 * Flush CPU caches if required to make sure any data isn't cached that
7296 * shouldn't be, etc.
7299 pmap_invalidate_range(kernel_pmap, base, tmpva);
7300 pmap_invalidate_cache_range(base, tmpva, FALSE);
7306 * Demotes any mapping within the direct map region that covers more than the
7307 * specified range of physical addresses. This range's size must be a power
7308 * of two and its starting address must be a multiple of its size. Since the
7309 * demotion does not change any attributes of the mapping, a TLB invalidation
7310 * is not mandatory. The caller may, however, request a TLB invalidation.
7313 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
7322 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
7323 KASSERT((base & (len - 1)) == 0,
7324 ("pmap_demote_DMAP: base is not a multiple of len"));
7325 if (len < NBPDP && base < dmaplimit) {
7326 va = PHYS_TO_DMAP(base);
7328 PMAP_LOCK(kernel_pmap);
7329 pdpe = pmap_pdpe(kernel_pmap, va);
7330 if ((*pdpe & X86_PG_V) == 0)
7331 panic("pmap_demote_DMAP: invalid PDPE");
7332 if ((*pdpe & PG_PS) != 0) {
7333 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
7334 panic("pmap_demote_DMAP: PDPE failed");
7338 pde = pmap_pdpe_to_pde(pdpe, va);
7339 if ((*pde & X86_PG_V) == 0)
7340 panic("pmap_demote_DMAP: invalid PDE");
7341 if ((*pde & PG_PS) != 0) {
7342 if (!pmap_demote_pde(kernel_pmap, pde, va))
7343 panic("pmap_demote_DMAP: PDE failed");
7347 if (changed && invalidate)
7348 pmap_invalidate_page(kernel_pmap, va);
7349 PMAP_UNLOCK(kernel_pmap);
7354 * perform the pmap work for mincore
7357 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
7360 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
7364 PG_A = pmap_accessed_bit(pmap);
7365 PG_M = pmap_modified_bit(pmap);
7366 PG_V = pmap_valid_bit(pmap);
7367 PG_RW = pmap_rw_bit(pmap);
7371 pdep = pmap_pde(pmap, addr);
7372 if (pdep != NULL && (*pdep & PG_V)) {
7373 if (*pdep & PG_PS) {
7375 /* Compute the physical address of the 4KB page. */
7376 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
7378 val = MINCORE_SUPER;
7380 pte = *pmap_pde_to_pte(pdep, addr);
7381 pa = pte & PG_FRAME;
7389 if ((pte & PG_V) != 0) {
7390 val |= MINCORE_INCORE;
7391 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7392 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
7393 if ((pte & PG_A) != 0)
7394 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
7396 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
7397 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
7398 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
7399 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
7400 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
7403 PA_UNLOCK_COND(*locked_pa);
7409 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
7411 uint32_t gen, new_gen, pcid_next;
7413 CRITICAL_ASSERT(curthread);
7414 gen = PCPU_GET(pcid_gen);
7415 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
7416 return (pti ? 0 : CR3_PCID_SAVE);
7417 if (pmap->pm_pcids[cpuid].pm_gen == gen)
7418 return (CR3_PCID_SAVE);
7419 pcid_next = PCPU_GET(pcid_next);
7420 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
7421 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
7422 ("cpu %d pcid_next %#x", cpuid, pcid_next));
7423 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
7424 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
7428 PCPU_SET(pcid_gen, new_gen);
7429 pcid_next = PMAP_PCID_KERN + 1;
7433 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
7434 pmap->pm_pcids[cpuid].pm_gen = new_gen;
7435 PCPU_SET(pcid_next, pcid_next + 1);
7440 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
7444 cached = pmap_pcid_alloc(pmap, cpuid);
7445 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
7446 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
7447 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
7448 pmap->pm_pcids[cpuid].pm_pcid));
7449 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
7450 pmap == kernel_pmap,
7451 ("non-kernel pmap pmap %p cpu %d pcid %#x",
7452 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
7457 pmap_activate_sw_pti_post(pmap_t pmap)
7460 if (pmap->pm_ucr3 != PMAP_NO_CR3)
7461 PCPU_GET(tssp)->tss_rsp0 = ((vm_offset_t)PCPU_PTR(pti_stack) +
7462 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful;
7466 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
7468 struct invpcid_descr d;
7469 uint64_t cached, cr3, kcr3, ucr3;
7471 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7473 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7474 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
7475 PCPU_SET(curpmap, pmap);
7476 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
7477 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
7480 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
7482 * Explicitly invalidate translations cached from the
7483 * user page table. They are not automatically
7484 * flushed by reload of cr3 with the kernel page table
7487 * Note that the if() condition is resolved statically
7488 * by using the function argument instead of
7489 * runtime-evaluated invpcid_works value.
7491 if (invpcid_works1) {
7492 d.pcid = PMAP_PCID_USER_PT |
7493 pmap->pm_pcids[cpuid].pm_pcid;
7496 invpcid(&d, INVPCID_CTX);
7498 pmap_pti_pcid_invalidate(ucr3, kcr3);
7502 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
7503 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
7505 PCPU_INC(pm_save_cnt);
7509 pmap_activate_sw_pcid_invpcid_pti(pmap_t pmap, u_int cpuid)
7512 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
7513 pmap_activate_sw_pti_post(pmap);
7517 pmap_activate_sw_pcid_noinvpcid_pti(pmap_t pmap, u_int cpuid)
7522 * If the INVPCID instruction is not available,
7523 * invltlb_pcid_handler() is used to handle an invalidate_all
7524 * IPI, which checks for curpmap == smp_tlb_pmap. The below
7525 * sequence of operations has a window where %CR3 is loaded
7526 * with the new pmap's PML4 address, but the curpmap value has
7527 * not yet been updated. This causes the invltlb IPI handler,
7528 * which is called between the updates, to execute as a NOP,
7529 * which leaves stale TLB entries.
7531 * Note that the most typical use of pmap_activate_sw(), from
7532 * the context switch, is immune to this race, because
7533 * interrupts are disabled (while the thread lock is owned),
7534 * and the IPI happens after curpmap is updated. Protect
7535 * other callers in a similar way, by disabling interrupts
7536 * around the %cr3 register reload and curpmap assignment.
7538 rflags = intr_disable();
7539 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
7540 intr_restore(rflags);
7541 pmap_activate_sw_pti_post(pmap);
7545 pmap_activate_sw_pcid_nopti(pmap_t pmap, u_int cpuid)
7547 uint64_t cached, cr3;
7549 cached = pmap_pcid_alloc_checked(pmap, cpuid);
7551 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
7552 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
7554 PCPU_SET(curpmap, pmap);
7556 PCPU_INC(pm_save_cnt);
7560 pmap_activate_sw_pcid_noinvpcid_nopti(pmap_t pmap, u_int cpuid)
7564 rflags = intr_disable();
7565 pmap_activate_sw_pcid_nopti(pmap, cpuid);
7566 intr_restore(rflags);
7570 pmap_activate_sw_nopcid_nopti(pmap_t pmap, u_int cpuid __unused)
7573 load_cr3(pmap->pm_cr3);
7574 PCPU_SET(curpmap, pmap);
7578 pmap_activate_sw_nopcid_pti(pmap_t pmap, u_int cpuid __unused)
7581 pmap_activate_sw_nopcid_nopti(pmap, cpuid);
7582 PCPU_SET(kcr3, pmap->pm_cr3);
7583 PCPU_SET(ucr3, pmap->pm_ucr3);
7584 pmap_activate_sw_pti_post(pmap);
7587 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (pmap_t, u_int), static)
7590 if (pmap_pcid_enabled && pti && invpcid_works)
7591 return (pmap_activate_sw_pcid_invpcid_pti);
7592 else if (pmap_pcid_enabled && pti && !invpcid_works)
7593 return (pmap_activate_sw_pcid_noinvpcid_pti);
7594 else if (pmap_pcid_enabled && !pti && invpcid_works)
7595 return (pmap_activate_sw_pcid_nopti);
7596 else if (pmap_pcid_enabled && !pti && !invpcid_works)
7597 return (pmap_activate_sw_pcid_noinvpcid_nopti);
7598 else if (!pmap_pcid_enabled && pti)
7599 return (pmap_activate_sw_nopcid_pti);
7600 else /* if (!pmap_pcid_enabled && !pti) */
7601 return (pmap_activate_sw_nopcid_nopti);
7605 pmap_activate_sw(struct thread *td)
7607 pmap_t oldpmap, pmap;
7610 oldpmap = PCPU_GET(curpmap);
7611 pmap = vmspace_pmap(td->td_proc->p_vmspace);
7612 if (oldpmap == pmap)
7614 cpuid = PCPU_GET(cpuid);
7616 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7618 CPU_SET(cpuid, &pmap->pm_active);
7620 pmap_activate_sw_mode(pmap, cpuid);
7622 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
7624 CPU_CLR(cpuid, &oldpmap->pm_active);
7629 pmap_activate(struct thread *td)
7633 pmap_activate_sw(td);
7638 pmap_activate_boot(pmap_t pmap)
7644 * kernel_pmap must be never deactivated, and we ensure that
7645 * by never activating it at all.
7647 MPASS(pmap != kernel_pmap);
7649 cpuid = PCPU_GET(cpuid);
7651 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
7653 CPU_SET(cpuid, &pmap->pm_active);
7655 PCPU_SET(curpmap, pmap);
7657 kcr3 = pmap->pm_cr3;
7658 if (pmap_pcid_enabled)
7659 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
7663 PCPU_SET(kcr3, kcr3);
7664 PCPU_SET(ucr3, PMAP_NO_CR3);
7668 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
7673 * Increase the starting virtual address of the given mapping if a
7674 * different alignment might result in more superpage mappings.
7677 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
7678 vm_offset_t *addr, vm_size_t size)
7680 vm_offset_t superpage_offset;
7684 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
7685 offset += ptoa(object->pg_color);
7686 superpage_offset = offset & PDRMASK;
7687 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
7688 (*addr & PDRMASK) == superpage_offset)
7690 if ((*addr & PDRMASK) < superpage_offset)
7691 *addr = (*addr & ~PDRMASK) + superpage_offset;
7693 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
7697 static unsigned long num_dirty_emulations;
7698 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
7699 &num_dirty_emulations, 0, NULL);
7701 static unsigned long num_accessed_emulations;
7702 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
7703 &num_accessed_emulations, 0, NULL);
7705 static unsigned long num_superpage_accessed_emulations;
7706 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
7707 &num_superpage_accessed_emulations, 0, NULL);
7709 static unsigned long ad_emulation_superpage_promotions;
7710 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
7711 &ad_emulation_superpage_promotions, 0, NULL);
7712 #endif /* INVARIANTS */
7715 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
7718 struct rwlock *lock;
7719 #if VM_NRESERVLEVEL > 0
7723 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
7725 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
7726 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
7728 if (!pmap_emulate_ad_bits(pmap))
7731 PG_A = pmap_accessed_bit(pmap);
7732 PG_M = pmap_modified_bit(pmap);
7733 PG_V = pmap_valid_bit(pmap);
7734 PG_RW = pmap_rw_bit(pmap);
7740 pde = pmap_pde(pmap, va);
7741 if (pde == NULL || (*pde & PG_V) == 0)
7744 if ((*pde & PG_PS) != 0) {
7745 if (ftype == VM_PROT_READ) {
7747 atomic_add_long(&num_superpage_accessed_emulations, 1);
7755 pte = pmap_pde_to_pte(pde, va);
7756 if ((*pte & PG_V) == 0)
7759 if (ftype == VM_PROT_WRITE) {
7760 if ((*pte & PG_RW) == 0)
7763 * Set the modified and accessed bits simultaneously.
7765 * Intel EPT PTEs that do software emulation of A/D bits map
7766 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
7767 * An EPT misconfiguration is triggered if the PTE is writable
7768 * but not readable (WR=10). This is avoided by setting PG_A
7769 * and PG_M simultaneously.
7771 *pte |= PG_M | PG_A;
7776 #if VM_NRESERVLEVEL > 0
7777 /* try to promote the mapping */
7778 if (va < VM_MAXUSER_ADDRESS)
7779 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7783 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7785 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
7786 pmap_ps_enabled(pmap) &&
7787 (m->flags & PG_FICTITIOUS) == 0 &&
7788 vm_reserv_level_iffullpop(m) == 0) {
7789 pmap_promote_pde(pmap, pde, va, &lock);
7791 atomic_add_long(&ad_emulation_superpage_promotions, 1);
7797 if (ftype == VM_PROT_WRITE)
7798 atomic_add_long(&num_dirty_emulations, 1);
7800 atomic_add_long(&num_accessed_emulations, 1);
7802 rv = 0; /* success */
7811 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
7816 pt_entry_t *pte, PG_V;
7820 PG_V = pmap_valid_bit(pmap);
7823 pml4 = pmap_pml4e(pmap, va);
7825 if ((*pml4 & PG_V) == 0)
7828 pdp = pmap_pml4e_to_pdpe(pml4, va);
7830 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
7833 pde = pmap_pdpe_to_pde(pdp, va);
7835 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
7838 pte = pmap_pde_to_pte(pde, va);
7847 * Get the kernel virtual address of a set of physical pages. If there are
7848 * physical addresses not covered by the DMAP perform a transient mapping
7849 * that will be removed when calling pmap_unmap_io_transient.
7851 * \param page The pages the caller wishes to obtain the virtual
7852 * address on the kernel memory map.
7853 * \param vaddr On return contains the kernel virtual memory address
7854 * of the pages passed in the page parameter.
7855 * \param count Number of pages passed in.
7856 * \param can_fault TRUE if the thread using the mapped pages can take
7857 * page faults, FALSE otherwise.
7859 * \returns TRUE if the caller must call pmap_unmap_io_transient when
7860 * finished or FALSE otherwise.
7864 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7865 boolean_t can_fault)
7868 boolean_t needs_mapping;
7870 int cache_bits, error __unused, i;
7873 * Allocate any KVA space that we need, this is done in a separate
7874 * loop to prevent calling vmem_alloc while pinned.
7876 needs_mapping = FALSE;
7877 for (i = 0; i < count; i++) {
7878 paddr = VM_PAGE_TO_PHYS(page[i]);
7879 if (__predict_false(paddr >= dmaplimit)) {
7880 error = vmem_alloc(kernel_arena, PAGE_SIZE,
7881 M_BESTFIT | M_WAITOK, &vaddr[i]);
7882 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7883 needs_mapping = TRUE;
7885 vaddr[i] = PHYS_TO_DMAP(paddr);
7889 /* Exit early if everything is covered by the DMAP */
7894 * NB: The sequence of updating a page table followed by accesses
7895 * to the corresponding pages used in the !DMAP case is subject to
7896 * the situation described in the "AMD64 Architecture Programmer's
7897 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7898 * Coherency Considerations". Therefore, issuing the INVLPG right
7899 * after modifying the PTE bits is crucial.
7903 for (i = 0; i < count; i++) {
7904 paddr = VM_PAGE_TO_PHYS(page[i]);
7905 if (paddr >= dmaplimit) {
7908 * Slow path, since we can get page faults
7909 * while mappings are active don't pin the
7910 * thread to the CPU and instead add a global
7911 * mapping visible to all CPUs.
7913 pmap_qenter(vaddr[i], &page[i], 1);
7915 pte = vtopte(vaddr[i]);
7916 cache_bits = pmap_cache_bits(kernel_pmap,
7917 page[i]->md.pat_mode, 0);
7918 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7925 return (needs_mapping);
7929 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7930 boolean_t can_fault)
7937 for (i = 0; i < count; i++) {
7938 paddr = VM_PAGE_TO_PHYS(page[i]);
7939 if (paddr >= dmaplimit) {
7941 pmap_qremove(vaddr[i], 1);
7942 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7948 pmap_quick_enter_page(vm_page_t m)
7952 paddr = VM_PAGE_TO_PHYS(m);
7953 if (paddr < dmaplimit)
7954 return (PHYS_TO_DMAP(paddr));
7955 mtx_lock_spin(&qframe_mtx);
7956 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7957 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7958 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7963 pmap_quick_remove_page(vm_offset_t addr)
7968 pte_store(vtopte(qframe), 0);
7970 mtx_unlock_spin(&qframe_mtx);
7974 pmap_pti_alloc_page(void)
7978 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
7979 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
7980 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
7985 pmap_pti_free_page(vm_page_t m)
7988 KASSERT(m->wire_count > 0, ("page %p not wired", m));
7989 if (!vm_page_unwire_noq(m))
7991 vm_page_free_zero(m);
8005 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
8006 VM_OBJECT_WLOCK(pti_obj);
8007 pml4_pg = pmap_pti_alloc_page();
8008 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
8009 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
8010 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
8011 pdpe = pmap_pti_pdpe(va);
8012 pmap_pti_wire_pte(pdpe);
8014 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
8015 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
8016 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
8017 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
8018 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
8019 sizeof(struct gate_descriptor) * NIDT, false);
8020 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
8021 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
8023 /* Doublefault stack IST 1 */
8024 va = common_tss[i].tss_ist1;
8025 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8026 /* NMI stack IST 2 */
8027 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
8028 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8029 /* MC# stack IST 3 */
8030 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
8031 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8032 /* DB# stack IST 4 */
8033 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
8034 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
8036 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
8037 (vm_offset_t)etext, true);
8038 pti_finalized = true;
8039 VM_OBJECT_WUNLOCK(pti_obj);
8041 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
8043 static pdp_entry_t *
8044 pmap_pti_pdpe(vm_offset_t va)
8046 pml4_entry_t *pml4e;
8049 vm_pindex_t pml4_idx;
8052 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8054 pml4_idx = pmap_pml4e_index(va);
8055 pml4e = &pti_pml4[pml4_idx];
8059 panic("pml4 alloc after finalization\n");
8060 m = pmap_pti_alloc_page();
8062 pmap_pti_free_page(m);
8063 mphys = *pml4e & ~PAGE_MASK;
8065 mphys = VM_PAGE_TO_PHYS(m);
8066 *pml4e = mphys | X86_PG_RW | X86_PG_V;
8069 mphys = *pml4e & ~PAGE_MASK;
8071 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
8076 pmap_pti_wire_pte(void *pte)
8080 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8081 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8086 pmap_pti_unwire_pde(void *pde, bool only_ref)
8090 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8091 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
8092 MPASS(m->wire_count > 0);
8093 MPASS(only_ref || m->wire_count > 1);
8094 pmap_pti_free_page(m);
8098 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
8103 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8104 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
8105 MPASS(m->wire_count > 0);
8106 if (pmap_pti_free_page(m)) {
8107 pde = pmap_pti_pde(va);
8108 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
8110 pmap_pti_unwire_pde(pde, false);
8115 pmap_pti_pde(vm_offset_t va)
8123 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8125 pdpe = pmap_pti_pdpe(va);
8127 m = pmap_pti_alloc_page();
8129 pmap_pti_free_page(m);
8130 MPASS((*pdpe & X86_PG_PS) == 0);
8131 mphys = *pdpe & ~PAGE_MASK;
8133 mphys = VM_PAGE_TO_PHYS(m);
8134 *pdpe = mphys | X86_PG_RW | X86_PG_V;
8137 MPASS((*pdpe & X86_PG_PS) == 0);
8138 mphys = *pdpe & ~PAGE_MASK;
8141 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
8142 pd_idx = pmap_pde_index(va);
8148 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
8155 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8157 pde = pmap_pti_pde(va);
8158 if (unwire_pde != NULL) {
8160 pmap_pti_wire_pte(pde);
8163 m = pmap_pti_alloc_page();
8165 pmap_pti_free_page(m);
8166 MPASS((*pde & X86_PG_PS) == 0);
8167 mphys = *pde & ~(PAGE_MASK | pg_nx);
8169 mphys = VM_PAGE_TO_PHYS(m);
8170 *pde = mphys | X86_PG_RW | X86_PG_V;
8171 if (unwire_pde != NULL)
8172 *unwire_pde = false;
8175 MPASS((*pde & X86_PG_PS) == 0);
8176 mphys = *pde & ~(PAGE_MASK | pg_nx);
8179 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
8180 pte += pmap_pte_index(va);
8186 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
8190 pt_entry_t *pte, ptev;
8193 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
8195 sva = trunc_page(sva);
8196 MPASS(sva > VM_MAXUSER_ADDRESS);
8197 eva = round_page(eva);
8199 for (; sva < eva; sva += PAGE_SIZE) {
8200 pte = pmap_pti_pte(sva, &unwire_pde);
8201 pa = pmap_kextract(sva);
8202 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
8203 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
8204 VM_MEMATTR_DEFAULT, FALSE);
8206 pte_store(pte, ptev);
8207 pmap_pti_wire_pte(pte);
8209 KASSERT(!pti_finalized,
8210 ("pti overlap after fin %#lx %#lx %#lx",
8212 KASSERT(*pte == ptev,
8213 ("pti non-identical pte after fin %#lx %#lx %#lx",
8217 pde = pmap_pti_pde(sva);
8218 pmap_pti_unwire_pde(pde, true);
8224 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
8229 VM_OBJECT_WLOCK(pti_obj);
8230 pmap_pti_add_kva_locked(sva, eva, exec);
8231 VM_OBJECT_WUNLOCK(pti_obj);
8235 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
8242 sva = rounddown2(sva, PAGE_SIZE);
8243 MPASS(sva > VM_MAXUSER_ADDRESS);
8244 eva = roundup2(eva, PAGE_SIZE);
8246 VM_OBJECT_WLOCK(pti_obj);
8247 for (va = sva; va < eva; va += PAGE_SIZE) {
8248 pte = pmap_pti_pte(va, NULL);
8249 KASSERT((*pte & X86_PG_V) != 0,
8250 ("invalid pte va %#lx pte %#lx pt %#lx", va,
8251 (u_long)pte, *pte));
8253 pmap_pti_unwire_pte(pte, va);
8255 pmap_invalidate_range(kernel_pmap, sva, eva);
8256 VM_OBJECT_WUNLOCK(pti_obj);
8259 #include "opt_ddb.h"
8261 #include <sys/kdb.h>
8262 #include <ddb/ddb.h>
8264 DB_SHOW_COMMAND(pte, pmap_print_pte)
8270 pt_entry_t *pte, PG_V;
8274 db_printf("show pte addr\n");
8277 va = (vm_offset_t)addr;
8279 if (kdb_thread != NULL)
8280 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
8282 pmap = PCPU_GET(curpmap);
8284 PG_V = pmap_valid_bit(pmap);
8285 pml4 = pmap_pml4e(pmap, va);
8286 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
8287 if ((*pml4 & PG_V) == 0) {
8291 pdp = pmap_pml4e_to_pdpe(pml4, va);
8292 db_printf(" pdpe %#016lx", *pdp);
8293 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
8297 pde = pmap_pdpe_to_pde(pdp, va);
8298 db_printf(" pde %#016lx", *pde);
8299 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
8303 pte = pmap_pde_to_pte(pde, va);
8304 db_printf(" pte %#016lx\n", *pte);
8307 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
8312 a = (vm_paddr_t)addr;
8313 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
8315 db_printf("show phys2dmap addr\n");