2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
168 static __inline boolean_t
169 pmap_type_guest(pmap_t pmap)
172 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
175 static __inline boolean_t
176 pmap_emulate_ad_bits(pmap_t pmap)
179 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
182 static __inline pt_entry_t
183 pmap_valid_bit(pmap_t pmap)
187 switch (pmap->pm_type) {
193 if (pmap_emulate_ad_bits(pmap))
194 mask = EPT_PG_EMUL_V;
199 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
205 static __inline pt_entry_t
206 pmap_rw_bit(pmap_t pmap)
210 switch (pmap->pm_type) {
216 if (pmap_emulate_ad_bits(pmap))
217 mask = EPT_PG_EMUL_RW;
222 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
228 static pt_entry_t pg_g;
230 static __inline pt_entry_t
231 pmap_global_bit(pmap_t pmap)
235 switch (pmap->pm_type) {
244 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
250 static __inline pt_entry_t
251 pmap_accessed_bit(pmap_t pmap)
255 switch (pmap->pm_type) {
261 if (pmap_emulate_ad_bits(pmap))
267 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
273 static __inline pt_entry_t
274 pmap_modified_bit(pmap_t pmap)
278 switch (pmap->pm_type) {
284 if (pmap_emulate_ad_bits(pmap))
290 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
296 static __inline pt_entry_t
297 pmap_pku_mask_bit(pmap_t pmap)
300 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
303 #if !defined(DIAGNOSTIC)
304 #ifdef __GNUC_GNU_INLINE__
305 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
307 #define PMAP_INLINE extern inline
314 #define PV_STAT(x) do { x ; } while (0)
316 #define PV_STAT(x) do { } while (0)
319 #define pa_index(pa) ((pa) >> PDRSHIFT)
320 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
322 #define NPV_LIST_LOCKS MAXCPU
324 #define PHYS_TO_PV_LIST_LOCK(pa) \
325 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
327 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
328 struct rwlock **_lockp = (lockp); \
329 struct rwlock *_new_lock; \
331 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
332 if (_new_lock != *_lockp) { \
333 if (*_lockp != NULL) \
334 rw_wunlock(*_lockp); \
335 *_lockp = _new_lock; \
340 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
341 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
343 #define RELEASE_PV_LIST_LOCK(lockp) do { \
344 struct rwlock **_lockp = (lockp); \
346 if (*_lockp != NULL) { \
347 rw_wunlock(*_lockp); \
352 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
353 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
355 struct pmap kernel_pmap_store;
357 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
358 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
361 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
362 "Number of kernel page table pages allocated on bootup");
365 vm_paddr_t dmaplimit;
366 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
369 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
371 /* Unused, kept for ABI stability on the stable branch. */
372 static int pat_works = 1;
373 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
374 "Is page attribute table fully functional?");
376 static int pg_ps_enabled = 1;
377 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
378 &pg_ps_enabled, 0, "Are large page mappings enabled?");
380 #define PAT_INDEX_SIZE 8
381 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
383 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
384 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
385 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
386 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
388 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
389 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
390 static int ndmpdpphys; /* number of DMPDPphys pages */
392 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
395 * pmap_mapdev support pre initialization (i.e. console)
397 #define PMAP_PREINIT_MAPPING_COUNT 8
398 static struct pmap_preinit_mapping {
403 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
404 static int pmap_initialized;
407 * Data for the pv entry allocation mechanism.
408 * Updates to pv_invl_gen are protected by the pv_list_locks[]
409 * elements, but reads are not.
411 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
412 static struct mtx __exclusive_cache_line pv_chunks_mutex;
413 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
414 static u_long pv_invl_gen[NPV_LIST_LOCKS];
415 static struct md_page *pv_table;
416 static struct md_page pv_dummy;
419 * All those kernel PT submaps that BSD is so fond of
421 pt_entry_t *CMAP1 = NULL;
423 static vm_offset_t qframe = 0;
424 static struct mtx qframe_mtx;
426 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
428 static vmem_t *large_vmem;
429 static u_int lm_ents;
430 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
431 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
433 int pmap_pcid_enabled = 1;
434 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
435 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
436 int invpcid_works = 0;
437 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
438 "Is the invpcid instruction available ?");
440 int __read_frequently pti = 0;
441 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
443 "Page Table Isolation enabled");
444 static vm_object_t pti_obj;
445 static pml4_entry_t *pti_pml4;
446 static vm_pindex_t pti_pg_idx;
447 static bool pti_finalized;
449 struct pmap_pkru_range {
450 struct rs_el pkru_rs_el;
455 static uma_zone_t pmap_pkru_ranges_zone;
456 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
457 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
458 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
459 static void *pkru_dup_range(void *ctx, void *data);
460 static void pkru_free_range(void *ctx, void *node);
461 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
462 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
463 static void pmap_pkru_deassign_all(pmap_t pmap);
466 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
473 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
475 return (sysctl_handle_64(oidp, &res, 0, req));
477 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
478 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
479 "Count of saved TLB context on switch");
481 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
482 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
483 static struct mtx invl_gen_mtx;
484 /* Fake lock object to satisfy turnstiles interface. */
485 static struct lock_object invl_gen_ts = {
488 static struct pmap_invl_gen pmap_invl_gen_head = {
492 static u_long pmap_invl_gen = 1;
493 static int pmap_invl_waiters;
494 static struct callout pmap_invl_callout;
495 static bool pmap_invl_callout_inited;
497 #define PMAP_ASSERT_NOT_IN_DI() \
498 KASSERT(pmap_not_in_di(), ("DI already started"))
505 if ((cpu_feature2 & CPUID2_CX16) == 0)
508 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
513 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
517 locked = pmap_di_locked();
518 return (sysctl_handle_int(oidp, &locked, 0, req));
520 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
521 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
522 "Locked delayed invalidation");
524 static bool pmap_not_in_di_l(void);
525 static bool pmap_not_in_di_u(void);
526 DEFINE_IFUNC(, bool, pmap_not_in_di, (void), static)
529 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
533 pmap_not_in_di_l(void)
535 struct pmap_invl_gen *invl_gen;
537 invl_gen = &curthread->td_md.md_invl_gen;
538 return (invl_gen->gen == 0);
542 pmap_thread_init_invl_gen_l(struct thread *td)
544 struct pmap_invl_gen *invl_gen;
546 invl_gen = &td->td_md.md_invl_gen;
551 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
553 struct turnstile *ts;
555 ts = turnstile_trywait(&invl_gen_ts);
556 if (*m_gen > atomic_load_long(invl_gen))
557 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
559 turnstile_cancel(ts);
563 pmap_delayed_invl_finish_unblock(u_long new_gen)
565 struct turnstile *ts;
567 turnstile_chain_lock(&invl_gen_ts);
568 ts = turnstile_lookup(&invl_gen_ts);
570 pmap_invl_gen = new_gen;
572 turnstile_broadcast(ts, TS_SHARED_QUEUE);
573 turnstile_unpend(ts);
575 turnstile_chain_unlock(&invl_gen_ts);
579 * Start a new Delayed Invalidation (DI) block of code, executed by
580 * the current thread. Within a DI block, the current thread may
581 * destroy both the page table and PV list entries for a mapping and
582 * then release the corresponding PV list lock before ensuring that
583 * the mapping is flushed from the TLBs of any processors with the
587 pmap_delayed_invl_start_l(void)
589 struct pmap_invl_gen *invl_gen;
592 invl_gen = &curthread->td_md.md_invl_gen;
593 PMAP_ASSERT_NOT_IN_DI();
594 mtx_lock(&invl_gen_mtx);
595 if (LIST_EMPTY(&pmap_invl_gen_tracker))
596 currgen = pmap_invl_gen;
598 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
599 invl_gen->gen = currgen + 1;
600 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
601 mtx_unlock(&invl_gen_mtx);
605 * Finish the DI block, previously started by the current thread. All
606 * required TLB flushes for the pages marked by
607 * pmap_delayed_invl_page() must be finished before this function is
610 * This function works by bumping the global DI generation number to
611 * the generation number of the current thread's DI, unless there is a
612 * pending DI that started earlier. In the latter case, bumping the
613 * global DI generation number would incorrectly signal that the
614 * earlier DI had finished. Instead, this function bumps the earlier
615 * DI's generation number to match the generation number of the
616 * current thread's DI.
619 pmap_delayed_invl_finish_l(void)
621 struct pmap_invl_gen *invl_gen, *next;
623 invl_gen = &curthread->td_md.md_invl_gen;
624 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
625 mtx_lock(&invl_gen_mtx);
626 next = LIST_NEXT(invl_gen, link);
628 pmap_delayed_invl_finish_unblock(invl_gen->gen);
630 next->gen = invl_gen->gen;
631 LIST_REMOVE(invl_gen, link);
632 mtx_unlock(&invl_gen_mtx);
637 pmap_not_in_di_u(void)
639 struct pmap_invl_gen *invl_gen;
641 invl_gen = &curthread->td_md.md_invl_gen;
642 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
646 pmap_thread_init_invl_gen_u(struct thread *td)
648 struct pmap_invl_gen *invl_gen;
650 invl_gen = &td->td_md.md_invl_gen;
652 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
656 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
658 uint64_t new_high, new_low, old_high, old_low;
661 old_low = new_low = 0;
662 old_high = new_high = (uintptr_t)0;
664 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
665 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
666 : "b"(new_low), "c" (new_high)
669 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
672 out->next = (void *)old_high;
675 out->next = (void *)new_high;
681 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
682 struct pmap_invl_gen *new_val)
684 uint64_t new_high, new_low, old_high, old_low;
687 new_low = new_val->gen;
688 new_high = (uintptr_t)new_val->next;
689 old_low = old_val->gen;
690 old_high = (uintptr_t)old_val->next;
692 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
693 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
694 : "b"(new_low), "c" (new_high)
700 static long invl_start_restart;
701 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
702 &invl_start_restart, 0,
704 static long invl_finish_restart;
705 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
706 &invl_finish_restart, 0,
708 static int invl_max_qlen;
709 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
714 static struct lock_delay_config __read_frequently di_delay;
715 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
718 pmap_delayed_invl_start_u(void)
720 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
722 struct lock_delay_arg lda;
730 invl_gen = &td->td_md.md_invl_gen;
731 PMAP_ASSERT_NOT_IN_DI();
732 lock_delay_arg_init(&lda, &di_delay);
733 invl_gen->saved_pri = 0;
734 pri = td->td_base_pri;
737 pri = td->td_base_pri;
739 invl_gen->saved_pri = pri;
746 for (p = &pmap_invl_gen_head;; p = prev.next) {
748 prevl = atomic_load_ptr(&p->next);
749 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
750 PV_STAT(atomic_add_long(&invl_start_restart, 1));
756 prev.next = (void *)prevl;
759 if ((ii = invl_max_qlen) < i)
760 atomic_cmpset_int(&invl_max_qlen, ii, i);
763 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
764 PV_STAT(atomic_add_long(&invl_start_restart, 1));
769 new_prev.gen = prev.gen;
770 new_prev.next = invl_gen;
771 invl_gen->gen = prev.gen + 1;
773 /* Formal fence between store to invl->gen and updating *p. */
774 atomic_thread_fence_rel();
777 * After inserting an invl_gen element with invalid bit set,
778 * this thread blocks any other thread trying to enter the
779 * delayed invalidation block. Do not allow to remove us from
780 * the CPU, because it causes starvation for other threads.
785 * ABA for *p is not possible there, since p->gen can only
786 * increase. So if the *p thread finished its di, then
787 * started a new one and got inserted into the list at the
788 * same place, its gen will appear greater than the previously
791 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
793 PV_STAT(atomic_add_long(&invl_start_restart, 1));
799 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
800 * invl_gen->next, allowing other threads to iterate past us.
801 * pmap_di_store_invl() provides fence between the generation
802 * write and the update of next.
804 invl_gen->next = NULL;
809 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
810 struct pmap_invl_gen *p)
812 struct pmap_invl_gen prev, new_prev;
816 * Load invl_gen->gen after setting invl_gen->next
817 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
818 * generations to propagate to our invl_gen->gen. Lock prefix
819 * in atomic_set_ptr() worked as seq_cst fence.
821 mygen = atomic_load_long(&invl_gen->gen);
823 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
826 KASSERT(prev.gen < mygen,
827 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
828 new_prev.gen = mygen;
829 new_prev.next = (void *)((uintptr_t)invl_gen->next &
830 ~PMAP_INVL_GEN_NEXT_INVALID);
832 /* Formal fence between load of prev and storing update to it. */
833 atomic_thread_fence_rel();
835 return (pmap_di_store_invl(p, &prev, &new_prev));
839 pmap_delayed_invl_finish_u(void)
841 struct pmap_invl_gen *invl_gen, *p;
843 struct lock_delay_arg lda;
847 invl_gen = &td->td_md.md_invl_gen;
848 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
849 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
850 ("missed invl_start: INVALID"));
851 lock_delay_arg_init(&lda, &di_delay);
854 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
855 prevl = atomic_load_ptr(&p->next);
856 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
857 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
861 if ((void *)prevl == invl_gen)
866 * It is legitimate to not find ourself on the list if a
867 * thread before us finished its DI and started it again.
869 if (__predict_false(p == NULL)) {
870 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
876 atomic_set_ptr((uintptr_t *)&invl_gen->next,
877 PMAP_INVL_GEN_NEXT_INVALID);
878 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
879 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
880 PMAP_INVL_GEN_NEXT_INVALID);
882 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
887 if (atomic_load_int(&pmap_invl_waiters) > 0)
888 pmap_delayed_invl_finish_unblock(0);
889 if (invl_gen->saved_pri != 0) {
891 sched_prio(td, invl_gen->saved_pri);
897 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
899 struct pmap_invl_gen *p, *pn;
904 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
906 nextl = atomic_load_ptr(&p->next);
907 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
908 td = first ? NULL : __containerof(p, struct thread,
910 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
911 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
912 td != NULL ? td->td_tid : -1);
918 static long invl_wait;
919 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
920 "Number of times DI invalidation blocked pmap_remove_all/write");
921 static long invl_wait_slow;
922 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
923 "Number of slow invalidation waits for lockless DI");
927 pmap_delayed_invl_genp(vm_page_t m)
930 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
934 pmap_delayed_invl_callout_func(void *arg __unused)
937 if (atomic_load_int(&pmap_invl_waiters) == 0)
939 pmap_delayed_invl_finish_unblock(0);
943 pmap_delayed_invl_callout_init(void *arg __unused)
946 if (pmap_di_locked())
948 callout_init(&pmap_invl_callout, 1);
949 pmap_invl_callout_inited = true;
951 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
952 pmap_delayed_invl_callout_init, NULL);
955 * Ensure that all currently executing DI blocks, that need to flush
956 * TLB for the given page m, actually flushed the TLB at the time the
957 * function returned. If the page m has an empty PV list and we call
958 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
959 * valid mapping for the page m in either its page table or TLB.
961 * This function works by blocking until the global DI generation
962 * number catches up with the generation number associated with the
963 * given page m and its PV list. Since this function's callers
964 * typically own an object lock and sometimes own a page lock, it
965 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
969 pmap_delayed_invl_wait_l(vm_page_t m)
973 bool accounted = false;
976 m_gen = pmap_delayed_invl_genp(m);
977 while (*m_gen > pmap_invl_gen) {
980 atomic_add_long(&invl_wait, 1);
984 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
989 pmap_delayed_invl_wait_u(vm_page_t m)
992 struct lock_delay_arg lda;
996 m_gen = pmap_delayed_invl_genp(m);
997 lock_delay_arg_init(&lda, &di_delay);
998 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
999 if (fast || !pmap_invl_callout_inited) {
1000 PV_STAT(atomic_add_long(&invl_wait, 1));
1005 * The page's invalidation generation number
1006 * is still below the current thread's number.
1007 * Prepare to block so that we do not waste
1008 * CPU cycles or worse, suffer livelock.
1010 * Since it is impossible to block without
1011 * racing with pmap_delayed_invl_finish_u(),
1012 * prepare for the race by incrementing
1013 * pmap_invl_waiters and arming a 1-tick
1014 * callout which will unblock us if we lose
1017 atomic_add_int(&pmap_invl_waiters, 1);
1020 * Re-check the current thread's invalidation
1021 * generation after incrementing
1022 * pmap_invl_waiters, so that there is no race
1023 * with pmap_delayed_invl_finish_u() setting
1024 * the page generation and checking
1025 * pmap_invl_waiters. The only race allowed
1026 * is for a missed unblock, which is handled
1030 atomic_load_long(&pmap_invl_gen_head.gen)) {
1031 callout_reset(&pmap_invl_callout, 1,
1032 pmap_delayed_invl_callout_func, NULL);
1033 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1034 pmap_delayed_invl_wait_block(m_gen,
1035 &pmap_invl_gen_head.gen);
1037 atomic_add_int(&pmap_invl_waiters, -1);
1042 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *), static)
1045 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1046 pmap_thread_init_invl_gen_u);
1049 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void), static)
1052 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1053 pmap_delayed_invl_start_u);
1056 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void), static)
1059 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1060 pmap_delayed_invl_finish_u);
1063 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t), static)
1066 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1067 pmap_delayed_invl_wait_u);
1071 * Mark the page m's PV list as participating in the current thread's
1072 * DI block. Any threads concurrently using m's PV list to remove or
1073 * restrict all mappings to m will wait for the current thread's DI
1074 * block to complete before proceeding.
1076 * The function works by setting the DI generation number for m's PV
1077 * list to at least the DI generation number of the current thread.
1078 * This forces a caller of pmap_delayed_invl_wait() to block until
1079 * current thread calls pmap_delayed_invl_finish().
1082 pmap_delayed_invl_page(vm_page_t m)
1086 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1087 gen = curthread->td_md.md_invl_gen.gen;
1090 m_gen = pmap_delayed_invl_genp(m);
1098 static caddr_t crashdumpmap;
1101 * Internal flags for pmap_enter()'s helper functions.
1103 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1104 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1107 * Internal flags for pmap_mapdev_internal() and
1108 * pmap_change_props_locked().
1110 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1111 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1112 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1114 TAILQ_HEAD(pv_chunklist, pv_chunk);
1116 static void free_pv_chunk(struct pv_chunk *pc);
1117 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1118 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1119 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1120 static int popcnt_pc_map_pq(uint64_t *map);
1121 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1122 static void reserve_pv_entries(pmap_t pmap, int needed,
1123 struct rwlock **lockp);
1124 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1125 struct rwlock **lockp);
1126 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1127 u_int flags, struct rwlock **lockp);
1128 #if VM_NRESERVLEVEL > 0
1129 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1130 struct rwlock **lockp);
1132 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1133 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1136 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1137 vm_prot_t prot, int mode, int flags);
1138 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1139 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1140 vm_offset_t va, struct rwlock **lockp);
1141 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1143 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1144 vm_prot_t prot, struct rwlock **lockp);
1145 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1146 u_int flags, vm_page_t m, struct rwlock **lockp);
1147 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1148 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1149 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1150 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1151 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1153 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1155 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1157 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1158 static vm_page_t pmap_large_map_getptp_unlocked(void);
1159 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1160 #if VM_NRESERVLEVEL > 0
1161 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1162 struct rwlock **lockp);
1164 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1166 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1167 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1169 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1170 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1171 static void pmap_pti_wire_pte(void *pte);
1172 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1173 struct spglist *free, struct rwlock **lockp);
1174 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1175 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1176 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1177 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1178 struct spglist *free);
1179 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1180 pd_entry_t *pde, struct spglist *free,
1181 struct rwlock **lockp);
1182 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1183 vm_page_t m, struct rwlock **lockp);
1184 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1186 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1188 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1189 struct rwlock **lockp);
1190 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1191 struct rwlock **lockp);
1192 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1193 struct rwlock **lockp);
1195 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1196 struct spglist *free);
1197 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1199 /********************/
1200 /* Inline functions */
1201 /********************/
1203 /* Return a non-clipped PD index for a given VA */
1204 static __inline vm_pindex_t
1205 pmap_pde_pindex(vm_offset_t va)
1207 return (va >> PDRSHIFT);
1211 /* Return a pointer to the PML4 slot that corresponds to a VA */
1212 static __inline pml4_entry_t *
1213 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1216 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1219 /* Return a pointer to the PDP slot that corresponds to a VA */
1220 static __inline pdp_entry_t *
1221 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1225 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1226 return (&pdpe[pmap_pdpe_index(va)]);
1229 /* Return a pointer to the PDP slot that corresponds to a VA */
1230 static __inline pdp_entry_t *
1231 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1233 pml4_entry_t *pml4e;
1236 PG_V = pmap_valid_bit(pmap);
1237 pml4e = pmap_pml4e(pmap, va);
1238 if ((*pml4e & PG_V) == 0)
1240 return (pmap_pml4e_to_pdpe(pml4e, va));
1243 /* Return a pointer to the PD slot that corresponds to a VA */
1244 static __inline pd_entry_t *
1245 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1249 KASSERT((*pdpe & PG_PS) == 0,
1250 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1251 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1252 return (&pde[pmap_pde_index(va)]);
1255 /* Return a pointer to the PD slot that corresponds to a VA */
1256 static __inline pd_entry_t *
1257 pmap_pde(pmap_t pmap, vm_offset_t va)
1262 PG_V = pmap_valid_bit(pmap);
1263 pdpe = pmap_pdpe(pmap, va);
1264 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1266 return (pmap_pdpe_to_pde(pdpe, va));
1269 /* Return a pointer to the PT slot that corresponds to a VA */
1270 static __inline pt_entry_t *
1271 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1275 KASSERT((*pde & PG_PS) == 0,
1276 ("%s: pde %#lx is a leaf", __func__, *pde));
1277 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1278 return (&pte[pmap_pte_index(va)]);
1281 /* Return a pointer to the PT slot that corresponds to a VA */
1282 static __inline pt_entry_t *
1283 pmap_pte(pmap_t pmap, vm_offset_t va)
1288 PG_V = pmap_valid_bit(pmap);
1289 pde = pmap_pde(pmap, va);
1290 if (pde == NULL || (*pde & PG_V) == 0)
1292 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1293 return ((pt_entry_t *)pde);
1294 return (pmap_pde_to_pte(pde, va));
1297 static __inline void
1298 pmap_resident_count_inc(pmap_t pmap, int count)
1301 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1302 pmap->pm_stats.resident_count += count;
1305 static __inline void
1306 pmap_resident_count_dec(pmap_t pmap, int count)
1309 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1310 KASSERT(pmap->pm_stats.resident_count >= count,
1311 ("pmap %p resident count underflow %ld %d", pmap,
1312 pmap->pm_stats.resident_count, count));
1313 pmap->pm_stats.resident_count -= count;
1316 PMAP_INLINE pt_entry_t *
1317 vtopte(vm_offset_t va)
1319 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1321 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1323 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1326 static __inline pd_entry_t *
1327 vtopde(vm_offset_t va)
1329 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1331 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1333 return (PDmap + ((va >> PDRSHIFT) & mask));
1337 allocpages(vm_paddr_t *firstaddr, int n)
1342 bzero((void *)ret, n * PAGE_SIZE);
1343 *firstaddr += n * PAGE_SIZE;
1347 CTASSERT(powerof2(NDMPML4E));
1349 /* number of kernel PDP slots */
1350 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1353 nkpt_init(vm_paddr_t addr)
1360 pt_pages = howmany(addr, 1 << PDRSHIFT);
1361 pt_pages += NKPDPE(pt_pages);
1364 * Add some slop beyond the bare minimum required for bootstrapping
1367 * This is quite important when allocating KVA for kernel modules.
1368 * The modules are required to be linked in the negative 2GB of
1369 * the address space. If we run out of KVA in this region then
1370 * pmap_growkernel() will need to allocate page table pages to map
1371 * the entire 512GB of KVA space which is an unnecessary tax on
1374 * Secondly, device memory mapped as part of setting up the low-
1375 * level console(s) is taken from KVA, starting at virtual_avail.
1376 * This is because cninit() is called after pmap_bootstrap() but
1377 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1380 pt_pages += 32; /* 64MB additional slop. */
1386 * Returns the proper write/execute permission for a physical page that is
1387 * part of the initial boot allocations.
1389 * If the page has kernel text, it is marked as read-only. If the page has
1390 * kernel read-only data, it is marked as read-only/not-executable. If the
1391 * page has only read-write data, it is marked as read-write/not-executable.
1392 * If the page is below/above the kernel range, it is marked as read-write.
1394 * This function operates on 2M pages, since we map the kernel space that
1397 * Note that this doesn't currently provide any protection for modules.
1399 static inline pt_entry_t
1400 bootaddr_rwx(vm_paddr_t pa)
1404 * Everything in the same 2M page as the start of the kernel
1405 * should be static. On the other hand, things in the same 2M
1406 * page as the end of the kernel could be read-write/executable,
1407 * as the kernel image is not guaranteed to end on a 2M boundary.
1409 if (pa < trunc_2mpage(btext - KERNBASE) ||
1410 pa >= trunc_2mpage(_end - KERNBASE))
1413 * The linker should ensure that the read-only and read-write
1414 * portions don't share the same 2M page, so this shouldn't
1415 * impact read-only data. However, in any case, any page with
1416 * read-write data needs to be read-write.
1418 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1419 return (X86_PG_RW | pg_nx);
1421 * Mark any 2M page containing kernel text as read-only. Mark
1422 * other pages with read-only data as read-only and not executable.
1423 * (It is likely a small portion of the read-only data section will
1424 * be marked as read-only, but executable. This should be acceptable
1425 * since the read-only protection will keep the data from changing.)
1426 * Note that fixups to the .text section will still work until we
1429 if (pa < round_2mpage(etext - KERNBASE))
1435 create_pagetables(vm_paddr_t *firstaddr)
1437 int i, j, ndm1g, nkpdpe, nkdmpde;
1441 uint64_t DMPDkernphys;
1443 /* Allocate page table pages for the direct map */
1444 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1445 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1447 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1448 if (ndmpdpphys > NDMPML4E) {
1450 * Each NDMPML4E allows 512 GB, so limit to that,
1451 * and then readjust ndmpdp and ndmpdpphys.
1453 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1454 Maxmem = atop(NDMPML4E * NBPML4);
1455 ndmpdpphys = NDMPML4E;
1456 ndmpdp = NDMPML4E * NPDEPG;
1458 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1460 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1462 * Calculate the number of 1G pages that will fully fit in
1465 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1468 * Allocate 2M pages for the kernel. These will be used in
1469 * place of the first one or more 1G pages from ndm1g.
1471 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1472 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1475 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1476 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1478 /* Allocate pages */
1479 KPML4phys = allocpages(firstaddr, 1);
1480 KPDPphys = allocpages(firstaddr, NKPML4E);
1483 * Allocate the initial number of kernel page table pages required to
1484 * bootstrap. We defer this until after all memory-size dependent
1485 * allocations are done (e.g. direct map), so that we don't have to
1486 * build in too much slop in our estimate.
1488 * Note that when NKPML4E > 1, we have an empty page underneath
1489 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1490 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1492 nkpt_init(*firstaddr);
1493 nkpdpe = NKPDPE(nkpt);
1495 KPTphys = allocpages(firstaddr, nkpt);
1496 KPDphys = allocpages(firstaddr, nkpdpe);
1499 * Connect the zero-filled PT pages to their PD entries. This
1500 * implicitly maps the PT pages at their correct locations within
1503 pd_p = (pd_entry_t *)KPDphys;
1504 for (i = 0; i < nkpt; i++)
1505 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1508 * Map from physical address zero to the end of loader preallocated
1509 * memory using 2MB pages. This replaces some of the PD entries
1512 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1513 /* Preset PG_M and PG_A because demotion expects it. */
1514 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1515 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1518 * Because we map the physical blocks in 2M pages, adjust firstaddr
1519 * to record the physical blocks we've actually mapped into kernel
1520 * virtual address space.
1522 if (*firstaddr < round_2mpage(KERNend))
1523 *firstaddr = round_2mpage(KERNend);
1525 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1526 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1527 for (i = 0; i < nkpdpe; i++)
1528 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1531 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1532 * the end of physical memory is not aligned to a 1GB page boundary,
1533 * then the residual physical memory is mapped with 2MB pages. Later,
1534 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1535 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1536 * that are partially used.
1538 pd_p = (pd_entry_t *)DMPDphys;
1539 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1540 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1541 /* Preset PG_M and PG_A because demotion expects it. */
1542 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1543 X86_PG_M | X86_PG_A | pg_nx;
1545 pdp_p = (pdp_entry_t *)DMPDPphys;
1546 for (i = 0; i < ndm1g; i++) {
1547 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1548 /* Preset PG_M and PG_A because demotion expects it. */
1549 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1550 X86_PG_M | X86_PG_A | pg_nx;
1552 for (j = 0; i < ndmpdp; i++, j++) {
1553 pdp_p[i] = DMPDphys + ptoa(j);
1554 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1558 * Instead of using a 1G page for the memory containing the kernel,
1559 * use 2M pages with read-only and no-execute permissions. (If using 1G
1560 * pages, this will partially overwrite the PDPEs above.)
1563 pd_p = (pd_entry_t *)DMPDkernphys;
1564 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1565 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1566 X86_PG_M | X86_PG_A | pg_nx |
1567 bootaddr_rwx(i << PDRSHIFT);
1568 for (i = 0; i < nkdmpde; i++)
1569 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1573 /* And recursively map PML4 to itself in order to get PTmap */
1574 p4_p = (pml4_entry_t *)KPML4phys;
1575 p4_p[PML4PML4I] = KPML4phys;
1576 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1578 /* Connect the Direct Map slot(s) up to the PML4. */
1579 for (i = 0; i < ndmpdpphys; i++) {
1580 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1581 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1584 /* Connect the KVA slots up to the PML4 */
1585 for (i = 0; i < NKPML4E; i++) {
1586 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1587 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1592 * Bootstrap the system enough to run with virtual memory.
1594 * On amd64 this is called after mapping has already been enabled
1595 * and just syncs the pmap module with what has already been done.
1596 * [We can't call it easily with mapping off since the kernel is not
1597 * mapped with PA == VA, hence we would have to relocate every address
1598 * from the linked base (virtual) address "KERNBASE" to the actual
1599 * (physical) address starting relative to 0]
1602 pmap_bootstrap(vm_paddr_t *firstaddr)
1605 pt_entry_t *pte, *pcpu_pte;
1606 uint64_t cr4, pcpu_phys;
1610 KERNend = *firstaddr;
1611 res = atop(KERNend - (vm_paddr_t)kernphys);
1617 * Create an initial set of page tables to run the kernel in.
1619 create_pagetables(firstaddr);
1621 pcpu_phys = allocpages(firstaddr, MAXCPU);
1624 * Add a physical memory segment (vm_phys_seg) corresponding to the
1625 * preallocated kernel page table pages so that vm_page structures
1626 * representing these pages will be created. The vm_page structures
1627 * are required for promotion of the corresponding kernel virtual
1628 * addresses to superpage mappings.
1630 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1633 * Account for the virtual addresses mapped by create_pagetables().
1635 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1636 virtual_end = VM_MAX_KERNEL_ADDRESS;
1639 * Enable PG_G global pages, then switch to the kernel page
1640 * table from the bootstrap page table. After the switch, it
1641 * is possible to enable SMEP and SMAP since PG_U bits are
1647 load_cr3(KPML4phys);
1648 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1650 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1655 * Initialize the kernel pmap (which is statically allocated).
1656 * Count bootstrap data as being resident in case any of this data is
1657 * later unmapped (using pmap_remove()) and freed.
1659 PMAP_LOCK_INIT(kernel_pmap);
1660 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1661 kernel_pmap->pm_cr3 = KPML4phys;
1662 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1663 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1664 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1665 kernel_pmap->pm_stats.resident_count = res;
1666 kernel_pmap->pm_flags = pmap_flags;
1669 * Initialize the TLB invalidations generation number lock.
1671 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1674 * Reserve some special page table entries/VA space for temporary
1677 #define SYSMAP(c, p, v, n) \
1678 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1684 * Crashdump maps. The first page is reused as CMAP1 for the
1687 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1688 CADDR1 = crashdumpmap;
1690 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1693 for (i = 0; i < MAXCPU; i++) {
1694 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1695 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1697 STAILQ_INIT(&cpuhead);
1698 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1699 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1700 amd64_bsp_pcpu_init1(&__pcpu[0]);
1701 amd64_bsp_ist_init(&__pcpu[0]);
1702 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1703 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1706 * Initialize the PAT MSR.
1707 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1708 * side-effect, invalidates stale PG_G TLB entries that might
1709 * have been created in our pre-boot environment.
1713 /* Initialize TLB Context Id. */
1714 if (pmap_pcid_enabled) {
1715 for (i = 0; i < MAXCPU; i++) {
1716 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1717 kernel_pmap->pm_pcids[i].pm_gen = 1;
1721 * PMAP_PCID_KERN + 1 is used for initialization of
1722 * proc0 pmap. The pmap' pcid state might be used by
1723 * EFIRT entry before first context switch, so it
1724 * needs to be valid.
1726 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1727 PCPU_SET(pcid_gen, 1);
1730 * pcpu area for APs is zeroed during AP startup.
1731 * pc_pcid_next and pc_pcid_gen are initialized by AP
1732 * during pcpu setup.
1734 load_cr4(rcr4() | CR4_PCIDE);
1739 * Setup the PAT MSR.
1748 /* Bail if this CPU doesn't implement PAT. */
1749 if ((cpu_feature & CPUID_PAT) == 0)
1752 /* Set default PAT index table. */
1753 for (i = 0; i < PAT_INDEX_SIZE; i++)
1755 pat_index[PAT_WRITE_BACK] = 0;
1756 pat_index[PAT_WRITE_THROUGH] = 1;
1757 pat_index[PAT_UNCACHEABLE] = 3;
1758 pat_index[PAT_WRITE_COMBINING] = 6;
1759 pat_index[PAT_WRITE_PROTECTED] = 5;
1760 pat_index[PAT_UNCACHED] = 2;
1763 * Initialize default PAT entries.
1764 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1765 * Program 5 and 6 as WP and WC.
1767 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1768 * mapping for a 2M page uses a PAT value with the bit 3 set due
1769 * to its overload with PG_PS.
1771 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1772 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1773 PAT_VALUE(2, PAT_UNCACHED) |
1774 PAT_VALUE(3, PAT_UNCACHEABLE) |
1775 PAT_VALUE(4, PAT_WRITE_BACK) |
1776 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1777 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1778 PAT_VALUE(7, PAT_UNCACHEABLE);
1782 load_cr4(cr4 & ~CR4_PGE);
1784 /* Disable caches (CD = 1, NW = 0). */
1786 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1788 /* Flushes caches and TLBs. */
1792 /* Update PAT and index table. */
1793 wrmsr(MSR_PAT, pat_msr);
1795 /* Flush caches and TLBs again. */
1799 /* Restore caches and PGE. */
1805 * Initialize a vm_page's machine-dependent fields.
1808 pmap_page_init(vm_page_t m)
1811 TAILQ_INIT(&m->md.pv_list);
1812 m->md.pat_mode = PAT_WRITE_BACK;
1815 static int pmap_allow_2m_x_ept;
1816 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1817 &pmap_allow_2m_x_ept, 0,
1818 "Allow executable superpage mappings in EPT");
1821 pmap_allow_2m_x_ept_recalculate(void)
1824 * SKL002, SKL012S. Since the EPT format is only used by
1825 * Intel CPUs, the vendor check is merely a formality.
1827 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1828 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1829 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1830 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1831 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1832 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1833 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1834 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1835 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1836 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1837 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1838 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1839 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1840 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1841 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1842 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1843 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1844 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1845 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1846 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1847 CPUID_TO_MODEL(cpu_id) == 0x85))))
1848 pmap_allow_2m_x_ept = 1;
1849 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1853 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1856 return (pmap->pm_type != PT_EPT || !executable ||
1857 !pmap_allow_2m_x_ept);
1861 * Initialize the pmap module.
1862 * Called by vm_init, to initialize any structures that the pmap
1863 * system needs to map virtual memory.
1868 struct pmap_preinit_mapping *ppim;
1871 int error, i, pv_npg, ret, skz63;
1873 /* L1TF, reserve page @0 unconditionally */
1874 vm_page_blacklist_add(0, bootverbose);
1876 /* Detect bare-metal Skylake Server and Skylake-X. */
1877 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1878 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1880 * Skylake-X errata SKZ63. Processor May Hang When
1881 * Executing Code In an HLE Transaction Region between
1882 * 40000000H and 403FFFFFH.
1884 * Mark the pages in the range as preallocated. It
1885 * seems to be impossible to distinguish between
1886 * Skylake Server and Skylake X.
1889 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1892 printf("SKZ63: skipping 4M RAM starting "
1893 "at physical 1G\n");
1894 for (i = 0; i < atop(0x400000); i++) {
1895 ret = vm_page_blacklist_add(0x40000000 +
1897 if (!ret && bootverbose)
1898 printf("page at %#lx already used\n",
1899 0x40000000 + ptoa(i));
1905 pmap_allow_2m_x_ept_recalculate();
1908 * Initialize the vm page array entries for the kernel pmap's
1911 PMAP_LOCK(kernel_pmap);
1912 for (i = 0; i < nkpt; i++) {
1913 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1914 KASSERT(mpte >= vm_page_array &&
1915 mpte < &vm_page_array[vm_page_array_size],
1916 ("pmap_init: page table page is out of range"));
1917 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1918 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1919 mpte->wire_count = 1;
1922 * Collect the page table pages that were replaced by a 2MB
1923 * page in create_pagetables(). They are zero filled.
1925 if (i << PDRSHIFT < KERNend &&
1926 pmap_insert_pt_page(kernel_pmap, mpte, false))
1927 panic("pmap_init: pmap_insert_pt_page failed");
1929 PMAP_UNLOCK(kernel_pmap);
1933 * If the kernel is running on a virtual machine, then it must assume
1934 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1935 * be prepared for the hypervisor changing the vendor and family that
1936 * are reported by CPUID. Consequently, the workaround for AMD Family
1937 * 10h Erratum 383 is enabled if the processor's feature set does not
1938 * include at least one feature that is only supported by older Intel
1939 * or newer AMD processors.
1941 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1942 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1943 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1945 workaround_erratum383 = 1;
1948 * Are large page mappings enabled?
1950 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1951 if (pg_ps_enabled) {
1952 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1953 ("pmap_init: can't assign to pagesizes[1]"));
1954 pagesizes[1] = NBPDR;
1958 * Initialize the pv chunk list mutex.
1960 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1963 * Initialize the pool of pv list locks.
1965 for (i = 0; i < NPV_LIST_LOCKS; i++)
1966 rw_init(&pv_list_locks[i], "pmap pv list");
1969 * Calculate the size of the pv head table for superpages.
1971 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1974 * Allocate memory for the pv head table for superpages.
1976 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1978 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1979 for (i = 0; i < pv_npg; i++)
1980 TAILQ_INIT(&pv_table[i].pv_list);
1981 TAILQ_INIT(&pv_dummy.pv_list);
1983 pmap_initialized = 1;
1984 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1985 ppim = pmap_preinit_mapping + i;
1988 /* Make the direct map consistent */
1989 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1990 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1991 ppim->sz, ppim->mode);
1995 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1996 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1999 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2000 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2001 (vmem_addr_t *)&qframe);
2003 panic("qframe allocation failed");
2006 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2007 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2008 lm_ents = LMEPML4I - LMSPML4I + 1;
2010 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
2011 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2013 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2014 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2015 if (large_vmem == NULL) {
2016 printf("pmap: cannot create large map\n");
2019 for (i = 0; i < lm_ents; i++) {
2020 m = pmap_large_map_getptp_unlocked();
2021 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
2022 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2028 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
2029 "2MB page mapping counters");
2031 static u_long pmap_pde_demotions;
2032 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2033 &pmap_pde_demotions, 0, "2MB page demotions");
2035 static u_long pmap_pde_mappings;
2036 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2037 &pmap_pde_mappings, 0, "2MB page mappings");
2039 static u_long pmap_pde_p_failures;
2040 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2041 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2043 static u_long pmap_pde_promotions;
2044 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2045 &pmap_pde_promotions, 0, "2MB page promotions");
2047 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
2048 "1GB page mapping counters");
2050 static u_long pmap_pdpe_demotions;
2051 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2052 &pmap_pdpe_demotions, 0, "1GB page demotions");
2054 /***************************************************
2055 * Low level helper routines.....
2056 ***************************************************/
2059 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2061 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2063 switch (pmap->pm_type) {
2066 /* Verify that both PAT bits are not set at the same time */
2067 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2068 ("Invalid PAT bits in entry %#lx", entry));
2070 /* Swap the PAT bits if one of them is set */
2071 if ((entry & x86_pat_bits) != 0)
2072 entry ^= x86_pat_bits;
2076 * Nothing to do - the memory attributes are represented
2077 * the same way for regular pages and superpages.
2081 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2088 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2091 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2092 pat_index[(int)mode] >= 0);
2096 * Determine the appropriate bits to set in a PTE or PDE for a specified
2100 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2102 int cache_bits, pat_flag, pat_idx;
2104 if (!pmap_is_valid_memattr(pmap, mode))
2105 panic("Unknown caching mode %d\n", mode);
2107 switch (pmap->pm_type) {
2110 /* The PAT bit is different for PTE's and PDE's. */
2111 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2113 /* Map the caching mode to a PAT index. */
2114 pat_idx = pat_index[mode];
2116 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2119 cache_bits |= pat_flag;
2121 cache_bits |= PG_NC_PCD;
2123 cache_bits |= PG_NC_PWT;
2127 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2131 panic("unsupported pmap type %d", pmap->pm_type);
2134 return (cache_bits);
2138 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2142 switch (pmap->pm_type) {
2145 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2148 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2151 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2158 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2160 int pat_flag, pat_idx;
2163 switch (pmap->pm_type) {
2166 /* The PAT bit is different for PTE's and PDE's. */
2167 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2169 if ((pte & pat_flag) != 0)
2171 if ((pte & PG_NC_PCD) != 0)
2173 if ((pte & PG_NC_PWT) != 0)
2177 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2178 panic("EPT PTE %#lx has no PAT memory type", pte);
2179 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2183 /* See pmap_init_pat(). */
2193 pmap_ps_enabled(pmap_t pmap)
2196 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2200 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2203 switch (pmap->pm_type) {
2210 * This is a little bogus since the generation number is
2211 * supposed to be bumped up when a region of the address
2212 * space is invalidated in the page tables.
2214 * In this case the old PDE entry is valid but yet we want
2215 * to make sure that any mappings using the old entry are
2216 * invalidated in the TLB.
2218 * The reason this works as expected is because we rendezvous
2219 * "all" host cpus and force any vcpu context to exit as a
2222 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2225 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2227 pde_store(pde, newpde);
2231 * After changing the page size for the specified virtual address in the page
2232 * table, flush the corresponding entries from the processor's TLB. Only the
2233 * calling processor's TLB is affected.
2235 * The calling thread must be pinned to a processor.
2238 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2242 if (pmap_type_guest(pmap))
2245 KASSERT(pmap->pm_type == PT_X86,
2246 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2248 PG_G = pmap_global_bit(pmap);
2250 if ((newpde & PG_PS) == 0)
2251 /* Demotion: flush a specific 2MB page mapping. */
2253 else if ((newpde & PG_G) == 0)
2255 * Promotion: flush every 4KB page mapping from the TLB
2256 * because there are too many to flush individually.
2261 * Promotion: flush every 4KB page mapping from the TLB,
2262 * including any global (PG_G) mappings.
2270 * For SMP, these functions have to use the IPI mechanism for coherence.
2272 * N.B.: Before calling any of the following TLB invalidation functions,
2273 * the calling processor must ensure that all stores updating a non-
2274 * kernel page table are globally performed. Otherwise, another
2275 * processor could cache an old, pre-update entry without being
2276 * invalidated. This can happen one of two ways: (1) The pmap becomes
2277 * active on another processor after its pm_active field is checked by
2278 * one of the following functions but before a store updating the page
2279 * table is globally performed. (2) The pmap becomes active on another
2280 * processor before its pm_active field is checked but due to
2281 * speculative loads one of the following functions stills reads the
2282 * pmap as inactive on the other processor.
2284 * The kernel page table is exempt because its pm_active field is
2285 * immutable. The kernel page table is always active on every
2290 * Interrupt the cpus that are executing in the guest context.
2291 * This will force the vcpu to exit and the cached EPT mappings
2292 * will be invalidated by the host before the next vmresume.
2294 static __inline void
2295 pmap_invalidate_ept(pmap_t pmap)
2300 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2301 ("pmap_invalidate_ept: absurd pm_active"));
2304 * The TLB mappings associated with a vcpu context are not
2305 * flushed each time a different vcpu is chosen to execute.
2307 * This is in contrast with a process's vtop mappings that
2308 * are flushed from the TLB on each context switch.
2310 * Therefore we need to do more than just a TLB shootdown on
2311 * the active cpus in 'pmap->pm_active'. To do this we keep
2312 * track of the number of invalidations performed on this pmap.
2314 * Each vcpu keeps a cache of this counter and compares it
2315 * just before a vmresume. If the counter is out-of-date an
2316 * invept will be done to flush stale mappings from the TLB.
2318 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2321 * Force the vcpu to exit and trap back into the hypervisor.
2323 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2324 ipi_selected(pmap->pm_active, ipinum);
2329 pmap_invalidate_cpu_mask(pmap_t pmap)
2331 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2335 pmap_invalidate_preipi_pcid(pmap_t pmap)
2341 cpuid = PCPU_GET(cpuid);
2342 if (pmap != PCPU_GET(curpmap))
2343 cpuid = 0xffffffff; /* An impossible value */
2347 pmap->pm_pcids[i].pm_gen = 0;
2351 * The fence is between stores to pm_gen and the read of the
2352 * pm_active mask. We need to ensure that it is impossible
2353 * for us to miss the bit update in pm_active and
2354 * simultaneously observe a non-zero pm_gen in
2355 * pmap_activate_sw(), otherwise TLB update is missed.
2356 * Without the fence, IA32 allows such an outcome. Note that
2357 * pm_active is updated by a locked operation, which provides
2358 * the reciprocal fence.
2360 atomic_thread_fence_seq_cst();
2364 pmap_invalidate_preipi_nopcid(pmap_t pmap __unused)
2369 DEFINE_IFUNC(static, void, pmap_invalidate_preipi, (pmap_t), static)
2371 return (pmap_pcid_enabled ? pmap_invalidate_preipi_pcid :
2372 pmap_invalidate_preipi_nopcid);
2376 pmap_invalidate_page_pcid_cb(pmap_t pmap, vm_offset_t va,
2377 const bool invpcid_works1)
2379 struct invpcid_descr d;
2380 uint64_t kcr3, ucr3;
2385 * Because pm_pcid is recalculated on a context switch, we
2386 * must ensure there is no preemption, not just pinning.
2387 * Otherwise, we might use a stale value below.
2389 CRITICAL_ASSERT(curthread);
2392 * No need to do anything with user page tables invalidation
2393 * if there is no user page table.
2395 if (pmap->pm_ucr3 == PMAP_NO_CR3)
2398 cpuid = PCPU_GET(cpuid);
2400 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2401 if (invpcid_works1) {
2402 d.pcid = pcid | PMAP_PCID_USER_PT;
2405 invpcid(&d, INVPCID_ADDR);
2407 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2408 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2409 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2414 pmap_invalidate_page_pcid_invpcid_cb(pmap_t pmap, vm_offset_t va)
2416 pmap_invalidate_page_pcid_cb(pmap, va, true);
2420 pmap_invalidate_page_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t va)
2422 pmap_invalidate_page_pcid_cb(pmap, va, false);
2426 pmap_invalidate_page_nopcid_cb(pmap_t pmap __unused, vm_offset_t va __unused)
2430 DEFINE_IFUNC(static, void, pmap_invalidate_page_cb, (pmap_t, vm_offset_t),
2433 if (pmap_pcid_enabled)
2434 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid_cb :
2435 pmap_invalidate_page_pcid_noinvpcid_cb);
2436 return (pmap_invalidate_page_nopcid_cb);
2440 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2441 vm_offset_t addr2 __unused)
2443 if (pmap == kernel_pmap) {
2445 } else if (pmap == PCPU_GET(curpmap)) {
2447 pmap_invalidate_page_cb(pmap, va);
2452 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2454 if (pmap_type_guest(pmap)) {
2455 pmap_invalidate_ept(pmap);
2459 KASSERT(pmap->pm_type == PT_X86,
2460 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2462 pmap_invalidate_preipi(pmap);
2463 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2464 pmap_invalidate_page_curcpu_cb);
2467 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2468 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2471 pmap_invalidate_range_pcid_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2472 const bool invpcid_works1)
2474 struct invpcid_descr d;
2475 uint64_t kcr3, ucr3;
2479 CRITICAL_ASSERT(curthread);
2481 if (pmap != PCPU_GET(curpmap) ||
2482 pmap->pm_ucr3 == PMAP_NO_CR3)
2485 cpuid = PCPU_GET(cpuid);
2487 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2488 if (invpcid_works1) {
2489 d.pcid = pcid | PMAP_PCID_USER_PT;
2491 for (d.addr = sva; d.addr < eva; d.addr += PAGE_SIZE)
2492 invpcid(&d, INVPCID_ADDR);
2494 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2495 ucr3 = pmap->pm_ucr3 | pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2496 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2501 pmap_invalidate_range_pcid_invpcid_cb(pmap_t pmap, vm_offset_t sva,
2504 pmap_invalidate_range_pcid_cb(pmap, sva, eva, true);
2508 pmap_invalidate_range_pcid_noinvpcid_cb(pmap_t pmap, vm_offset_t sva,
2511 pmap_invalidate_range_pcid_cb(pmap, sva, eva, false);
2515 pmap_invalidate_range_nopcid_cb(pmap_t pmap __unused, vm_offset_t sva __unused,
2516 vm_offset_t eva __unused)
2520 DEFINE_IFUNC(static, void, pmap_invalidate_range_cb, (pmap_t, vm_offset_t,
2521 vm_offset_t), static)
2523 if (pmap_pcid_enabled)
2524 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid_cb :
2525 pmap_invalidate_range_pcid_noinvpcid_cb);
2526 return (pmap_invalidate_range_nopcid_cb);
2530 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2534 if (pmap == kernel_pmap) {
2535 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2537 } else if (pmap == PCPU_GET(curpmap)) {
2538 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2540 pmap_invalidate_range_cb(pmap, sva, eva);
2545 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2547 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2548 pmap_invalidate_all(pmap);
2552 if (pmap_type_guest(pmap)) {
2553 pmap_invalidate_ept(pmap);
2557 KASSERT(pmap->pm_type == PT_X86,
2558 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2560 pmap_invalidate_preipi(pmap);
2561 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
2562 pmap_invalidate_range_curcpu_cb);
2566 pmap_invalidate_all_pcid_cb(pmap_t pmap, bool invpcid_works1)
2568 struct invpcid_descr d;
2569 uint64_t kcr3, ucr3;
2573 if (pmap == kernel_pmap) {
2574 if (invpcid_works1) {
2575 bzero(&d, sizeof(d));
2576 invpcid(&d, INVPCID_CTXGLOB);
2580 } else if (pmap == PCPU_GET(curpmap)) {
2581 CRITICAL_ASSERT(curthread);
2582 cpuid = PCPU_GET(cpuid);
2584 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2585 if (invpcid_works1) {
2589 invpcid(&d, INVPCID_CTX);
2590 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2591 d.pcid |= PMAP_PCID_USER_PT;
2592 invpcid(&d, INVPCID_CTX);
2595 kcr3 = pmap->pm_cr3 | pcid;
2596 ucr3 = pmap->pm_ucr3;
2597 if (ucr3 != PMAP_NO_CR3) {
2598 ucr3 |= pcid | PMAP_PCID_USER_PT;
2599 pmap_pti_pcid_invalidate(ucr3, kcr3);
2608 pmap_invalidate_all_pcid_invpcid_cb(pmap_t pmap)
2610 pmap_invalidate_all_pcid_cb(pmap, true);
2614 pmap_invalidate_all_pcid_noinvpcid_cb(pmap_t pmap)
2616 pmap_invalidate_all_pcid_cb(pmap, false);
2620 pmap_invalidate_all_nopcid_cb(pmap_t pmap)
2622 if (pmap == kernel_pmap)
2624 else if (pmap == PCPU_GET(curpmap))
2628 DEFINE_IFUNC(static, void, pmap_invalidate_all_cb, (pmap_t), static)
2630 if (pmap_pcid_enabled)
2631 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid_cb :
2632 pmap_invalidate_all_pcid_noinvpcid_cb);
2633 return (pmap_invalidate_all_nopcid_cb);
2637 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
2638 vm_offset_t addr2 __unused)
2640 pmap_invalidate_all_cb(pmap);
2644 pmap_invalidate_all(pmap_t pmap)
2646 if (pmap_type_guest(pmap)) {
2647 pmap_invalidate_ept(pmap);
2651 KASSERT(pmap->pm_type == PT_X86,
2652 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2654 pmap_invalidate_preipi(pmap);
2655 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
2656 pmap_invalidate_all_curcpu_cb);
2660 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
2661 vm_offset_t addr2 __unused)
2667 pmap_invalidate_cache(void)
2670 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
2674 cpuset_t invalidate; /* processors that invalidate their TLB */
2679 u_int store; /* processor that updates the PDE */
2683 pmap_update_pde_action(void *arg)
2685 struct pde_action *act = arg;
2687 if (act->store == PCPU_GET(cpuid))
2688 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2692 pmap_update_pde_teardown(void *arg)
2694 struct pde_action *act = arg;
2696 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2697 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2701 * Change the page size for the specified virtual address in a way that
2702 * prevents any possibility of the TLB ever having two entries that map the
2703 * same virtual address using different page sizes. This is the recommended
2704 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2705 * machine check exception for a TLB state that is improperly diagnosed as a
2709 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2711 struct pde_action act;
2712 cpuset_t active, other_cpus;
2716 cpuid = PCPU_GET(cpuid);
2717 other_cpus = all_cpus;
2718 CPU_CLR(cpuid, &other_cpus);
2719 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2722 active = pmap->pm_active;
2724 if (CPU_OVERLAP(&active, &other_cpus)) {
2726 act.invalidate = active;
2730 act.newpde = newpde;
2731 CPU_SET(cpuid, &active);
2732 smp_rendezvous_cpus(active,
2733 smp_no_rendezvous_barrier, pmap_update_pde_action,
2734 pmap_update_pde_teardown, &act);
2736 pmap_update_pde_store(pmap, pde, newpde);
2737 if (CPU_ISSET(cpuid, &active))
2738 pmap_update_pde_invalidate(pmap, va, newpde);
2744 * Normal, non-SMP, invalidation functions.
2747 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2749 struct invpcid_descr d;
2750 uint64_t kcr3, ucr3;
2753 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2757 KASSERT(pmap->pm_type == PT_X86,
2758 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2760 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2762 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2763 pmap->pm_ucr3 != PMAP_NO_CR3) {
2765 pcid = pmap->pm_pcids[0].pm_pcid;
2766 if (invpcid_works) {
2767 d.pcid = pcid | PMAP_PCID_USER_PT;
2770 invpcid(&d, INVPCID_ADDR);
2772 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2773 ucr3 = pmap->pm_ucr3 | pcid |
2774 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2775 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2779 } else if (pmap_pcid_enabled)
2780 pmap->pm_pcids[0].pm_gen = 0;
2784 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2786 struct invpcid_descr d;
2788 uint64_t kcr3, ucr3;
2790 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2794 KASSERT(pmap->pm_type == PT_X86,
2795 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2797 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2798 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2800 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2801 pmap->pm_ucr3 != PMAP_NO_CR3) {
2803 if (invpcid_works) {
2804 d.pcid = pmap->pm_pcids[0].pm_pcid |
2808 for (; d.addr < eva; d.addr += PAGE_SIZE)
2809 invpcid(&d, INVPCID_ADDR);
2811 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2812 pm_pcid | CR3_PCID_SAVE;
2813 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2814 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2815 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2819 } else if (pmap_pcid_enabled) {
2820 pmap->pm_pcids[0].pm_gen = 0;
2825 pmap_invalidate_all(pmap_t pmap)
2827 struct invpcid_descr d;
2828 uint64_t kcr3, ucr3;
2830 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2834 KASSERT(pmap->pm_type == PT_X86,
2835 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2837 if (pmap == kernel_pmap) {
2838 if (pmap_pcid_enabled && invpcid_works) {
2839 bzero(&d, sizeof(d));
2840 invpcid(&d, INVPCID_CTXGLOB);
2844 } else if (pmap == PCPU_GET(curpmap)) {
2845 if (pmap_pcid_enabled) {
2847 if (invpcid_works) {
2848 d.pcid = pmap->pm_pcids[0].pm_pcid;
2851 invpcid(&d, INVPCID_CTX);
2852 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2853 d.pcid |= PMAP_PCID_USER_PT;
2854 invpcid(&d, INVPCID_CTX);
2857 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2858 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2859 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2860 0].pm_pcid | PMAP_PCID_USER_PT;
2861 pmap_pti_pcid_invalidate(ucr3, kcr3);
2869 } else if (pmap_pcid_enabled) {
2870 pmap->pm_pcids[0].pm_gen = 0;
2875 pmap_invalidate_cache(void)
2882 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2885 pmap_update_pde_store(pmap, pde, newpde);
2886 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2887 pmap_update_pde_invalidate(pmap, va, newpde);
2889 pmap->pm_pcids[0].pm_gen = 0;
2894 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2898 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2899 * by a promotion that did not invalidate the 512 4KB page mappings
2900 * that might exist in the TLB. Consequently, at this point, the TLB
2901 * may hold both 4KB and 2MB page mappings for the address range [va,
2902 * va + NBPDR). Therefore, the entire range must be invalidated here.
2903 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2904 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2905 * single INVLPG suffices to invalidate the 2MB page mapping from the
2908 if ((pde & PG_PROMOTED) != 0)
2909 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2911 pmap_invalidate_page(pmap, va);
2914 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2915 (vm_offset_t sva, vm_offset_t eva), static)
2918 if ((cpu_feature & CPUID_SS) != 0)
2919 return (pmap_invalidate_cache_range_selfsnoop);
2920 if ((cpu_feature & CPUID_CLFSH) != 0)
2921 return (pmap_force_invalidate_cache_range);
2922 return (pmap_invalidate_cache_range_all);
2925 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2928 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2931 KASSERT((sva & PAGE_MASK) == 0,
2932 ("pmap_invalidate_cache_range: sva not page-aligned"));
2933 KASSERT((eva & PAGE_MASK) == 0,
2934 ("pmap_invalidate_cache_range: eva not page-aligned"));
2938 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2941 pmap_invalidate_cache_range_check_align(sva, eva);
2945 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2948 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2951 * XXX: Some CPUs fault, hang, or trash the local APIC
2952 * registers if we use CLFLUSH on the local APIC range. The
2953 * local APIC is always uncached, so we don't need to flush
2954 * for that range anyway.
2956 if (pmap_kextract(sva) == lapic_paddr)
2959 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2961 * Do per-cache line flush. Use a locked
2962 * instruction to insure that previous stores are
2963 * included in the write-back. The processor
2964 * propagates flush to other processors in the cache
2967 atomic_thread_fence_seq_cst();
2968 for (; sva < eva; sva += cpu_clflush_line_size)
2970 atomic_thread_fence_seq_cst();
2973 * Writes are ordered by CLFLUSH on Intel CPUs.
2975 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2977 for (; sva < eva; sva += cpu_clflush_line_size)
2979 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2985 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2988 pmap_invalidate_cache_range_check_align(sva, eva);
2989 pmap_invalidate_cache();
2993 * Remove the specified set of pages from the data and instruction caches.
2995 * In contrast to pmap_invalidate_cache_range(), this function does not
2996 * rely on the CPU's self-snoop feature, because it is intended for use
2997 * when moving pages into a different cache domain.
3000 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3002 vm_offset_t daddr, eva;
3006 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3007 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3008 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3009 pmap_invalidate_cache();
3012 atomic_thread_fence_seq_cst();
3013 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3015 for (i = 0; i < count; i++) {
3016 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3017 eva = daddr + PAGE_SIZE;
3018 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3026 atomic_thread_fence_seq_cst();
3027 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3033 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3036 pmap_invalidate_cache_range_check_align(sva, eva);
3038 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3039 pmap_force_invalidate_cache_range(sva, eva);
3043 /* See comment in pmap_force_invalidate_cache_range(). */
3044 if (pmap_kextract(sva) == lapic_paddr)
3047 atomic_thread_fence_seq_cst();
3048 for (; sva < eva; sva += cpu_clflush_line_size)
3050 atomic_thread_fence_seq_cst();
3054 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3058 int error, pte_bits;
3060 KASSERT((spa & PAGE_MASK) == 0,
3061 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3062 KASSERT((epa & PAGE_MASK) == 0,
3063 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3065 if (spa < dmaplimit) {
3066 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3068 if (dmaplimit >= epa)
3073 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3075 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3077 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3078 pte = vtopte(vaddr);
3079 for (; spa < epa; spa += PAGE_SIZE) {
3081 pte_store(pte, spa | pte_bits);
3083 /* XXXKIB atomic inside flush_cache_range are excessive */
3084 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3087 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3091 * Routine: pmap_extract
3093 * Extract the physical page address associated
3094 * with the given map/virtual_address pair.
3097 pmap_extract(pmap_t pmap, vm_offset_t va)
3101 pt_entry_t *pte, PG_V;
3105 PG_V = pmap_valid_bit(pmap);
3107 pdpe = pmap_pdpe(pmap, va);
3108 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3109 if ((*pdpe & PG_PS) != 0)
3110 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3112 pde = pmap_pdpe_to_pde(pdpe, va);
3113 if ((*pde & PG_V) != 0) {
3114 if ((*pde & PG_PS) != 0) {
3115 pa = (*pde & PG_PS_FRAME) |
3118 pte = pmap_pde_to_pte(pde, va);
3119 pa = (*pte & PG_FRAME) |
3130 * Routine: pmap_extract_and_hold
3132 * Atomically extract and hold the physical page
3133 * with the given pmap and virtual address pair
3134 * if that mapping permits the given protection.
3137 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3139 pd_entry_t pde, *pdep;
3140 pt_entry_t pte, PG_RW, PG_V;
3146 PG_RW = pmap_rw_bit(pmap);
3147 PG_V = pmap_valid_bit(pmap);
3150 pdep = pmap_pde(pmap, va);
3151 if (pdep != NULL && (pde = *pdep)) {
3153 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
3154 if (vm_page_pa_tryrelock(pmap, (pde &
3155 PG_PS_FRAME) | (va & PDRMASK), &pa))
3157 m = PHYS_TO_VM_PAGE(pa);
3160 pte = *pmap_pde_to_pte(pdep, va);
3162 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
3163 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
3166 m = PHYS_TO_VM_PAGE(pa);
3178 pmap_kextract(vm_offset_t va)
3183 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3184 pa = DMAP_TO_PHYS(va);
3185 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3186 pa = pmap_large_map_kextract(va);
3190 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3193 * Beware of a concurrent promotion that changes the
3194 * PDE at this point! For example, vtopte() must not
3195 * be used to access the PTE because it would use the
3196 * new PDE. It is, however, safe to use the old PDE
3197 * because the page table page is preserved by the
3200 pa = *pmap_pde_to_pte(&pde, va);
3201 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3207 /***************************************************
3208 * Low level mapping routines.....
3209 ***************************************************/
3212 * Add a wired page to the kva.
3213 * Note: not SMP coherent.
3216 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3221 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3224 static __inline void
3225 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3231 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3232 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3236 * Remove a page from the kernel pagetables.
3237 * Note: not SMP coherent.
3240 pmap_kremove(vm_offset_t va)
3249 * Used to map a range of physical addresses into kernel
3250 * virtual address space.
3252 * The value passed in '*virt' is a suggested virtual address for
3253 * the mapping. Architectures which can support a direct-mapped
3254 * physical to virtual region can return the appropriate address
3255 * within that region, leaving '*virt' unchanged. Other
3256 * architectures should map the pages starting at '*virt' and
3257 * update '*virt' with the first usable address after the mapped
3261 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3263 return PHYS_TO_DMAP(start);
3268 * Add a list of wired pages to the kva
3269 * this routine is only used for temporary
3270 * kernel mappings that do not need to have
3271 * page modification or references recorded.
3272 * Note that old mappings are simply written
3273 * over. The page *must* be wired.
3274 * Note: SMP coherent. Uses a ranged shootdown IPI.
3277 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3279 pt_entry_t *endpte, oldpte, pa, *pte;
3285 endpte = pte + count;
3286 while (pte < endpte) {
3288 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3289 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3290 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3292 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3296 if (__predict_false((oldpte & X86_PG_V) != 0))
3297 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3302 * This routine tears out page mappings from the
3303 * kernel -- it is meant only for temporary mappings.
3304 * Note: SMP coherent. Uses a ranged shootdown IPI.
3307 pmap_qremove(vm_offset_t sva, int count)
3312 while (count-- > 0) {
3313 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3317 pmap_invalidate_range(kernel_pmap, sva, va);
3320 /***************************************************
3321 * Page table page management routines.....
3322 ***************************************************/
3324 * Schedule the specified unused page table page to be freed. Specifically,
3325 * add the page to the specified list of pages that will be released to the
3326 * physical memory manager after the TLB has been updated.
3328 static __inline void
3329 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3330 boolean_t set_PG_ZERO)
3334 m->flags |= PG_ZERO;
3336 m->flags &= ~PG_ZERO;
3337 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3341 * Inserts the specified page table page into the specified pmap's collection
3342 * of idle page table pages. Each of a pmap's page table pages is responsible
3343 * for mapping a distinct range of virtual addresses. The pmap's collection is
3344 * ordered by this virtual address range.
3346 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3349 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3352 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3353 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3354 return (vm_radix_insert(&pmap->pm_root, mpte));
3358 * Removes the page table page mapping the specified virtual address from the
3359 * specified pmap's collection of idle page table pages, and returns it.
3360 * Otherwise, returns NULL if there is no page table page corresponding to the
3361 * specified virtual address.
3363 static __inline vm_page_t
3364 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3367 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3368 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3372 * Decrements a page table page's wire count, which is used to record the
3373 * number of valid page table entries within the page. If the wire count
3374 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3375 * page table page was unmapped and FALSE otherwise.
3377 static inline boolean_t
3378 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3382 if (m->wire_count == 0) {
3383 _pmap_unwire_ptp(pmap, va, m, free);
3390 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3393 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3395 * unmap the page table page
3397 if (m->pindex >= (NUPDE + NUPDPE)) {
3400 pml4 = pmap_pml4e(pmap, va);
3402 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3403 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3406 } else if (m->pindex >= NUPDE) {
3409 pdp = pmap_pdpe(pmap, va);
3414 pd = pmap_pde(pmap, va);
3417 pmap_resident_count_dec(pmap, 1);
3418 if (m->pindex < NUPDE) {
3419 /* We just released a PT, unhold the matching PD */
3422 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3423 pmap_unwire_ptp(pmap, va, pdpg, free);
3425 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3426 /* We just released a PD, unhold the matching PDP */
3429 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3430 pmap_unwire_ptp(pmap, va, pdppg, free);
3434 * Put page on a list so that it is released after
3435 * *ALL* TLB shootdown is done
3437 pmap_add_delayed_free_list(m, free, TRUE);
3441 * After removing a page table entry, this routine is used to
3442 * conditionally free the page, and manage the hold/wire counts.
3445 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3446 struct spglist *free)
3450 if (va >= VM_MAXUSER_ADDRESS)
3452 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3453 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3454 return (pmap_unwire_ptp(pmap, va, mpte, free));
3458 pmap_pinit0(pmap_t pmap)
3464 PMAP_LOCK_INIT(pmap);
3465 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3466 pmap->pm_pml4u = NULL;
3467 pmap->pm_cr3 = KPML4phys;
3468 /* hack to keep pmap_pti_pcid_invalidate() alive */
3469 pmap->pm_ucr3 = PMAP_NO_CR3;
3470 pmap->pm_root.rt_root = 0;
3471 CPU_ZERO(&pmap->pm_active);
3472 TAILQ_INIT(&pmap->pm_pvchunk);
3473 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3474 pmap->pm_flags = pmap_flags;
3476 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3477 pmap->pm_pcids[i].pm_gen = 1;
3479 pmap_activate_boot(pmap);
3484 p->p_amd64_md_flags |= P_MD_KPTI;
3487 pmap_thread_init_invl_gen(td);
3489 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3490 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3491 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3497 pmap_pinit_pml4(vm_page_t pml4pg)
3499 pml4_entry_t *pm_pml4;
3502 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3504 /* Wire in kernel global address entries. */
3505 for (i = 0; i < NKPML4E; i++) {
3506 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3509 for (i = 0; i < ndmpdpphys; i++) {
3510 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3514 /* install self-referential address mapping entry(s) */
3515 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3516 X86_PG_A | X86_PG_M;
3518 /* install large map entries if configured */
3519 for (i = 0; i < lm_ents; i++)
3520 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3524 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3526 pml4_entry_t *pm_pml4;
3529 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3530 for (i = 0; i < NPML4EPG; i++)
3531 pm_pml4[i] = pti_pml4[i];
3535 * Initialize a preallocated and zeroed pmap structure,
3536 * such as one in a vmspace structure.
3539 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3541 vm_page_t pml4pg, pml4pgu;
3542 vm_paddr_t pml4phys;
3546 * allocate the page directory page
3548 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3549 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3551 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3552 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3554 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3555 pmap->pm_pcids[i].pm_gen = 0;
3557 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3558 pmap->pm_ucr3 = PMAP_NO_CR3;
3559 pmap->pm_pml4u = NULL;
3561 pmap->pm_type = pm_type;
3562 if ((pml4pg->flags & PG_ZERO) == 0)
3563 pagezero(pmap->pm_pml4);
3566 * Do not install the host kernel mappings in the nested page
3567 * tables. These mappings are meaningless in the guest physical
3569 * Install minimal kernel mappings in PTI case.
3571 if (pm_type == PT_X86) {
3572 pmap->pm_cr3 = pml4phys;
3573 pmap_pinit_pml4(pml4pg);
3574 if ((curproc->p_amd64_md_flags & P_MD_KPTI) != 0) {
3575 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3576 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3577 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3578 VM_PAGE_TO_PHYS(pml4pgu));
3579 pmap_pinit_pml4_pti(pml4pgu);
3580 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3582 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3583 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3584 pkru_free_range, pmap, M_NOWAIT);
3588 pmap->pm_root.rt_root = 0;
3589 CPU_ZERO(&pmap->pm_active);
3590 TAILQ_INIT(&pmap->pm_pvchunk);
3591 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3592 pmap->pm_flags = flags;
3593 pmap->pm_eptgen = 0;
3599 pmap_pinit(pmap_t pmap)
3602 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3606 * This routine is called if the desired page table page does not exist.
3608 * If page table page allocation fails, this routine may sleep before
3609 * returning NULL. It sleeps only if a lock pointer was given.
3611 * Note: If a page allocation fails at page table level two or three,
3612 * one or two pages may be held during the wait, only to be released
3613 * afterwards. This conservative approach is easily argued to avoid
3616 * The ptepindexes, i.e. page indices, of the page table pages encountered
3617 * while translating virtual address va are defined as follows:
3618 * - for the page table page (last level),
3619 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
3620 * in other words, it is just the index of the PDE that maps the page
3622 * - for the page directory page,
3623 * ptepindex = NUPDE (number of userland PD entries) +
3624 * (pmap_pde_index(va) >> NPDEPGSHIFT)
3625 * i.e. index of PDPE is put after the last index of PDE,
3626 * - for the page directory pointer page,
3627 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
3629 * i.e. index of pml4e is put after the last index of PDPE.
3631 * Define an order on the paging entries, where all entries of the
3632 * same height are put together, then heights are put from deepest to
3633 * root. Then ptexpindex is the sequential number of the
3634 * corresponding paging entry in this order.
3636 * The root page at PML4 does not participate in this indexing scheme, since
3637 * it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
3640 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3642 vm_page_t m, pdppg, pdpg;
3643 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3645 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3647 PG_A = pmap_accessed_bit(pmap);
3648 PG_M = pmap_modified_bit(pmap);
3649 PG_V = pmap_valid_bit(pmap);
3650 PG_RW = pmap_rw_bit(pmap);
3653 * Allocate a page table page.
3655 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3656 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3657 if (lockp != NULL) {
3658 RELEASE_PV_LIST_LOCK(lockp);
3660 PMAP_ASSERT_NOT_IN_DI();
3666 * Indicate the need to retry. While waiting, the page table
3667 * page may have been allocated.
3671 if ((m->flags & PG_ZERO) == 0)
3675 * Map the pagetable page into the process address space, if
3676 * it isn't already there.
3679 if (ptepindex >= (NUPDE + NUPDPE)) {
3680 pml4_entry_t *pml4, *pml4u;
3681 vm_pindex_t pml4index;
3683 /* Wire up a new PDPE page */
3684 pml4index = ptepindex - (NUPDE + NUPDPE);
3685 pml4 = &pmap->pm_pml4[pml4index];
3686 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3687 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3689 * PTI: Make all user-space mappings in the
3690 * kernel-mode page table no-execute so that
3691 * we detect any programming errors that leave
3692 * the kernel-mode page table active on return
3695 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3698 pml4u = &pmap->pm_pml4u[pml4index];
3699 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3703 } else if (ptepindex >= NUPDE) {
3704 vm_pindex_t pml4index;
3705 vm_pindex_t pdpindex;
3709 /* Wire up a new PDE page */
3710 pdpindex = ptepindex - NUPDE;
3711 pml4index = pdpindex >> NPML4EPGSHIFT;
3713 pml4 = &pmap->pm_pml4[pml4index];
3714 if ((*pml4 & PG_V) == 0) {
3715 /* Have to allocate a new pdp, recurse */
3716 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3718 vm_page_unwire_noq(m);
3719 vm_page_free_zero(m);
3723 /* Add reference to pdp page */
3724 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3725 pdppg->wire_count++;
3727 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3729 /* Now find the pdp page */
3730 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3731 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3734 vm_pindex_t pml4index;
3735 vm_pindex_t pdpindex;
3740 /* Wire up a new PTE page */
3741 pdpindex = ptepindex >> NPDPEPGSHIFT;
3742 pml4index = pdpindex >> NPML4EPGSHIFT;
3744 /* First, find the pdp and check that its valid. */
3745 pml4 = &pmap->pm_pml4[pml4index];
3746 if ((*pml4 & PG_V) == 0) {
3747 /* Have to allocate a new pd, recurse */
3748 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3750 vm_page_unwire_noq(m);
3751 vm_page_free_zero(m);
3754 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3755 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3757 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3758 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3759 if ((*pdp & PG_V) == 0) {
3760 /* Have to allocate a new pd, recurse */
3761 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3763 vm_page_unwire_noq(m);
3764 vm_page_free_zero(m);
3768 /* Add reference to the pd page */
3769 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3773 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3775 /* Now we know where the page directory page is */
3776 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3777 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3780 pmap_resident_count_inc(pmap, 1);
3786 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3788 vm_pindex_t pdpindex, ptepindex;
3789 pdp_entry_t *pdpe, PG_V;
3792 PG_V = pmap_valid_bit(pmap);
3795 pdpe = pmap_pdpe(pmap, va);
3796 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3797 /* Add a reference to the pd page. */
3798 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3801 /* Allocate a pd page. */
3802 ptepindex = pmap_pde_pindex(va);
3803 pdpindex = ptepindex >> NPDPEPGSHIFT;
3804 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3805 if (pdpg == NULL && lockp != NULL)
3812 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3814 vm_pindex_t ptepindex;
3815 pd_entry_t *pd, PG_V;
3818 PG_V = pmap_valid_bit(pmap);
3821 * Calculate pagetable page index
3823 ptepindex = pmap_pde_pindex(va);
3826 * Get the page directory entry
3828 pd = pmap_pde(pmap, va);
3831 * This supports switching from a 2MB page to a
3834 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3835 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3837 * Invalidation of the 2MB page mapping may have caused
3838 * the deallocation of the underlying PD page.
3845 * If the page table page is mapped, we just increment the
3846 * hold count, and activate it.
3848 if (pd != NULL && (*pd & PG_V) != 0) {
3849 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3853 * Here if the pte page isn't mapped, or if it has been
3856 m = _pmap_allocpte(pmap, ptepindex, lockp);
3857 if (m == NULL && lockp != NULL)
3864 /***************************************************
3865 * Pmap allocation/deallocation routines.
3866 ***************************************************/
3869 * Release any resources held by the given physical map.
3870 * Called when a pmap initialized by pmap_pinit is being released.
3871 * Should only be called if the map contains no valid mappings.
3874 pmap_release(pmap_t pmap)
3879 KASSERT(pmap->pm_stats.resident_count == 0,
3880 ("pmap_release: pmap resident count %ld != 0",
3881 pmap->pm_stats.resident_count));
3882 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3883 ("pmap_release: pmap has reserved page table page(s)"));
3884 KASSERT(CPU_EMPTY(&pmap->pm_active),
3885 ("releasing active pmap %p", pmap));
3887 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3889 for (i = 0; i < NKPML4E; i++) /* KVA */
3890 pmap->pm_pml4[KPML4BASE + i] = 0;
3891 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3892 pmap->pm_pml4[DMPML4I + i] = 0;
3893 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3894 for (i = 0; i < lm_ents; i++) /* Large Map */
3895 pmap->pm_pml4[LMSPML4I + i] = 0;
3897 vm_page_unwire_noq(m);
3898 vm_page_free_zero(m);
3900 if (pmap->pm_pml4u != NULL) {
3901 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3902 vm_page_unwire_noq(m);
3905 if (pmap->pm_type == PT_X86 &&
3906 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3907 rangeset_fini(&pmap->pm_pkru);
3911 kvm_size(SYSCTL_HANDLER_ARGS)
3913 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3915 return sysctl_handle_long(oidp, &ksize, 0, req);
3917 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3918 0, 0, kvm_size, "LU", "Size of KVM");
3921 kvm_free(SYSCTL_HANDLER_ARGS)
3923 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3925 return sysctl_handle_long(oidp, &kfree, 0, req);
3927 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3928 0, 0, kvm_free, "LU", "Amount of KVM free");
3931 * grow the number of kernel page table entries, if needed
3934 pmap_growkernel(vm_offset_t addr)
3938 pd_entry_t *pde, newpdir;
3941 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3944 * Return if "addr" is within the range of kernel page table pages
3945 * that were preallocated during pmap bootstrap. Moreover, leave
3946 * "kernel_vm_end" and the kernel page table as they were.
3948 * The correctness of this action is based on the following
3949 * argument: vm_map_insert() allocates contiguous ranges of the
3950 * kernel virtual address space. It calls this function if a range
3951 * ends after "kernel_vm_end". If the kernel is mapped between
3952 * "kernel_vm_end" and "addr", then the range cannot begin at
3953 * "kernel_vm_end". In fact, its beginning address cannot be less
3954 * than the kernel. Thus, there is no immediate need to allocate
3955 * any new kernel page table pages between "kernel_vm_end" and
3958 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3961 addr = roundup2(addr, NBPDR);
3962 if (addr - 1 >= vm_map_max(kernel_map))
3963 addr = vm_map_max(kernel_map);
3964 while (kernel_vm_end < addr) {
3965 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3966 if ((*pdpe & X86_PG_V) == 0) {
3967 /* We need a new PDP entry */
3968 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3969 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3970 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3972 panic("pmap_growkernel: no memory to grow kernel");
3973 if ((nkpg->flags & PG_ZERO) == 0)
3974 pmap_zero_page(nkpg);
3975 paddr = VM_PAGE_TO_PHYS(nkpg);
3976 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3977 X86_PG_A | X86_PG_M);
3978 continue; /* try again */
3980 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3981 if ((*pde & X86_PG_V) != 0) {
3982 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3983 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3984 kernel_vm_end = vm_map_max(kernel_map);
3990 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3991 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3994 panic("pmap_growkernel: no memory to grow kernel");
3995 if ((nkpg->flags & PG_ZERO) == 0)
3996 pmap_zero_page(nkpg);
3997 paddr = VM_PAGE_TO_PHYS(nkpg);
3998 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3999 pde_store(pde, newpdir);
4001 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4002 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4003 kernel_vm_end = vm_map_max(kernel_map);
4010 /***************************************************
4011 * page management routines.
4012 ***************************************************/
4014 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4015 CTASSERT(_NPCM == 3);
4016 CTASSERT(_NPCPV == 168);
4018 static __inline struct pv_chunk *
4019 pv_to_chunk(pv_entry_t pv)
4022 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4025 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4027 #define PC_FREE0 0xfffffffffffffffful
4028 #define PC_FREE1 0xfffffffffffffffful
4029 #define PC_FREE2 0x000000fffffffffful
4031 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4034 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4036 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4037 "Current number of pv entry chunks");
4038 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4039 "Current number of pv entry chunks allocated");
4040 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4041 "Current number of pv entry chunks frees");
4042 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4043 "Number of times tried to get a chunk page but failed.");
4045 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4046 static int pv_entry_spare;
4048 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4049 "Current number of pv entry frees");
4050 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4051 "Current number of pv entry allocs");
4052 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4053 "Current number of pv entries");
4054 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4055 "Current number of spare pv entries");
4059 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4064 pmap_invalidate_all(pmap);
4065 if (pmap != locked_pmap)
4068 pmap_delayed_invl_finish();
4072 * We are in a serious low memory condition. Resort to
4073 * drastic measures to free some pages so we can allocate
4074 * another pv entry chunk.
4076 * Returns NULL if PV entries were reclaimed from the specified pmap.
4078 * We do not, however, unmap 2mpages because subsequent accesses will
4079 * allocate per-page pv entries until repromotion occurs, thereby
4080 * exacerbating the shortage of free pv entries.
4083 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4085 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4086 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4087 struct md_page *pvh;
4089 pmap_t next_pmap, pmap;
4090 pt_entry_t *pte, tpte;
4091 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4095 struct spglist free;
4097 int bit, field, freed;
4099 static int active_reclaims = 0;
4101 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4102 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4105 PG_G = PG_A = PG_M = PG_RW = 0;
4107 bzero(&pc_marker_b, sizeof(pc_marker_b));
4108 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4109 pc_marker = (struct pv_chunk *)&pc_marker_b;
4110 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4113 * A delayed invalidation block should already be active if
4114 * pmap_advise() or pmap_remove() called this function by way
4115 * of pmap_demote_pde_locked().
4117 start_di = pmap_not_in_di();
4119 mtx_lock(&pv_chunks_mutex);
4121 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
4122 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
4123 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4124 SLIST_EMPTY(&free)) {
4125 next_pmap = pc->pc_pmap;
4126 if (next_pmap == NULL) {
4128 * The next chunk is a marker. However, it is
4129 * not our marker, so active_reclaims must be
4130 * > 1. Consequently, the next_chunk code
4131 * will not rotate the pv_chunks list.
4135 mtx_unlock(&pv_chunks_mutex);
4138 * A pv_chunk can only be removed from the pc_lru list
4139 * when both pc_chunks_mutex is owned and the
4140 * corresponding pmap is locked.
4142 if (pmap != next_pmap) {
4143 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4146 /* Avoid deadlock and lock recursion. */
4147 if (pmap > locked_pmap) {
4148 RELEASE_PV_LIST_LOCK(lockp);
4151 pmap_delayed_invl_start();
4152 mtx_lock(&pv_chunks_mutex);
4154 } else if (pmap != locked_pmap) {
4155 if (PMAP_TRYLOCK(pmap)) {
4157 pmap_delayed_invl_start();
4158 mtx_lock(&pv_chunks_mutex);
4161 pmap = NULL; /* pmap is not locked */
4162 mtx_lock(&pv_chunks_mutex);
4163 pc = TAILQ_NEXT(pc_marker, pc_lru);
4165 pc->pc_pmap != next_pmap)
4169 } else if (start_di)
4170 pmap_delayed_invl_start();
4171 PG_G = pmap_global_bit(pmap);
4172 PG_A = pmap_accessed_bit(pmap);
4173 PG_M = pmap_modified_bit(pmap);
4174 PG_RW = pmap_rw_bit(pmap);
4178 * Destroy every non-wired, 4 KB page mapping in the chunk.
4181 for (field = 0; field < _NPCM; field++) {
4182 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4183 inuse != 0; inuse &= ~(1UL << bit)) {
4185 pv = &pc->pc_pventry[field * 64 + bit];
4187 pde = pmap_pde(pmap, va);
4188 if ((*pde & PG_PS) != 0)
4190 pte = pmap_pde_to_pte(pde, va);
4191 if ((*pte & PG_W) != 0)
4193 tpte = pte_load_clear(pte);
4194 if ((tpte & PG_G) != 0)
4195 pmap_invalidate_page(pmap, va);
4196 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4197 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4199 if ((tpte & PG_A) != 0)
4200 vm_page_aflag_set(m, PGA_REFERENCED);
4201 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4202 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4204 if (TAILQ_EMPTY(&m->md.pv_list) &&
4205 (m->flags & PG_FICTITIOUS) == 0) {
4206 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4207 if (TAILQ_EMPTY(&pvh->pv_list)) {
4208 vm_page_aflag_clear(m,
4212 pmap_delayed_invl_page(m);
4213 pc->pc_map[field] |= 1UL << bit;
4214 pmap_unuse_pt(pmap, va, *pde, &free);
4219 mtx_lock(&pv_chunks_mutex);
4222 /* Every freed mapping is for a 4 KB page. */
4223 pmap_resident_count_dec(pmap, freed);
4224 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4225 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4226 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4227 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4228 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4229 pc->pc_map[2] == PC_FREE2) {
4230 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4231 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4232 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4233 /* Entire chunk is free; return it. */
4234 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4235 dump_drop_page(m_pc->phys_addr);
4236 mtx_lock(&pv_chunks_mutex);
4237 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4240 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4241 mtx_lock(&pv_chunks_mutex);
4242 /* One freed pv entry in locked_pmap is sufficient. */
4243 if (pmap == locked_pmap)
4246 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4247 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
4248 if (active_reclaims == 1 && pmap != NULL) {
4250 * Rotate the pv chunks list so that we do not
4251 * scan the same pv chunks that could not be
4252 * freed (because they contained a wired
4253 * and/or superpage mapping) on every
4254 * invocation of reclaim_pv_chunk().
4256 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4257 MPASS(pc->pc_pmap != NULL);
4258 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4259 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4263 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4264 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4266 mtx_unlock(&pv_chunks_mutex);
4267 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4268 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4269 m_pc = SLIST_FIRST(&free);
4270 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4271 /* Recycle a freed page table page. */
4272 m_pc->wire_count = 1;
4274 vm_page_free_pages_toq(&free, true);
4279 * free the pv_entry back to the free list
4282 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4284 struct pv_chunk *pc;
4285 int idx, field, bit;
4287 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4288 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4289 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4290 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4291 pc = pv_to_chunk(pv);
4292 idx = pv - &pc->pc_pventry[0];
4295 pc->pc_map[field] |= 1ul << bit;
4296 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4297 pc->pc_map[2] != PC_FREE2) {
4298 /* 98% of the time, pc is already at the head of the list. */
4299 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4300 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4301 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4305 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4310 free_pv_chunk_dequeued(struct pv_chunk *pc)
4314 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4315 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4316 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4317 /* entire chunk is free, return it */
4318 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4319 dump_drop_page(m->phys_addr);
4320 vm_page_unwire_noq(m);
4325 free_pv_chunk(struct pv_chunk *pc)
4328 mtx_lock(&pv_chunks_mutex);
4329 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4330 mtx_unlock(&pv_chunks_mutex);
4331 free_pv_chunk_dequeued(pc);
4335 free_pv_chunk_batch(struct pv_chunklist *batch)
4337 struct pv_chunk *pc, *npc;
4339 if (TAILQ_EMPTY(batch))
4342 mtx_lock(&pv_chunks_mutex);
4343 TAILQ_FOREACH(pc, batch, pc_list) {
4344 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4346 mtx_unlock(&pv_chunks_mutex);
4348 TAILQ_FOREACH_SAFE(pc, batch, pc_list, npc) {
4349 free_pv_chunk_dequeued(pc);
4354 * Returns a new PV entry, allocating a new PV chunk from the system when
4355 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4356 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4359 * The given PV list lock may be released.
4362 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4366 struct pv_chunk *pc;
4369 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4370 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4372 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4374 for (field = 0; field < _NPCM; field++) {
4375 if (pc->pc_map[field]) {
4376 bit = bsfq(pc->pc_map[field]);
4380 if (field < _NPCM) {
4381 pv = &pc->pc_pventry[field * 64 + bit];
4382 pc->pc_map[field] &= ~(1ul << bit);
4383 /* If this was the last item, move it to tail */
4384 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4385 pc->pc_map[2] == 0) {
4386 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4387 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4390 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4391 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4395 /* No free items, allocate another chunk */
4396 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4399 if (lockp == NULL) {
4400 PV_STAT(pc_chunk_tryfail++);
4403 m = reclaim_pv_chunk(pmap, lockp);
4407 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4408 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4409 dump_add_page(m->phys_addr);
4410 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4412 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4413 pc->pc_map[1] = PC_FREE1;
4414 pc->pc_map[2] = PC_FREE2;
4415 mtx_lock(&pv_chunks_mutex);
4416 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4417 mtx_unlock(&pv_chunks_mutex);
4418 pv = &pc->pc_pventry[0];
4419 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4420 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4421 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4426 * Returns the number of one bits within the given PV chunk map.
4428 * The erratas for Intel processors state that "POPCNT Instruction May
4429 * Take Longer to Execute Than Expected". It is believed that the
4430 * issue is the spurious dependency on the destination register.
4431 * Provide a hint to the register rename logic that the destination
4432 * value is overwritten, by clearing it, as suggested in the
4433 * optimization manual. It should be cheap for unaffected processors
4436 * Reference numbers for erratas are
4437 * 4th Gen Core: HSD146
4438 * 5th Gen Core: BDM85
4439 * 6th Gen Core: SKL029
4442 popcnt_pc_map_pq(uint64_t *map)
4446 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4447 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4448 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4449 : "=&r" (result), "=&r" (tmp)
4450 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4455 * Ensure that the number of spare PV entries in the specified pmap meets or
4456 * exceeds the given count, "needed".
4458 * The given PV list lock may be released.
4461 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4463 struct pch new_tail;
4464 struct pv_chunk *pc;
4469 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4470 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4473 * Newly allocated PV chunks must be stored in a private list until
4474 * the required number of PV chunks have been allocated. Otherwise,
4475 * reclaim_pv_chunk() could recycle one of these chunks. In
4476 * contrast, these chunks must be added to the pmap upon allocation.
4478 TAILQ_INIT(&new_tail);
4481 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4483 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4484 bit_count((bitstr_t *)pc->pc_map, 0,
4485 sizeof(pc->pc_map) * NBBY, &free);
4488 free = popcnt_pc_map_pq(pc->pc_map);
4492 if (avail >= needed)
4495 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4496 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4499 m = reclaim_pv_chunk(pmap, lockp);
4504 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4505 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4506 dump_add_page(m->phys_addr);
4507 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4509 pc->pc_map[0] = PC_FREE0;
4510 pc->pc_map[1] = PC_FREE1;
4511 pc->pc_map[2] = PC_FREE2;
4512 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4513 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4514 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4517 * The reclaim might have freed a chunk from the current pmap.
4518 * If that chunk contained available entries, we need to
4519 * re-count the number of available entries.
4524 if (!TAILQ_EMPTY(&new_tail)) {
4525 mtx_lock(&pv_chunks_mutex);
4526 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4527 mtx_unlock(&pv_chunks_mutex);
4532 * First find and then remove the pv entry for the specified pmap and virtual
4533 * address from the specified pv list. Returns the pv entry if found and NULL
4534 * otherwise. This operation can be performed on pv lists for either 4KB or
4535 * 2MB page mappings.
4537 static __inline pv_entry_t
4538 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4542 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4543 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4544 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4553 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4554 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4555 * entries for each of the 4KB page mappings.
4558 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4559 struct rwlock **lockp)
4561 struct md_page *pvh;
4562 struct pv_chunk *pc;
4564 vm_offset_t va_last;
4568 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4569 KASSERT((pa & PDRMASK) == 0,
4570 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4571 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4574 * Transfer the 2mpage's pv entry for this mapping to the first
4575 * page's pv list. Once this transfer begins, the pv list lock
4576 * must not be released until the last pv entry is reinstantiated.
4578 pvh = pa_to_pvh(pa);
4579 va = trunc_2mpage(va);
4580 pv = pmap_pvh_remove(pvh, pmap, va);
4581 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4582 m = PHYS_TO_VM_PAGE(pa);
4583 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4585 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4586 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4587 va_last = va + NBPDR - PAGE_SIZE;
4589 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4590 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4591 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4592 for (field = 0; field < _NPCM; field++) {
4593 while (pc->pc_map[field]) {
4594 bit = bsfq(pc->pc_map[field]);
4595 pc->pc_map[field] &= ~(1ul << bit);
4596 pv = &pc->pc_pventry[field * 64 + bit];
4600 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4601 ("pmap_pv_demote_pde: page %p is not managed", m));
4602 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4608 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4609 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4612 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4613 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4614 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4616 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4617 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4620 #if VM_NRESERVLEVEL > 0
4622 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4623 * replace the many pv entries for the 4KB page mappings by a single pv entry
4624 * for the 2MB page mapping.
4627 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4628 struct rwlock **lockp)
4630 struct md_page *pvh;
4632 vm_offset_t va_last;
4635 KASSERT((pa & PDRMASK) == 0,
4636 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4637 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4640 * Transfer the first page's pv entry for this mapping to the 2mpage's
4641 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4642 * a transfer avoids the possibility that get_pv_entry() calls
4643 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4644 * mappings that is being promoted.
4646 m = PHYS_TO_VM_PAGE(pa);
4647 va = trunc_2mpage(va);
4648 pv = pmap_pvh_remove(&m->md, pmap, va);
4649 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4650 pvh = pa_to_pvh(pa);
4651 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4653 /* Free the remaining NPTEPG - 1 pv entries. */
4654 va_last = va + NBPDR - PAGE_SIZE;
4658 pmap_pvh_free(&m->md, pmap, va);
4659 } while (va < va_last);
4661 #endif /* VM_NRESERVLEVEL > 0 */
4664 * First find and then destroy the pv entry for the specified pmap and virtual
4665 * address. This operation can be performed on pv lists for either 4KB or 2MB
4669 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4673 pv = pmap_pvh_remove(pvh, pmap, va);
4674 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4675 free_pv_entry(pmap, pv);
4679 * Conditionally create the PV entry for a 4KB page mapping if the required
4680 * memory can be allocated without resorting to reclamation.
4683 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4684 struct rwlock **lockp)
4688 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4689 /* Pass NULL instead of the lock pointer to disable reclamation. */
4690 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4692 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4693 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4701 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4702 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4703 * false if the PV entry cannot be allocated without resorting to reclamation.
4706 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4707 struct rwlock **lockp)
4709 struct md_page *pvh;
4713 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4714 /* Pass NULL instead of the lock pointer to disable reclamation. */
4715 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4716 NULL : lockp)) == NULL)
4719 pa = pde & PG_PS_FRAME;
4720 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4721 pvh = pa_to_pvh(pa);
4722 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4728 * Fills a page table page with mappings to consecutive physical pages.
4731 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4735 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4737 newpte += PAGE_SIZE;
4742 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4743 * mapping is invalidated.
4746 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4748 struct rwlock *lock;
4752 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4759 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4763 pt_entry_t *xpte, *ypte;
4765 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4766 xpte++, newpte += PAGE_SIZE) {
4767 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4768 printf("pmap_demote_pde: xpte %zd and newpte map "
4769 "different pages: found %#lx, expected %#lx\n",
4770 xpte - firstpte, *xpte, newpte);
4771 printf("page table dump\n");
4772 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4773 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4778 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4779 ("pmap_demote_pde: firstpte and newpte map different physical"
4786 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4787 pd_entry_t oldpde, struct rwlock **lockp)
4789 struct spglist free;
4793 sva = trunc_2mpage(va);
4794 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4795 if ((oldpde & pmap_global_bit(pmap)) == 0)
4796 pmap_invalidate_pde_page(pmap, sva, oldpde);
4797 vm_page_free_pages_toq(&free, true);
4798 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
4803 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4804 struct rwlock **lockp)
4806 pd_entry_t newpde, oldpde;
4807 pt_entry_t *firstpte, newpte;
4808 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4814 PG_A = pmap_accessed_bit(pmap);
4815 PG_G = pmap_global_bit(pmap);
4816 PG_M = pmap_modified_bit(pmap);
4817 PG_RW = pmap_rw_bit(pmap);
4818 PG_V = pmap_valid_bit(pmap);
4819 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4820 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4822 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4823 in_kernel = va >= VM_MAXUSER_ADDRESS;
4825 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4826 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4829 * Invalidate the 2MB page mapping and return "failure" if the
4830 * mapping was never accessed.
4832 if ((oldpde & PG_A) == 0) {
4833 KASSERT((oldpde & PG_W) == 0,
4834 ("pmap_demote_pde: a wired mapping is missing PG_A"));
4835 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4839 mpte = pmap_remove_pt_page(pmap, va);
4841 KASSERT((oldpde & PG_W) == 0,
4842 ("pmap_demote_pde: page table page for a wired mapping"
4846 * If the page table page is missing and the mapping
4847 * is for a kernel address, the mapping must belong to
4848 * the direct map. Page table pages are preallocated
4849 * for every other part of the kernel address space,
4850 * so the direct map region is the only part of the
4851 * kernel address space that must be handled here.
4853 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
4854 va < DMAP_MAX_ADDRESS),
4855 ("pmap_demote_pde: No saved mpte for va %#lx", va));
4858 * If the 2MB page mapping belongs to the direct map
4859 * region of the kernel's address space, then the page
4860 * allocation request specifies the highest possible
4861 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
4862 * priority is normal.
4864 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
4865 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4866 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4869 * If the allocation of the new page table page fails,
4870 * invalidate the 2MB page mapping and return "failure".
4873 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4878 mpte->wire_count = NPTEPG;
4879 pmap_resident_count_inc(pmap, 1);
4882 mptepa = VM_PAGE_TO_PHYS(mpte);
4883 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4884 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4885 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4886 ("pmap_demote_pde: oldpde is missing PG_M"));
4887 newpte = oldpde & ~PG_PS;
4888 newpte = pmap_swap_pat(pmap, newpte);
4891 * If the page table page is not leftover from an earlier promotion,
4894 if (mpte->valid == 0)
4895 pmap_fill_ptp(firstpte, newpte);
4897 pmap_demote_pde_check(firstpte, newpte);
4900 * If the mapping has changed attributes, update the page table
4903 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4904 pmap_fill_ptp(firstpte, newpte);
4907 * The spare PV entries must be reserved prior to demoting the
4908 * mapping, that is, prior to changing the PDE. Otherwise, the state
4909 * of the PDE and the PV lists will be inconsistent, which can result
4910 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4911 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4912 * PV entry for the 2MB page mapping that is being demoted.
4914 if ((oldpde & PG_MANAGED) != 0)
4915 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4918 * Demote the mapping. This pmap is locked. The old PDE has
4919 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4920 * set. Thus, there is no danger of a race with another
4921 * processor changing the setting of PG_A and/or PG_M between
4922 * the read above and the store below.
4924 if (workaround_erratum383)
4925 pmap_update_pde(pmap, va, pde, newpde);
4927 pde_store(pde, newpde);
4930 * Invalidate a stale recursive mapping of the page table page.
4933 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4936 * Demote the PV entry.
4938 if ((oldpde & PG_MANAGED) != 0)
4939 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4941 atomic_add_long(&pmap_pde_demotions, 1);
4942 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
4948 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4951 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4957 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4958 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4959 mpte = pmap_remove_pt_page(pmap, va);
4961 panic("pmap_remove_kernel_pde: Missing pt page.");
4963 mptepa = VM_PAGE_TO_PHYS(mpte);
4964 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4967 * If this page table page was unmapped by a promotion, then it
4968 * contains valid mappings. Zero it to invalidate those mappings.
4970 if (mpte->valid != 0)
4971 pagezero((void *)PHYS_TO_DMAP(mptepa));
4974 * Demote the mapping.
4976 if (workaround_erratum383)
4977 pmap_update_pde(pmap, va, pde, newpde);
4979 pde_store(pde, newpde);
4982 * Invalidate a stale recursive mapping of the page table page.
4984 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4988 * pmap_remove_pde: do the things to unmap a superpage in a process
4991 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4992 struct spglist *free, struct rwlock **lockp)
4994 struct md_page *pvh;
4996 vm_offset_t eva, va;
4998 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5000 PG_G = pmap_global_bit(pmap);
5001 PG_A = pmap_accessed_bit(pmap);
5002 PG_M = pmap_modified_bit(pmap);
5003 PG_RW = pmap_rw_bit(pmap);
5005 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5006 KASSERT((sva & PDRMASK) == 0,
5007 ("pmap_remove_pde: sva is not 2mpage aligned"));
5008 oldpde = pte_load_clear(pdq);
5010 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5011 if ((oldpde & PG_G) != 0)
5012 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5013 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5014 if (oldpde & PG_MANAGED) {
5015 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5016 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5017 pmap_pvh_free(pvh, pmap, sva);
5019 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5020 va < eva; va += PAGE_SIZE, m++) {
5021 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5024 vm_page_aflag_set(m, PGA_REFERENCED);
5025 if (TAILQ_EMPTY(&m->md.pv_list) &&
5026 TAILQ_EMPTY(&pvh->pv_list))
5027 vm_page_aflag_clear(m, PGA_WRITEABLE);
5028 pmap_delayed_invl_page(m);
5031 if (pmap == kernel_pmap) {
5032 pmap_remove_kernel_pde(pmap, pdq, sva);
5034 mpte = pmap_remove_pt_page(pmap, sva);
5036 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5037 ("pmap_remove_pde: pte page not promoted"));
5038 pmap_resident_count_dec(pmap, 1);
5039 KASSERT(mpte->wire_count == NPTEPG,
5040 ("pmap_remove_pde: pte page wire count error"));
5041 mpte->wire_count = 0;
5042 pmap_add_delayed_free_list(mpte, free, FALSE);
5045 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5049 * pmap_remove_pte: do the things to unmap a page in a process
5052 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5053 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5055 struct md_page *pvh;
5056 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5059 PG_A = pmap_accessed_bit(pmap);
5060 PG_M = pmap_modified_bit(pmap);
5061 PG_RW = pmap_rw_bit(pmap);
5063 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5064 oldpte = pte_load_clear(ptq);
5066 pmap->pm_stats.wired_count -= 1;
5067 pmap_resident_count_dec(pmap, 1);
5068 if (oldpte & PG_MANAGED) {
5069 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5070 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5073 vm_page_aflag_set(m, PGA_REFERENCED);
5074 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5075 pmap_pvh_free(&m->md, pmap, va);
5076 if (TAILQ_EMPTY(&m->md.pv_list) &&
5077 (m->flags & PG_FICTITIOUS) == 0) {
5078 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5079 if (TAILQ_EMPTY(&pvh->pv_list))
5080 vm_page_aflag_clear(m, PGA_WRITEABLE);
5082 pmap_delayed_invl_page(m);
5084 return (pmap_unuse_pt(pmap, va, ptepde, free));
5088 * Remove a single page from a process address space
5091 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5092 struct spglist *free)
5094 struct rwlock *lock;
5095 pt_entry_t *pte, PG_V;
5097 PG_V = pmap_valid_bit(pmap);
5098 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5099 if ((*pde & PG_V) == 0)
5101 pte = pmap_pde_to_pte(pde, va);
5102 if ((*pte & PG_V) == 0)
5105 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5108 pmap_invalidate_page(pmap, va);
5112 * Removes the specified range of addresses from the page table page.
5115 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5116 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5118 pt_entry_t PG_G, *pte;
5122 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5123 PG_G = pmap_global_bit(pmap);
5126 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5130 pmap_invalidate_range(pmap, va, sva);
5135 if ((*pte & PG_G) == 0)
5139 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5145 pmap_invalidate_range(pmap, va, sva);
5150 * Remove the given range of addresses from the specified map.
5152 * It is assumed that the start and end are properly
5153 * rounded to the page size.
5156 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5158 struct rwlock *lock;
5159 vm_offset_t va_next;
5160 pml4_entry_t *pml4e;
5162 pd_entry_t ptpaddr, *pde;
5163 pt_entry_t PG_G, PG_V;
5164 struct spglist free;
5167 PG_G = pmap_global_bit(pmap);
5168 PG_V = pmap_valid_bit(pmap);
5171 * Perform an unsynchronized read. This is, however, safe.
5173 if (pmap->pm_stats.resident_count == 0)
5179 pmap_delayed_invl_start();
5181 pmap_pkru_on_remove(pmap, sva, eva);
5184 * special handling of removing one page. a very
5185 * common operation and easy to short circuit some
5188 if (sva + PAGE_SIZE == eva) {
5189 pde = pmap_pde(pmap, sva);
5190 if (pde && (*pde & PG_PS) == 0) {
5191 pmap_remove_page(pmap, sva, pde, &free);
5197 for (; sva < eva; sva = va_next) {
5199 if (pmap->pm_stats.resident_count == 0)
5202 pml4e = pmap_pml4e(pmap, sva);
5203 if ((*pml4e & PG_V) == 0) {
5204 va_next = (sva + NBPML4) & ~PML4MASK;
5210 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5211 if ((*pdpe & PG_V) == 0) {
5212 va_next = (sva + NBPDP) & ~PDPMASK;
5219 * Calculate index for next page table.
5221 va_next = (sva + NBPDR) & ~PDRMASK;
5225 pde = pmap_pdpe_to_pde(pdpe, sva);
5229 * Weed out invalid mappings.
5235 * Check for large page.
5237 if ((ptpaddr & PG_PS) != 0) {
5239 * Are we removing the entire large page? If not,
5240 * demote the mapping and fall through.
5242 if (sva + NBPDR == va_next && eva >= va_next) {
5244 * The TLB entry for a PG_G mapping is
5245 * invalidated by pmap_remove_pde().
5247 if ((ptpaddr & PG_G) == 0)
5249 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5251 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5253 /* The large page mapping was destroyed. */
5260 * Limit our scan to either the end of the va represented
5261 * by the current page table page, or to the end of the
5262 * range being removed.
5267 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5274 pmap_invalidate_all(pmap);
5276 pmap_delayed_invl_finish();
5277 vm_page_free_pages_toq(&free, true);
5281 * Routine: pmap_remove_all
5283 * Removes this physical page from
5284 * all physical maps in which it resides.
5285 * Reflects back modify bits to the pager.
5288 * Original versions of this routine were very
5289 * inefficient because they iteratively called
5290 * pmap_remove (slow...)
5294 pmap_remove_all(vm_page_t m)
5296 struct md_page *pvh;
5299 struct rwlock *lock;
5300 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5303 struct spglist free;
5304 int pvh_gen, md_gen;
5306 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5307 ("pmap_remove_all: page %p is not managed", m));
5309 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5310 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5311 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5314 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5316 if (!PMAP_TRYLOCK(pmap)) {
5317 pvh_gen = pvh->pv_gen;
5321 if (pvh_gen != pvh->pv_gen) {
5328 pde = pmap_pde(pmap, va);
5329 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5332 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5334 if (!PMAP_TRYLOCK(pmap)) {
5335 pvh_gen = pvh->pv_gen;
5336 md_gen = m->md.pv_gen;
5340 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5346 PG_A = pmap_accessed_bit(pmap);
5347 PG_M = pmap_modified_bit(pmap);
5348 PG_RW = pmap_rw_bit(pmap);
5349 pmap_resident_count_dec(pmap, 1);
5350 pde = pmap_pde(pmap, pv->pv_va);
5351 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5352 " a 2mpage in page %p's pv list", m));
5353 pte = pmap_pde_to_pte(pde, pv->pv_va);
5354 tpte = pte_load_clear(pte);
5356 pmap->pm_stats.wired_count--;
5358 vm_page_aflag_set(m, PGA_REFERENCED);
5361 * Update the vm_page_t clean and reference bits.
5363 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5365 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5366 pmap_invalidate_page(pmap, pv->pv_va);
5367 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5369 free_pv_entry(pmap, pv);
5372 vm_page_aflag_clear(m, PGA_WRITEABLE);
5374 pmap_delayed_invl_wait(m);
5375 vm_page_free_pages_toq(&free, true);
5379 * pmap_protect_pde: do the things to protect a 2mpage in a process
5382 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5384 pd_entry_t newpde, oldpde;
5386 boolean_t anychanged;
5387 pt_entry_t PG_G, PG_M, PG_RW;
5389 PG_G = pmap_global_bit(pmap);
5390 PG_M = pmap_modified_bit(pmap);
5391 PG_RW = pmap_rw_bit(pmap);
5393 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5394 KASSERT((sva & PDRMASK) == 0,
5395 ("pmap_protect_pde: sva is not 2mpage aligned"));
5398 oldpde = newpde = *pde;
5399 if ((prot & VM_PROT_WRITE) == 0) {
5400 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5401 (PG_MANAGED | PG_M | PG_RW)) {
5402 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5403 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5406 newpde &= ~(PG_RW | PG_M);
5408 if ((prot & VM_PROT_EXECUTE) == 0)
5410 if (newpde != oldpde) {
5412 * As an optimization to future operations on this PDE, clear
5413 * PG_PROMOTED. The impending invalidation will remove any
5414 * lingering 4KB page mappings from the TLB.
5416 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5418 if ((oldpde & PG_G) != 0)
5419 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5423 return (anychanged);
5427 * Set the physical protection on the
5428 * specified range of this map as requested.
5431 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5433 vm_offset_t va_next;
5434 pml4_entry_t *pml4e;
5436 pd_entry_t ptpaddr, *pde;
5437 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5438 boolean_t anychanged;
5440 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5441 if (prot == VM_PROT_NONE) {
5442 pmap_remove(pmap, sva, eva);
5446 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5447 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5450 PG_G = pmap_global_bit(pmap);
5451 PG_M = pmap_modified_bit(pmap);
5452 PG_V = pmap_valid_bit(pmap);
5453 PG_RW = pmap_rw_bit(pmap);
5457 * Although this function delays and batches the invalidation
5458 * of stale TLB entries, it does not need to call
5459 * pmap_delayed_invl_start() and
5460 * pmap_delayed_invl_finish(), because it does not
5461 * ordinarily destroy mappings. Stale TLB entries from
5462 * protection-only changes need only be invalidated before the
5463 * pmap lock is released, because protection-only changes do
5464 * not destroy PV entries. Even operations that iterate over
5465 * a physical page's PV list of mappings, like
5466 * pmap_remove_write(), acquire the pmap lock for each
5467 * mapping. Consequently, for protection-only changes, the
5468 * pmap lock suffices to synchronize both page table and TLB
5471 * This function only destroys a mapping if pmap_demote_pde()
5472 * fails. In that case, stale TLB entries are immediately
5477 for (; sva < eva; sva = va_next) {
5479 pml4e = pmap_pml4e(pmap, sva);
5480 if ((*pml4e & PG_V) == 0) {
5481 va_next = (sva + NBPML4) & ~PML4MASK;
5487 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5488 if ((*pdpe & PG_V) == 0) {
5489 va_next = (sva + NBPDP) & ~PDPMASK;
5495 va_next = (sva + NBPDR) & ~PDRMASK;
5499 pde = pmap_pdpe_to_pde(pdpe, sva);
5503 * Weed out invalid mappings.
5509 * Check for large page.
5511 if ((ptpaddr & PG_PS) != 0) {
5513 * Are we protecting the entire large page? If not,
5514 * demote the mapping and fall through.
5516 if (sva + NBPDR == va_next && eva >= va_next) {
5518 * The TLB entry for a PG_G mapping is
5519 * invalidated by pmap_protect_pde().
5521 if (pmap_protect_pde(pmap, pde, sva, prot))
5524 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5526 * The large page mapping was destroyed.
5535 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5537 pt_entry_t obits, pbits;
5541 obits = pbits = *pte;
5542 if ((pbits & PG_V) == 0)
5545 if ((prot & VM_PROT_WRITE) == 0) {
5546 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5547 (PG_MANAGED | PG_M | PG_RW)) {
5548 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5551 pbits &= ~(PG_RW | PG_M);
5553 if ((prot & VM_PROT_EXECUTE) == 0)
5556 if (pbits != obits) {
5557 if (!atomic_cmpset_long(pte, obits, pbits))
5560 pmap_invalidate_page(pmap, sva);
5567 pmap_invalidate_all(pmap);
5571 #if VM_NRESERVLEVEL > 0
5573 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5576 if (pmap->pm_type != PT_EPT)
5578 return ((pde & EPT_PG_EXECUTE) != 0);
5582 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5583 * single page table page (PTP) to a single 2MB page mapping. For promotion
5584 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5585 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5586 * identical characteristics.
5589 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5590 struct rwlock **lockp)
5593 pt_entry_t *firstpte, oldpte, pa, *pte;
5594 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5598 PG_A = pmap_accessed_bit(pmap);
5599 PG_G = pmap_global_bit(pmap);
5600 PG_M = pmap_modified_bit(pmap);
5601 PG_V = pmap_valid_bit(pmap);
5602 PG_RW = pmap_rw_bit(pmap);
5603 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5604 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5606 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5609 * Examine the first PTE in the specified PTP. Abort if this PTE is
5610 * either invalid, unused, or does not map the first 4KB physical page
5611 * within a 2MB page.
5613 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5616 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5617 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5619 atomic_add_long(&pmap_pde_p_failures, 1);
5620 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5621 " in pmap %p", va, pmap);
5624 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5626 * When PG_M is already clear, PG_RW can be cleared without
5627 * a TLB invalidation.
5629 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5635 * Examine each of the other PTEs in the specified PTP. Abort if this
5636 * PTE maps an unexpected 4KB physical page or does not have identical
5637 * characteristics to the first PTE.
5639 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5640 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5643 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5644 atomic_add_long(&pmap_pde_p_failures, 1);
5645 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5646 " in pmap %p", va, pmap);
5649 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5651 * When PG_M is already clear, PG_RW can be cleared
5652 * without a TLB invalidation.
5654 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5657 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5658 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5659 (va & ~PDRMASK), pmap);
5661 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5662 atomic_add_long(&pmap_pde_p_failures, 1);
5663 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5664 " in pmap %p", va, pmap);
5671 * Save the page table page in its current state until the PDE
5672 * mapping the superpage is demoted by pmap_demote_pde() or
5673 * destroyed by pmap_remove_pde().
5675 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5676 KASSERT(mpte >= vm_page_array &&
5677 mpte < &vm_page_array[vm_page_array_size],
5678 ("pmap_promote_pde: page table page is out of range"));
5679 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5680 ("pmap_promote_pde: page table page's pindex is wrong"));
5681 if (pmap_insert_pt_page(pmap, mpte, true)) {
5682 atomic_add_long(&pmap_pde_p_failures, 1);
5684 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5690 * Promote the pv entries.
5692 if ((newpde & PG_MANAGED) != 0)
5693 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5696 * Propagate the PAT index to its proper position.
5698 newpde = pmap_swap_pat(pmap, newpde);
5701 * Map the superpage.
5703 if (workaround_erratum383)
5704 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5706 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5708 atomic_add_long(&pmap_pde_promotions, 1);
5709 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5710 " in pmap %p", va, pmap);
5712 #endif /* VM_NRESERVLEVEL > 0 */
5715 * Insert the given physical page (p) at
5716 * the specified virtual address (v) in the
5717 * target physical map with the protection requested.
5719 * If specified, the page will be wired down, meaning
5720 * that the related pte can not be reclaimed.
5722 * NB: This is the only routine which MAY NOT lazy-evaluate
5723 * or lose information. That is, this routine must actually
5724 * insert this page into the given map NOW.
5726 * When destroying both a page table and PV entry, this function
5727 * performs the TLB invalidation before releasing the PV list
5728 * lock, so we do not need pmap_delayed_invl_page() calls here.
5731 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5732 u_int flags, int8_t psind)
5734 struct rwlock *lock;
5736 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5737 pt_entry_t newpte, origpte;
5744 PG_A = pmap_accessed_bit(pmap);
5745 PG_G = pmap_global_bit(pmap);
5746 PG_M = pmap_modified_bit(pmap);
5747 PG_V = pmap_valid_bit(pmap);
5748 PG_RW = pmap_rw_bit(pmap);
5750 va = trunc_page(va);
5751 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5752 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5753 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5755 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5756 va >= kmi.clean_eva,
5757 ("pmap_enter: managed mapping within the clean submap"));
5758 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5759 VM_OBJECT_ASSERT_LOCKED(m->object);
5760 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5761 ("pmap_enter: flags %u has reserved bits set", flags));
5762 pa = VM_PAGE_TO_PHYS(m);
5763 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5764 if ((flags & VM_PROT_WRITE) != 0)
5766 if ((prot & VM_PROT_WRITE) != 0)
5768 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5769 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5770 if ((prot & VM_PROT_EXECUTE) == 0)
5772 if ((flags & PMAP_ENTER_WIRED) != 0)
5774 if (va < VM_MAXUSER_ADDRESS)
5776 if (pmap == kernel_pmap)
5778 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5781 * Set modified bit gratuitously for writeable mappings if
5782 * the page is unmanaged. We do not want to take a fault
5783 * to do the dirty bit accounting for these mappings.
5785 if ((m->oflags & VPO_UNMANAGED) != 0) {
5786 if ((newpte & PG_RW) != 0)
5789 newpte |= PG_MANAGED;
5794 /* Assert the required virtual and physical alignment. */
5795 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5796 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5797 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5803 * In the case that a page table page is not
5804 * resident, we are creating it here.
5807 pde = pmap_pde(pmap, va);
5808 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5809 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5810 pte = pmap_pde_to_pte(pde, va);
5811 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5812 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5815 } else if (va < VM_MAXUSER_ADDRESS) {
5817 * Here if the pte page isn't mapped, or if it has been
5820 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5821 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5822 nosleep ? NULL : &lock);
5823 if (mpte == NULL && nosleep) {
5824 rv = KERN_RESOURCE_SHORTAGE;
5829 panic("pmap_enter: invalid page directory va=%#lx", va);
5833 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5834 newpte |= pmap_pkru_get(pmap, va);
5837 * Is the specified virtual address already mapped?
5839 if ((origpte & PG_V) != 0) {
5841 * Wiring change, just update stats. We don't worry about
5842 * wiring PT pages as they remain resident as long as there
5843 * are valid mappings in them. Hence, if a user page is wired,
5844 * the PT page will be also.
5846 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5847 pmap->pm_stats.wired_count++;
5848 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5849 pmap->pm_stats.wired_count--;
5852 * Remove the extra PT page reference.
5856 KASSERT(mpte->wire_count > 0,
5857 ("pmap_enter: missing reference to page table page,"
5862 * Has the physical page changed?
5864 opa = origpte & PG_FRAME;
5867 * No, might be a protection or wiring change.
5869 if ((origpte & PG_MANAGED) != 0 &&
5870 (newpte & PG_RW) != 0)
5871 vm_page_aflag_set(m, PGA_WRITEABLE);
5872 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5878 * The physical page has changed. Temporarily invalidate
5879 * the mapping. This ensures that all threads sharing the
5880 * pmap keep a consistent view of the mapping, which is
5881 * necessary for the correct handling of COW faults. It
5882 * also permits reuse of the old mapping's PV entry,
5883 * avoiding an allocation.
5885 * For consistency, handle unmanaged mappings the same way.
5887 origpte = pte_load_clear(pte);
5888 KASSERT((origpte & PG_FRAME) == opa,
5889 ("pmap_enter: unexpected pa update for %#lx", va));
5890 if ((origpte & PG_MANAGED) != 0) {
5891 om = PHYS_TO_VM_PAGE(opa);
5894 * The pmap lock is sufficient to synchronize with
5895 * concurrent calls to pmap_page_test_mappings() and
5896 * pmap_ts_referenced().
5898 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5900 if ((origpte & PG_A) != 0)
5901 vm_page_aflag_set(om, PGA_REFERENCED);
5902 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5903 pv = pmap_pvh_remove(&om->md, pmap, va);
5905 ("pmap_enter: no PV entry for %#lx", va));
5906 if ((newpte & PG_MANAGED) == 0)
5907 free_pv_entry(pmap, pv);
5908 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5909 TAILQ_EMPTY(&om->md.pv_list) &&
5910 ((om->flags & PG_FICTITIOUS) != 0 ||
5911 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5912 vm_page_aflag_clear(om, PGA_WRITEABLE);
5914 if ((origpte & PG_A) != 0)
5915 pmap_invalidate_page(pmap, va);
5919 * Increment the counters.
5921 if ((newpte & PG_W) != 0)
5922 pmap->pm_stats.wired_count++;
5923 pmap_resident_count_inc(pmap, 1);
5927 * Enter on the PV list if part of our managed memory.
5929 if ((newpte & PG_MANAGED) != 0) {
5931 pv = get_pv_entry(pmap, &lock);
5934 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5935 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5937 if ((newpte & PG_RW) != 0)
5938 vm_page_aflag_set(m, PGA_WRITEABLE);
5944 if ((origpte & PG_V) != 0) {
5946 origpte = pte_load_store(pte, newpte);
5947 KASSERT((origpte & PG_FRAME) == pa,
5948 ("pmap_enter: unexpected pa update for %#lx", va));
5949 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5951 if ((origpte & PG_MANAGED) != 0)
5955 * Although the PTE may still have PG_RW set, TLB
5956 * invalidation may nonetheless be required because
5957 * the PTE no longer has PG_M set.
5959 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5961 * This PTE change does not require TLB invalidation.
5965 if ((origpte & PG_A) != 0)
5966 pmap_invalidate_page(pmap, va);
5968 pte_store(pte, newpte);
5972 #if VM_NRESERVLEVEL > 0
5974 * If both the page table page and the reservation are fully
5975 * populated, then attempt promotion.
5977 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5978 pmap_ps_enabled(pmap) &&
5979 (m->flags & PG_FICTITIOUS) == 0 &&
5980 vm_reserv_level_iffullpop(m) == 0)
5981 pmap_promote_pde(pmap, pde, va, &lock);
5993 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5994 * if successful. Returns false if (1) a page table page cannot be allocated
5995 * without sleeping, (2) a mapping already exists at the specified virtual
5996 * address, or (3) a PV entry cannot be allocated without reclaiming another
6000 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6001 struct rwlock **lockp)
6006 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6007 PG_V = pmap_valid_bit(pmap);
6008 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6010 if ((m->oflags & VPO_UNMANAGED) == 0)
6011 newpde |= PG_MANAGED;
6012 if ((prot & VM_PROT_EXECUTE) == 0)
6014 if (va < VM_MAXUSER_ADDRESS)
6016 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6017 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6022 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6023 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6024 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6025 * a mapping already exists at the specified virtual address. Returns
6026 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6027 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6028 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6030 * The parameter "m" is only used when creating a managed, writeable mapping.
6033 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6034 vm_page_t m, struct rwlock **lockp)
6036 struct spglist free;
6037 pd_entry_t oldpde, *pde;
6038 pt_entry_t PG_G, PG_RW, PG_V;
6041 PG_G = pmap_global_bit(pmap);
6042 PG_RW = pmap_rw_bit(pmap);
6043 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6044 ("pmap_enter_pde: newpde is missing PG_M"));
6045 PG_V = pmap_valid_bit(pmap);
6046 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6048 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6050 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6051 " in pmap %p", va, pmap);
6052 return (KERN_FAILURE);
6054 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
6055 NULL : lockp)) == NULL) {
6056 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6057 " in pmap %p", va, pmap);
6058 return (KERN_RESOURCE_SHORTAGE);
6062 * If pkru is not same for the whole pde range, return failure
6063 * and let vm_fault() cope. Check after pde allocation, since
6066 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6068 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6069 pmap_invalidate_page(pmap, va);
6070 vm_page_free_pages_toq(&free, true);
6072 return (KERN_FAILURE);
6074 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6075 newpde &= ~X86_PG_PKU_MASK;
6076 newpde |= pmap_pkru_get(pmap, va);
6079 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6080 pde = &pde[pmap_pde_index(va)];
6082 if ((oldpde & PG_V) != 0) {
6083 KASSERT(pdpg->wire_count > 1,
6084 ("pmap_enter_pde: pdpg's wire count is too low"));
6085 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
6087 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6088 " in pmap %p", va, pmap);
6089 return (KERN_FAILURE);
6091 /* Break the existing mapping(s). */
6093 if ((oldpde & PG_PS) != 0) {
6095 * The reference to the PD page that was acquired by
6096 * pmap_allocpde() ensures that it won't be freed.
6097 * However, if the PDE resulted from a promotion, then
6098 * a reserved PT page could be freed.
6100 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6101 if ((oldpde & PG_G) == 0)
6102 pmap_invalidate_pde_page(pmap, va, oldpde);
6104 pmap_delayed_invl_start();
6105 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6107 pmap_invalidate_all(pmap);
6108 pmap_delayed_invl_finish();
6110 vm_page_free_pages_toq(&free, true);
6111 if (va >= VM_MAXUSER_ADDRESS) {
6113 * Both pmap_remove_pde() and pmap_remove_ptes() will
6114 * leave the kernel page table page zero filled.
6116 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6117 if (pmap_insert_pt_page(pmap, mt, false))
6118 panic("pmap_enter_pde: trie insert failed");
6120 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6123 if ((newpde & PG_MANAGED) != 0) {
6125 * Abort this mapping if its PV entry could not be created.
6127 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6129 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6131 * Although "va" is not mapped, paging-
6132 * structure caches could nonetheless have
6133 * entries that refer to the freed page table
6134 * pages. Invalidate those entries.
6136 pmap_invalidate_page(pmap, va);
6137 vm_page_free_pages_toq(&free, true);
6139 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6140 " in pmap %p", va, pmap);
6141 return (KERN_RESOURCE_SHORTAGE);
6143 if ((newpde & PG_RW) != 0) {
6144 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6145 vm_page_aflag_set(mt, PGA_WRITEABLE);
6150 * Increment counters.
6152 if ((newpde & PG_W) != 0)
6153 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6154 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6157 * Map the superpage. (This is not a promoted mapping; there will not
6158 * be any lingering 4KB page mappings in the TLB.)
6160 pde_store(pde, newpde);
6162 atomic_add_long(&pmap_pde_mappings, 1);
6163 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
6164 " in pmap %p", va, pmap);
6165 return (KERN_SUCCESS);
6169 * Maps a sequence of resident pages belonging to the same object.
6170 * The sequence begins with the given page m_start. This page is
6171 * mapped at the given virtual address start. Each subsequent page is
6172 * mapped at a virtual address that is offset from start by the same
6173 * amount as the page is offset from m_start within the object. The
6174 * last page in the sequence is the page with the largest offset from
6175 * m_start that can be mapped at a virtual address less than the given
6176 * virtual address end. Not every virtual page between start and end
6177 * is mapped; only those for which a resident page exists with the
6178 * corresponding offset from m_start are mapped.
6181 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6182 vm_page_t m_start, vm_prot_t prot)
6184 struct rwlock *lock;
6187 vm_pindex_t diff, psize;
6189 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6191 psize = atop(end - start);
6196 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6197 va = start + ptoa(diff);
6198 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6199 m->psind == 1 && pmap_ps_enabled(pmap) &&
6200 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6201 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6202 m = &m[NBPDR / PAGE_SIZE - 1];
6204 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6206 m = TAILQ_NEXT(m, listq);
6214 * this code makes some *MAJOR* assumptions:
6215 * 1. Current pmap & pmap exists.
6218 * 4. No page table pages.
6219 * but is *MUCH* faster than pmap_enter...
6223 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6225 struct rwlock *lock;
6229 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6236 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6237 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6239 struct spglist free;
6240 pt_entry_t newpte, *pte, PG_V;
6242 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6243 (m->oflags & VPO_UNMANAGED) != 0,
6244 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6245 PG_V = pmap_valid_bit(pmap);
6246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6249 * In the case that a page table page is not
6250 * resident, we are creating it here.
6252 if (va < VM_MAXUSER_ADDRESS) {
6253 vm_pindex_t ptepindex;
6257 * Calculate pagetable page index
6259 ptepindex = pmap_pde_pindex(va);
6260 if (mpte && (mpte->pindex == ptepindex)) {
6264 * Get the page directory entry
6266 ptepa = pmap_pde(pmap, va);
6269 * If the page table page is mapped, we just increment
6270 * the hold count, and activate it. Otherwise, we
6271 * attempt to allocate a page table page. If this
6272 * attempt fails, we don't retry. Instead, we give up.
6274 if (ptepa && (*ptepa & PG_V) != 0) {
6277 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6281 * Pass NULL instead of the PV list lock
6282 * pointer, because we don't intend to sleep.
6284 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6289 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6290 pte = &pte[pmap_pte_index(va)];
6304 * Enter on the PV list if part of our managed memory.
6306 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6307 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6310 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6312 * Although "va" is not mapped, paging-
6313 * structure caches could nonetheless have
6314 * entries that refer to the freed page table
6315 * pages. Invalidate those entries.
6317 pmap_invalidate_page(pmap, va);
6318 vm_page_free_pages_toq(&free, true);
6326 * Increment counters
6328 pmap_resident_count_inc(pmap, 1);
6330 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6331 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6332 if ((m->oflags & VPO_UNMANAGED) == 0)
6333 newpte |= PG_MANAGED;
6334 if ((prot & VM_PROT_EXECUTE) == 0)
6336 if (va < VM_MAXUSER_ADDRESS)
6337 newpte |= PG_U | pmap_pkru_get(pmap, va);
6338 pte_store(pte, newpte);
6343 * Make a temporary mapping for a physical address. This is only intended
6344 * to be used for panic dumps.
6347 pmap_kenter_temporary(vm_paddr_t pa, int i)
6351 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6352 pmap_kenter(va, pa);
6354 return ((void *)crashdumpmap);
6358 * This code maps large physical mmap regions into the
6359 * processor address space. Note that some shortcuts
6360 * are taken, but the code works.
6363 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6364 vm_pindex_t pindex, vm_size_t size)
6367 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6368 vm_paddr_t pa, ptepa;
6372 PG_A = pmap_accessed_bit(pmap);
6373 PG_M = pmap_modified_bit(pmap);
6374 PG_V = pmap_valid_bit(pmap);
6375 PG_RW = pmap_rw_bit(pmap);
6377 VM_OBJECT_ASSERT_WLOCKED(object);
6378 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6379 ("pmap_object_init_pt: non-device object"));
6380 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6381 if (!pmap_ps_enabled(pmap))
6383 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6385 p = vm_page_lookup(object, pindex);
6386 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6387 ("pmap_object_init_pt: invalid page %p", p));
6388 pat_mode = p->md.pat_mode;
6391 * Abort the mapping if the first page is not physically
6392 * aligned to a 2MB page boundary.
6394 ptepa = VM_PAGE_TO_PHYS(p);
6395 if (ptepa & (NBPDR - 1))
6399 * Skip the first page. Abort the mapping if the rest of
6400 * the pages are not physically contiguous or have differing
6401 * memory attributes.
6403 p = TAILQ_NEXT(p, listq);
6404 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6406 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6407 ("pmap_object_init_pt: invalid page %p", p));
6408 if (pa != VM_PAGE_TO_PHYS(p) ||
6409 pat_mode != p->md.pat_mode)
6411 p = TAILQ_NEXT(p, listq);
6415 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6416 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6417 * will not affect the termination of this loop.
6420 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6421 pa < ptepa + size; pa += NBPDR) {
6422 pdpg = pmap_allocpde(pmap, addr, NULL);
6425 * The creation of mappings below is only an
6426 * optimization. If a page directory page
6427 * cannot be allocated without blocking,
6428 * continue on to the next mapping rather than
6434 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6435 pde = &pde[pmap_pde_index(addr)];
6436 if ((*pde & PG_V) == 0) {
6437 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6438 PG_U | PG_RW | PG_V);
6439 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6440 atomic_add_long(&pmap_pde_mappings, 1);
6442 /* Continue on if the PDE is already valid. */
6444 KASSERT(pdpg->wire_count > 0,
6445 ("pmap_object_init_pt: missing reference "
6446 "to page directory page, va: 0x%lx", addr));
6455 * Clear the wired attribute from the mappings for the specified range of
6456 * addresses in the given pmap. Every valid mapping within that range
6457 * must have the wired attribute set. In contrast, invalid mappings
6458 * cannot have the wired attribute set, so they are ignored.
6460 * The wired attribute of the page table entry is not a hardware
6461 * feature, so there is no need to invalidate any TLB entries.
6462 * Since pmap_demote_pde() for the wired entry must never fail,
6463 * pmap_delayed_invl_start()/finish() calls around the
6464 * function are not needed.
6467 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6469 vm_offset_t va_next;
6470 pml4_entry_t *pml4e;
6473 pt_entry_t *pte, PG_V;
6475 PG_V = pmap_valid_bit(pmap);
6477 for (; sva < eva; sva = va_next) {
6478 pml4e = pmap_pml4e(pmap, sva);
6479 if ((*pml4e & PG_V) == 0) {
6480 va_next = (sva + NBPML4) & ~PML4MASK;
6485 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6486 if ((*pdpe & PG_V) == 0) {
6487 va_next = (sva + NBPDP) & ~PDPMASK;
6492 va_next = (sva + NBPDR) & ~PDRMASK;
6495 pde = pmap_pdpe_to_pde(pdpe, sva);
6496 if ((*pde & PG_V) == 0)
6498 if ((*pde & PG_PS) != 0) {
6499 if ((*pde & PG_W) == 0)
6500 panic("pmap_unwire: pde %#jx is missing PG_W",
6504 * Are we unwiring the entire large page? If not,
6505 * demote the mapping and fall through.
6507 if (sva + NBPDR == va_next && eva >= va_next) {
6508 atomic_clear_long(pde, PG_W);
6509 pmap->pm_stats.wired_count -= NBPDR /
6512 } else if (!pmap_demote_pde(pmap, pde, sva))
6513 panic("pmap_unwire: demotion failed");
6517 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6519 if ((*pte & PG_V) == 0)
6521 if ((*pte & PG_W) == 0)
6522 panic("pmap_unwire: pte %#jx is missing PG_W",
6526 * PG_W must be cleared atomically. Although the pmap
6527 * lock synchronizes access to PG_W, another processor
6528 * could be setting PG_M and/or PG_A concurrently.
6530 atomic_clear_long(pte, PG_W);
6531 pmap->pm_stats.wired_count--;
6538 * Copy the range specified by src_addr/len
6539 * from the source map to the range dst_addr/len
6540 * in the destination map.
6542 * This routine is only advisory and need not do anything.
6545 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6546 vm_offset_t src_addr)
6548 struct rwlock *lock;
6549 struct spglist free;
6550 pml4_entry_t *pml4e;
6552 pd_entry_t *pde, srcptepaddr;
6553 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6554 vm_offset_t addr, end_addr, va_next;
6555 vm_page_t dst_pdpg, dstmpte, srcmpte;
6557 if (dst_addr != src_addr)
6560 if (dst_pmap->pm_type != src_pmap->pm_type)
6564 * EPT page table entries that require emulation of A/D bits are
6565 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6566 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6567 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6568 * implementations flag an EPT misconfiguration for exec-only
6569 * mappings we skip this function entirely for emulated pmaps.
6571 if (pmap_emulate_ad_bits(dst_pmap))
6574 end_addr = src_addr + len;
6576 if (dst_pmap < src_pmap) {
6577 PMAP_LOCK(dst_pmap);
6578 PMAP_LOCK(src_pmap);
6580 PMAP_LOCK(src_pmap);
6581 PMAP_LOCK(dst_pmap);
6584 PG_A = pmap_accessed_bit(dst_pmap);
6585 PG_M = pmap_modified_bit(dst_pmap);
6586 PG_V = pmap_valid_bit(dst_pmap);
6588 for (addr = src_addr; addr < end_addr; addr = va_next) {
6589 KASSERT(addr < UPT_MIN_ADDRESS,
6590 ("pmap_copy: invalid to pmap_copy page tables"));
6592 pml4e = pmap_pml4e(src_pmap, addr);
6593 if ((*pml4e & PG_V) == 0) {
6594 va_next = (addr + NBPML4) & ~PML4MASK;
6600 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6601 if ((*pdpe & PG_V) == 0) {
6602 va_next = (addr + NBPDP) & ~PDPMASK;
6608 va_next = (addr + NBPDR) & ~PDRMASK;
6612 pde = pmap_pdpe_to_pde(pdpe, addr);
6614 if (srcptepaddr == 0)
6617 if (srcptepaddr & PG_PS) {
6618 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6620 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6621 if (dst_pdpg == NULL)
6623 pde = (pd_entry_t *)
6624 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6625 pde = &pde[pmap_pde_index(addr)];
6626 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6627 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6628 PMAP_ENTER_NORECLAIM, &lock))) {
6629 *pde = srcptepaddr & ~PG_W;
6630 pmap_resident_count_inc(dst_pmap, NBPDR /
6632 atomic_add_long(&pmap_pde_mappings, 1);
6634 dst_pdpg->wire_count--;
6638 srcptepaddr &= PG_FRAME;
6639 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6640 KASSERT(srcmpte->wire_count > 0,
6641 ("pmap_copy: source page table page is unused"));
6643 if (va_next > end_addr)
6646 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6647 src_pte = &src_pte[pmap_pte_index(addr)];
6649 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6653 * We only virtual copy managed pages.
6655 if ((ptetemp & PG_MANAGED) == 0)
6658 if (dstmpte != NULL) {
6659 KASSERT(dstmpte->pindex ==
6660 pmap_pde_pindex(addr),
6661 ("dstmpte pindex/addr mismatch"));
6662 dstmpte->wire_count++;
6663 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6666 dst_pte = (pt_entry_t *)
6667 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6668 dst_pte = &dst_pte[pmap_pte_index(addr)];
6669 if (*dst_pte == 0 &&
6670 pmap_try_insert_pv_entry(dst_pmap, addr,
6671 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6673 * Clear the wired, modified, and accessed
6674 * (referenced) bits during the copy.
6676 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6677 pmap_resident_count_inc(dst_pmap, 1);
6680 if (pmap_unwire_ptp(dst_pmap, addr, dstmpte,
6683 * Although "addr" is not mapped,
6684 * paging-structure caches could
6685 * nonetheless have entries that refer
6686 * to the freed page table pages.
6687 * Invalidate those entries.
6689 pmap_invalidate_page(dst_pmap, addr);
6690 vm_page_free_pages_toq(&free, true);
6694 /* Have we copied all of the valid mappings? */
6695 if (dstmpte->wire_count >= srcmpte->wire_count)
6702 PMAP_UNLOCK(src_pmap);
6703 PMAP_UNLOCK(dst_pmap);
6707 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6711 if (dst_pmap->pm_type != src_pmap->pm_type ||
6712 dst_pmap->pm_type != PT_X86 ||
6713 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6716 if (dst_pmap < src_pmap) {
6717 PMAP_LOCK(dst_pmap);
6718 PMAP_LOCK(src_pmap);
6720 PMAP_LOCK(src_pmap);
6721 PMAP_LOCK(dst_pmap);
6723 error = pmap_pkru_copy(dst_pmap, src_pmap);
6724 /* Clean up partial copy on failure due to no memory. */
6725 if (error == ENOMEM)
6726 pmap_pkru_deassign_all(dst_pmap);
6727 PMAP_UNLOCK(src_pmap);
6728 PMAP_UNLOCK(dst_pmap);
6729 if (error != ENOMEM)
6737 * Zero the specified hardware page.
6740 pmap_zero_page(vm_page_t m)
6742 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6744 pagezero((void *)va);
6748 * Zero an an area within a single hardware page. off and size must not
6749 * cover an area beyond a single hardware page.
6752 pmap_zero_page_area(vm_page_t m, int off, int size)
6754 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6756 if (off == 0 && size == PAGE_SIZE)
6757 pagezero((void *)va);
6759 bzero((char *)va + off, size);
6763 * Copy 1 specified hardware page to another.
6766 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6768 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6769 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6771 pagecopy((void *)src, (void *)dst);
6774 int unmapped_buf_allowed = 1;
6777 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6778 vm_offset_t b_offset, int xfersize)
6782 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6786 while (xfersize > 0) {
6787 a_pg_offset = a_offset & PAGE_MASK;
6788 pages[0] = ma[a_offset >> PAGE_SHIFT];
6789 b_pg_offset = b_offset & PAGE_MASK;
6790 pages[1] = mb[b_offset >> PAGE_SHIFT];
6791 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6792 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6793 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6794 a_cp = (char *)vaddr[0] + a_pg_offset;
6795 b_cp = (char *)vaddr[1] + b_pg_offset;
6796 bcopy(a_cp, b_cp, cnt);
6797 if (__predict_false(mapped))
6798 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6806 * Returns true if the pmap's pv is one of the first
6807 * 16 pvs linked to from this page. This count may
6808 * be changed upwards or downwards in the future; it
6809 * is only necessary that true be returned for a small
6810 * subset of pmaps for proper page aging.
6813 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6815 struct md_page *pvh;
6816 struct rwlock *lock;
6821 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6822 ("pmap_page_exists_quick: page %p is not managed", m));
6824 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6826 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6827 if (PV_PMAP(pv) == pmap) {
6835 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6836 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6837 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6838 if (PV_PMAP(pv) == pmap) {
6852 * pmap_page_wired_mappings:
6854 * Return the number of managed mappings to the given physical page
6858 pmap_page_wired_mappings(vm_page_t m)
6860 struct rwlock *lock;
6861 struct md_page *pvh;
6865 int count, md_gen, pvh_gen;
6867 if ((m->oflags & VPO_UNMANAGED) != 0)
6869 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6873 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6875 if (!PMAP_TRYLOCK(pmap)) {
6876 md_gen = m->md.pv_gen;
6880 if (md_gen != m->md.pv_gen) {
6885 pte = pmap_pte(pmap, pv->pv_va);
6886 if ((*pte & PG_W) != 0)
6890 if ((m->flags & PG_FICTITIOUS) == 0) {
6891 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6892 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6894 if (!PMAP_TRYLOCK(pmap)) {
6895 md_gen = m->md.pv_gen;
6896 pvh_gen = pvh->pv_gen;
6900 if (md_gen != m->md.pv_gen ||
6901 pvh_gen != pvh->pv_gen) {
6906 pte = pmap_pde(pmap, pv->pv_va);
6907 if ((*pte & PG_W) != 0)
6917 * Returns TRUE if the given page is mapped individually or as part of
6918 * a 2mpage. Otherwise, returns FALSE.
6921 pmap_page_is_mapped(vm_page_t m)
6923 struct rwlock *lock;
6926 if ((m->oflags & VPO_UNMANAGED) != 0)
6928 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6930 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6931 ((m->flags & PG_FICTITIOUS) == 0 &&
6932 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6938 * Destroy all managed, non-wired mappings in the given user-space
6939 * pmap. This pmap cannot be active on any processor besides the
6942 * This function cannot be applied to the kernel pmap. Moreover, it
6943 * is not intended for general use. It is only to be used during
6944 * process termination. Consequently, it can be implemented in ways
6945 * that make it faster than pmap_remove(). First, it can more quickly
6946 * destroy mappings by iterating over the pmap's collection of PV
6947 * entries, rather than searching the page table. Second, it doesn't
6948 * have to test and clear the page table entries atomically, because
6949 * no processor is currently accessing the user address space. In
6950 * particular, a page table entry's dirty bit won't change state once
6951 * this function starts.
6953 * Although this function destroys all of the pmap's managed,
6954 * non-wired mappings, it can delay and batch the invalidation of TLB
6955 * entries without calling pmap_delayed_invl_start() and
6956 * pmap_delayed_invl_finish(). Because the pmap is not active on
6957 * any other processor, none of these TLB entries will ever be used
6958 * before their eventual invalidation. Consequently, there is no need
6959 * for either pmap_remove_all() or pmap_remove_write() to wait for
6960 * that eventual TLB invalidation.
6963 pmap_remove_pages(pmap_t pmap)
6966 pt_entry_t *pte, tpte;
6967 pt_entry_t PG_M, PG_RW, PG_V;
6968 struct spglist free;
6969 struct pv_chunklist free_chunks;
6970 vm_page_t m, mpte, mt;
6972 struct md_page *pvh;
6973 struct pv_chunk *pc, *npc;
6974 struct rwlock *lock;
6976 uint64_t inuse, bitmask;
6977 int allfree, field, freed, idx;
6978 boolean_t superpage;
6982 * Assert that the given pmap is only active on the current
6983 * CPU. Unfortunately, we cannot block another CPU from
6984 * activating the pmap while this function is executing.
6986 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6989 cpuset_t other_cpus;
6991 other_cpus = all_cpus;
6993 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6994 CPU_AND(&other_cpus, &pmap->pm_active);
6996 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7001 PG_M = pmap_modified_bit(pmap);
7002 PG_V = pmap_valid_bit(pmap);
7003 PG_RW = pmap_rw_bit(pmap);
7005 TAILQ_INIT(&free_chunks);
7008 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7011 for (field = 0; field < _NPCM; field++) {
7012 inuse = ~pc->pc_map[field] & pc_freemask[field];
7013 while (inuse != 0) {
7015 bitmask = 1UL << bit;
7016 idx = field * 64 + bit;
7017 pv = &pc->pc_pventry[idx];
7020 pte = pmap_pdpe(pmap, pv->pv_va);
7022 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7024 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7027 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7029 pte = &pte[pmap_pte_index(pv->pv_va)];
7033 * Keep track whether 'tpte' is a
7034 * superpage explicitly instead of
7035 * relying on PG_PS being set.
7037 * This is because PG_PS is numerically
7038 * identical to PG_PTE_PAT and thus a
7039 * regular page could be mistaken for
7045 if ((tpte & PG_V) == 0) {
7046 panic("bad pte va %lx pte %lx",
7051 * We cannot remove wired pages from a process' mapping at this time
7059 pa = tpte & PG_PS_FRAME;
7061 pa = tpte & PG_FRAME;
7063 m = PHYS_TO_VM_PAGE(pa);
7064 KASSERT(m->phys_addr == pa,
7065 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7066 m, (uintmax_t)m->phys_addr,
7069 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7070 m < &vm_page_array[vm_page_array_size],
7071 ("pmap_remove_pages: bad tpte %#jx",
7077 * Update the vm_page_t clean/reference bits.
7079 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7081 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7087 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7090 pc->pc_map[field] |= bitmask;
7092 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7093 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7094 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7096 if (TAILQ_EMPTY(&pvh->pv_list)) {
7097 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7098 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
7099 TAILQ_EMPTY(&mt->md.pv_list))
7100 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7102 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7104 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7105 ("pmap_remove_pages: pte page not promoted"));
7106 pmap_resident_count_dec(pmap, 1);
7107 KASSERT(mpte->wire_count == NPTEPG,
7108 ("pmap_remove_pages: pte page wire count error"));
7109 mpte->wire_count = 0;
7110 pmap_add_delayed_free_list(mpte, &free, FALSE);
7113 pmap_resident_count_dec(pmap, 1);
7114 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7116 if ((m->aflags & PGA_WRITEABLE) != 0 &&
7117 TAILQ_EMPTY(&m->md.pv_list) &&
7118 (m->flags & PG_FICTITIOUS) == 0) {
7119 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7120 if (TAILQ_EMPTY(&pvh->pv_list))
7121 vm_page_aflag_clear(m, PGA_WRITEABLE);
7124 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7128 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7129 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7130 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7132 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7133 TAILQ_INSERT_TAIL(&free_chunks, pc, pc_list);
7138 pmap_invalidate_all(pmap);
7139 pmap_pkru_deassign_all(pmap);
7140 free_pv_chunk_batch(&free_chunks);
7142 vm_page_free_pages_toq(&free, true);
7146 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7148 struct rwlock *lock;
7150 struct md_page *pvh;
7151 pt_entry_t *pte, mask;
7152 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7154 int md_gen, pvh_gen;
7158 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7161 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7163 if (!PMAP_TRYLOCK(pmap)) {
7164 md_gen = m->md.pv_gen;
7168 if (md_gen != m->md.pv_gen) {
7173 pte = pmap_pte(pmap, pv->pv_va);
7176 PG_M = pmap_modified_bit(pmap);
7177 PG_RW = pmap_rw_bit(pmap);
7178 mask |= PG_RW | PG_M;
7181 PG_A = pmap_accessed_bit(pmap);
7182 PG_V = pmap_valid_bit(pmap);
7183 mask |= PG_V | PG_A;
7185 rv = (*pte & mask) == mask;
7190 if ((m->flags & PG_FICTITIOUS) == 0) {
7191 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7192 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7194 if (!PMAP_TRYLOCK(pmap)) {
7195 md_gen = m->md.pv_gen;
7196 pvh_gen = pvh->pv_gen;
7200 if (md_gen != m->md.pv_gen ||
7201 pvh_gen != pvh->pv_gen) {
7206 pte = pmap_pde(pmap, pv->pv_va);
7209 PG_M = pmap_modified_bit(pmap);
7210 PG_RW = pmap_rw_bit(pmap);
7211 mask |= PG_RW | PG_M;
7214 PG_A = pmap_accessed_bit(pmap);
7215 PG_V = pmap_valid_bit(pmap);
7216 mask |= PG_V | PG_A;
7218 rv = (*pte & mask) == mask;
7232 * Return whether or not the specified physical page was modified
7233 * in any physical maps.
7236 pmap_is_modified(vm_page_t m)
7239 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7240 ("pmap_is_modified: page %p is not managed", m));
7243 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7244 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
7245 * is clear, no PTEs can have PG_M set.
7247 VM_OBJECT_ASSERT_WLOCKED(m->object);
7248 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7250 return (pmap_page_test_mappings(m, FALSE, TRUE));
7254 * pmap_is_prefaultable:
7256 * Return whether or not the specified virtual address is eligible
7260 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7263 pt_entry_t *pte, PG_V;
7266 PG_V = pmap_valid_bit(pmap);
7269 pde = pmap_pde(pmap, addr);
7270 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7271 pte = pmap_pde_to_pte(pde, addr);
7272 rv = (*pte & PG_V) == 0;
7279 * pmap_is_referenced:
7281 * Return whether or not the specified physical page was referenced
7282 * in any physical maps.
7285 pmap_is_referenced(vm_page_t m)
7288 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7289 ("pmap_is_referenced: page %p is not managed", m));
7290 return (pmap_page_test_mappings(m, TRUE, FALSE));
7294 * Clear the write and modified bits in each of the given page's mappings.
7297 pmap_remove_write(vm_page_t m)
7299 struct md_page *pvh;
7301 struct rwlock *lock;
7302 pv_entry_t next_pv, pv;
7304 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7306 int pvh_gen, md_gen;
7308 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7309 ("pmap_remove_write: page %p is not managed", m));
7312 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7313 * set by another thread while the object is locked. Thus,
7314 * if PGA_WRITEABLE is clear, no page table entries need updating.
7316 VM_OBJECT_ASSERT_WLOCKED(m->object);
7317 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7319 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7320 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7321 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7324 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7326 if (!PMAP_TRYLOCK(pmap)) {
7327 pvh_gen = pvh->pv_gen;
7331 if (pvh_gen != pvh->pv_gen) {
7337 PG_RW = pmap_rw_bit(pmap);
7339 pde = pmap_pde(pmap, va);
7340 if ((*pde & PG_RW) != 0)
7341 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7342 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7343 ("inconsistent pv lock %p %p for page %p",
7344 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7347 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7349 if (!PMAP_TRYLOCK(pmap)) {
7350 pvh_gen = pvh->pv_gen;
7351 md_gen = m->md.pv_gen;
7355 if (pvh_gen != pvh->pv_gen ||
7356 md_gen != m->md.pv_gen) {
7362 PG_M = pmap_modified_bit(pmap);
7363 PG_RW = pmap_rw_bit(pmap);
7364 pde = pmap_pde(pmap, pv->pv_va);
7365 KASSERT((*pde & PG_PS) == 0,
7366 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7368 pte = pmap_pde_to_pte(pde, pv->pv_va);
7371 if (oldpte & PG_RW) {
7372 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7375 if ((oldpte & PG_M) != 0)
7377 pmap_invalidate_page(pmap, pv->pv_va);
7382 vm_page_aflag_clear(m, PGA_WRITEABLE);
7383 pmap_delayed_invl_wait(m);
7386 static __inline boolean_t
7387 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7390 if (!pmap_emulate_ad_bits(pmap))
7393 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7396 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7397 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7398 * if the EPT_PG_WRITE bit is set.
7400 if ((pte & EPT_PG_WRITE) != 0)
7404 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7406 if ((pte & EPT_PG_EXECUTE) == 0 ||
7407 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7414 * pmap_ts_referenced:
7416 * Return a count of reference bits for a page, clearing those bits.
7417 * It is not necessary for every reference bit to be cleared, but it
7418 * is necessary that 0 only be returned when there are truly no
7419 * reference bits set.
7421 * As an optimization, update the page's dirty field if a modified bit is
7422 * found while counting reference bits. This opportunistic update can be
7423 * performed at low cost and can eliminate the need for some future calls
7424 * to pmap_is_modified(). However, since this function stops after
7425 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7426 * dirty pages. Those dirty pages will only be detected by a future call
7427 * to pmap_is_modified().
7429 * A DI block is not needed within this function, because
7430 * invalidations are performed before the PV list lock is
7434 pmap_ts_referenced(vm_page_t m)
7436 struct md_page *pvh;
7439 struct rwlock *lock;
7440 pd_entry_t oldpde, *pde;
7441 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7444 int cleared, md_gen, not_cleared, pvh_gen;
7445 struct spglist free;
7448 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7449 ("pmap_ts_referenced: page %p is not managed", m));
7452 pa = VM_PAGE_TO_PHYS(m);
7453 lock = PHYS_TO_PV_LIST_LOCK(pa);
7454 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7458 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7459 goto small_mappings;
7465 if (!PMAP_TRYLOCK(pmap)) {
7466 pvh_gen = pvh->pv_gen;
7470 if (pvh_gen != pvh->pv_gen) {
7475 PG_A = pmap_accessed_bit(pmap);
7476 PG_M = pmap_modified_bit(pmap);
7477 PG_RW = pmap_rw_bit(pmap);
7479 pde = pmap_pde(pmap, pv->pv_va);
7481 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7483 * Although "oldpde" is mapping a 2MB page, because
7484 * this function is called at a 4KB page granularity,
7485 * we only update the 4KB page under test.
7489 if ((oldpde & PG_A) != 0) {
7491 * Since this reference bit is shared by 512 4KB
7492 * pages, it should not be cleared every time it is
7493 * tested. Apply a simple "hash" function on the
7494 * physical page number, the virtual superpage number,
7495 * and the pmap address to select one 4KB page out of
7496 * the 512 on which testing the reference bit will
7497 * result in clearing that reference bit. This
7498 * function is designed to avoid the selection of the
7499 * same 4KB page for every 2MB page mapping.
7501 * On demotion, a mapping that hasn't been referenced
7502 * is simply destroyed. To avoid the possibility of a
7503 * subsequent page fault on a demoted wired mapping,
7504 * always leave its reference bit set. Moreover,
7505 * since the superpage is wired, the current state of
7506 * its reference bit won't affect page replacement.
7508 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7509 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7510 (oldpde & PG_W) == 0) {
7511 if (safe_to_clear_referenced(pmap, oldpde)) {
7512 atomic_clear_long(pde, PG_A);
7513 pmap_invalidate_page(pmap, pv->pv_va);
7515 } else if (pmap_demote_pde_locked(pmap, pde,
7516 pv->pv_va, &lock)) {
7518 * Remove the mapping to a single page
7519 * so that a subsequent access may
7520 * repromote. Since the underlying
7521 * page table page is fully populated,
7522 * this removal never frees a page
7526 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7528 pte = pmap_pde_to_pte(pde, va);
7529 pmap_remove_pte(pmap, pte, va, *pde,
7531 pmap_invalidate_page(pmap, va);
7537 * The superpage mapping was removed
7538 * entirely and therefore 'pv' is no
7546 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7547 ("inconsistent pv lock %p %p for page %p",
7548 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7553 /* Rotate the PV list if it has more than one entry. */
7554 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7555 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7556 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7559 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7561 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7563 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7570 if (!PMAP_TRYLOCK(pmap)) {
7571 pvh_gen = pvh->pv_gen;
7572 md_gen = m->md.pv_gen;
7576 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7581 PG_A = pmap_accessed_bit(pmap);
7582 PG_M = pmap_modified_bit(pmap);
7583 PG_RW = pmap_rw_bit(pmap);
7584 pde = pmap_pde(pmap, pv->pv_va);
7585 KASSERT((*pde & PG_PS) == 0,
7586 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7588 pte = pmap_pde_to_pte(pde, pv->pv_va);
7589 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7591 if ((*pte & PG_A) != 0) {
7592 if (safe_to_clear_referenced(pmap, *pte)) {
7593 atomic_clear_long(pte, PG_A);
7594 pmap_invalidate_page(pmap, pv->pv_va);
7596 } else if ((*pte & PG_W) == 0) {
7598 * Wired pages cannot be paged out so
7599 * doing accessed bit emulation for
7600 * them is wasted effort. We do the
7601 * hard work for unwired pages only.
7603 pmap_remove_pte(pmap, pte, pv->pv_va,
7604 *pde, &free, &lock);
7605 pmap_invalidate_page(pmap, pv->pv_va);
7610 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7611 ("inconsistent pv lock %p %p for page %p",
7612 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7617 /* Rotate the PV list if it has more than one entry. */
7618 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7619 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7620 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7623 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7624 not_cleared < PMAP_TS_REFERENCED_MAX);
7627 vm_page_free_pages_toq(&free, true);
7628 return (cleared + not_cleared);
7632 * Apply the given advice to the specified range of addresses within the
7633 * given pmap. Depending on the advice, clear the referenced and/or
7634 * modified flags in each mapping and set the mapped page's dirty field.
7637 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7639 struct rwlock *lock;
7640 pml4_entry_t *pml4e;
7642 pd_entry_t oldpde, *pde;
7643 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7644 vm_offset_t va, va_next;
7648 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7652 * A/D bit emulation requires an alternate code path when clearing
7653 * the modified and accessed bits below. Since this function is
7654 * advisory in nature we skip it entirely for pmaps that require
7655 * A/D bit emulation.
7657 if (pmap_emulate_ad_bits(pmap))
7660 PG_A = pmap_accessed_bit(pmap);
7661 PG_G = pmap_global_bit(pmap);
7662 PG_M = pmap_modified_bit(pmap);
7663 PG_V = pmap_valid_bit(pmap);
7664 PG_RW = pmap_rw_bit(pmap);
7666 pmap_delayed_invl_start();
7668 for (; sva < eva; sva = va_next) {
7669 pml4e = pmap_pml4e(pmap, sva);
7670 if ((*pml4e & PG_V) == 0) {
7671 va_next = (sva + NBPML4) & ~PML4MASK;
7676 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7677 if ((*pdpe & PG_V) == 0) {
7678 va_next = (sva + NBPDP) & ~PDPMASK;
7683 va_next = (sva + NBPDR) & ~PDRMASK;
7686 pde = pmap_pdpe_to_pde(pdpe, sva);
7688 if ((oldpde & PG_V) == 0)
7690 else if ((oldpde & PG_PS) != 0) {
7691 if ((oldpde & PG_MANAGED) == 0)
7694 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7699 * The large page mapping was destroyed.
7705 * Unless the page mappings are wired, remove the
7706 * mapping to a single page so that a subsequent
7707 * access may repromote. Choosing the last page
7708 * within the address range [sva, min(va_next, eva))
7709 * generally results in more repromotions. Since the
7710 * underlying page table page is fully populated, this
7711 * removal never frees a page table page.
7713 if ((oldpde & PG_W) == 0) {
7719 ("pmap_advise: no address gap"));
7720 pte = pmap_pde_to_pte(pde, va);
7721 KASSERT((*pte & PG_V) != 0,
7722 ("pmap_advise: invalid PTE"));
7723 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7733 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7735 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7737 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7738 if (advice == MADV_DONTNEED) {
7740 * Future calls to pmap_is_modified()
7741 * can be avoided by making the page
7744 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7747 atomic_clear_long(pte, PG_M | PG_A);
7748 } else if ((*pte & PG_A) != 0)
7749 atomic_clear_long(pte, PG_A);
7753 if ((*pte & PG_G) != 0) {
7760 if (va != va_next) {
7761 pmap_invalidate_range(pmap, va, sva);
7766 pmap_invalidate_range(pmap, va, sva);
7769 pmap_invalidate_all(pmap);
7771 pmap_delayed_invl_finish();
7775 * Clear the modify bits on the specified physical page.
7778 pmap_clear_modify(vm_page_t m)
7780 struct md_page *pvh;
7782 pv_entry_t next_pv, pv;
7783 pd_entry_t oldpde, *pde;
7784 pt_entry_t *pte, PG_M, PG_RW;
7785 struct rwlock *lock;
7787 int md_gen, pvh_gen;
7789 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7790 ("pmap_clear_modify: page %p is not managed", m));
7791 VM_OBJECT_ASSERT_WLOCKED(m->object);
7792 KASSERT(!vm_page_xbusied(m),
7793 ("pmap_clear_modify: page %p is exclusive busied", m));
7796 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7797 * If the object containing the page is locked and the page is not
7798 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7800 if ((m->aflags & PGA_WRITEABLE) == 0)
7802 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7803 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7804 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7807 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7809 if (!PMAP_TRYLOCK(pmap)) {
7810 pvh_gen = pvh->pv_gen;
7814 if (pvh_gen != pvh->pv_gen) {
7819 PG_M = pmap_modified_bit(pmap);
7820 PG_RW = pmap_rw_bit(pmap);
7822 pde = pmap_pde(pmap, va);
7824 /* If oldpde has PG_RW set, then it also has PG_M set. */
7825 if ((oldpde & PG_RW) != 0 &&
7826 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
7827 (oldpde & PG_W) == 0) {
7829 * Write protect the mapping to a single page so that
7830 * a subsequent write access may repromote.
7832 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
7833 pte = pmap_pde_to_pte(pde, va);
7834 atomic_clear_long(pte, PG_M | PG_RW);
7836 pmap_invalidate_page(pmap, va);
7840 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7842 if (!PMAP_TRYLOCK(pmap)) {
7843 md_gen = m->md.pv_gen;
7844 pvh_gen = pvh->pv_gen;
7848 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7853 PG_M = pmap_modified_bit(pmap);
7854 PG_RW = pmap_rw_bit(pmap);
7855 pde = pmap_pde(pmap, pv->pv_va);
7856 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7857 " a 2mpage in page %p's pv list", m));
7858 pte = pmap_pde_to_pte(pde, pv->pv_va);
7859 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7860 atomic_clear_long(pte, PG_M);
7861 pmap_invalidate_page(pmap, pv->pv_va);
7869 * Miscellaneous support routines follow
7872 /* Adjust the properties for a leaf page table entry. */
7873 static __inline void
7874 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
7878 opte = *(u_long *)pte;
7880 npte = opte & ~mask;
7882 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
7887 * Map a set of physical memory pages into the kernel virtual
7888 * address space. Return a pointer to where it is mapped. This
7889 * routine is intended to be used for mapping device memory,
7893 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
7895 struct pmap_preinit_mapping *ppim;
7896 vm_offset_t va, offset;
7900 offset = pa & PAGE_MASK;
7901 size = round_page(offset + size);
7902 pa = trunc_page(pa);
7904 if (!pmap_initialized) {
7906 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7907 ppim = pmap_preinit_mapping + i;
7908 if (ppim->va == 0) {
7912 ppim->va = virtual_avail;
7913 virtual_avail += size;
7919 panic("%s: too many preinit mappings", __func__);
7922 * If we have a preinit mapping, re-use it.
7924 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7925 ppim = pmap_preinit_mapping + i;
7926 if (ppim->pa == pa && ppim->sz == size &&
7927 (ppim->mode == mode ||
7928 (flags & MAPDEV_SETATTR) == 0))
7929 return ((void *)(ppim->va + offset));
7932 * If the specified range of physical addresses fits within
7933 * the direct map window, use the direct map.
7935 if (pa < dmaplimit && pa + size <= dmaplimit) {
7936 va = PHYS_TO_DMAP(pa);
7937 if ((flags & MAPDEV_SETATTR) != 0) {
7938 PMAP_LOCK(kernel_pmap);
7939 i = pmap_change_props_locked(va, size,
7940 PROT_NONE, mode, flags);
7941 PMAP_UNLOCK(kernel_pmap);
7945 return ((void *)(va + offset));
7947 va = kva_alloc(size);
7949 panic("%s: Couldn't allocate KVA", __func__);
7951 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7952 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7953 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7954 if ((flags & MAPDEV_FLUSHCACHE) != 0)
7955 pmap_invalidate_cache_range(va, va + tmpsize);
7956 return ((void *)(va + offset));
7960 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7963 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
7968 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7971 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
7975 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7978 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
7983 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7986 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
7987 MAPDEV_FLUSHCACHE));
7991 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7993 struct pmap_preinit_mapping *ppim;
7997 /* If we gave a direct map region in pmap_mapdev, do nothing */
7998 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8000 offset = va & PAGE_MASK;
8001 size = round_page(offset + size);
8002 va = trunc_page(va);
8003 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8004 ppim = pmap_preinit_mapping + i;
8005 if (ppim->va == va && ppim->sz == size) {
8006 if (pmap_initialized)
8012 if (va + size == virtual_avail)
8017 if (pmap_initialized) {
8018 pmap_qremove(va, atop(size));
8024 * Tries to demote a 1GB page mapping.
8027 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8029 pdp_entry_t newpdpe, oldpdpe;
8030 pd_entry_t *firstpde, newpde, *pde;
8031 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8035 PG_A = pmap_accessed_bit(pmap);
8036 PG_M = pmap_modified_bit(pmap);
8037 PG_V = pmap_valid_bit(pmap);
8038 PG_RW = pmap_rw_bit(pmap);
8040 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8042 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8043 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8044 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8045 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8046 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8047 " in pmap %p", va, pmap);
8050 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8051 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8052 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8053 KASSERT((oldpdpe & PG_A) != 0,
8054 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8055 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8056 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8060 * Initialize the page directory page.
8062 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8068 * Demote the mapping.
8073 * Invalidate a stale recursive mapping of the page directory page.
8075 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8077 pmap_pdpe_demotions++;
8078 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8079 " in pmap %p", va, pmap);
8084 * Sets the memory attribute for the specified page.
8087 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8090 m->md.pat_mode = ma;
8093 * If "m" is a normal page, update its direct mapping. This update
8094 * can be relied upon to perform any cache operations that are
8095 * required for data coherence.
8097 if ((m->flags & PG_FICTITIOUS) == 0 &&
8098 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8100 panic("memory attribute change on the direct map failed");
8104 * Changes the specified virtual address range's memory type to that given by
8105 * the parameter "mode". The specified virtual address range must be
8106 * completely contained within either the direct map or the kernel map. If
8107 * the virtual address range is contained within the kernel map, then the
8108 * memory type for each of the corresponding ranges of the direct map is also
8109 * changed. (The corresponding ranges of the direct map are those ranges that
8110 * map the same physical pages as the specified virtual address range.) These
8111 * changes to the direct map are necessary because Intel describes the
8112 * behavior of their processors as "undefined" if two or more mappings to the
8113 * same physical page have different memory types.
8115 * Returns zero if the change completed successfully, and either EINVAL or
8116 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8117 * of the virtual address range was not mapped, and ENOMEM is returned if
8118 * there was insufficient memory available to complete the change. In the
8119 * latter case, the memory type may have been changed on some part of the
8120 * virtual address range or the direct map.
8123 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8127 PMAP_LOCK(kernel_pmap);
8128 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8130 PMAP_UNLOCK(kernel_pmap);
8135 * Changes the specified virtual address range's protections to those
8136 * specified by "prot". Like pmap_change_attr(), protections for aliases
8137 * in the direct map are updated as well. Protections on aliasing mappings may
8138 * be a subset of the requested protections; for example, mappings in the direct
8139 * map are never executable.
8142 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8146 /* Only supported within the kernel map. */
8147 if (va < VM_MIN_KERNEL_ADDRESS)
8150 PMAP_LOCK(kernel_pmap);
8151 error = pmap_change_props_locked(va, size, prot, -1,
8152 MAPDEV_ASSERTVALID);
8153 PMAP_UNLOCK(kernel_pmap);
8158 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8159 int mode, int flags)
8161 vm_offset_t base, offset, tmpva;
8162 vm_paddr_t pa_start, pa_end, pa_end1;
8164 pd_entry_t *pde, pde_bits, pde_mask;
8165 pt_entry_t *pte, pte_bits, pte_mask;
8169 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8170 base = trunc_page(va);
8171 offset = va & PAGE_MASK;
8172 size = round_page(offset + size);
8175 * Only supported on kernel virtual addresses, including the direct
8176 * map but excluding the recursive map.
8178 if (base < DMAP_MIN_ADDRESS)
8182 * Construct our flag sets and masks. "bits" is the subset of
8183 * "mask" that will be set in each modified PTE.
8185 * Mappings in the direct map are never allowed to be executable.
8187 pde_bits = pte_bits = 0;
8188 pde_mask = pte_mask = 0;
8190 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8191 pde_mask |= X86_PG_PDE_CACHE;
8192 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8193 pte_mask |= X86_PG_PTE_CACHE;
8195 if (prot != VM_PROT_NONE) {
8196 if ((prot & VM_PROT_WRITE) != 0) {
8197 pde_bits |= X86_PG_RW;
8198 pte_bits |= X86_PG_RW;
8200 if ((prot & VM_PROT_EXECUTE) == 0 ||
8201 va < VM_MIN_KERNEL_ADDRESS) {
8205 pde_mask |= X86_PG_RW | pg_nx;
8206 pte_mask |= X86_PG_RW | pg_nx;
8210 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8211 * into 4KB pages if required.
8213 for (tmpva = base; tmpva < base + size; ) {
8214 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8215 if (pdpe == NULL || *pdpe == 0) {
8216 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8217 ("%s: addr %#lx is not mapped", __func__, tmpva));
8220 if (*pdpe & PG_PS) {
8222 * If the current 1GB page already has the required
8223 * properties, then we need not demote this page. Just
8224 * increment tmpva to the next 1GB page frame.
8226 if ((*pdpe & pde_mask) == pde_bits) {
8227 tmpva = trunc_1gpage(tmpva) + NBPDP;
8232 * If the current offset aligns with a 1GB page frame
8233 * and there is at least 1GB left within the range, then
8234 * we need not break down this page into 2MB pages.
8236 if ((tmpva & PDPMASK) == 0 &&
8237 tmpva + PDPMASK < base + size) {
8241 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8244 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8246 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8247 ("%s: addr %#lx is not mapped", __func__, tmpva));
8252 * If the current 2MB page already has the required
8253 * properties, then we need not demote this page. Just
8254 * increment tmpva to the next 2MB page frame.
8256 if ((*pde & pde_mask) == pde_bits) {
8257 tmpva = trunc_2mpage(tmpva) + NBPDR;
8262 * If the current offset aligns with a 2MB page frame
8263 * and there is at least 2MB left within the range, then
8264 * we need not break down this page into 4KB pages.
8266 if ((tmpva & PDRMASK) == 0 &&
8267 tmpva + PDRMASK < base + size) {
8271 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8274 pte = pmap_pde_to_pte(pde, tmpva);
8276 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8277 ("%s: addr %#lx is not mapped", __func__, tmpva));
8285 * Ok, all the pages exist, so run through them updating their
8286 * properties if required.
8289 pa_start = pa_end = 0;
8290 for (tmpva = base; tmpva < base + size; ) {
8291 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8292 if (*pdpe & PG_PS) {
8293 if ((*pdpe & pde_mask) != pde_bits) {
8294 pmap_pte_props(pdpe, pde_bits, pde_mask);
8297 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8298 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8299 if (pa_start == pa_end) {
8300 /* Start physical address run. */
8301 pa_start = *pdpe & PG_PS_FRAME;
8302 pa_end = pa_start + NBPDP;
8303 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8306 /* Run ended, update direct map. */
8307 error = pmap_change_props_locked(
8308 PHYS_TO_DMAP(pa_start),
8309 pa_end - pa_start, prot, mode,
8313 /* Start physical address run. */
8314 pa_start = *pdpe & PG_PS_FRAME;
8315 pa_end = pa_start + NBPDP;
8318 tmpva = trunc_1gpage(tmpva) + NBPDP;
8321 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8323 if ((*pde & pde_mask) != pde_bits) {
8324 pmap_pte_props(pde, pde_bits, pde_mask);
8327 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8328 (*pde & PG_PS_FRAME) < dmaplimit) {
8329 if (pa_start == pa_end) {
8330 /* Start physical address run. */
8331 pa_start = *pde & PG_PS_FRAME;
8332 pa_end = pa_start + NBPDR;
8333 } else if (pa_end == (*pde & PG_PS_FRAME))
8336 /* Run ended, update direct map. */
8337 error = pmap_change_props_locked(
8338 PHYS_TO_DMAP(pa_start),
8339 pa_end - pa_start, prot, mode,
8343 /* Start physical address run. */
8344 pa_start = *pde & PG_PS_FRAME;
8345 pa_end = pa_start + NBPDR;
8348 tmpva = trunc_2mpage(tmpva) + NBPDR;
8350 pte = pmap_pde_to_pte(pde, tmpva);
8351 if ((*pte & pte_mask) != pte_bits) {
8352 pmap_pte_props(pte, pte_bits, pte_mask);
8355 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8356 (*pte & PG_FRAME) < dmaplimit) {
8357 if (pa_start == pa_end) {
8358 /* Start physical address run. */
8359 pa_start = *pte & PG_FRAME;
8360 pa_end = pa_start + PAGE_SIZE;
8361 } else if (pa_end == (*pte & PG_FRAME))
8362 pa_end += PAGE_SIZE;
8364 /* Run ended, update direct map. */
8365 error = pmap_change_props_locked(
8366 PHYS_TO_DMAP(pa_start),
8367 pa_end - pa_start, prot, mode,
8371 /* Start physical address run. */
8372 pa_start = *pte & PG_FRAME;
8373 pa_end = pa_start + PAGE_SIZE;
8379 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8380 pa_end1 = MIN(pa_end, dmaplimit);
8381 if (pa_start != pa_end1)
8382 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
8383 pa_end1 - pa_start, prot, mode, flags);
8387 * Flush CPU caches if required to make sure any data isn't cached that
8388 * shouldn't be, etc.
8391 pmap_invalidate_range(kernel_pmap, base, tmpva);
8392 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8393 pmap_invalidate_cache_range(base, tmpva);
8399 * Demotes any mapping within the direct map region that covers more than the
8400 * specified range of physical addresses. This range's size must be a power
8401 * of two and its starting address must be a multiple of its size. Since the
8402 * demotion does not change any attributes of the mapping, a TLB invalidation
8403 * is not mandatory. The caller may, however, request a TLB invalidation.
8406 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8415 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8416 KASSERT((base & (len - 1)) == 0,
8417 ("pmap_demote_DMAP: base is not a multiple of len"));
8418 if (len < NBPDP && base < dmaplimit) {
8419 va = PHYS_TO_DMAP(base);
8421 PMAP_LOCK(kernel_pmap);
8422 pdpe = pmap_pdpe(kernel_pmap, va);
8423 if ((*pdpe & X86_PG_V) == 0)
8424 panic("pmap_demote_DMAP: invalid PDPE");
8425 if ((*pdpe & PG_PS) != 0) {
8426 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8427 panic("pmap_demote_DMAP: PDPE failed");
8431 pde = pmap_pdpe_to_pde(pdpe, va);
8432 if ((*pde & X86_PG_V) == 0)
8433 panic("pmap_demote_DMAP: invalid PDE");
8434 if ((*pde & PG_PS) != 0) {
8435 if (!pmap_demote_pde(kernel_pmap, pde, va))
8436 panic("pmap_demote_DMAP: PDE failed");
8440 if (changed && invalidate)
8441 pmap_invalidate_page(kernel_pmap, va);
8442 PMAP_UNLOCK(kernel_pmap);
8447 * perform the pmap work for mincore
8450 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8453 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8457 PG_A = pmap_accessed_bit(pmap);
8458 PG_M = pmap_modified_bit(pmap);
8459 PG_V = pmap_valid_bit(pmap);
8460 PG_RW = pmap_rw_bit(pmap);
8464 pdep = pmap_pde(pmap, addr);
8465 if (pdep != NULL && (*pdep & PG_V)) {
8466 if (*pdep & PG_PS) {
8468 /* Compute the physical address of the 4KB page. */
8469 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8471 val = MINCORE_SUPER;
8473 pte = *pmap_pde_to_pte(pdep, addr);
8474 pa = pte & PG_FRAME;
8482 if ((pte & PG_V) != 0) {
8483 val |= MINCORE_INCORE;
8484 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8485 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8486 if ((pte & PG_A) != 0)
8487 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8489 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8490 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8491 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8492 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8493 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8496 PA_UNLOCK_COND(*locked_pa);
8502 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8504 uint32_t gen, new_gen, pcid_next;
8506 CRITICAL_ASSERT(curthread);
8507 gen = PCPU_GET(pcid_gen);
8508 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8509 return (pti ? 0 : CR3_PCID_SAVE);
8510 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8511 return (CR3_PCID_SAVE);
8512 pcid_next = PCPU_GET(pcid_next);
8513 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8514 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8515 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8516 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8517 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8521 PCPU_SET(pcid_gen, new_gen);
8522 pcid_next = PMAP_PCID_KERN + 1;
8526 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8527 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8528 PCPU_SET(pcid_next, pcid_next + 1);
8533 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8537 cached = pmap_pcid_alloc(pmap, cpuid);
8538 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8539 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8540 pmap->pm_pcids[cpuid].pm_pcid));
8541 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8542 pmap == kernel_pmap,
8543 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8544 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8549 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8552 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8553 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
8557 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8559 struct invpcid_descr d;
8560 uint64_t cached, cr3, kcr3, ucr3;
8562 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8564 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8565 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8566 PCPU_SET(curpmap, pmap);
8567 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8568 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8571 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8573 * Explicitly invalidate translations cached from the
8574 * user page table. They are not automatically
8575 * flushed by reload of cr3 with the kernel page table
8578 * Note that the if() condition is resolved statically
8579 * by using the function argument instead of
8580 * runtime-evaluated invpcid_works value.
8582 if (invpcid_works1) {
8583 d.pcid = PMAP_PCID_USER_PT |
8584 pmap->pm_pcids[cpuid].pm_pcid;
8587 invpcid(&d, INVPCID_CTX);
8589 pmap_pti_pcid_invalidate(ucr3, kcr3);
8593 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8594 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8596 PCPU_INC(pm_save_cnt);
8600 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8603 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8604 pmap_activate_sw_pti_post(td, pmap);
8608 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8614 * If the INVPCID instruction is not available,
8615 * invltlb_pcid_handler() is used to handle an invalidate_all
8616 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8617 * sequence of operations has a window where %CR3 is loaded
8618 * with the new pmap's PML4 address, but the curpmap value has
8619 * not yet been updated. This causes the invltlb IPI handler,
8620 * which is called between the updates, to execute as a NOP,
8621 * which leaves stale TLB entries.
8623 * Note that the most typical use of pmap_activate_sw(), from
8624 * the context switch, is immune to this race, because
8625 * interrupts are disabled (while the thread lock is owned),
8626 * and the IPI happens after curpmap is updated. Protect
8627 * other callers in a similar way, by disabling interrupts
8628 * around the %cr3 register reload and curpmap assignment.
8630 rflags = intr_disable();
8631 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8632 intr_restore(rflags);
8633 pmap_activate_sw_pti_post(td, pmap);
8637 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8640 uint64_t cached, cr3;
8642 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8644 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8645 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8647 PCPU_SET(curpmap, pmap);
8649 PCPU_INC(pm_save_cnt);
8653 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8658 rflags = intr_disable();
8659 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8660 intr_restore(rflags);
8664 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8665 u_int cpuid __unused)
8668 load_cr3(pmap->pm_cr3);
8669 PCPU_SET(curpmap, pmap);
8673 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8674 u_int cpuid __unused)
8677 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8678 PCPU_SET(kcr3, pmap->pm_cr3);
8679 PCPU_SET(ucr3, pmap->pm_ucr3);
8680 pmap_activate_sw_pti_post(td, pmap);
8683 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8687 if (pmap_pcid_enabled && pti && invpcid_works)
8688 return (pmap_activate_sw_pcid_invpcid_pti);
8689 else if (pmap_pcid_enabled && pti && !invpcid_works)
8690 return (pmap_activate_sw_pcid_noinvpcid_pti);
8691 else if (pmap_pcid_enabled && !pti && invpcid_works)
8692 return (pmap_activate_sw_pcid_nopti);
8693 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8694 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8695 else if (!pmap_pcid_enabled && pti)
8696 return (pmap_activate_sw_nopcid_pti);
8697 else /* if (!pmap_pcid_enabled && !pti) */
8698 return (pmap_activate_sw_nopcid_nopti);
8702 pmap_activate_sw(struct thread *td)
8704 pmap_t oldpmap, pmap;
8707 oldpmap = PCPU_GET(curpmap);
8708 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8709 if (oldpmap == pmap) {
8710 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8714 cpuid = PCPU_GET(cpuid);
8716 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8718 CPU_SET(cpuid, &pmap->pm_active);
8720 pmap_activate_sw_mode(td, pmap, cpuid);
8722 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8724 CPU_CLR(cpuid, &oldpmap->pm_active);
8729 pmap_activate(struct thread *td)
8733 pmap_activate_sw(td);
8738 pmap_activate_boot(pmap_t pmap)
8744 * kernel_pmap must be never deactivated, and we ensure that
8745 * by never activating it at all.
8747 MPASS(pmap != kernel_pmap);
8749 cpuid = PCPU_GET(cpuid);
8751 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8753 CPU_SET(cpuid, &pmap->pm_active);
8755 PCPU_SET(curpmap, pmap);
8757 kcr3 = pmap->pm_cr3;
8758 if (pmap_pcid_enabled)
8759 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8763 PCPU_SET(kcr3, kcr3);
8764 PCPU_SET(ucr3, PMAP_NO_CR3);
8768 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8773 * Increase the starting virtual address of the given mapping if a
8774 * different alignment might result in more superpage mappings.
8777 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8778 vm_offset_t *addr, vm_size_t size)
8780 vm_offset_t superpage_offset;
8784 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8785 offset += ptoa(object->pg_color);
8786 superpage_offset = offset & PDRMASK;
8787 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8788 (*addr & PDRMASK) == superpage_offset)
8790 if ((*addr & PDRMASK) < superpage_offset)
8791 *addr = (*addr & ~PDRMASK) + superpage_offset;
8793 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8797 static unsigned long num_dirty_emulations;
8798 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8799 &num_dirty_emulations, 0, NULL);
8801 static unsigned long num_accessed_emulations;
8802 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8803 &num_accessed_emulations, 0, NULL);
8805 static unsigned long num_superpage_accessed_emulations;
8806 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8807 &num_superpage_accessed_emulations, 0, NULL);
8809 static unsigned long ad_emulation_superpage_promotions;
8810 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8811 &ad_emulation_superpage_promotions, 0, NULL);
8812 #endif /* INVARIANTS */
8815 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8818 struct rwlock *lock;
8819 #if VM_NRESERVLEVEL > 0
8823 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8825 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8826 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8828 if (!pmap_emulate_ad_bits(pmap))
8831 PG_A = pmap_accessed_bit(pmap);
8832 PG_M = pmap_modified_bit(pmap);
8833 PG_V = pmap_valid_bit(pmap);
8834 PG_RW = pmap_rw_bit(pmap);
8840 pde = pmap_pde(pmap, va);
8841 if (pde == NULL || (*pde & PG_V) == 0)
8844 if ((*pde & PG_PS) != 0) {
8845 if (ftype == VM_PROT_READ) {
8847 atomic_add_long(&num_superpage_accessed_emulations, 1);
8855 pte = pmap_pde_to_pte(pde, va);
8856 if ((*pte & PG_V) == 0)
8859 if (ftype == VM_PROT_WRITE) {
8860 if ((*pte & PG_RW) == 0)
8863 * Set the modified and accessed bits simultaneously.
8865 * Intel EPT PTEs that do software emulation of A/D bits map
8866 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8867 * An EPT misconfiguration is triggered if the PTE is writable
8868 * but not readable (WR=10). This is avoided by setting PG_A
8869 * and PG_M simultaneously.
8871 *pte |= PG_M | PG_A;
8876 #if VM_NRESERVLEVEL > 0
8877 /* try to promote the mapping */
8878 if (va < VM_MAXUSER_ADDRESS)
8879 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8883 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8885 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8886 pmap_ps_enabled(pmap) &&
8887 (m->flags & PG_FICTITIOUS) == 0 &&
8888 vm_reserv_level_iffullpop(m) == 0) {
8889 pmap_promote_pde(pmap, pde, va, &lock);
8891 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8897 if (ftype == VM_PROT_WRITE)
8898 atomic_add_long(&num_dirty_emulations, 1);
8900 atomic_add_long(&num_accessed_emulations, 1);
8902 rv = 0; /* success */
8911 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8916 pt_entry_t *pte, PG_V;
8920 PG_V = pmap_valid_bit(pmap);
8923 pml4 = pmap_pml4e(pmap, va);
8925 if ((*pml4 & PG_V) == 0)
8928 pdp = pmap_pml4e_to_pdpe(pml4, va);
8930 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8933 pde = pmap_pdpe_to_pde(pdp, va);
8935 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8938 pte = pmap_pde_to_pte(pde, va);
8947 * Get the kernel virtual address of a set of physical pages. If there are
8948 * physical addresses not covered by the DMAP perform a transient mapping
8949 * that will be removed when calling pmap_unmap_io_transient.
8951 * \param page The pages the caller wishes to obtain the virtual
8952 * address on the kernel memory map.
8953 * \param vaddr On return contains the kernel virtual memory address
8954 * of the pages passed in the page parameter.
8955 * \param count Number of pages passed in.
8956 * \param can_fault TRUE if the thread using the mapped pages can take
8957 * page faults, FALSE otherwise.
8959 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8960 * finished or FALSE otherwise.
8964 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8965 boolean_t can_fault)
8968 boolean_t needs_mapping;
8970 int cache_bits, error __unused, i;
8973 * Allocate any KVA space that we need, this is done in a separate
8974 * loop to prevent calling vmem_alloc while pinned.
8976 needs_mapping = FALSE;
8977 for (i = 0; i < count; i++) {
8978 paddr = VM_PAGE_TO_PHYS(page[i]);
8979 if (__predict_false(paddr >= dmaplimit)) {
8980 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8981 M_BESTFIT | M_WAITOK, &vaddr[i]);
8982 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8983 needs_mapping = TRUE;
8985 vaddr[i] = PHYS_TO_DMAP(paddr);
8989 /* Exit early if everything is covered by the DMAP */
8994 * NB: The sequence of updating a page table followed by accesses
8995 * to the corresponding pages used in the !DMAP case is subject to
8996 * the situation described in the "AMD64 Architecture Programmer's
8997 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8998 * Coherency Considerations". Therefore, issuing the INVLPG right
8999 * after modifying the PTE bits is crucial.
9003 for (i = 0; i < count; i++) {
9004 paddr = VM_PAGE_TO_PHYS(page[i]);
9005 if (paddr >= dmaplimit) {
9008 * Slow path, since we can get page faults
9009 * while mappings are active don't pin the
9010 * thread to the CPU and instead add a global
9011 * mapping visible to all CPUs.
9013 pmap_qenter(vaddr[i], &page[i], 1);
9015 pte = vtopte(vaddr[i]);
9016 cache_bits = pmap_cache_bits(kernel_pmap,
9017 page[i]->md.pat_mode, 0);
9018 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9025 return (needs_mapping);
9029 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9030 boolean_t can_fault)
9037 for (i = 0; i < count; i++) {
9038 paddr = VM_PAGE_TO_PHYS(page[i]);
9039 if (paddr >= dmaplimit) {
9041 pmap_qremove(vaddr[i], 1);
9042 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9048 pmap_quick_enter_page(vm_page_t m)
9052 paddr = VM_PAGE_TO_PHYS(m);
9053 if (paddr < dmaplimit)
9054 return (PHYS_TO_DMAP(paddr));
9055 mtx_lock_spin(&qframe_mtx);
9056 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9057 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9058 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9063 pmap_quick_remove_page(vm_offset_t addr)
9068 pte_store(vtopte(qframe), 0);
9070 mtx_unlock_spin(&qframe_mtx);
9074 * Pdp pages from the large map are managed differently from either
9075 * kernel or user page table pages. They are permanently allocated at
9076 * initialization time, and their wire count is permanently set to
9077 * zero. The pml4 entries pointing to those pages are copied into
9078 * each allocated pmap.
9080 * In contrast, pd and pt pages are managed like user page table
9081 * pages. They are dynamically allocated, and their wire count
9082 * represents the number of valid entries within the page.
9085 pmap_large_map_getptp_unlocked(void)
9089 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9091 if (m != NULL && (m->flags & PG_ZERO) == 0)
9097 pmap_large_map_getptp(void)
9101 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9102 m = pmap_large_map_getptp_unlocked();
9104 PMAP_UNLOCK(kernel_pmap);
9106 PMAP_LOCK(kernel_pmap);
9107 /* Callers retry. */
9112 static pdp_entry_t *
9113 pmap_large_map_pdpe(vm_offset_t va)
9115 vm_pindex_t pml4_idx;
9118 pml4_idx = pmap_pml4e_index(va);
9119 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9120 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9122 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9123 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
9124 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9125 "LMSPML4I %#jx lm_ents %d",
9126 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9127 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
9128 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9132 pmap_large_map_pde(vm_offset_t va)
9139 pdpe = pmap_large_map_pdpe(va);
9141 m = pmap_large_map_getptp();
9144 mphys = VM_PAGE_TO_PHYS(m);
9145 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9147 MPASS((*pdpe & X86_PG_PS) == 0);
9148 mphys = *pdpe & PG_FRAME;
9150 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9154 pmap_large_map_pte(vm_offset_t va)
9161 pde = pmap_large_map_pde(va);
9163 m = pmap_large_map_getptp();
9166 mphys = VM_PAGE_TO_PHYS(m);
9167 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9168 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
9170 MPASS((*pde & X86_PG_PS) == 0);
9171 mphys = *pde & PG_FRAME;
9173 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9177 pmap_large_map_kextract(vm_offset_t va)
9179 pdp_entry_t *pdpe, pdp;
9180 pd_entry_t *pde, pd;
9181 pt_entry_t *pte, pt;
9183 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9184 ("not largemap range %#lx", (u_long)va));
9185 pdpe = pmap_large_map_pdpe(va);
9187 KASSERT((pdp & X86_PG_V) != 0,
9188 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9189 (u_long)pdpe, pdp));
9190 if ((pdp & X86_PG_PS) != 0) {
9191 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9192 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9193 (u_long)pdpe, pdp));
9194 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9196 pde = pmap_pdpe_to_pde(pdpe, va);
9198 KASSERT((pd & X86_PG_V) != 0,
9199 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9200 if ((pd & X86_PG_PS) != 0)
9201 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9202 pte = pmap_pde_to_pte(pde, va);
9204 KASSERT((pt & X86_PG_V) != 0,
9205 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9206 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9210 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9211 vmem_addr_t *vmem_res)
9215 * Large mappings are all but static. Consequently, there
9216 * is no point in waiting for an earlier allocation to be
9219 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9220 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9224 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9230 vm_offset_t va, inc;
9231 vmem_addr_t vmem_res;
9235 if (len == 0 || spa + len < spa)
9238 /* See if DMAP can serve. */
9239 if (spa + len <= dmaplimit) {
9240 va = PHYS_TO_DMAP(spa);
9242 return (pmap_change_attr(va, len, mattr));
9246 * No, allocate KVA. Fit the address with best possible
9247 * alignment for superpages. Fall back to worse align if
9251 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9252 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9253 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9255 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9257 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9260 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9265 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9266 * in the pagetable to minimize flushing. No need to
9267 * invalidate TLB, since we only update invalid entries.
9269 PMAP_LOCK(kernel_pmap);
9270 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9272 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9273 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9274 pdpe = pmap_large_map_pdpe(va);
9276 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9277 X86_PG_V | X86_PG_A | pg_nx |
9278 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9280 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9281 (va & PDRMASK) == 0) {
9282 pde = pmap_large_map_pde(va);
9284 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9285 X86_PG_V | X86_PG_A | pg_nx |
9286 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9287 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9291 pte = pmap_large_map_pte(va);
9293 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9294 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9296 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9301 PMAP_UNLOCK(kernel_pmap);
9304 *addr = (void *)vmem_res;
9309 pmap_large_unmap(void *svaa, vm_size_t len)
9311 vm_offset_t sva, va;
9313 pdp_entry_t *pdpe, pdp;
9314 pd_entry_t *pde, pd;
9317 struct spglist spgf;
9319 sva = (vm_offset_t)svaa;
9320 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9321 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9325 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9326 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9327 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9328 PMAP_LOCK(kernel_pmap);
9329 for (va = sva; va < sva + len; va += inc) {
9330 pdpe = pmap_large_map_pdpe(va);
9332 KASSERT((pdp & X86_PG_V) != 0,
9333 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9334 (u_long)pdpe, pdp));
9335 if ((pdp & X86_PG_PS) != 0) {
9336 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9337 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9338 (u_long)pdpe, pdp));
9339 KASSERT((va & PDPMASK) == 0,
9340 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9341 (u_long)pdpe, pdp));
9342 KASSERT(va + NBPDP <= sva + len,
9343 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9344 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9345 (u_long)pdpe, pdp, len));
9350 pde = pmap_pdpe_to_pde(pdpe, va);
9352 KASSERT((pd & X86_PG_V) != 0,
9353 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9355 if ((pd & X86_PG_PS) != 0) {
9356 KASSERT((va & PDRMASK) == 0,
9357 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9359 KASSERT(va + NBPDR <= sva + len,
9360 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9361 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9365 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9367 if (m->wire_count == 0) {
9369 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9373 pte = pmap_pde_to_pte(pde, va);
9374 KASSERT((*pte & X86_PG_V) != 0,
9375 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9376 (u_long)pte, *pte));
9379 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9381 if (m->wire_count == 0) {
9383 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9384 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9386 if (m->wire_count == 0) {
9388 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9392 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9393 PMAP_UNLOCK(kernel_pmap);
9394 vm_page_free_pages_toq(&spgf, false);
9395 vmem_free(large_vmem, sva, len);
9399 pmap_large_map_wb_fence_mfence(void)
9406 pmap_large_map_wb_fence_atomic(void)
9409 atomic_thread_fence_seq_cst();
9413 pmap_large_map_wb_fence_nop(void)
9417 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void), static)
9420 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9421 return (pmap_large_map_wb_fence_mfence);
9422 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9423 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9424 return (pmap_large_map_wb_fence_atomic);
9426 /* clflush is strongly enough ordered */
9427 return (pmap_large_map_wb_fence_nop);
9431 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9434 for (; len > 0; len -= cpu_clflush_line_size,
9435 va += cpu_clflush_line_size)
9440 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9443 for (; len > 0; len -= cpu_clflush_line_size,
9444 va += cpu_clflush_line_size)
9449 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9452 for (; len > 0; len -= cpu_clflush_line_size,
9453 va += cpu_clflush_line_size)
9458 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9462 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t),
9466 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9467 return (pmap_large_map_flush_range_clwb);
9468 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9469 return (pmap_large_map_flush_range_clflushopt);
9470 else if ((cpu_feature & CPUID_CLFSH) != 0)
9471 return (pmap_large_map_flush_range_clflush);
9473 return (pmap_large_map_flush_range_nop);
9477 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9479 volatile u_long *pe;
9485 for (va = sva; va < eva; va += inc) {
9487 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9488 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9490 if ((p & X86_PG_PS) != 0)
9494 pe = (volatile u_long *)pmap_large_map_pde(va);
9496 if ((p & X86_PG_PS) != 0)
9500 pe = (volatile u_long *)pmap_large_map_pte(va);
9506 if ((p & X86_PG_AVAIL1) != 0) {
9508 * Spin-wait for the end of a parallel
9515 * If we saw other write-back
9516 * occuring, we cannot rely on PG_M to
9517 * indicate state of the cache. The
9518 * PG_M bit is cleared before the
9519 * flush to avoid ignoring new writes,
9520 * and writes which are relevant for
9521 * us might happen after.
9527 if ((p & X86_PG_M) != 0 || seen_other) {
9528 if (!atomic_fcmpset_long(pe, &p,
9529 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9531 * If we saw PG_M without
9532 * PG_AVAIL1, and then on the
9533 * next attempt we do not
9534 * observe either PG_M or
9535 * PG_AVAIL1, the other
9536 * write-back started after us
9537 * and finished before us. We
9538 * can rely on it doing our
9542 pmap_large_map_flush_range(va, inc);
9543 atomic_clear_long(pe, X86_PG_AVAIL1);
9552 * Write-back cache lines for the given address range.
9554 * Must be called only on the range or sub-range returned from
9555 * pmap_large_map(). Must not be called on the coalesced ranges.
9557 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9558 * instructions support.
9561 pmap_large_map_wb(void *svap, vm_size_t len)
9563 vm_offset_t eva, sva;
9565 sva = (vm_offset_t)svap;
9567 pmap_large_map_wb_fence();
9568 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9569 pmap_large_map_flush_range(sva, len);
9571 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9572 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9573 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9574 pmap_large_map_wb_large(sva, eva);
9576 pmap_large_map_wb_fence();
9580 pmap_pti_alloc_page(void)
9584 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9585 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9586 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9591 pmap_pti_free_page(vm_page_t m)
9594 KASSERT(m->wire_count > 0, ("page %p not wired", m));
9595 if (!vm_page_unwire_noq(m))
9597 vm_page_free_zero(m);
9611 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9612 VM_OBJECT_WLOCK(pti_obj);
9613 pml4_pg = pmap_pti_alloc_page();
9614 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9615 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9616 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9617 pdpe = pmap_pti_pdpe(va);
9618 pmap_pti_wire_pte(pdpe);
9620 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9621 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9622 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9623 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9624 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9625 sizeof(struct gate_descriptor) * NIDT, false);
9626 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9627 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9629 /* Doublefault stack IST 1 */
9630 va = common_tss[i].tss_ist1;
9631 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9632 /* NMI stack IST 2 */
9633 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9634 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9635 /* MC# stack IST 3 */
9636 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9637 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9638 /* DB# stack IST 4 */
9639 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9640 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9642 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9643 (vm_offset_t)etext, true);
9644 pti_finalized = true;
9645 VM_OBJECT_WUNLOCK(pti_obj);
9647 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9649 static pdp_entry_t *
9650 pmap_pti_pdpe(vm_offset_t va)
9652 pml4_entry_t *pml4e;
9655 vm_pindex_t pml4_idx;
9658 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9660 pml4_idx = pmap_pml4e_index(va);
9661 pml4e = &pti_pml4[pml4_idx];
9665 panic("pml4 alloc after finalization\n");
9666 m = pmap_pti_alloc_page();
9668 pmap_pti_free_page(m);
9669 mphys = *pml4e & ~PAGE_MASK;
9671 mphys = VM_PAGE_TO_PHYS(m);
9672 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9675 mphys = *pml4e & ~PAGE_MASK;
9677 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9682 pmap_pti_wire_pte(void *pte)
9686 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9687 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9692 pmap_pti_unwire_pde(void *pde, bool only_ref)
9696 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9697 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9698 MPASS(m->wire_count > 0);
9699 MPASS(only_ref || m->wire_count > 1);
9700 pmap_pti_free_page(m);
9704 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9709 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9710 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9711 MPASS(m->wire_count > 0);
9712 if (pmap_pti_free_page(m)) {
9713 pde = pmap_pti_pde(va);
9714 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9716 pmap_pti_unwire_pde(pde, false);
9721 pmap_pti_pde(vm_offset_t va)
9729 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9731 pdpe = pmap_pti_pdpe(va);
9733 m = pmap_pti_alloc_page();
9735 pmap_pti_free_page(m);
9736 MPASS((*pdpe & X86_PG_PS) == 0);
9737 mphys = *pdpe & ~PAGE_MASK;
9739 mphys = VM_PAGE_TO_PHYS(m);
9740 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9743 MPASS((*pdpe & X86_PG_PS) == 0);
9744 mphys = *pdpe & ~PAGE_MASK;
9747 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9748 pd_idx = pmap_pde_index(va);
9754 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9761 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9763 pde = pmap_pti_pde(va);
9764 if (unwire_pde != NULL) {
9766 pmap_pti_wire_pte(pde);
9769 m = pmap_pti_alloc_page();
9771 pmap_pti_free_page(m);
9772 MPASS((*pde & X86_PG_PS) == 0);
9773 mphys = *pde & ~(PAGE_MASK | pg_nx);
9775 mphys = VM_PAGE_TO_PHYS(m);
9776 *pde = mphys | X86_PG_RW | X86_PG_V;
9777 if (unwire_pde != NULL)
9778 *unwire_pde = false;
9781 MPASS((*pde & X86_PG_PS) == 0);
9782 mphys = *pde & ~(PAGE_MASK | pg_nx);
9785 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9786 pte += pmap_pte_index(va);
9792 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9796 pt_entry_t *pte, ptev;
9799 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9801 sva = trunc_page(sva);
9802 MPASS(sva > VM_MAXUSER_ADDRESS);
9803 eva = round_page(eva);
9805 for (; sva < eva; sva += PAGE_SIZE) {
9806 pte = pmap_pti_pte(sva, &unwire_pde);
9807 pa = pmap_kextract(sva);
9808 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9809 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9810 VM_MEMATTR_DEFAULT, FALSE);
9812 pte_store(pte, ptev);
9813 pmap_pti_wire_pte(pte);
9815 KASSERT(!pti_finalized,
9816 ("pti overlap after fin %#lx %#lx %#lx",
9818 KASSERT(*pte == ptev,
9819 ("pti non-identical pte after fin %#lx %#lx %#lx",
9823 pde = pmap_pti_pde(sva);
9824 pmap_pti_unwire_pde(pde, true);
9830 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9835 VM_OBJECT_WLOCK(pti_obj);
9836 pmap_pti_add_kva_locked(sva, eva, exec);
9837 VM_OBJECT_WUNLOCK(pti_obj);
9841 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9848 sva = rounddown2(sva, PAGE_SIZE);
9849 MPASS(sva > VM_MAXUSER_ADDRESS);
9850 eva = roundup2(eva, PAGE_SIZE);
9852 VM_OBJECT_WLOCK(pti_obj);
9853 for (va = sva; va < eva; va += PAGE_SIZE) {
9854 pte = pmap_pti_pte(va, NULL);
9855 KASSERT((*pte & X86_PG_V) != 0,
9856 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9857 (u_long)pte, *pte));
9859 pmap_pti_unwire_pte(pte, va);
9861 pmap_invalidate_range(kernel_pmap, sva, eva);
9862 VM_OBJECT_WUNLOCK(pti_obj);
9866 pkru_dup_range(void *ctx __unused, void *data)
9868 struct pmap_pkru_range *node, *new_node;
9870 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9871 if (new_node == NULL)
9874 memcpy(new_node, node, sizeof(*node));
9879 pkru_free_range(void *ctx __unused, void *node)
9882 uma_zfree(pmap_pkru_ranges_zone, node);
9886 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9889 struct pmap_pkru_range *ppr;
9892 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9893 MPASS(pmap->pm_type == PT_X86);
9894 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9895 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9896 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9898 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9901 ppr->pkru_keyidx = keyidx;
9902 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9903 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9905 uma_zfree(pmap_pkru_ranges_zone, ppr);
9910 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9913 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9914 MPASS(pmap->pm_type == PT_X86);
9915 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9916 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9920 pmap_pkru_deassign_all(pmap_t pmap)
9923 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9924 if (pmap->pm_type == PT_X86 &&
9925 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9926 rangeset_remove_all(&pmap->pm_pkru);
9930 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9932 struct pmap_pkru_range *ppr, *prev_ppr;
9935 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9936 if (pmap->pm_type != PT_X86 ||
9937 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9938 sva >= VM_MAXUSER_ADDRESS)
9940 MPASS(eva <= VM_MAXUSER_ADDRESS);
9941 for (va = sva, prev_ppr = NULL; va < eva;) {
9942 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9943 if ((ppr == NULL) ^ (prev_ppr == NULL))
9949 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9951 va = ppr->pkru_rs_el.re_end;
9957 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9959 struct pmap_pkru_range *ppr;
9961 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9962 if (pmap->pm_type != PT_X86 ||
9963 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9964 va >= VM_MAXUSER_ADDRESS)
9966 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9968 return (X86_PG_PKU(ppr->pkru_keyidx));
9973 pred_pkru_on_remove(void *ctx __unused, void *r)
9975 struct pmap_pkru_range *ppr;
9978 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9982 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9985 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9986 if (pmap->pm_type == PT_X86 &&
9987 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9988 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9989 pred_pkru_on_remove);
9994 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9997 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9998 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9999 MPASS(dst_pmap->pm_type == PT_X86);
10000 MPASS(src_pmap->pm_type == PT_X86);
10001 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10002 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10004 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10008 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10011 pml4_entry_t *pml4e;
10013 pd_entry_t newpde, ptpaddr, *pde;
10014 pt_entry_t newpte, *ptep, pte;
10015 vm_offset_t va, va_next;
10018 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10019 MPASS(pmap->pm_type == PT_X86);
10020 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10022 for (changed = false, va = sva; va < eva; va = va_next) {
10023 pml4e = pmap_pml4e(pmap, va);
10024 if ((*pml4e & X86_PG_V) == 0) {
10025 va_next = (va + NBPML4) & ~PML4MASK;
10031 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10032 if ((*pdpe & X86_PG_V) == 0) {
10033 va_next = (va + NBPDP) & ~PDPMASK;
10039 va_next = (va + NBPDR) & ~PDRMASK;
10043 pde = pmap_pdpe_to_pde(pdpe, va);
10048 MPASS((ptpaddr & X86_PG_V) != 0);
10049 if ((ptpaddr & PG_PS) != 0) {
10050 if (va + NBPDR == va_next && eva >= va_next) {
10051 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10052 X86_PG_PKU(keyidx);
10053 if (newpde != ptpaddr) {
10058 } else if (!pmap_demote_pde(pmap, pde, va)) {
10066 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10067 ptep++, va += PAGE_SIZE) {
10069 if ((pte & X86_PG_V) == 0)
10071 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10072 if (newpte != pte) {
10079 pmap_invalidate_range(pmap, sva, eva);
10083 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10084 u_int keyidx, int flags)
10087 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10088 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10090 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10092 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10098 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10103 sva = trunc_page(sva);
10104 eva = round_page(eva);
10105 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10110 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10112 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10114 if (error != ENOMEM)
10122 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10126 sva = trunc_page(sva);
10127 eva = round_page(eva);
10128 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10133 error = pmap_pkru_deassign(pmap, sva, eva);
10135 pmap_pkru_update_range(pmap, sva, eva, 0);
10137 if (error != ENOMEM)
10145 * Track a range of the kernel's virtual address space that is contiguous
10146 * in various mapping attributes.
10148 struct pmap_kernel_map_range {
10157 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10163 if (eva <= range->sva)
10166 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10167 for (i = 0; i < PAT_INDEX_SIZE; i++)
10168 if (pat_index[i] == pat_idx)
10172 case PAT_WRITE_BACK:
10175 case PAT_WRITE_THROUGH:
10178 case PAT_UNCACHEABLE:
10184 case PAT_WRITE_PROTECTED:
10187 case PAT_WRITE_COMBINING:
10191 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10192 __func__, pat_idx, range->sva, eva);
10197 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10199 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10200 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10201 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10202 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10203 mode, range->pdpes, range->pdes, range->ptes);
10205 /* Reset to sentinel value. */
10206 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10210 * Determine whether the attributes specified by a page table entry match those
10211 * being tracked by the current range. This is not quite as simple as a direct
10212 * flag comparison since some PAT modes have multiple representations.
10215 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10217 pt_entry_t diff, mask;
10219 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10220 diff = (range->attrs ^ attrs) & mask;
10223 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10224 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10225 pmap_pat_index(kernel_pmap, attrs, true))
10231 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10235 memset(range, 0, sizeof(*range));
10237 range->attrs = attrs;
10241 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10242 * those of the current run, dump the address range and its attributes, and
10246 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10247 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10252 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10254 attrs |= pdpe & pg_nx;
10255 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10256 if ((pdpe & PG_PS) != 0) {
10257 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10258 } else if (pde != 0) {
10259 attrs |= pde & pg_nx;
10260 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10262 if ((pde & PG_PS) != 0) {
10263 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10264 } else if (pte != 0) {
10265 attrs |= pte & pg_nx;
10266 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10267 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10269 /* Canonicalize by always using the PDE PAT bit. */
10270 if ((attrs & X86_PG_PTE_PAT) != 0)
10271 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10274 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10275 sysctl_kmaps_dump(sb, range, va);
10276 sysctl_kmaps_reinit(range, va, attrs);
10281 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10283 struct pmap_kernel_map_range range;
10284 struct sbuf sbuf, *sb;
10285 pml4_entry_t pml4e;
10286 pdp_entry_t *pdp, pdpe;
10287 pd_entry_t *pd, pde;
10288 pt_entry_t *pt, pte;
10291 int error, i, j, k, l;
10293 error = sysctl_wire_old_buffer(req, 0);
10297 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10299 /* Sentinel value. */
10300 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10303 * Iterate over the kernel page tables without holding the kernel pmap
10304 * lock. Outside of the large map, kernel page table pages are never
10305 * freed, so at worst we will observe inconsistencies in the output.
10306 * Within the large map, ensure that PDP and PD page addresses are
10307 * valid before descending.
10309 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10312 sbuf_printf(sb, "\nRecursive map:\n");
10315 sbuf_printf(sb, "\nDirect map:\n");
10318 sbuf_printf(sb, "\nKernel map:\n");
10321 sbuf_printf(sb, "\nLarge map:\n");
10325 /* Convert to canonical form. */
10326 if (sva == 1ul << 47)
10330 pml4e = kernel_pmap->pm_pml4[i];
10331 if ((pml4e & X86_PG_V) == 0) {
10332 sva = rounddown2(sva, NBPML4);
10333 sysctl_kmaps_dump(sb, &range, sva);
10337 pa = pml4e & PG_FRAME;
10338 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10340 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10342 if ((pdpe & X86_PG_V) == 0) {
10343 sva = rounddown2(sva, NBPDP);
10344 sysctl_kmaps_dump(sb, &range, sva);
10348 pa = pdpe & PG_FRAME;
10349 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10350 vm_phys_paddr_to_vm_page(pa) == NULL)
10352 if ((pdpe & PG_PS) != 0) {
10353 sva = rounddown2(sva, NBPDP);
10354 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10360 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10362 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10364 if ((pde & X86_PG_V) == 0) {
10365 sva = rounddown2(sva, NBPDR);
10366 sysctl_kmaps_dump(sb, &range, sva);
10370 pa = pde & PG_FRAME;
10371 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10372 vm_phys_paddr_to_vm_page(pa) == NULL)
10374 if ((pde & PG_PS) != 0) {
10375 sva = rounddown2(sva, NBPDR);
10376 sysctl_kmaps_check(sb, &range, sva,
10377 pml4e, pdpe, pde, 0);
10382 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10384 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10385 sva += PAGE_SIZE) {
10387 if ((pte & X86_PG_V) == 0) {
10388 sysctl_kmaps_dump(sb, &range,
10392 sysctl_kmaps_check(sb, &range, sva,
10393 pml4e, pdpe, pde, pte);
10400 error = sbuf_finish(sb);
10404 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10405 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10406 NULL, 0, sysctl_kmaps, "A",
10407 "Dump kernel address layout");
10410 DB_SHOW_COMMAND(pte, pmap_print_pte)
10413 pml4_entry_t *pml4;
10416 pt_entry_t *pte, PG_V;
10420 db_printf("show pte addr\n");
10423 va = (vm_offset_t)addr;
10425 if (kdb_thread != NULL)
10426 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10428 pmap = PCPU_GET(curpmap);
10430 PG_V = pmap_valid_bit(pmap);
10431 pml4 = pmap_pml4e(pmap, va);
10432 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10433 if ((*pml4 & PG_V) == 0) {
10437 pdp = pmap_pml4e_to_pdpe(pml4, va);
10438 db_printf(" pdpe 0x%016lx", *pdp);
10439 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10443 pde = pmap_pdpe_to_pde(pdp, va);
10444 db_printf(" pde 0x%016lx", *pde);
10445 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10449 pte = pmap_pde_to_pte(pde, va);
10450 db_printf(" pte 0x%016lx\n", *pte);
10453 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10458 a = (vm_paddr_t)addr;
10459 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10461 db_printf("show phys2dmap addr\n");