2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * Since the information managed by this module is
86 * also stored by the logical address mapping module,
87 * this module may throw away valid virtual-to-physical
88 * mappings at almost any time. However, invalidations
89 * of virtual-to-physical mappings must be done as
92 * In order to cope with hardware architectures which
93 * make virtual-to-physical map invalidates expensive,
94 * this module may delay invalidate or reduced protection
95 * operations until such time as they are actually
96 * necessary. This module is given full information as
97 * to which processors are currently using which maps,
98 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
104 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/mutex.h>
113 #include <sys/proc.h>
114 #include <sys/rwlock.h>
116 #include <sys/vmmeter.h>
117 #include <sys/sched.h>
118 #include <sys/sysctl.h>
119 #include <sys/_unrhdr.h>
123 #include <vm/vm_param.h>
124 #include <vm/vm_kern.h>
125 #include <vm/vm_page.h>
126 #include <vm/vm_map.h>
127 #include <vm/vm_object.h>
128 #include <vm/vm_extern.h>
129 #include <vm/vm_pageout.h>
130 #include <vm/vm_pager.h>
131 #include <vm/vm_radix.h>
132 #include <vm/vm_reserv.h>
135 #include <machine/intr_machdep.h>
136 #include <machine/apicvar.h>
137 #include <machine/cpu.h>
138 #include <machine/cputypes.h>
139 #include <machine/md_var.h>
140 #include <machine/pcb.h>
141 #include <machine/specialreg.h>
143 #include <machine/smp.h>
146 #if !defined(DIAGNOSTIC)
147 #ifdef __GNUC_GNU_INLINE__
148 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
150 #define PMAP_INLINE extern inline
157 #define PV_STAT(x) do { x ; } while (0)
159 #define PV_STAT(x) do { } while (0)
162 #define pa_index(pa) ((pa) >> PDRSHIFT)
163 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
165 #define NPV_LIST_LOCKS MAXCPU
167 #define PHYS_TO_PV_LIST_LOCK(pa) \
168 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
170 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
171 struct rwlock **_lockp = (lockp); \
172 struct rwlock *_new_lock; \
174 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
175 if (_new_lock != *_lockp) { \
176 if (*_lockp != NULL) \
177 rw_wunlock(*_lockp); \
178 *_lockp = _new_lock; \
183 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
184 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
186 #define RELEASE_PV_LIST_LOCK(lockp) do { \
187 struct rwlock **_lockp = (lockp); \
189 if (*_lockp != NULL) { \
190 rw_wunlock(*_lockp); \
195 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
196 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
198 struct pmap kernel_pmap_store;
200 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
201 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
204 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
205 "Number of kernel page table pages allocated on bootup");
208 static vm_paddr_t dmaplimit;
209 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
212 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
214 static int pat_works = 1;
215 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
216 "Is page attribute table fully functional?");
218 static int pg_ps_enabled = 1;
219 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
220 "Are large page mappings enabled?");
222 #define PAT_INDEX_SIZE 8
223 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
225 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
226 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
227 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
228 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
230 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
231 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
232 static int ndmpdpphys; /* number of DMPDPphys pages */
234 static struct rwlock_padalign pvh_global_lock;
237 * Data for the pv entry allocation mechanism
239 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
240 static struct mtx pv_chunks_mutex;
241 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
242 static struct md_page *pv_table;
245 * All those kernel PT submaps that BSD is so fond of
247 pt_entry_t *CMAP1 = 0;
250 static struct unrhdr pcid_unr;
251 static struct mtx pcid_mtx;
252 int pmap_pcid_enabled = 1;
253 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN, &pmap_pcid_enabled,
254 0, "Is TLB Context ID enabled ?");
255 int invpcid_works = 0;
258 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
265 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
267 return (sysctl_handle_64(oidp, &res, 0, req));
269 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
270 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
271 "Count of saved TLB context on switch");
276 static caddr_t crashdumpmap;
278 static void free_pv_chunk(struct pv_chunk *pc);
279 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
280 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
281 static int popcnt_pc_map_elem(uint64_t elem);
282 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
283 static void reserve_pv_entries(pmap_t pmap, int needed,
284 struct rwlock **lockp);
285 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
286 struct rwlock **lockp);
287 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
288 struct rwlock **lockp);
289 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
290 struct rwlock **lockp);
291 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
292 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
295 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
296 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
297 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
298 vm_offset_t va, struct rwlock **lockp);
299 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
301 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
302 vm_prot_t prot, struct rwlock **lockp);
303 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
304 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
305 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
306 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
307 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
308 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
309 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
310 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
311 struct rwlock **lockp);
312 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
314 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
315 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
316 struct spglist *free, struct rwlock **lockp);
317 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
318 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
319 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
320 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
321 struct spglist *free);
322 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
323 vm_page_t m, struct rwlock **lockp);
324 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
326 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
328 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
329 struct rwlock **lockp);
330 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
331 struct rwlock **lockp);
332 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
333 struct rwlock **lockp);
335 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
336 struct spglist *free);
337 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
338 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
341 * Move the kernel virtual free pointer to the next
342 * 2MB. This is used to help improve performance
343 * by using a large (2MB) page for much of the kernel
344 * (.text, .data, .bss)
347 pmap_kmem_choose(vm_offset_t addr)
349 vm_offset_t newaddr = addr;
351 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
355 /********************/
356 /* Inline functions */
357 /********************/
359 /* Return a non-clipped PD index for a given VA */
360 static __inline vm_pindex_t
361 pmap_pde_pindex(vm_offset_t va)
363 return (va >> PDRSHIFT);
367 /* Return various clipped indexes for a given VA */
368 static __inline vm_pindex_t
369 pmap_pte_index(vm_offset_t va)
372 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
375 static __inline vm_pindex_t
376 pmap_pde_index(vm_offset_t va)
379 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
382 static __inline vm_pindex_t
383 pmap_pdpe_index(vm_offset_t va)
386 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
389 static __inline vm_pindex_t
390 pmap_pml4e_index(vm_offset_t va)
393 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
396 /* Return a pointer to the PML4 slot that corresponds to a VA */
397 static __inline pml4_entry_t *
398 pmap_pml4e(pmap_t pmap, vm_offset_t va)
401 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
404 /* Return a pointer to the PDP slot that corresponds to a VA */
405 static __inline pdp_entry_t *
406 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
410 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
411 return (&pdpe[pmap_pdpe_index(va)]);
414 /* Return a pointer to the PDP slot that corresponds to a VA */
415 static __inline pdp_entry_t *
416 pmap_pdpe(pmap_t pmap, vm_offset_t va)
420 pml4e = pmap_pml4e(pmap, va);
421 if ((*pml4e & PG_V) == 0)
423 return (pmap_pml4e_to_pdpe(pml4e, va));
426 /* Return a pointer to the PD slot that corresponds to a VA */
427 static __inline pd_entry_t *
428 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
432 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
433 return (&pde[pmap_pde_index(va)]);
436 /* Return a pointer to the PD slot that corresponds to a VA */
437 static __inline pd_entry_t *
438 pmap_pde(pmap_t pmap, vm_offset_t va)
442 pdpe = pmap_pdpe(pmap, va);
443 if (pdpe == NULL || (*pdpe & PG_V) == 0)
445 return (pmap_pdpe_to_pde(pdpe, va));
448 /* Return a pointer to the PT slot that corresponds to a VA */
449 static __inline pt_entry_t *
450 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
454 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
455 return (&pte[pmap_pte_index(va)]);
458 /* Return a pointer to the PT slot that corresponds to a VA */
459 static __inline pt_entry_t *
460 pmap_pte(pmap_t pmap, vm_offset_t va)
464 pde = pmap_pde(pmap, va);
465 if (pde == NULL || (*pde & PG_V) == 0)
467 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
468 return ((pt_entry_t *)pde);
469 return (pmap_pde_to_pte(pde, va));
473 pmap_resident_count_inc(pmap_t pmap, int count)
476 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
477 pmap->pm_stats.resident_count += count;
481 pmap_resident_count_dec(pmap_t pmap, int count)
484 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
485 pmap->pm_stats.resident_count -= count;
488 PMAP_INLINE pt_entry_t *
489 vtopte(vm_offset_t va)
491 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
493 return (PTmap + ((va >> PAGE_SHIFT) & mask));
496 static __inline pd_entry_t *
497 vtopde(vm_offset_t va)
499 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
501 return (PDmap + ((va >> PDRSHIFT) & mask));
505 allocpages(vm_paddr_t *firstaddr, int n)
510 bzero((void *)ret, n * PAGE_SIZE);
511 *firstaddr += n * PAGE_SIZE;
515 CTASSERT(powerof2(NDMPML4E));
517 /* number of kernel PDP slots */
518 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
521 nkpt_init(vm_paddr_t addr)
528 pt_pages = howmany(addr, 1 << PDRSHIFT);
529 pt_pages += NKPDPE(pt_pages);
532 * Add some slop beyond the bare minimum required for bootstrapping
535 * This is quite important when allocating KVA for kernel modules.
536 * The modules are required to be linked in the negative 2GB of
537 * the address space. If we run out of KVA in this region then
538 * pmap_growkernel() will need to allocate page table pages to map
539 * the entire 512GB of KVA space which is an unnecessary tax on
542 pt_pages += 8; /* 16MB additional slop for kernel modules */
548 create_pagetables(vm_paddr_t *firstaddr)
550 int i, j, ndm1g, nkpdpe;
556 /* Allocate page table pages for the direct map */
557 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
558 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
560 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
561 if (ndmpdpphys > NDMPML4E) {
563 * Each NDMPML4E allows 512 GB, so limit to that,
564 * and then readjust ndmpdp and ndmpdpphys.
566 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
567 Maxmem = atop(NDMPML4E * NBPML4);
568 ndmpdpphys = NDMPML4E;
569 ndmpdp = NDMPML4E * NPDEPG;
571 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
573 if ((amd_feature & AMDID_PAGE1GB) != 0)
574 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
576 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
577 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
580 KPML4phys = allocpages(firstaddr, 1);
581 KPDPphys = allocpages(firstaddr, NKPML4E);
584 * Allocate the initial number of kernel page table pages required to
585 * bootstrap. We defer this until after all memory-size dependent
586 * allocations are done (e.g. direct map), so that we don't have to
587 * build in too much slop in our estimate.
589 * Note that when NKPML4E > 1, we have an empty page underneath
590 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
591 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
593 nkpt_init(*firstaddr);
594 nkpdpe = NKPDPE(nkpt);
596 KPTphys = allocpages(firstaddr, nkpt);
597 KPDphys = allocpages(firstaddr, nkpdpe);
599 /* Fill in the underlying page table pages */
600 /* Nominally read-only (but really R/W) from zero to physfree */
601 /* XXX not fully used, underneath 2M pages */
602 pt_p = (pt_entry_t *)KPTphys;
603 for (i = 0; ptoa(i) < *firstaddr; i++)
604 pt_p[i] = ptoa(i) | PG_RW | PG_V | PG_G;
606 /* Now map the page tables at their location within PTmap */
607 pd_p = (pd_entry_t *)KPDphys;
608 for (i = 0; i < nkpt; i++)
609 pd_p[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
611 /* Map from zero to end of allocations under 2M pages */
612 /* This replaces some of the KPTphys entries above */
613 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
614 pd_p[i] = (i << PDRSHIFT) | PG_RW | PG_V | PG_PS | PG_G;
616 /* And connect up the PD to the PDP (leaving room for L4 pages) */
617 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
618 for (i = 0; i < nkpdpe; i++)
619 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | PG_RW | PG_V | PG_U;
622 * Now, set up the direct map region using 2MB and/or 1GB pages. If
623 * the end of physical memory is not aligned to a 1GB page boundary,
624 * then the residual physical memory is mapped with 2MB pages. Later,
625 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
626 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
627 * that are partially used.
629 pd_p = (pd_entry_t *)DMPDphys;
630 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
631 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
632 /* Preset PG_M and PG_A because demotion expects it. */
633 pd_p[j] |= PG_RW | PG_V | PG_PS | PG_G |
636 pdp_p = (pdp_entry_t *)DMPDPphys;
637 for (i = 0; i < ndm1g; i++) {
638 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
639 /* Preset PG_M and PG_A because demotion expects it. */
640 pdp_p[i] |= PG_RW | PG_V | PG_PS | PG_G |
643 for (j = 0; i < ndmpdp; i++, j++) {
644 pdp_p[i] = DMPDphys + ptoa(j);
645 pdp_p[i] |= PG_RW | PG_V | PG_U;
648 /* And recursively map PML4 to itself in order to get PTmap */
649 p4_p = (pml4_entry_t *)KPML4phys;
650 p4_p[PML4PML4I] = KPML4phys;
651 p4_p[PML4PML4I] |= PG_RW | PG_V | PG_U;
653 /* Connect the Direct Map slot(s) up to the PML4. */
654 for (i = 0; i < ndmpdpphys; i++) {
655 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
656 p4_p[DMPML4I + i] |= PG_RW | PG_V | PG_U;
659 /* Connect the KVA slots up to the PML4 */
660 for (i = 0; i < NKPML4E; i++) {
661 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
662 p4_p[KPML4BASE + i] |= PG_RW | PG_V | PG_U;
667 * Bootstrap the system enough to run with virtual memory.
669 * On amd64 this is called after mapping has already been enabled
670 * and just syncs the pmap module with what has already been done.
671 * [We can't call it easily with mapping off since the kernel is not
672 * mapped with PA == VA, hence we would have to relocate every address
673 * from the linked base (virtual) address "KERNBASE" to the actual
674 * (physical) address starting relative to 0]
677 pmap_bootstrap(vm_paddr_t *firstaddr)
680 pt_entry_t *pte, *unused;
683 * Create an initial set of page tables to run the kernel in.
685 create_pagetables(firstaddr);
687 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
688 virtual_avail = pmap_kmem_choose(virtual_avail);
690 virtual_end = VM_MAX_KERNEL_ADDRESS;
693 /* XXX do %cr0 as well */
694 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
696 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
697 load_cr4(rcr4() | CR4_SMEP);
700 * Initialize the kernel pmap (which is statically allocated).
702 PMAP_LOCK_INIT(kernel_pmap);
703 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
704 kernel_pmap->pm_cr3 = KPML4phys;
705 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
706 CPU_ZERO(&kernel_pmap->pm_save);
707 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
710 * Initialize the global pv list lock.
712 rw_init(&pvh_global_lock, "pmap pv global");
715 * Reserve some special page table entries/VA space for temporary
718 #define SYSMAP(c, p, v, n) \
719 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
725 * CMAP1 is only used for the memory test.
727 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
732 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
736 /* Initialize the PAT MSR. */
739 /* Initialize TLB Context Id. */
740 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
741 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
742 load_cr4(rcr4() | CR4_PCIDE);
743 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
744 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
745 /* Check for INVPCID support */
746 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
748 kernel_pmap->pm_pcid = 0;
750 pmap_pcid_enabled = 0;
753 pmap_pcid_enabled = 0;
762 int pat_table[PAT_INDEX_SIZE];
767 /* Bail if this CPU doesn't implement PAT. */
768 if ((cpu_feature & CPUID_PAT) == 0)
771 /* Set default PAT index table. */
772 for (i = 0; i < PAT_INDEX_SIZE; i++)
774 pat_table[PAT_WRITE_BACK] = 0;
775 pat_table[PAT_WRITE_THROUGH] = 1;
776 pat_table[PAT_UNCACHEABLE] = 3;
777 pat_table[PAT_WRITE_COMBINING] = 3;
778 pat_table[PAT_WRITE_PROTECTED] = 3;
779 pat_table[PAT_UNCACHED] = 3;
781 /* Initialize default PAT entries. */
782 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
783 PAT_VALUE(1, PAT_WRITE_THROUGH) |
784 PAT_VALUE(2, PAT_UNCACHED) |
785 PAT_VALUE(3, PAT_UNCACHEABLE) |
786 PAT_VALUE(4, PAT_WRITE_BACK) |
787 PAT_VALUE(5, PAT_WRITE_THROUGH) |
788 PAT_VALUE(6, PAT_UNCACHED) |
789 PAT_VALUE(7, PAT_UNCACHEABLE);
793 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
794 * Program 5 and 6 as WP and WC.
795 * Leave 4 and 7 as WB and UC.
797 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
798 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
799 PAT_VALUE(6, PAT_WRITE_COMBINING);
800 pat_table[PAT_UNCACHED] = 2;
801 pat_table[PAT_WRITE_PROTECTED] = 5;
802 pat_table[PAT_WRITE_COMBINING] = 6;
805 * Just replace PAT Index 2 with WC instead of UC-.
807 pat_msr &= ~PAT_MASK(2);
808 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
809 pat_table[PAT_WRITE_COMBINING] = 2;
814 load_cr4(cr4 & ~CR4_PGE);
816 /* Disable caches (CD = 1, NW = 0). */
818 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
820 /* Flushes caches and TLBs. */
824 /* Update PAT and index table. */
825 wrmsr(MSR_PAT, pat_msr);
826 for (i = 0; i < PAT_INDEX_SIZE; i++)
827 pat_index[i] = pat_table[i];
829 /* Flush caches and TLBs again. */
833 /* Restore caches and PGE. */
839 * Initialize a vm_page's machine-dependent fields.
842 pmap_page_init(vm_page_t m)
845 TAILQ_INIT(&m->md.pv_list);
846 m->md.pat_mode = PAT_WRITE_BACK;
850 * Initialize the pmap module.
851 * Called by vm_init, to initialize any structures that the pmap
852 * system needs to map virtual memory.
862 * Initialize the vm page array entries for the kernel pmap's
865 for (i = 0; i < nkpt; i++) {
866 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
867 KASSERT(mpte >= vm_page_array &&
868 mpte < &vm_page_array[vm_page_array_size],
869 ("pmap_init: page table page is out of range"));
870 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
871 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
875 * If the kernel is running in a virtual machine on an AMD Family 10h
876 * processor, then it must assume that MCA is enabled by the virtual
879 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
880 CPUID_TO_FAMILY(cpu_id) == 0x10)
881 workaround_erratum383 = 1;
884 * Are large page mappings enabled?
886 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
888 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
889 ("pmap_init: can't assign to pagesizes[1]"));
890 pagesizes[1] = NBPDR;
894 * Initialize the pv chunk list mutex.
896 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
899 * Initialize the pool of pv list locks.
901 for (i = 0; i < NPV_LIST_LOCKS; i++)
902 rw_init(&pv_list_locks[i], "pmap pv list");
905 * Calculate the size of the pv head table for superpages.
907 for (i = 0; phys_avail[i + 1]; i += 2);
908 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
911 * Allocate memory for the pv head table for superpages.
913 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
915 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
917 for (i = 0; i < pv_npg; i++)
918 TAILQ_INIT(&pv_table[i].pv_list);
921 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
922 "2MB page mapping counters");
924 static u_long pmap_pde_demotions;
925 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
926 &pmap_pde_demotions, 0, "2MB page demotions");
928 static u_long pmap_pde_mappings;
929 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
930 &pmap_pde_mappings, 0, "2MB page mappings");
932 static u_long pmap_pde_p_failures;
933 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
934 &pmap_pde_p_failures, 0, "2MB page promotion failures");
936 static u_long pmap_pde_promotions;
937 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
938 &pmap_pde_promotions, 0, "2MB page promotions");
940 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
941 "1GB page mapping counters");
943 static u_long pmap_pdpe_demotions;
944 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
945 &pmap_pdpe_demotions, 0, "1GB page demotions");
947 /***************************************************
948 * Low level helper routines.....
949 ***************************************************/
952 * Determine the appropriate bits to set in a PTE or PDE for a specified
956 pmap_cache_bits(int mode, boolean_t is_pde)
958 int cache_bits, pat_flag, pat_idx;
960 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
961 panic("Unknown caching mode %d\n", mode);
963 /* The PAT bit is different for PTE's and PDE's. */
964 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
966 /* Map the caching mode to a PAT index. */
967 pat_idx = pat_index[mode];
969 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
972 cache_bits |= pat_flag;
974 cache_bits |= PG_NC_PCD;
976 cache_bits |= PG_NC_PWT;
981 * After changing the page size for the specified virtual address in the page
982 * table, flush the corresponding entries from the processor's TLB. Only the
983 * calling processor's TLB is affected.
985 * The calling thread must be pinned to a processor.
988 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
991 if ((newpde & PG_PS) == 0)
992 /* Demotion: flush a specific 2MB page mapping. */
994 else if ((newpde & PG_G) == 0)
996 * Promotion: flush every 4KB page mapping from the TLB
997 * because there are too many to flush individually.
1002 * Promotion: flush every 4KB page mapping from the TLB,
1003 * including any global (PG_G) mappings.
1011 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1013 struct invpcid_descr d;
1016 if (invpcid_works) {
1017 d.pcid = pmap->pm_pcid;
1020 invpcid(&d, INVPCID_ADDR);
1026 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1028 load_cr3(cr3 | CR3_PCID_SAVE);
1033 * For SMP, these functions have to use the IPI mechanism for coherence.
1035 * N.B.: Before calling any of the following TLB invalidation functions,
1036 * the calling processor must ensure that all stores updating a non-
1037 * kernel page table are globally performed. Otherwise, another
1038 * processor could cache an old, pre-update entry without being
1039 * invalidated. This can happen one of two ways: (1) The pmap becomes
1040 * active on another processor after its pm_active field is checked by
1041 * one of the following functions but before a store updating the page
1042 * table is globally performed. (2) The pmap becomes active on another
1043 * processor before its pm_active field is checked but due to
1044 * speculative loads one of the following functions stills reads the
1045 * pmap as inactive on the other processor.
1047 * The kernel page table is exempt because its pm_active field is
1048 * immutable. The kernel page table is always active on every
1052 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1054 cpuset_t other_cpus;
1058 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1059 if (!pmap_pcid_enabled) {
1062 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1063 if (pmap == PCPU_GET(curpmap))
1066 pmap_invalidate_page_pcid(pmap, va);
1071 smp_invlpg(pmap, va);
1073 cpuid = PCPU_GET(cpuid);
1074 other_cpus = all_cpus;
1075 CPU_CLR(cpuid, &other_cpus);
1076 if (CPU_ISSET(cpuid, &pmap->pm_active))
1078 else if (pmap_pcid_enabled) {
1079 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1080 pmap_invalidate_page_pcid(pmap, va);
1084 if (pmap_pcid_enabled)
1085 CPU_AND(&other_cpus, &pmap->pm_save);
1087 CPU_AND(&other_cpus, &pmap->pm_active);
1088 if (!CPU_EMPTY(&other_cpus))
1089 smp_masked_invlpg(other_cpus, pmap, va);
1095 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1097 struct invpcid_descr d;
1101 if (invpcid_works) {
1102 d.pcid = pmap->pm_pcid;
1104 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1106 invpcid(&d, INVPCID_ADDR);
1113 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1114 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1116 load_cr3(cr3 | CR3_PCID_SAVE);
1121 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1123 cpuset_t other_cpus;
1128 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1129 if (!pmap_pcid_enabled) {
1130 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1133 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1134 if (pmap == PCPU_GET(curpmap)) {
1135 for (addr = sva; addr < eva;
1139 pmap_invalidate_range_pcid(pmap,
1146 smp_invlpg_range(pmap, sva, eva);
1148 cpuid = PCPU_GET(cpuid);
1149 other_cpus = all_cpus;
1150 CPU_CLR(cpuid, &other_cpus);
1151 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1152 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1154 } else if (pmap_pcid_enabled) {
1155 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1156 pmap_invalidate_range_pcid(pmap, sva, eva);
1160 if (pmap_pcid_enabled)
1161 CPU_AND(&other_cpus, &pmap->pm_save);
1163 CPU_AND(&other_cpus, &pmap->pm_active);
1164 if (!CPU_EMPTY(&other_cpus))
1165 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1171 pmap_invalidate_all(pmap_t pmap)
1173 cpuset_t other_cpus;
1174 struct invpcid_descr d;
1179 cpuid = PCPU_GET(cpuid);
1180 if (pmap == kernel_pmap ||
1181 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1182 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1183 if (invpcid_works) {
1184 bzero(&d, sizeof(d));
1185 invpcid(&d, INVPCID_CTXGLOB);
1189 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1192 other_cpus = all_cpus;
1193 CPU_CLR(cpuid, &other_cpus);
1196 * This logic is duplicated in the Xinvltlb shootdown
1199 if (pmap_pcid_enabled) {
1200 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1201 if (invpcid_works) {
1202 d.pcid = pmap->pm_pcid;
1205 invpcid(&d, INVPCID_CTX);
1211 * Bit 63 is clear, pcid TLB
1212 * entries are invalidated.
1214 load_cr3(pmap->pm_cr3);
1215 load_cr3(cr3 | CR3_PCID_SAVE);
1221 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1223 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1224 if (pmap_pcid_enabled)
1225 CPU_AND(&other_cpus, &pmap->pm_save);
1227 CPU_AND(&other_cpus, &pmap->pm_active);
1228 if (!CPU_EMPTY(&other_cpus))
1229 smp_masked_invltlb(other_cpus, pmap);
1235 pmap_invalidate_cache(void)
1245 cpuset_t invalidate; /* processors that invalidate their TLB */
1249 u_int store; /* processor that updates the PDE */
1253 pmap_update_pde_action(void *arg)
1255 struct pde_action *act = arg;
1257 if (act->store == PCPU_GET(cpuid))
1258 pde_store(act->pde, act->newpde);
1262 pmap_update_pde_teardown(void *arg)
1264 struct pde_action *act = arg;
1266 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1267 pmap_update_pde_invalidate(act->va, act->newpde);
1271 * Change the page size for the specified virtual address in a way that
1272 * prevents any possibility of the TLB ever having two entries that map the
1273 * same virtual address using different page sizes. This is the recommended
1274 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1275 * machine check exception for a TLB state that is improperly diagnosed as a
1279 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1281 struct pde_action act;
1282 cpuset_t active, other_cpus;
1286 cpuid = PCPU_GET(cpuid);
1287 other_cpus = all_cpus;
1288 CPU_CLR(cpuid, &other_cpus);
1289 if (pmap == kernel_pmap)
1292 active = pmap->pm_active;
1293 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1295 if (CPU_OVERLAP(&active, &other_cpus)) {
1297 act.invalidate = active;
1300 act.newpde = newpde;
1301 CPU_SET(cpuid, &active);
1302 smp_rendezvous_cpus(active,
1303 smp_no_rendevous_barrier, pmap_update_pde_action,
1304 pmap_update_pde_teardown, &act);
1306 pde_store(pde, newpde);
1307 if (CPU_ISSET(cpuid, &active))
1308 pmap_update_pde_invalidate(va, newpde);
1314 * Normal, non-SMP, invalidation functions.
1315 * We inline these within pmap.c for speed.
1318 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1321 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1326 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1330 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1331 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1336 pmap_invalidate_all(pmap_t pmap)
1339 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1344 pmap_invalidate_cache(void)
1351 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1354 pde_store(pde, newpde);
1355 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1356 pmap_update_pde_invalidate(va, newpde);
1358 CPU_ZERO(&pmap->pm_save);
1362 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1365 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1368 KASSERT((sva & PAGE_MASK) == 0,
1369 ("pmap_invalidate_cache_range: sva not page-aligned"));
1370 KASSERT((eva & PAGE_MASK) == 0,
1371 ("pmap_invalidate_cache_range: eva not page-aligned"));
1373 if (cpu_feature & CPUID_SS)
1374 ; /* If "Self Snoop" is supported, do nothing. */
1375 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1376 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1379 * XXX: Some CPUs fault, hang, or trash the local APIC
1380 * registers if we use CLFLUSH on the local APIC
1381 * range. The local APIC is always uncached, so we
1382 * don't need to flush for that range anyway.
1384 if (pmap_kextract(sva) == lapic_paddr)
1388 * Otherwise, do per-cache line flush. Use the mfence
1389 * instruction to insure that previous stores are
1390 * included in the write-back. The processor
1391 * propagates flush to other processors in the cache
1395 for (; sva < eva; sva += cpu_clflush_line_size)
1401 * No targeted cache flush methods are supported by CPU,
1402 * or the supplied range is bigger than 2MB.
1403 * Globally invalidate cache.
1405 pmap_invalidate_cache();
1410 * Remove the specified set of pages from the data and instruction caches.
1412 * In contrast to pmap_invalidate_cache_range(), this function does not
1413 * rely on the CPU's self-snoop feature, because it is intended for use
1414 * when moving pages into a different cache domain.
1417 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1419 vm_offset_t daddr, eva;
1422 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1423 (cpu_feature & CPUID_CLFSH) == 0)
1424 pmap_invalidate_cache();
1427 for (i = 0; i < count; i++) {
1428 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1429 eva = daddr + PAGE_SIZE;
1430 for (; daddr < eva; daddr += cpu_clflush_line_size)
1438 * Are we current address space or kernel?
1441 pmap_is_current(pmap_t pmap)
1443 return (pmap == kernel_pmap ||
1444 (pmap->pm_pml4[PML4PML4I] & PG_FRAME) == (PML4pml4e[0] & PG_FRAME));
1448 * Routine: pmap_extract
1450 * Extract the physical page address associated
1451 * with the given map/virtual_address pair.
1454 pmap_extract(pmap_t pmap, vm_offset_t va)
1463 pdpe = pmap_pdpe(pmap, va);
1464 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1465 if ((*pdpe & PG_PS) != 0)
1466 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1468 pde = pmap_pdpe_to_pde(pdpe, va);
1469 if ((*pde & PG_V) != 0) {
1470 if ((*pde & PG_PS) != 0) {
1471 pa = (*pde & PG_PS_FRAME) |
1474 pte = pmap_pde_to_pte(pde, va);
1475 pa = (*pte & PG_FRAME) |
1486 * Routine: pmap_extract_and_hold
1488 * Atomically extract and hold the physical page
1489 * with the given pmap and virtual address pair
1490 * if that mapping permits the given protection.
1493 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1495 pd_entry_t pde, *pdep;
1504 pdep = pmap_pde(pmap, va);
1505 if (pdep != NULL && (pde = *pdep)) {
1507 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1508 if (vm_page_pa_tryrelock(pmap, (pde &
1509 PG_PS_FRAME) | (va & PDRMASK), &pa))
1511 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1516 pte = *pmap_pde_to_pte(pdep, va);
1518 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1519 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1522 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1533 pmap_kextract(vm_offset_t va)
1538 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1539 pa = DMAP_TO_PHYS(va);
1543 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1546 * Beware of a concurrent promotion that changes the
1547 * PDE at this point! For example, vtopte() must not
1548 * be used to access the PTE because it would use the
1549 * new PDE. It is, however, safe to use the old PDE
1550 * because the page table page is preserved by the
1553 pa = *pmap_pde_to_pte(&pde, va);
1554 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1560 /***************************************************
1561 * Low level mapping routines.....
1562 ***************************************************/
1565 * Add a wired page to the kva.
1566 * Note: not SMP coherent.
1569 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1574 pte_store(pte, pa | PG_RW | PG_V | PG_G);
1577 static __inline void
1578 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1583 pte_store(pte, pa | PG_RW | PG_V | PG_G | pmap_cache_bits(mode, 0));
1587 * Remove a page from the kernel pagetables.
1588 * Note: not SMP coherent.
1591 pmap_kremove(vm_offset_t va)
1600 * Used to map a range of physical addresses into kernel
1601 * virtual address space.
1603 * The value passed in '*virt' is a suggested virtual address for
1604 * the mapping. Architectures which can support a direct-mapped
1605 * physical to virtual region can return the appropriate address
1606 * within that region, leaving '*virt' unchanged. Other
1607 * architectures should map the pages starting at '*virt' and
1608 * update '*virt' with the first usable address after the mapped
1612 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1614 return PHYS_TO_DMAP(start);
1619 * Add a list of wired pages to the kva
1620 * this routine is only used for temporary
1621 * kernel mappings that do not need to have
1622 * page modification or references recorded.
1623 * Note that old mappings are simply written
1624 * over. The page *must* be wired.
1625 * Note: SMP coherent. Uses a ranged shootdown IPI.
1628 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1630 pt_entry_t *endpte, oldpte, pa, *pte;
1635 endpte = pte + count;
1636 while (pte < endpte) {
1638 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1639 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1641 pte_store(pte, pa | PG_G | PG_RW | PG_V);
1645 if (__predict_false((oldpte & PG_V) != 0))
1646 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1651 * This routine tears out page mappings from the
1652 * kernel -- it is meant only for temporary mappings.
1653 * Note: SMP coherent. Uses a ranged shootdown IPI.
1656 pmap_qremove(vm_offset_t sva, int count)
1661 while (count-- > 0) {
1662 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
1666 pmap_invalidate_range(kernel_pmap, sva, va);
1669 /***************************************************
1670 * Page table page management routines.....
1671 ***************************************************/
1672 static __inline void
1673 pmap_free_zero_pages(struct spglist *free)
1677 while ((m = SLIST_FIRST(free)) != NULL) {
1678 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1679 /* Preserve the page's PG_ZERO setting. */
1680 vm_page_free_toq(m);
1685 * Schedule the specified unused page table page to be freed. Specifically,
1686 * add the page to the specified list of pages that will be released to the
1687 * physical memory manager after the TLB has been updated.
1689 static __inline void
1690 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1691 boolean_t set_PG_ZERO)
1695 m->flags |= PG_ZERO;
1697 m->flags &= ~PG_ZERO;
1698 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1702 * Inserts the specified page table page into the specified pmap's collection
1703 * of idle page table pages. Each of a pmap's page table pages is responsible
1704 * for mapping a distinct range of virtual addresses. The pmap's collection is
1705 * ordered by this virtual address range.
1708 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1711 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1712 return (vm_radix_insert(&pmap->pm_root, mpte));
1716 * Looks for a page table page mapping the specified virtual address in the
1717 * specified pmap's collection of idle page table pages. Returns NULL if there
1718 * is no page table page corresponding to the specified virtual address.
1720 static __inline vm_page_t
1721 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1725 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
1729 * Removes the specified page table page from the specified pmap's collection
1730 * of idle page table pages. The specified page table page must be a member of
1731 * the pmap's collection.
1733 static __inline void
1734 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1737 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1738 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1742 * Decrements a page table page's wire count, which is used to record the
1743 * number of valid page table entries within the page. If the wire count
1744 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1745 * page table page was unmapped and FALSE otherwise.
1747 static inline boolean_t
1748 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1752 if (m->wire_count == 0) {
1753 _pmap_unwire_ptp(pmap, va, m, free);
1760 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1765 * unmap the page table page
1767 if (m->pindex >= (NUPDE + NUPDPE)) {
1770 pml4 = pmap_pml4e(pmap, va);
1772 } else if (m->pindex >= NUPDE) {
1775 pdp = pmap_pdpe(pmap, va);
1780 pd = pmap_pde(pmap, va);
1783 pmap_resident_count_dec(pmap, 1);
1784 if (m->pindex < NUPDE) {
1785 /* We just released a PT, unhold the matching PD */
1788 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
1789 pmap_unwire_ptp(pmap, va, pdpg, free);
1791 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
1792 /* We just released a PD, unhold the matching PDP */
1795 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
1796 pmap_unwire_ptp(pmap, va, pdppg, free);
1800 * This is a release store so that the ordinary store unmapping
1801 * the page table page is globally performed before TLB shoot-
1804 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1807 * Put page on a list so that it is released after
1808 * *ALL* TLB shootdown is done
1810 pmap_add_delayed_free_list(m, free, TRUE);
1814 * After removing a page table entry, this routine is used to
1815 * conditionally free the page, and manage the hold/wire counts.
1818 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1819 struct spglist *free)
1823 if (va >= VM_MAXUSER_ADDRESS)
1825 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1826 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1827 return (pmap_unwire_ptp(pmap, va, mpte, free));
1831 pmap_pinit0(pmap_t pmap)
1834 PMAP_LOCK_INIT(pmap);
1835 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1836 pmap->pm_cr3 = KPML4phys;
1837 pmap->pm_root.rt_root = 0;
1838 CPU_ZERO(&pmap->pm_active);
1839 CPU_ZERO(&pmap->pm_save);
1840 PCPU_SET(curpmap, pmap);
1841 TAILQ_INIT(&pmap->pm_pvchunk);
1842 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1843 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
1847 * Initialize a preallocated and zeroed pmap structure,
1848 * such as one in a vmspace structure.
1851 pmap_pinit(pmap_t pmap)
1857 * allocate the page directory page
1859 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1860 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1863 pmap->pm_cr3 = VM_PAGE_TO_PHYS(pml4pg);
1864 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pmap->pm_cr3);
1866 if ((pml4pg->flags & PG_ZERO) == 0)
1867 pagezero(pmap->pm_pml4);
1869 /* Wire in kernel global address entries. */
1870 for (i = 0; i < NKPML4E; i++) {
1871 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + (i << PAGE_SHIFT)) |
1872 PG_RW | PG_V | PG_U;
1874 for (i = 0; i < ndmpdpphys; i++) {
1875 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + (i << PAGE_SHIFT)) |
1876 PG_RW | PG_V | PG_U;
1879 /* install self-referential address mapping entry(s) */
1880 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | PG_V | PG_RW | PG_A | PG_M;
1882 pmap->pm_root.rt_root = 0;
1883 CPU_ZERO(&pmap->pm_active);
1884 TAILQ_INIT(&pmap->pm_pvchunk);
1885 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1886 if (pmap_pcid_enabled) {
1887 pmap->pm_pcid = alloc_unr(&pcid_unr);
1888 if (pmap->pm_pcid != -1)
1889 pmap->pm_cr3 |= pmap->pm_pcid;
1893 CPU_ZERO(&pmap->pm_save);
1899 * This routine is called if the desired page table page does not exist.
1901 * If page table page allocation fails, this routine may sleep before
1902 * returning NULL. It sleeps only if a lock pointer was given.
1904 * Note: If a page allocation fails at page table level two or three,
1905 * one or two pages may be held during the wait, only to be released
1906 * afterwards. This conservative approach is easily argued to avoid
1910 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1912 vm_page_t m, pdppg, pdpg;
1914 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1917 * Allocate a page table page.
1919 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1920 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1921 if (lockp != NULL) {
1922 RELEASE_PV_LIST_LOCK(lockp);
1924 rw_runlock(&pvh_global_lock);
1926 rw_rlock(&pvh_global_lock);
1931 * Indicate the need to retry. While waiting, the page table
1932 * page may have been allocated.
1936 if ((m->flags & PG_ZERO) == 0)
1940 * Map the pagetable page into the process address space, if
1941 * it isn't already there.
1944 if (ptepindex >= (NUPDE + NUPDPE)) {
1946 vm_pindex_t pml4index;
1948 /* Wire up a new PDPE page */
1949 pml4index = ptepindex - (NUPDE + NUPDPE);
1950 pml4 = &pmap->pm_pml4[pml4index];
1951 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1953 } else if (ptepindex >= NUPDE) {
1954 vm_pindex_t pml4index;
1955 vm_pindex_t pdpindex;
1959 /* Wire up a new PDE page */
1960 pdpindex = ptepindex - NUPDE;
1961 pml4index = pdpindex >> NPML4EPGSHIFT;
1963 pml4 = &pmap->pm_pml4[pml4index];
1964 if ((*pml4 & PG_V) == 0) {
1965 /* Have to allocate a new pdp, recurse */
1966 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
1969 atomic_subtract_int(&cnt.v_wire_count, 1);
1970 vm_page_free_zero(m);
1974 /* Add reference to pdp page */
1975 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
1976 pdppg->wire_count++;
1978 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1980 /* Now find the pdp page */
1981 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1982 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1985 vm_pindex_t pml4index;
1986 vm_pindex_t pdpindex;
1991 /* Wire up a new PTE page */
1992 pdpindex = ptepindex >> NPDPEPGSHIFT;
1993 pml4index = pdpindex >> NPML4EPGSHIFT;
1995 /* First, find the pdp and check that its valid. */
1996 pml4 = &pmap->pm_pml4[pml4index];
1997 if ((*pml4 & PG_V) == 0) {
1998 /* Have to allocate a new pd, recurse */
1999 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2002 atomic_subtract_int(&cnt.v_wire_count, 1);
2003 vm_page_free_zero(m);
2006 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2007 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2009 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2010 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2011 if ((*pdp & PG_V) == 0) {
2012 /* Have to allocate a new pd, recurse */
2013 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2016 atomic_subtract_int(&cnt.v_wire_count,
2018 vm_page_free_zero(m);
2022 /* Add reference to the pd page */
2023 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2027 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2029 /* Now we know where the page directory page is */
2030 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2031 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2034 pmap_resident_count_inc(pmap, 1);
2040 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2042 vm_pindex_t pdpindex, ptepindex;
2047 pdpe = pmap_pdpe(pmap, va);
2048 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2049 /* Add a reference to the pd page. */
2050 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2053 /* Allocate a pd page. */
2054 ptepindex = pmap_pde_pindex(va);
2055 pdpindex = ptepindex >> NPDPEPGSHIFT;
2056 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2057 if (pdpg == NULL && lockp != NULL)
2064 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2066 vm_pindex_t ptepindex;
2071 * Calculate pagetable page index
2073 ptepindex = pmap_pde_pindex(va);
2076 * Get the page directory entry
2078 pd = pmap_pde(pmap, va);
2081 * This supports switching from a 2MB page to a
2084 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2085 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2087 * Invalidation of the 2MB page mapping may have caused
2088 * the deallocation of the underlying PD page.
2095 * If the page table page is mapped, we just increment the
2096 * hold count, and activate it.
2098 if (pd != NULL && (*pd & PG_V) != 0) {
2099 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2103 * Here if the pte page isn't mapped, or if it has been
2106 m = _pmap_allocpte(pmap, ptepindex, lockp);
2107 if (m == NULL && lockp != NULL)
2114 /***************************************************
2115 * Pmap allocation/deallocation routines.
2116 ***************************************************/
2119 * Release any resources held by the given physical map.
2120 * Called when a pmap initialized by pmap_pinit is being released.
2121 * Should only be called if the map contains no valid mappings.
2124 pmap_release(pmap_t pmap)
2129 KASSERT(pmap->pm_stats.resident_count == 0,
2130 ("pmap_release: pmap resident count %ld != 0",
2131 pmap->pm_stats.resident_count));
2132 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2133 ("pmap_release: pmap has reserved page table page(s)"));
2135 if (pmap_pcid_enabled) {
2137 * Invalidate any left TLB entries, to allow the reuse
2140 pmap_invalidate_all(pmap);
2143 m = PHYS_TO_VM_PAGE(pmap->pm_pml4[PML4PML4I] & PG_FRAME);
2145 for (i = 0; i < NKPML4E; i++) /* KVA */
2146 pmap->pm_pml4[KPML4BASE + i] = 0;
2147 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2148 pmap->pm_pml4[DMPML4I + i] = 0;
2149 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2152 atomic_subtract_int(&cnt.v_wire_count, 1);
2153 vm_page_free_zero(m);
2154 if (pmap->pm_pcid != -1)
2155 free_unr(&pcid_unr, pmap->pm_pcid);
2159 kvm_size(SYSCTL_HANDLER_ARGS)
2161 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2163 return sysctl_handle_long(oidp, &ksize, 0, req);
2165 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2166 0, 0, kvm_size, "LU", "Size of KVM");
2169 kvm_free(SYSCTL_HANDLER_ARGS)
2171 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2173 return sysctl_handle_long(oidp, &kfree, 0, req);
2175 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2176 0, 0, kvm_free, "LU", "Amount of KVM free");
2179 * grow the number of kernel page table entries, if needed
2182 pmap_growkernel(vm_offset_t addr)
2186 pd_entry_t *pde, newpdir;
2189 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2192 * Return if "addr" is within the range of kernel page table pages
2193 * that were preallocated during pmap bootstrap. Moreover, leave
2194 * "kernel_vm_end" and the kernel page table as they were.
2196 * The correctness of this action is based on the following
2197 * argument: vm_map_findspace() allocates contiguous ranges of the
2198 * kernel virtual address space. It calls this function if a range
2199 * ends after "kernel_vm_end". If the kernel is mapped between
2200 * "kernel_vm_end" and "addr", then the range cannot begin at
2201 * "kernel_vm_end". In fact, its beginning address cannot be less
2202 * than the kernel. Thus, there is no immediate need to allocate
2203 * any new kernel page table pages between "kernel_vm_end" and
2206 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2209 addr = roundup2(addr, NBPDR);
2210 if (addr - 1 >= kernel_map->max_offset)
2211 addr = kernel_map->max_offset;
2212 while (kernel_vm_end < addr) {
2213 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2214 if ((*pdpe & PG_V) == 0) {
2215 /* We need a new PDP entry */
2216 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2217 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2218 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2220 panic("pmap_growkernel: no memory to grow kernel");
2221 if ((nkpg->flags & PG_ZERO) == 0)
2222 pmap_zero_page(nkpg);
2223 paddr = VM_PAGE_TO_PHYS(nkpg);
2224 *pdpe = (pdp_entry_t)
2225 (paddr | PG_V | PG_RW | PG_A | PG_M);
2226 continue; /* try again */
2228 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2229 if ((*pde & PG_V) != 0) {
2230 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2231 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2232 kernel_vm_end = kernel_map->max_offset;
2238 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2239 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2242 panic("pmap_growkernel: no memory to grow kernel");
2243 if ((nkpg->flags & PG_ZERO) == 0)
2244 pmap_zero_page(nkpg);
2245 paddr = VM_PAGE_TO_PHYS(nkpg);
2246 newpdir = (pd_entry_t) (paddr | PG_V | PG_RW | PG_A | PG_M);
2247 pde_store(pde, newpdir);
2249 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2250 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2251 kernel_vm_end = kernel_map->max_offset;
2258 /***************************************************
2259 * page management routines.
2260 ***************************************************/
2262 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2263 CTASSERT(_NPCM == 3);
2264 CTASSERT(_NPCPV == 168);
2266 static __inline struct pv_chunk *
2267 pv_to_chunk(pv_entry_t pv)
2270 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2273 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2275 #define PC_FREE0 0xfffffffffffffffful
2276 #define PC_FREE1 0xfffffffffffffffful
2277 #define PC_FREE2 0x000000fffffffffful
2279 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2282 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2284 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2285 "Current number of pv entry chunks");
2286 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2287 "Current number of pv entry chunks allocated");
2288 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2289 "Current number of pv entry chunks frees");
2290 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2291 "Number of times tried to get a chunk page but failed.");
2293 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2294 static int pv_entry_spare;
2296 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2297 "Current number of pv entry frees");
2298 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2299 "Current number of pv entry allocs");
2300 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2301 "Current number of pv entries");
2302 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2303 "Current number of spare pv entries");
2307 * We are in a serious low memory condition. Resort to
2308 * drastic measures to free some pages so we can allocate
2309 * another pv entry chunk.
2311 * Returns NULL if PV entries were reclaimed from the specified pmap.
2313 * We do not, however, unmap 2mpages because subsequent accesses will
2314 * allocate per-page pv entries until repromotion occurs, thereby
2315 * exacerbating the shortage of free pv entries.
2318 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2320 struct pch new_tail;
2321 struct pv_chunk *pc;
2322 struct md_page *pvh;
2325 pt_entry_t *pte, tpte;
2329 struct spglist free;
2331 int bit, field, freed;
2333 rw_assert(&pvh_global_lock, RA_LOCKED);
2334 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2335 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2339 TAILQ_INIT(&new_tail);
2340 mtx_lock(&pv_chunks_mutex);
2341 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2342 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2343 mtx_unlock(&pv_chunks_mutex);
2344 if (pmap != pc->pc_pmap) {
2346 pmap_invalidate_all(pmap);
2347 if (pmap != locked_pmap)
2351 /* Avoid deadlock and lock recursion. */
2352 if (pmap > locked_pmap) {
2353 RELEASE_PV_LIST_LOCK(lockp);
2355 } else if (pmap != locked_pmap &&
2356 !PMAP_TRYLOCK(pmap)) {
2358 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2359 mtx_lock(&pv_chunks_mutex);
2365 * Destroy every non-wired, 4 KB page mapping in the chunk.
2368 for (field = 0; field < _NPCM; field++) {
2369 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2370 inuse != 0; inuse &= ~(1UL << bit)) {
2372 pv = &pc->pc_pventry[field * 64 + bit];
2374 pde = pmap_pde(pmap, va);
2375 if ((*pde & PG_PS) != 0)
2377 pte = pmap_pde_to_pte(pde, va);
2378 if ((*pte & PG_W) != 0)
2380 tpte = pte_load_clear(pte);
2381 if ((tpte & PG_G) != 0)
2382 pmap_invalidate_page(pmap, va);
2383 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2384 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2386 if ((tpte & PG_A) != 0)
2387 vm_page_aflag_set(m, PGA_REFERENCED);
2388 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2389 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2391 if (TAILQ_EMPTY(&m->md.pv_list) &&
2392 (m->flags & PG_FICTITIOUS) == 0) {
2393 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2394 if (TAILQ_EMPTY(&pvh->pv_list)) {
2395 vm_page_aflag_clear(m,
2399 pc->pc_map[field] |= 1UL << bit;
2400 pmap_unuse_pt(pmap, va, *pde, &free);
2405 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2406 mtx_lock(&pv_chunks_mutex);
2409 /* Every freed mapping is for a 4 KB page. */
2410 pmap_resident_count_dec(pmap, freed);
2411 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2412 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2413 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2414 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2415 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2416 pc->pc_map[2] == PC_FREE2) {
2417 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2418 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2419 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2420 /* Entire chunk is free; return it. */
2421 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2422 dump_drop_page(m_pc->phys_addr);
2423 mtx_lock(&pv_chunks_mutex);
2426 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2427 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2428 mtx_lock(&pv_chunks_mutex);
2429 /* One freed pv entry in locked_pmap is sufficient. */
2430 if (pmap == locked_pmap)
2433 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2434 mtx_unlock(&pv_chunks_mutex);
2436 pmap_invalidate_all(pmap);
2437 if (pmap != locked_pmap)
2440 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2441 m_pc = SLIST_FIRST(&free);
2442 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2443 /* Recycle a freed page table page. */
2444 m_pc->wire_count = 1;
2445 atomic_add_int(&cnt.v_wire_count, 1);
2447 pmap_free_zero_pages(&free);
2452 * free the pv_entry back to the free list
2455 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2457 struct pv_chunk *pc;
2458 int idx, field, bit;
2460 rw_assert(&pvh_global_lock, RA_LOCKED);
2461 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2462 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2463 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2464 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2465 pc = pv_to_chunk(pv);
2466 idx = pv - &pc->pc_pventry[0];
2469 pc->pc_map[field] |= 1ul << bit;
2470 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2471 pc->pc_map[2] != PC_FREE2) {
2472 /* 98% of the time, pc is already at the head of the list. */
2473 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2474 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2475 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2479 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2484 free_pv_chunk(struct pv_chunk *pc)
2488 mtx_lock(&pv_chunks_mutex);
2489 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2490 mtx_unlock(&pv_chunks_mutex);
2491 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2492 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2493 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2494 /* entire chunk is free, return it */
2495 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2496 dump_drop_page(m->phys_addr);
2497 vm_page_unwire(m, 0);
2502 * Returns a new PV entry, allocating a new PV chunk from the system when
2503 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2504 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2507 * The given PV list lock may be released.
2510 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2514 struct pv_chunk *pc;
2517 rw_assert(&pvh_global_lock, RA_LOCKED);
2518 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2519 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2521 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2523 for (field = 0; field < _NPCM; field++) {
2524 if (pc->pc_map[field]) {
2525 bit = bsfq(pc->pc_map[field]);
2529 if (field < _NPCM) {
2530 pv = &pc->pc_pventry[field * 64 + bit];
2531 pc->pc_map[field] &= ~(1ul << bit);
2532 /* If this was the last item, move it to tail */
2533 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2534 pc->pc_map[2] == 0) {
2535 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2536 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2539 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2540 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2544 /* No free items, allocate another chunk */
2545 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2548 if (lockp == NULL) {
2549 PV_STAT(pc_chunk_tryfail++);
2552 m = reclaim_pv_chunk(pmap, lockp);
2556 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2557 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2558 dump_add_page(m->phys_addr);
2559 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2561 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2562 pc->pc_map[1] = PC_FREE1;
2563 pc->pc_map[2] = PC_FREE2;
2564 mtx_lock(&pv_chunks_mutex);
2565 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2566 mtx_unlock(&pv_chunks_mutex);
2567 pv = &pc->pc_pventry[0];
2568 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2569 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2570 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2575 * Returns the number of one bits within the given PV chunk map element.
2578 popcnt_pc_map_elem(uint64_t elem)
2583 * This simple method of counting the one bits performs well because
2584 * the given element typically contains more zero bits than one bits.
2587 for (; elem != 0; elem &= elem - 1)
2593 * Ensure that the number of spare PV entries in the specified pmap meets or
2594 * exceeds the given count, "needed".
2596 * The given PV list lock may be released.
2599 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2601 struct pch new_tail;
2602 struct pv_chunk *pc;
2606 rw_assert(&pvh_global_lock, RA_LOCKED);
2607 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2608 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2611 * Newly allocated PV chunks must be stored in a private list until
2612 * the required number of PV chunks have been allocated. Otherwise,
2613 * reclaim_pv_chunk() could recycle one of these chunks. In
2614 * contrast, these chunks must be added to the pmap upon allocation.
2616 TAILQ_INIT(&new_tail);
2619 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2620 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
2621 free = popcnt_pc_map_elem(pc->pc_map[0]);
2622 free += popcnt_pc_map_elem(pc->pc_map[1]);
2623 free += popcnt_pc_map_elem(pc->pc_map[2]);
2625 free = popcntq(pc->pc_map[0]);
2626 free += popcntq(pc->pc_map[1]);
2627 free += popcntq(pc->pc_map[2]);
2632 if (avail >= needed)
2635 for (; avail < needed; avail += _NPCPV) {
2636 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2639 m = reclaim_pv_chunk(pmap, lockp);
2643 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2644 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2645 dump_add_page(m->phys_addr);
2646 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2648 pc->pc_map[0] = PC_FREE0;
2649 pc->pc_map[1] = PC_FREE1;
2650 pc->pc_map[2] = PC_FREE2;
2651 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2652 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2653 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2655 if (!TAILQ_EMPTY(&new_tail)) {
2656 mtx_lock(&pv_chunks_mutex);
2657 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2658 mtx_unlock(&pv_chunks_mutex);
2663 * First find and then remove the pv entry for the specified pmap and virtual
2664 * address from the specified pv list. Returns the pv entry if found and NULL
2665 * otherwise. This operation can be performed on pv lists for either 4KB or
2666 * 2MB page mappings.
2668 static __inline pv_entry_t
2669 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2673 rw_assert(&pvh_global_lock, RA_LOCKED);
2674 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2675 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2676 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2685 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2686 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2687 * entries for each of the 4KB page mappings.
2690 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2691 struct rwlock **lockp)
2693 struct md_page *pvh;
2694 struct pv_chunk *pc;
2696 vm_offset_t va_last;
2700 rw_assert(&pvh_global_lock, RA_LOCKED);
2701 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2702 KASSERT((pa & PDRMASK) == 0,
2703 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
2704 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2707 * Transfer the 2mpage's pv entry for this mapping to the first
2708 * page's pv list. Once this transfer begins, the pv list lock
2709 * must not be released until the last pv entry is reinstantiated.
2711 pvh = pa_to_pvh(pa);
2712 va = trunc_2mpage(va);
2713 pv = pmap_pvh_remove(pvh, pmap, va);
2714 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2715 m = PHYS_TO_VM_PAGE(pa);
2716 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2718 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2719 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
2720 va_last = va + NBPDR - PAGE_SIZE;
2722 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2723 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2724 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
2725 for (field = 0; field < _NPCM; field++) {
2726 while (pc->pc_map[field]) {
2727 bit = bsfq(pc->pc_map[field]);
2728 pc->pc_map[field] &= ~(1ul << bit);
2729 pv = &pc->pc_pventry[field * 64 + bit];
2733 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2734 ("pmap_pv_demote_pde: page %p is not managed", m));
2735 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2741 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2742 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2745 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2746 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2747 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2749 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
2750 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
2754 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2755 * replace the many pv entries for the 4KB page mappings by a single pv entry
2756 * for the 2MB page mapping.
2759 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2760 struct rwlock **lockp)
2762 struct md_page *pvh;
2764 vm_offset_t va_last;
2767 rw_assert(&pvh_global_lock, RA_LOCKED);
2768 KASSERT((pa & PDRMASK) == 0,
2769 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
2770 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2773 * Transfer the first page's pv entry for this mapping to the 2mpage's
2774 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2775 * a transfer avoids the possibility that get_pv_entry() calls
2776 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2777 * mappings that is being promoted.
2779 m = PHYS_TO_VM_PAGE(pa);
2780 va = trunc_2mpage(va);
2781 pv = pmap_pvh_remove(&m->md, pmap, va);
2782 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2783 pvh = pa_to_pvh(pa);
2784 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2786 /* Free the remaining NPTEPG - 1 pv entries. */
2787 va_last = va + NBPDR - PAGE_SIZE;
2791 pmap_pvh_free(&m->md, pmap, va);
2792 } while (va < va_last);
2796 * First find and then destroy the pv entry for the specified pmap and virtual
2797 * address. This operation can be performed on pv lists for either 4KB or 2MB
2801 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2805 pv = pmap_pvh_remove(pvh, pmap, va);
2806 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2807 free_pv_entry(pmap, pv);
2811 * Conditionally create the PV entry for a 4KB page mapping if the required
2812 * memory can be allocated without resorting to reclamation.
2815 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2816 struct rwlock **lockp)
2820 rw_assert(&pvh_global_lock, RA_LOCKED);
2821 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2822 /* Pass NULL instead of the lock pointer to disable reclamation. */
2823 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2825 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2826 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2834 * Conditionally create the PV entry for a 2MB page mapping if the required
2835 * memory can be allocated without resorting to reclamation.
2838 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2839 struct rwlock **lockp)
2841 struct md_page *pvh;
2844 rw_assert(&pvh_global_lock, RA_LOCKED);
2845 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2846 /* Pass NULL instead of the lock pointer to disable reclamation. */
2847 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2849 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2850 pvh = pa_to_pvh(pa);
2851 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2859 * Fills a page table page with mappings to consecutive physical pages.
2862 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2866 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2868 newpte += PAGE_SIZE;
2873 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
2874 * mapping is invalidated.
2877 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2879 struct rwlock *lock;
2883 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
2890 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
2891 struct rwlock **lockp)
2893 pd_entry_t newpde, oldpde;
2894 pt_entry_t *firstpte, newpte;
2897 struct spglist free;
2899 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2901 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2902 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2903 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2905 pmap_remove_pt_page(pmap, mpte);
2907 KASSERT((oldpde & PG_W) == 0,
2908 ("pmap_demote_pde: page table page for a wired mapping"
2912 * Invalidate the 2MB page mapping and return "failure" if the
2913 * mapping was never accessed or the allocation of the new
2914 * page table page fails. If the 2MB page mapping belongs to
2915 * the direct map region of the kernel's address space, then
2916 * the page allocation request specifies the highest possible
2917 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
2918 * normal. Page table pages are preallocated for every other
2919 * part of the kernel address space, so the direct map region
2920 * is the only part of the kernel address space that must be
2923 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2924 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
2925 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
2926 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2928 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
2930 pmap_invalidate_page(pmap, trunc_2mpage(va));
2931 pmap_free_zero_pages(&free);
2932 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
2933 " in pmap %p", va, pmap);
2936 if (va < VM_MAXUSER_ADDRESS)
2937 pmap_resident_count_inc(pmap, 1);
2939 mptepa = VM_PAGE_TO_PHYS(mpte);
2940 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
2941 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2942 KASSERT((oldpde & PG_A) != 0,
2943 ("pmap_demote_pde: oldpde is missing PG_A"));
2944 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2945 ("pmap_demote_pde: oldpde is missing PG_M"));
2946 newpte = oldpde & ~PG_PS;
2947 if ((newpte & PG_PDE_PAT) != 0)
2948 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2951 * If the page table page is new, initialize it.
2953 if (mpte->wire_count == 1) {
2954 mpte->wire_count = NPTEPG;
2955 pmap_fill_ptp(firstpte, newpte);
2957 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2958 ("pmap_demote_pde: firstpte and newpte map different physical"
2962 * If the mapping has changed attributes, update the page table
2965 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2966 pmap_fill_ptp(firstpte, newpte);
2969 * The spare PV entries must be reserved prior to demoting the
2970 * mapping, that is, prior to changing the PDE. Otherwise, the state
2971 * of the PDE and the PV lists will be inconsistent, which can result
2972 * in reclaim_pv_chunk() attempting to remove a PV entry from the
2973 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
2974 * PV entry for the 2MB page mapping that is being demoted.
2976 if ((oldpde & PG_MANAGED) != 0)
2977 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
2980 * Demote the mapping. This pmap is locked. The old PDE has
2981 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2982 * set. Thus, there is no danger of a race with another
2983 * processor changing the setting of PG_A and/or PG_M between
2984 * the read above and the store below.
2986 if (workaround_erratum383)
2987 pmap_update_pde(pmap, va, pde, newpde);
2989 pde_store(pde, newpde);
2992 * Invalidate a stale recursive mapping of the page table page.
2994 if (va >= VM_MAXUSER_ADDRESS)
2995 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2998 * Demote the PV entry.
3000 if ((oldpde & PG_MANAGED) != 0)
3001 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3003 atomic_add_long(&pmap_pde_demotions, 1);
3004 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3005 " in pmap %p", va, pmap);
3010 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3013 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3019 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3020 mpte = pmap_lookup_pt_page(pmap, va);
3022 panic("pmap_remove_kernel_pde: Missing pt page.");
3024 pmap_remove_pt_page(pmap, mpte);
3025 mptepa = VM_PAGE_TO_PHYS(mpte);
3026 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
3029 * Initialize the page table page.
3031 pagezero((void *)PHYS_TO_DMAP(mptepa));
3034 * Demote the mapping.
3036 if (workaround_erratum383)
3037 pmap_update_pde(pmap, va, pde, newpde);
3039 pde_store(pde, newpde);
3042 * Invalidate a stale recursive mapping of the page table page.
3044 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3048 * pmap_remove_pde: do the things to unmap a superpage in a process
3051 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3052 struct spglist *free, struct rwlock **lockp)
3054 struct md_page *pvh;
3056 vm_offset_t eva, va;
3059 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3060 KASSERT((sva & PDRMASK) == 0,
3061 ("pmap_remove_pde: sva is not 2mpage aligned"));
3062 oldpde = pte_load_clear(pdq);
3064 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3067 * Machines that don't support invlpg, also don't support
3071 pmap_invalidate_page(kernel_pmap, sva);
3072 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3073 if (oldpde & PG_MANAGED) {
3074 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3075 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3076 pmap_pvh_free(pvh, pmap, sva);
3078 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3079 va < eva; va += PAGE_SIZE, m++) {
3080 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3083 vm_page_aflag_set(m, PGA_REFERENCED);
3084 if (TAILQ_EMPTY(&m->md.pv_list) &&
3085 TAILQ_EMPTY(&pvh->pv_list))
3086 vm_page_aflag_clear(m, PGA_WRITEABLE);
3089 if (pmap == kernel_pmap) {
3090 pmap_remove_kernel_pde(pmap, pdq, sva);
3092 mpte = pmap_lookup_pt_page(pmap, sva);
3094 pmap_remove_pt_page(pmap, mpte);
3095 pmap_resident_count_dec(pmap, 1);
3096 KASSERT(mpte->wire_count == NPTEPG,
3097 ("pmap_remove_pde: pte page wire count error"));
3098 mpte->wire_count = 0;
3099 pmap_add_delayed_free_list(mpte, free, FALSE);
3100 atomic_subtract_int(&cnt.v_wire_count, 1);
3103 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3107 * pmap_remove_pte: do the things to unmap a page in a process
3110 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3111 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3113 struct md_page *pvh;
3117 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3118 oldpte = pte_load_clear(ptq);
3120 pmap->pm_stats.wired_count -= 1;
3121 pmap_resident_count_dec(pmap, 1);
3122 if (oldpte & PG_MANAGED) {
3123 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3124 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3127 vm_page_aflag_set(m, PGA_REFERENCED);
3128 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3129 pmap_pvh_free(&m->md, pmap, va);
3130 if (TAILQ_EMPTY(&m->md.pv_list) &&
3131 (m->flags & PG_FICTITIOUS) == 0) {
3132 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3133 if (TAILQ_EMPTY(&pvh->pv_list))
3134 vm_page_aflag_clear(m, PGA_WRITEABLE);
3137 return (pmap_unuse_pt(pmap, va, ptepde, free));
3141 * Remove a single page from a process address space
3144 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3145 struct spglist *free)
3147 struct rwlock *lock;
3150 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3151 if ((*pde & PG_V) == 0)
3153 pte = pmap_pde_to_pte(pde, va);
3154 if ((*pte & PG_V) == 0)
3157 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3160 pmap_invalidate_page(pmap, va);
3164 * Remove the given range of addresses from the specified map.
3166 * It is assumed that the start and end are properly
3167 * rounded to the page size.
3170 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3172 struct rwlock *lock;
3173 vm_offset_t va, va_next;
3174 pml4_entry_t *pml4e;
3176 pd_entry_t ptpaddr, *pde;
3178 struct spglist free;
3182 * Perform an unsynchronized read. This is, however, safe.
3184 if (pmap->pm_stats.resident_count == 0)
3190 rw_rlock(&pvh_global_lock);
3194 * special handling of removing one page. a very
3195 * common operation and easy to short circuit some
3198 if (sva + PAGE_SIZE == eva) {
3199 pde = pmap_pde(pmap, sva);
3200 if (pde && (*pde & PG_PS) == 0) {
3201 pmap_remove_page(pmap, sva, pde, &free);
3207 for (; sva < eva; sva = va_next) {
3209 if (pmap->pm_stats.resident_count == 0)
3212 pml4e = pmap_pml4e(pmap, sva);
3213 if ((*pml4e & PG_V) == 0) {
3214 va_next = (sva + NBPML4) & ~PML4MASK;
3220 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3221 if ((*pdpe & PG_V) == 0) {
3222 va_next = (sva + NBPDP) & ~PDPMASK;
3229 * Calculate index for next page table.
3231 va_next = (sva + NBPDR) & ~PDRMASK;
3235 pde = pmap_pdpe_to_pde(pdpe, sva);
3239 * Weed out invalid mappings.
3245 * Check for large page.
3247 if ((ptpaddr & PG_PS) != 0) {
3249 * Are we removing the entire large page? If not,
3250 * demote the mapping and fall through.
3252 if (sva + NBPDR == va_next && eva >= va_next) {
3254 * The TLB entry for a PG_G mapping is
3255 * invalidated by pmap_remove_pde().
3257 if ((ptpaddr & PG_G) == 0)
3259 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3261 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3263 /* The large page mapping was destroyed. */
3270 * Limit our scan to either the end of the va represented
3271 * by the current page table page, or to the end of the
3272 * range being removed.
3278 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3281 if (va != va_next) {
3282 pmap_invalidate_range(pmap, va, sva);
3287 if ((*pte & PG_G) == 0)
3289 else if (va == va_next)
3291 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3298 pmap_invalidate_range(pmap, va, sva);
3304 pmap_invalidate_all(pmap);
3305 rw_runlock(&pvh_global_lock);
3307 pmap_free_zero_pages(&free);
3311 * Routine: pmap_remove_all
3313 * Removes this physical page from
3314 * all physical maps in which it resides.
3315 * Reflects back modify bits to the pager.
3318 * Original versions of this routine were very
3319 * inefficient because they iteratively called
3320 * pmap_remove (slow...)
3324 pmap_remove_all(vm_page_t m)
3326 struct md_page *pvh;
3329 pt_entry_t *pte, tpte;
3332 struct spglist free;
3334 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3335 ("pmap_remove_all: page %p is not managed", m));
3337 rw_wlock(&pvh_global_lock);
3338 if ((m->flags & PG_FICTITIOUS) != 0)
3339 goto small_mappings;
3340 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3341 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3345 pde = pmap_pde(pmap, va);
3346 (void)pmap_demote_pde(pmap, pde, va);
3350 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3353 pmap_resident_count_dec(pmap, 1);
3354 pde = pmap_pde(pmap, pv->pv_va);
3355 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3356 " a 2mpage in page %p's pv list", m));
3357 pte = pmap_pde_to_pte(pde, pv->pv_va);
3358 tpte = pte_load_clear(pte);
3360 pmap->pm_stats.wired_count--;
3362 vm_page_aflag_set(m, PGA_REFERENCED);
3365 * Update the vm_page_t clean and reference bits.
3367 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3369 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3370 pmap_invalidate_page(pmap, pv->pv_va);
3371 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3373 free_pv_entry(pmap, pv);
3376 vm_page_aflag_clear(m, PGA_WRITEABLE);
3377 rw_wunlock(&pvh_global_lock);
3378 pmap_free_zero_pages(&free);
3382 * pmap_protect_pde: do the things to protect a 2mpage in a process
3385 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3387 pd_entry_t newpde, oldpde;
3388 vm_offset_t eva, va;
3390 boolean_t anychanged;
3392 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3393 KASSERT((sva & PDRMASK) == 0,
3394 ("pmap_protect_pde: sva is not 2mpage aligned"));
3397 oldpde = newpde = *pde;
3398 if (oldpde & PG_MANAGED) {
3400 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3401 va < eva; va += PAGE_SIZE, m++)
3402 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3405 if ((prot & VM_PROT_WRITE) == 0)
3406 newpde &= ~(PG_RW | PG_M);
3407 if ((prot & VM_PROT_EXECUTE) == 0)
3409 if (newpde != oldpde) {
3410 if (!atomic_cmpset_long(pde, oldpde, newpde))
3413 pmap_invalidate_page(pmap, sva);
3417 return (anychanged);
3421 * Set the physical protection on the
3422 * specified range of this map as requested.
3425 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3427 vm_offset_t va_next;
3428 pml4_entry_t *pml4e;
3430 pd_entry_t ptpaddr, *pde;
3432 boolean_t anychanged, pv_lists_locked;
3434 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3435 pmap_remove(pmap, sva, eva);
3439 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3440 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3443 pv_lists_locked = FALSE;
3448 for (; sva < eva; sva = va_next) {
3450 pml4e = pmap_pml4e(pmap, sva);
3451 if ((*pml4e & PG_V) == 0) {
3452 va_next = (sva + NBPML4) & ~PML4MASK;
3458 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3459 if ((*pdpe & PG_V) == 0) {
3460 va_next = (sva + NBPDP) & ~PDPMASK;
3466 va_next = (sva + NBPDR) & ~PDRMASK;
3470 pde = pmap_pdpe_to_pde(pdpe, sva);
3474 * Weed out invalid mappings.
3480 * Check for large page.
3482 if ((ptpaddr & PG_PS) != 0) {
3484 * Are we protecting the entire large page? If not,
3485 * demote the mapping and fall through.
3487 if (sva + NBPDR == va_next && eva >= va_next) {
3489 * The TLB entry for a PG_G mapping is
3490 * invalidated by pmap_protect_pde().
3492 if (pmap_protect_pde(pmap, pde, sva, prot))
3496 if (!pv_lists_locked) {
3497 pv_lists_locked = TRUE;
3498 if (!rw_try_rlock(&pvh_global_lock)) {
3500 pmap_invalidate_all(
3503 rw_rlock(&pvh_global_lock);
3507 if (!pmap_demote_pde(pmap, pde, sva)) {
3509 * The large page mapping was
3520 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3522 pt_entry_t obits, pbits;
3526 obits = pbits = *pte;
3527 if ((pbits & PG_V) == 0)
3530 if ((prot & VM_PROT_WRITE) == 0) {
3531 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3532 (PG_MANAGED | PG_M | PG_RW)) {
3533 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3536 pbits &= ~(PG_RW | PG_M);
3538 if ((prot & VM_PROT_EXECUTE) == 0)
3541 if (pbits != obits) {
3542 if (!atomic_cmpset_long(pte, obits, pbits))
3545 pmap_invalidate_page(pmap, sva);
3552 pmap_invalidate_all(pmap);
3553 if (pv_lists_locked)
3554 rw_runlock(&pvh_global_lock);
3559 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3560 * single page table page (PTP) to a single 2MB page mapping. For promotion
3561 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3562 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3563 * identical characteristics.
3566 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3567 struct rwlock **lockp)
3570 pt_entry_t *firstpte, oldpte, pa, *pte;
3571 vm_offset_t oldpteva;
3574 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3577 * Examine the first PTE in the specified PTP. Abort if this PTE is
3578 * either invalid, unused, or does not map the first 4KB physical page
3579 * within a 2MB page.
3581 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
3584 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3585 atomic_add_long(&pmap_pde_p_failures, 1);
3586 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3587 " in pmap %p", va, pmap);
3590 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3592 * When PG_M is already clear, PG_RW can be cleared without
3593 * a TLB invalidation.
3595 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
3601 * Examine each of the other PTEs in the specified PTP. Abort if this
3602 * PTE maps an unexpected 4KB physical page or does not have identical
3603 * characteristics to the first PTE.
3605 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3606 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3609 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3610 atomic_add_long(&pmap_pde_p_failures, 1);
3611 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3612 " in pmap %p", va, pmap);
3615 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3617 * When PG_M is already clear, PG_RW can be cleared
3618 * without a TLB invalidation.
3620 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
3623 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3625 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
3626 " in pmap %p", oldpteva, pmap);
3628 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3629 atomic_add_long(&pmap_pde_p_failures, 1);
3630 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3631 " in pmap %p", va, pmap);
3638 * Save the page table page in its current state until the PDE
3639 * mapping the superpage is demoted by pmap_demote_pde() or
3640 * destroyed by pmap_remove_pde().
3642 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3643 KASSERT(mpte >= vm_page_array &&
3644 mpte < &vm_page_array[vm_page_array_size],
3645 ("pmap_promote_pde: page table page is out of range"));
3646 KASSERT(mpte->pindex == pmap_pde_pindex(va),
3647 ("pmap_promote_pde: page table page's pindex is wrong"));
3648 if (pmap_insert_pt_page(pmap, mpte)) {
3649 atomic_add_long(&pmap_pde_p_failures, 1);
3651 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
3657 * Promote the pv entries.
3659 if ((newpde & PG_MANAGED) != 0)
3660 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
3663 * Propagate the PAT index to its proper position.
3665 if ((newpde & PG_PTE_PAT) != 0)
3666 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3669 * Map the superpage.
3671 if (workaround_erratum383)
3672 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3674 pde_store(pde, PG_PS | newpde);
3676 atomic_add_long(&pmap_pde_promotions, 1);
3677 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
3678 " in pmap %p", va, pmap);
3682 * Insert the given physical page (p) at
3683 * the specified virtual address (v) in the
3684 * target physical map with the protection requested.
3686 * If specified, the page will be wired down, meaning
3687 * that the related pte can not be reclaimed.
3689 * NB: This is the only routine which MAY NOT lazy-evaluate
3690 * or lose information. That is, this routine must actually
3691 * insert this page into the given map NOW.
3694 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3695 vm_prot_t prot, boolean_t wired)
3697 struct rwlock *lock;
3700 pt_entry_t newpte, origpte;
3705 va = trunc_page(va);
3706 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3707 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3708 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
3710 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
3711 va >= kmi.clean_eva,
3712 ("pmap_enter: managed mapping within the clean submap"));
3713 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3714 VM_OBJECT_ASSERT_WLOCKED(m->object);
3715 pa = VM_PAGE_TO_PHYS(m);
3716 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3717 if ((access & VM_PROT_WRITE) != 0)
3719 if ((prot & VM_PROT_WRITE) != 0)
3721 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3722 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't"));
3723 if ((prot & VM_PROT_EXECUTE) == 0)
3727 if (va < VM_MAXUSER_ADDRESS)
3729 if (pmap == kernel_pmap)
3731 newpte |= pmap_cache_bits(m->md.pat_mode, 0);
3736 rw_rlock(&pvh_global_lock);
3740 * In the case that a page table page is not
3741 * resident, we are creating it here.
3744 pde = pmap_pde(pmap, va);
3745 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
3746 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
3747 pte = pmap_pde_to_pte(pde, va);
3748 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3749 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3752 } else if (va < VM_MAXUSER_ADDRESS) {
3754 * Here if the pte page isn't mapped, or if it has been
3757 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock);
3760 panic("pmap_enter: invalid page directory va=%#lx", va);
3765 * Is the specified virtual address already mapped?
3767 if ((origpte & PG_V) != 0) {
3769 * Wiring change, just update stats. We don't worry about
3770 * wiring PT pages as they remain resident as long as there
3771 * are valid mappings in them. Hence, if a user page is wired,
3772 * the PT page will be also.
3774 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3775 pmap->pm_stats.wired_count++;
3776 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3777 pmap->pm_stats.wired_count--;
3780 * Remove the extra PT page reference.
3784 KASSERT(mpte->wire_count > 0,
3785 ("pmap_enter: missing reference to page table page,"
3790 * Has the physical page changed?
3792 opa = origpte & PG_FRAME;
3795 * No, might be a protection or wiring change.
3797 if ((origpte & PG_MANAGED) != 0) {
3798 newpte |= PG_MANAGED;
3799 if ((newpte & PG_RW) != 0)
3800 vm_page_aflag_set(m, PGA_WRITEABLE);
3802 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3808 * Increment the counters.
3810 if ((newpte & PG_W) != 0)
3811 pmap->pm_stats.wired_count++;
3812 pmap_resident_count_inc(pmap, 1);
3816 * Enter on the PV list if part of our managed memory.
3818 if ((m->oflags & VPO_UNMANAGED) == 0) {
3819 newpte |= PG_MANAGED;
3820 pv = get_pv_entry(pmap, &lock);
3822 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3823 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3825 if ((newpte & PG_RW) != 0)
3826 vm_page_aflag_set(m, PGA_WRITEABLE);
3832 if ((origpte & PG_V) != 0) {
3834 origpte = pte_load_store(pte, newpte);
3835 opa = origpte & PG_FRAME;
3837 if ((origpte & PG_MANAGED) != 0) {
3838 om = PHYS_TO_VM_PAGE(opa);
3839 if ((origpte & (PG_M | PG_RW)) == (PG_M |
3842 if ((origpte & PG_A) != 0)
3843 vm_page_aflag_set(om, PGA_REFERENCED);
3844 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3845 pmap_pvh_free(&om->md, pmap, va);
3846 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3847 TAILQ_EMPTY(&om->md.pv_list) &&
3848 ((om->flags & PG_FICTITIOUS) != 0 ||
3849 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3850 vm_page_aflag_clear(om, PGA_WRITEABLE);
3852 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
3853 PG_RW)) == (PG_M | PG_RW)) {
3854 if ((origpte & PG_MANAGED) != 0)
3858 * Although the PTE may still have PG_RW set, TLB
3859 * invalidation may nonetheless be required because
3860 * the PTE no longer has PG_M set.
3862 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3864 * This PTE change does not require TLB invalidation.
3868 if ((origpte & PG_A) != 0)
3869 pmap_invalidate_page(pmap, va);
3871 pte_store(pte, newpte);
3876 * If both the page table page and the reservation are fully
3877 * populated, then attempt promotion.
3879 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3880 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3881 vm_reserv_level_iffullpop(m) == 0)
3882 pmap_promote_pde(pmap, pde, va, &lock);
3886 rw_runlock(&pvh_global_lock);
3891 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
3892 * otherwise. Fails if (1) a page table page cannot be allocated without
3893 * blocking, (2) a mapping already exists at the specified virtual address, or
3894 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3897 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3898 struct rwlock **lockp)
3900 pd_entry_t *pde, newpde;
3902 struct spglist free;
3904 rw_assert(&pvh_global_lock, RA_LOCKED);
3905 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3906 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
3907 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3908 " in pmap %p", va, pmap);
3911 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
3912 pde = &pde[pmap_pde_index(va)];
3913 if ((*pde & PG_V) != 0) {
3914 KASSERT(mpde->wire_count > 1,
3915 ("pmap_enter_pde: mpde's wire count is too low"));
3917 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3918 " in pmap %p", va, pmap);
3921 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3923 if ((m->oflags & VPO_UNMANAGED) == 0) {
3924 newpde |= PG_MANAGED;
3927 * Abort this mapping if its PV entry could not be created.
3929 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
3932 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
3933 pmap_invalidate_page(pmap, va);
3934 pmap_free_zero_pages(&free);
3936 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3937 " in pmap %p", va, pmap);
3941 if ((prot & VM_PROT_EXECUTE) == 0)
3943 if (va < VM_MAXUSER_ADDRESS)
3947 * Increment counters.
3949 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3952 * Map the superpage.
3954 pde_store(pde, newpde);
3956 atomic_add_long(&pmap_pde_mappings, 1);
3957 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3958 " in pmap %p", va, pmap);
3963 * Maps a sequence of resident pages belonging to the same object.
3964 * The sequence begins with the given page m_start. This page is
3965 * mapped at the given virtual address start. Each subsequent page is
3966 * mapped at a virtual address that is offset from start by the same
3967 * amount as the page is offset from m_start within the object. The
3968 * last page in the sequence is the page with the largest offset from
3969 * m_start that can be mapped at a virtual address less than the given
3970 * virtual address end. Not every virtual page between start and end
3971 * is mapped; only those for which a resident page exists with the
3972 * corresponding offset from m_start are mapped.
3975 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3976 vm_page_t m_start, vm_prot_t prot)
3978 struct rwlock *lock;
3981 vm_pindex_t diff, psize;
3983 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3985 psize = atop(end - start);
3989 rw_rlock(&pvh_global_lock);
3991 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3992 va = start + ptoa(diff);
3993 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3994 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3995 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3996 pmap_enter_pde(pmap, va, m, prot, &lock))
3997 m = &m[NBPDR / PAGE_SIZE - 1];
3999 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4001 m = TAILQ_NEXT(m, listq);
4005 rw_runlock(&pvh_global_lock);
4010 * this code makes some *MAJOR* assumptions:
4011 * 1. Current pmap & pmap exists.
4014 * 4. No page table pages.
4015 * but is *MUCH* faster than pmap_enter...
4019 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4021 struct rwlock *lock;
4024 rw_rlock(&pvh_global_lock);
4026 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4029 rw_runlock(&pvh_global_lock);
4034 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4035 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4037 struct spglist free;
4041 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4042 (m->oflags & VPO_UNMANAGED) != 0,
4043 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4044 rw_assert(&pvh_global_lock, RA_LOCKED);
4045 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4048 * In the case that a page table page is not
4049 * resident, we are creating it here.
4051 if (va < VM_MAXUSER_ADDRESS) {
4052 vm_pindex_t ptepindex;
4056 * Calculate pagetable page index
4058 ptepindex = pmap_pde_pindex(va);
4059 if (mpte && (mpte->pindex == ptepindex)) {
4063 * Get the page directory entry
4065 ptepa = pmap_pde(pmap, va);
4068 * If the page table page is mapped, we just increment
4069 * the hold count, and activate it. Otherwise, we
4070 * attempt to allocate a page table page. If this
4071 * attempt fails, we don't retry. Instead, we give up.
4073 if (ptepa && (*ptepa & PG_V) != 0) {
4076 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4080 * Pass NULL instead of the PV list lock
4081 * pointer, because we don't intend to sleep.
4083 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4088 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4089 pte = &pte[pmap_pte_index(va)];
4103 * Enter on the PV list if part of our managed memory.
4105 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4106 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4109 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4110 pmap_invalidate_page(pmap, va);
4111 pmap_free_zero_pages(&free);
4119 * Increment counters
4121 pmap_resident_count_inc(pmap, 1);
4123 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
4124 if ((prot & VM_PROT_EXECUTE) == 0)
4128 * Now validate mapping with RO protection
4130 if ((m->oflags & VPO_UNMANAGED) != 0)
4131 pte_store(pte, pa | PG_V | PG_U);
4133 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4138 * Make a temporary mapping for a physical address. This is only intended
4139 * to be used for panic dumps.
4142 pmap_kenter_temporary(vm_paddr_t pa, int i)
4146 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4147 pmap_kenter(va, pa);
4149 return ((void *)crashdumpmap);
4153 * This code maps large physical mmap regions into the
4154 * processor address space. Note that some shortcuts
4155 * are taken, but the code works.
4158 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4159 vm_pindex_t pindex, vm_size_t size)
4162 vm_paddr_t pa, ptepa;
4166 VM_OBJECT_ASSERT_WLOCKED(object);
4167 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4168 ("pmap_object_init_pt: non-device object"));
4169 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4170 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4172 p = vm_page_lookup(object, pindex);
4173 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4174 ("pmap_object_init_pt: invalid page %p", p));
4175 pat_mode = p->md.pat_mode;
4178 * Abort the mapping if the first page is not physically
4179 * aligned to a 2MB page boundary.
4181 ptepa = VM_PAGE_TO_PHYS(p);
4182 if (ptepa & (NBPDR - 1))
4186 * Skip the first page. Abort the mapping if the rest of
4187 * the pages are not physically contiguous or have differing
4188 * memory attributes.
4190 p = TAILQ_NEXT(p, listq);
4191 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4193 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4194 ("pmap_object_init_pt: invalid page %p", p));
4195 if (pa != VM_PAGE_TO_PHYS(p) ||
4196 pat_mode != p->md.pat_mode)
4198 p = TAILQ_NEXT(p, listq);
4202 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4203 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4204 * will not affect the termination of this loop.
4207 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4208 size; pa += NBPDR) {
4209 pdpg = pmap_allocpde(pmap, addr, NULL);
4212 * The creation of mappings below is only an
4213 * optimization. If a page directory page
4214 * cannot be allocated without blocking,
4215 * continue on to the next mapping rather than
4221 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4222 pde = &pde[pmap_pde_index(addr)];
4223 if ((*pde & PG_V) == 0) {
4224 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4225 PG_U | PG_RW | PG_V);
4226 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4227 atomic_add_long(&pmap_pde_mappings, 1);
4229 /* Continue on if the PDE is already valid. */
4231 KASSERT(pdpg->wire_count > 0,
4232 ("pmap_object_init_pt: missing reference "
4233 "to page directory page, va: 0x%lx", addr));
4242 * Routine: pmap_change_wiring
4243 * Function: Change the wiring attribute for a map/virtual-address
4245 * In/out conditions:
4246 * The mapping must already exist in the pmap.
4249 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
4253 boolean_t pv_lists_locked;
4255 pv_lists_locked = FALSE;
4258 * Wiring is not a hardware characteristic so there is no need to
4263 pde = pmap_pde(pmap, va);
4264 if ((*pde & PG_PS) != 0) {
4265 if (!wired != ((*pde & PG_W) == 0)) {
4266 if (!pv_lists_locked) {
4267 pv_lists_locked = TRUE;
4268 if (!rw_try_rlock(&pvh_global_lock)) {
4270 rw_rlock(&pvh_global_lock);
4274 if (!pmap_demote_pde(pmap, pde, va))
4275 panic("pmap_change_wiring: demotion failed");
4279 pte = pmap_pde_to_pte(pde, va);
4280 if (wired && (*pte & PG_W) == 0) {
4281 pmap->pm_stats.wired_count++;
4282 atomic_set_long(pte, PG_W);
4283 } else if (!wired && (*pte & PG_W) != 0) {
4284 pmap->pm_stats.wired_count--;
4285 atomic_clear_long(pte, PG_W);
4288 if (pv_lists_locked)
4289 rw_runlock(&pvh_global_lock);
4294 * Copy the range specified by src_addr/len
4295 * from the source map to the range dst_addr/len
4296 * in the destination map.
4298 * This routine is only advisory and need not do anything.
4302 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4303 vm_offset_t src_addr)
4305 struct rwlock *lock;
4306 struct spglist free;
4308 vm_offset_t end_addr = src_addr + len;
4309 vm_offset_t va_next;
4311 if (dst_addr != src_addr)
4315 rw_rlock(&pvh_global_lock);
4316 if (dst_pmap < src_pmap) {
4317 PMAP_LOCK(dst_pmap);
4318 PMAP_LOCK(src_pmap);
4320 PMAP_LOCK(src_pmap);
4321 PMAP_LOCK(dst_pmap);
4323 for (addr = src_addr; addr < end_addr; addr = va_next) {
4324 pt_entry_t *src_pte, *dst_pte;
4325 vm_page_t dstmpde, dstmpte, srcmpte;
4326 pml4_entry_t *pml4e;
4328 pd_entry_t srcptepaddr, *pde;
4330 KASSERT(addr < UPT_MIN_ADDRESS,
4331 ("pmap_copy: invalid to pmap_copy page tables"));
4333 pml4e = pmap_pml4e(src_pmap, addr);
4334 if ((*pml4e & PG_V) == 0) {
4335 va_next = (addr + NBPML4) & ~PML4MASK;
4341 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4342 if ((*pdpe & PG_V) == 0) {
4343 va_next = (addr + NBPDP) & ~PDPMASK;
4349 va_next = (addr + NBPDR) & ~PDRMASK;
4353 pde = pmap_pdpe_to_pde(pdpe, addr);
4355 if (srcptepaddr == 0)
4358 if (srcptepaddr & PG_PS) {
4359 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4361 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4362 if (dstmpde == NULL)
4364 pde = (pd_entry_t *)
4365 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4366 pde = &pde[pmap_pde_index(addr)];
4367 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4368 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4369 PG_PS_FRAME, &lock))) {
4370 *pde = srcptepaddr & ~PG_W;
4371 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4373 dstmpde->wire_count--;
4377 srcptepaddr &= PG_FRAME;
4378 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4379 KASSERT(srcmpte->wire_count > 0,
4380 ("pmap_copy: source page table page is unused"));
4382 if (va_next > end_addr)
4385 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4386 src_pte = &src_pte[pmap_pte_index(addr)];
4388 while (addr < va_next) {
4392 * we only virtual copy managed pages
4394 if ((ptetemp & PG_MANAGED) != 0) {
4395 if (dstmpte != NULL &&
4396 dstmpte->pindex == pmap_pde_pindex(addr))
4397 dstmpte->wire_count++;
4398 else if ((dstmpte = pmap_allocpte(dst_pmap,
4399 addr, NULL)) == NULL)
4401 dst_pte = (pt_entry_t *)
4402 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4403 dst_pte = &dst_pte[pmap_pte_index(addr)];
4404 if (*dst_pte == 0 &&
4405 pmap_try_insert_pv_entry(dst_pmap, addr,
4406 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4409 * Clear the wired, modified, and
4410 * accessed (referenced) bits
4413 *dst_pte = ptetemp & ~(PG_W | PG_M |
4415 pmap_resident_count_inc(dst_pmap, 1);
4418 if (pmap_unwire_ptp(dst_pmap, addr,
4420 pmap_invalidate_page(dst_pmap,
4422 pmap_free_zero_pages(&free);
4426 if (dstmpte->wire_count >= srcmpte->wire_count)
4436 rw_runlock(&pvh_global_lock);
4437 PMAP_UNLOCK(src_pmap);
4438 PMAP_UNLOCK(dst_pmap);
4442 * pmap_zero_page zeros the specified hardware page by mapping
4443 * the page into KVM and using bzero to clear its contents.
4446 pmap_zero_page(vm_page_t m)
4448 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4450 pagezero((void *)va);
4454 * pmap_zero_page_area zeros the specified hardware page by mapping
4455 * the page into KVM and using bzero to clear its contents.
4457 * off and size may not cover an area beyond a single hardware page.
4460 pmap_zero_page_area(vm_page_t m, int off, int size)
4462 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4464 if (off == 0 && size == PAGE_SIZE)
4465 pagezero((void *)va);
4467 bzero((char *)va + off, size);
4471 * pmap_zero_page_idle zeros the specified hardware page by mapping
4472 * the page into KVM and using bzero to clear its contents. This
4473 * is intended to be called from the vm_pagezero process only and
4477 pmap_zero_page_idle(vm_page_t m)
4479 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4481 pagezero((void *)va);
4485 * pmap_copy_page copies the specified (machine independent)
4486 * page by mapping the page into virtual memory and using
4487 * bcopy to copy the page, one machine dependent page at a
4491 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4493 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4494 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4496 pagecopy((void *)src, (void *)dst);
4499 int unmapped_buf_allowed = 1;
4502 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4503 vm_offset_t b_offset, int xfersize)
4506 vm_offset_t a_pg_offset, b_pg_offset;
4509 while (xfersize > 0) {
4510 a_pg_offset = a_offset & PAGE_MASK;
4511 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4512 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]->
4513 phys_addr) + a_pg_offset;
4514 b_pg_offset = b_offset & PAGE_MASK;
4515 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4516 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]->
4517 phys_addr) + b_pg_offset;
4518 bcopy(a_cp, b_cp, cnt);
4526 * Returns true if the pmap's pv is one of the first
4527 * 16 pvs linked to from this page. This count may
4528 * be changed upwards or downwards in the future; it
4529 * is only necessary that true be returned for a small
4530 * subset of pmaps for proper page aging.
4533 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4535 struct md_page *pvh;
4536 struct rwlock *lock;
4541 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4542 ("pmap_page_exists_quick: page %p is not managed", m));
4544 rw_rlock(&pvh_global_lock);
4545 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4547 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4548 if (PV_PMAP(pv) == pmap) {
4556 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4557 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4558 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4559 if (PV_PMAP(pv) == pmap) {
4569 rw_runlock(&pvh_global_lock);
4574 * pmap_page_wired_mappings:
4576 * Return the number of managed mappings to the given physical page
4580 pmap_page_wired_mappings(vm_page_t m)
4582 struct rwlock *lock;
4583 struct md_page *pvh;
4587 int count, md_gen, pvh_gen;
4589 if ((m->oflags & VPO_UNMANAGED) != 0)
4591 rw_rlock(&pvh_global_lock);
4592 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4596 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4598 if (!PMAP_TRYLOCK(pmap)) {
4599 md_gen = m->md.pv_gen;
4603 if (md_gen != m->md.pv_gen) {
4608 pte = pmap_pte(pmap, pv->pv_va);
4609 if ((*pte & PG_W) != 0)
4613 if ((m->flags & PG_FICTITIOUS) == 0) {
4614 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4615 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4617 if (!PMAP_TRYLOCK(pmap)) {
4618 md_gen = m->md.pv_gen;
4619 pvh_gen = pvh->pv_gen;
4623 if (md_gen != m->md.pv_gen ||
4624 pvh_gen != pvh->pv_gen) {
4629 pte = pmap_pde(pmap, pv->pv_va);
4630 if ((*pte & PG_W) != 0)
4636 rw_runlock(&pvh_global_lock);
4641 * Returns TRUE if the given page is mapped individually or as part of
4642 * a 2mpage. Otherwise, returns FALSE.
4645 pmap_page_is_mapped(vm_page_t m)
4647 struct rwlock *lock;
4650 if ((m->oflags & VPO_UNMANAGED) != 0)
4652 rw_rlock(&pvh_global_lock);
4653 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4655 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4656 ((m->flags & PG_FICTITIOUS) == 0 &&
4657 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4659 rw_runlock(&pvh_global_lock);
4664 * Remove all pages from specified address space
4665 * this aids process exit speeds. Also, this code
4666 * is special cased for current process only, but
4667 * can have the more generic (and slightly slower)
4668 * mode enabled. This is much faster than pmap_remove
4669 * in the case of running down an entire address space.
4672 pmap_remove_pages(pmap_t pmap)
4675 pt_entry_t *pte, tpte;
4676 struct spglist free;
4677 vm_page_t m, mpte, mt;
4679 struct md_page *pvh;
4680 struct pv_chunk *pc, *npc;
4681 struct rwlock *lock;
4683 uint64_t inuse, bitmask;
4684 int allfree, field, freed, idx;
4685 boolean_t superpage;
4688 if (pmap != PCPU_GET(curpmap)) {
4689 printf("warning: pmap_remove_pages called with non-current pmap\n");
4694 rw_rlock(&pvh_global_lock);
4696 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4699 for (field = 0; field < _NPCM; field++) {
4700 inuse = ~pc->pc_map[field] & pc_freemask[field];
4701 while (inuse != 0) {
4703 bitmask = 1UL << bit;
4704 idx = field * 64 + bit;
4705 pv = &pc->pc_pventry[idx];
4708 pte = pmap_pdpe(pmap, pv->pv_va);
4710 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
4712 if ((tpte & (PG_PS | PG_V)) == PG_V) {
4715 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
4717 pte = &pte[pmap_pte_index(pv->pv_va)];
4721 * Keep track whether 'tpte' is a
4722 * superpage explicitly instead of
4723 * relying on PG_PS being set.
4725 * This is because PG_PS is numerically
4726 * identical to PG_PTE_PAT and thus a
4727 * regular page could be mistaken for
4733 if ((tpte & PG_V) == 0) {
4734 panic("bad pte va %lx pte %lx",
4739 * We cannot remove wired pages from a process' mapping at this time
4747 pa = tpte & PG_PS_FRAME;
4749 pa = tpte & PG_FRAME;
4751 m = PHYS_TO_VM_PAGE(pa);
4752 KASSERT(m->phys_addr == pa,
4753 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4754 m, (uintmax_t)m->phys_addr,
4757 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4758 m < &vm_page_array[vm_page_array_size],
4759 ("pmap_remove_pages: bad tpte %#jx",
4765 * Update the vm_page_t clean/reference bits.
4767 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4769 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4775 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4778 pc->pc_map[field] |= bitmask;
4780 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4781 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4782 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4784 if (TAILQ_EMPTY(&pvh->pv_list)) {
4785 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4786 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4787 TAILQ_EMPTY(&mt->md.pv_list))
4788 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4790 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4792 pmap_remove_pt_page(pmap, mpte);
4793 pmap_resident_count_dec(pmap, 1);
4794 KASSERT(mpte->wire_count == NPTEPG,
4795 ("pmap_remove_pages: pte page wire count error"));
4796 mpte->wire_count = 0;
4797 pmap_add_delayed_free_list(mpte, &free, FALSE);
4798 atomic_subtract_int(&cnt.v_wire_count, 1);
4801 pmap_resident_count_dec(pmap, 1);
4802 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4804 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4805 TAILQ_EMPTY(&m->md.pv_list) &&
4806 (m->flags & PG_FICTITIOUS) == 0) {
4807 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4808 if (TAILQ_EMPTY(&pvh->pv_list))
4809 vm_page_aflag_clear(m, PGA_WRITEABLE);
4812 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
4816 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4817 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4818 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4820 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4826 pmap_invalidate_all(pmap);
4827 rw_runlock(&pvh_global_lock);
4829 pmap_free_zero_pages(&free);
4833 pmap_page_test_mappings(vm_page_t m, pt_entry_t mask)
4835 struct rwlock *lock;
4837 struct md_page *pvh;
4840 int md_gen, pvh_gen;
4844 rw_rlock(&pvh_global_lock);
4845 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4848 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4850 if (!PMAP_TRYLOCK(pmap)) {
4851 md_gen = m->md.pv_gen;
4855 if (md_gen != m->md.pv_gen) {
4860 pte = pmap_pte(pmap, pv->pv_va);
4861 rv = (*pte & mask) == mask;
4866 if ((m->flags & PG_FICTITIOUS) == 0) {
4867 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4868 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4870 if (!PMAP_TRYLOCK(pmap)) {
4871 md_gen = m->md.pv_gen;
4872 pvh_gen = pvh->pv_gen;
4876 if (md_gen != m->md.pv_gen ||
4877 pvh_gen != pvh->pv_gen) {
4882 pte = pmap_pde(pmap, pv->pv_va);
4883 rv = (*pte & mask) == mask;
4891 rw_runlock(&pvh_global_lock);
4898 * Return whether or not the specified physical page was modified
4899 * in any physical maps.
4902 pmap_is_modified(vm_page_t m)
4905 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4906 ("pmap_is_modified: page %p is not managed", m));
4909 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4910 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4911 * is clear, no PTEs can have PG_M set.
4913 VM_OBJECT_ASSERT_WLOCKED(m->object);
4914 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4916 return (pmap_page_test_mappings(m, PG_M | PG_RW));
4920 * pmap_is_prefaultable:
4922 * Return whether or not the specified virtual address is elgible
4926 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4934 pde = pmap_pde(pmap, addr);
4935 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
4936 pte = pmap_pde_to_pte(pde, addr);
4937 rv = (*pte & PG_V) == 0;
4944 * pmap_is_referenced:
4946 * Return whether or not the specified physical page was referenced
4947 * in any physical maps.
4950 pmap_is_referenced(vm_page_t m)
4953 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4954 ("pmap_is_referenced: page %p is not managed", m));
4955 return (pmap_page_test_mappings(m, PG_A | PG_V));
4959 * Clear the write and modified bits in each of the given page's mappings.
4962 pmap_remove_write(vm_page_t m)
4964 struct md_page *pvh;
4966 struct rwlock *lock;
4967 pv_entry_t next_pv, pv;
4969 pt_entry_t oldpte, *pte;
4971 int pvh_gen, md_gen;
4973 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4974 ("pmap_remove_write: page %p is not managed", m));
4977 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4978 * set by another thread while the object is locked. Thus,
4979 * if PGA_WRITEABLE is clear, no page table entries need updating.
4981 VM_OBJECT_ASSERT_WLOCKED(m->object);
4982 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4984 rw_rlock(&pvh_global_lock);
4985 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4986 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4989 if ((m->flags & PG_FICTITIOUS) != 0)
4990 goto small_mappings;
4991 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4993 if (!PMAP_TRYLOCK(pmap)) {
4994 pvh_gen = pvh->pv_gen;
4998 if (pvh_gen != pvh->pv_gen) {
5005 pde = pmap_pde(pmap, va);
5006 if ((*pde & PG_RW) != 0)
5007 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5008 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5009 ("inconsistent pv lock %p %p for page %p",
5010 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5014 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5016 if (!PMAP_TRYLOCK(pmap)) {
5017 pvh_gen = pvh->pv_gen;
5018 md_gen = m->md.pv_gen;
5022 if (pvh_gen != pvh->pv_gen ||
5023 md_gen != m->md.pv_gen) {
5029 pde = pmap_pde(pmap, pv->pv_va);
5030 KASSERT((*pde & PG_PS) == 0,
5031 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5033 pte = pmap_pde_to_pte(pde, pv->pv_va);
5036 if (oldpte & PG_RW) {
5037 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5040 if ((oldpte & PG_M) != 0)
5042 pmap_invalidate_page(pmap, pv->pv_va);
5047 vm_page_aflag_clear(m, PGA_WRITEABLE);
5048 rw_runlock(&pvh_global_lock);
5051 #define PMAP_TS_REFERENCED_MAX 5
5054 * pmap_ts_referenced:
5056 * Return a count of reference bits for a page, clearing those bits.
5057 * It is not necessary for every reference bit to be cleared, but it
5058 * is necessary that 0 only be returned when there are truly no
5059 * reference bits set.
5061 * XXX: The exact number of bits to check and clear is a matter that
5062 * should be tested and standardized at some point in the future for
5063 * optimal aging of shared pages.
5066 pmap_ts_referenced(vm_page_t m)
5068 struct md_page *pvh;
5071 struct rwlock *lock;
5075 int cleared, md_gen, not_cleared, pvh_gen;
5077 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5078 ("pmap_ts_referenced: page %p is not managed", m));
5080 pa = VM_PAGE_TO_PHYS(m);
5081 lock = PHYS_TO_PV_LIST_LOCK(pa);
5082 pvh = pa_to_pvh(pa);
5083 rw_rlock(&pvh_global_lock);
5087 if ((m->flags & PG_FICTITIOUS) != 0 ||
5088 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5089 goto small_mappings;
5093 if (!PMAP_TRYLOCK(pmap)) {
5094 pvh_gen = pvh->pv_gen;
5098 if (pvh_gen != pvh->pv_gen) {
5103 pde = pmap_pde(pmap, pv->pv_va);
5104 if ((*pde & PG_A) != 0) {
5106 * Since this reference bit is shared by 512 4KB
5107 * pages, it should not be cleared every time it is
5108 * tested. Apply a simple "hash" function on the
5109 * physical page number, the virtual superpage number,
5110 * and the pmap address to select one 4KB page out of
5111 * the 512 on which testing the reference bit will
5112 * result in clearing that reference bit. This
5113 * function is designed to avoid the selection of the
5114 * same 4KB page for every 2MB page mapping.
5116 * On demotion, a mapping that hasn't been referenced
5117 * is simply destroyed. To avoid the possibility of a
5118 * subsequent page fault on a demoted wired mapping,
5119 * always leave its reference bit set. Moreover,
5120 * since the superpage is wired, the current state of
5121 * its reference bit won't affect page replacement.
5123 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5124 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5125 (*pde & PG_W) == 0) {
5126 atomic_clear_long(pde, PG_A);
5127 pmap_invalidate_page(pmap, pv->pv_va);
5133 /* Rotate the PV list if it has more than one entry. */
5134 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5135 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5136 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5139 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5141 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5143 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5148 if (!PMAP_TRYLOCK(pmap)) {
5149 pvh_gen = pvh->pv_gen;
5150 md_gen = m->md.pv_gen;
5154 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5159 pde = pmap_pde(pmap, pv->pv_va);
5160 KASSERT((*pde & PG_PS) == 0,
5161 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5163 pte = pmap_pde_to_pte(pde, pv->pv_va);
5164 if ((*pte & PG_A) != 0) {
5165 atomic_clear_long(pte, PG_A);
5166 pmap_invalidate_page(pmap, pv->pv_va);
5170 /* Rotate the PV list if it has more than one entry. */
5171 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5172 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5173 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5176 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5177 not_cleared < PMAP_TS_REFERENCED_MAX);
5180 rw_runlock(&pvh_global_lock);
5181 return (cleared + not_cleared);
5185 * Apply the given advice to the specified range of addresses within the
5186 * given pmap. Depending on the advice, clear the referenced and/or
5187 * modified flags in each mapping and set the mapped page's dirty field.
5190 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5192 struct rwlock *lock;
5193 pml4_entry_t *pml4e;
5195 pd_entry_t oldpde, *pde;
5197 vm_offset_t va_next;
5199 boolean_t anychanged, pv_lists_locked;
5201 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5203 pv_lists_locked = FALSE;
5207 for (; sva < eva; sva = va_next) {
5208 pml4e = pmap_pml4e(pmap, sva);
5209 if ((*pml4e & PG_V) == 0) {
5210 va_next = (sva + NBPML4) & ~PML4MASK;
5215 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5216 if ((*pdpe & PG_V) == 0) {
5217 va_next = (sva + NBPDP) & ~PDPMASK;
5222 va_next = (sva + NBPDR) & ~PDRMASK;
5225 pde = pmap_pdpe_to_pde(pdpe, sva);
5227 if ((oldpde & PG_V) == 0)
5229 else if ((oldpde & PG_PS) != 0) {
5230 if ((oldpde & PG_MANAGED) == 0)
5232 if (!pv_lists_locked) {
5233 pv_lists_locked = TRUE;
5234 if (!rw_try_rlock(&pvh_global_lock)) {
5236 pmap_invalidate_all(pmap);
5238 rw_rlock(&pvh_global_lock);
5243 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5248 * The large page mapping was destroyed.
5254 * Unless the page mappings are wired, remove the
5255 * mapping to a single page so that a subsequent
5256 * access may repromote. Since the underlying page
5257 * table page is fully populated, this removal never
5258 * frees a page table page.
5260 if ((oldpde & PG_W) == 0) {
5261 pte = pmap_pde_to_pte(pde, sva);
5262 KASSERT((*pte & PG_V) != 0,
5263 ("pmap_advise: invalid PTE"));
5264 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
5273 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5275 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
5278 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5279 if (advice == MADV_DONTNEED) {
5281 * Future calls to pmap_is_modified()
5282 * can be avoided by making the page
5285 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5288 atomic_clear_long(pte, PG_M | PG_A);
5289 } else if ((*pte & PG_A) != 0)
5290 atomic_clear_long(pte, PG_A);
5293 if ((*pte & PG_G) != 0)
5294 pmap_invalidate_page(pmap, sva);
5300 pmap_invalidate_all(pmap);
5301 if (pv_lists_locked)
5302 rw_runlock(&pvh_global_lock);
5307 * Clear the modify bits on the specified physical page.
5310 pmap_clear_modify(vm_page_t m)
5312 struct md_page *pvh;
5314 pv_entry_t next_pv, pv;
5315 pd_entry_t oldpde, *pde;
5316 pt_entry_t oldpte, *pte;
5317 struct rwlock *lock;
5319 int md_gen, pvh_gen;
5321 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5322 ("pmap_clear_modify: page %p is not managed", m));
5323 VM_OBJECT_ASSERT_WLOCKED(m->object);
5324 KASSERT(!vm_page_xbusied(m),
5325 ("pmap_clear_modify: page %p is exclusive busied", m));
5328 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5329 * If the object containing the page is locked and the page is not
5330 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5332 if ((m->aflags & PGA_WRITEABLE) == 0)
5334 rw_rlock(&pvh_global_lock);
5335 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5338 if ((m->flags & PG_FICTITIOUS) != 0)
5339 goto small_mappings;
5340 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5341 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5343 if (!PMAP_TRYLOCK(pmap)) {
5344 pvh_gen = pvh->pv_gen;
5348 if (pvh_gen != pvh->pv_gen) {
5354 pde = pmap_pde(pmap, va);
5356 if ((oldpde & PG_RW) != 0) {
5357 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
5358 if ((oldpde & PG_W) == 0) {
5360 * Write protect the mapping to a
5361 * single page so that a subsequent
5362 * write access may repromote.
5364 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5366 pte = pmap_pde_to_pte(pde, va);
5368 if ((oldpte & PG_V) != 0) {
5369 while (!atomic_cmpset_long(pte,
5371 oldpte & ~(PG_M | PG_RW)))
5374 pmap_invalidate_page(pmap, va);
5382 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5384 if (!PMAP_TRYLOCK(pmap)) {
5385 md_gen = m->md.pv_gen;
5386 pvh_gen = pvh->pv_gen;
5390 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5395 pde = pmap_pde(pmap, pv->pv_va);
5396 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5397 " a 2mpage in page %p's pv list", m));
5398 pte = pmap_pde_to_pte(pde, pv->pv_va);
5399 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5400 atomic_clear_long(pte, PG_M);
5401 pmap_invalidate_page(pmap, pv->pv_va);
5406 rw_runlock(&pvh_global_lock);
5410 * Miscellaneous support routines follow
5413 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5414 static __inline void
5415 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5420 * The cache mode bits are all in the low 32-bits of the
5421 * PTE, so we can just spin on updating the low 32-bits.
5424 opte = *(u_int *)pte;
5425 npte = opte & ~PG_PTE_CACHE;
5427 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5430 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
5431 static __inline void
5432 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5437 * The cache mode bits are all in the low 32-bits of the
5438 * PDE, so we can just spin on updating the low 32-bits.
5441 opde = *(u_int *)pde;
5442 npde = opde & ~PG_PDE_CACHE;
5444 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5448 * Map a set of physical memory pages into the kernel virtual
5449 * address space. Return a pointer to where it is mapped. This
5450 * routine is intended to be used for mapping device memory,
5454 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5456 vm_offset_t va, offset;
5460 * If the specified range of physical addresses fits within the direct
5461 * map window, use the direct map.
5463 if (pa < dmaplimit && pa + size < dmaplimit) {
5464 va = PHYS_TO_DMAP(pa);
5465 if (!pmap_change_attr(va, size, mode))
5466 return ((void *)va);
5468 offset = pa & PAGE_MASK;
5469 size = round_page(offset + size);
5470 va = kva_alloc(size);
5472 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5473 pa = trunc_page(pa);
5474 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5475 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5476 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5477 pmap_invalidate_cache_range(va, va + tmpsize);
5478 return ((void *)(va + offset));
5482 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5485 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5489 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5492 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5496 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5498 vm_offset_t base, offset;
5500 /* If we gave a direct map region in pmap_mapdev, do nothing */
5501 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
5503 base = trunc_page(va);
5504 offset = va & PAGE_MASK;
5505 size = round_page(offset + size);
5506 kva_free(base, size);
5510 * Tries to demote a 1GB page mapping.
5513 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
5515 pdp_entry_t newpdpe, oldpdpe;
5516 pd_entry_t *firstpde, newpde, *pde;
5520 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5522 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
5523 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
5524 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
5525 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5526 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
5527 " in pmap %p", va, pmap);
5530 mpdepa = VM_PAGE_TO_PHYS(mpde);
5531 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
5532 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
5533 KASSERT((oldpdpe & PG_A) != 0,
5534 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
5535 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
5536 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
5540 * Initialize the page directory page.
5542 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
5548 * Demote the mapping.
5553 * Invalidate a stale recursive mapping of the page directory page.
5555 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
5557 pmap_pdpe_demotions++;
5558 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
5559 " in pmap %p", va, pmap);
5564 * Sets the memory attribute for the specified page.
5567 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5570 m->md.pat_mode = ma;
5573 * If "m" is a normal page, update its direct mapping. This update
5574 * can be relied upon to perform any cache operations that are
5575 * required for data coherence.
5577 if ((m->flags & PG_FICTITIOUS) == 0 &&
5578 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5580 panic("memory attribute change on the direct map failed");
5584 * Changes the specified virtual address range's memory type to that given by
5585 * the parameter "mode". The specified virtual address range must be
5586 * completely contained within either the direct map or the kernel map. If
5587 * the virtual address range is contained within the kernel map, then the
5588 * memory type for each of the corresponding ranges of the direct map is also
5589 * changed. (The corresponding ranges of the direct map are those ranges that
5590 * map the same physical pages as the specified virtual address range.) These
5591 * changes to the direct map are necessary because Intel describes the
5592 * behavior of their processors as "undefined" if two or more mappings to the
5593 * same physical page have different memory types.
5595 * Returns zero if the change completed successfully, and either EINVAL or
5596 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5597 * of the virtual address range was not mapped, and ENOMEM is returned if
5598 * there was insufficient memory available to complete the change. In the
5599 * latter case, the memory type may have been changed on some part of the
5600 * virtual address range or the direct map.
5603 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5607 PMAP_LOCK(kernel_pmap);
5608 error = pmap_change_attr_locked(va, size, mode);
5609 PMAP_UNLOCK(kernel_pmap);
5614 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5616 vm_offset_t base, offset, tmpva;
5617 vm_paddr_t pa_start, pa_end;
5621 int cache_bits_pte, cache_bits_pde, error;
5624 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5625 base = trunc_page(va);
5626 offset = va & PAGE_MASK;
5627 size = round_page(offset + size);
5630 * Only supported on kernel virtual addresses, including the direct
5631 * map but excluding the recursive map.
5633 if (base < DMAP_MIN_ADDRESS)
5636 cache_bits_pde = pmap_cache_bits(mode, 1);
5637 cache_bits_pte = pmap_cache_bits(mode, 0);
5641 * Pages that aren't mapped aren't supported. Also break down 2MB pages
5642 * into 4KB pages if required.
5644 for (tmpva = base; tmpva < base + size; ) {
5645 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5648 if (*pdpe & PG_PS) {
5650 * If the current 1GB page already has the required
5651 * memory type, then we need not demote this page. Just
5652 * increment tmpva to the next 1GB page frame.
5654 if ((*pdpe & PG_PDE_CACHE) == cache_bits_pde) {
5655 tmpva = trunc_1gpage(tmpva) + NBPDP;
5660 * If the current offset aligns with a 1GB page frame
5661 * and there is at least 1GB left within the range, then
5662 * we need not break down this page into 2MB pages.
5664 if ((tmpva & PDPMASK) == 0 &&
5665 tmpva + PDPMASK < base + size) {
5669 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
5672 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5677 * If the current 2MB page already has the required
5678 * memory type, then we need not demote this page. Just
5679 * increment tmpva to the next 2MB page frame.
5681 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5682 tmpva = trunc_2mpage(tmpva) + NBPDR;
5687 * If the current offset aligns with a 2MB page frame
5688 * and there is at least 2MB left within the range, then
5689 * we need not break down this page into 4KB pages.
5691 if ((tmpva & PDRMASK) == 0 &&
5692 tmpva + PDRMASK < base + size) {
5696 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
5699 pte = pmap_pde_to_pte(pde, tmpva);
5707 * Ok, all the pages exist, so run through them updating their
5708 * cache mode if required.
5710 pa_start = pa_end = 0;
5711 for (tmpva = base; tmpva < base + size; ) {
5712 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5713 if (*pdpe & PG_PS) {
5714 if ((*pdpe & PG_PDE_CACHE) != cache_bits_pde) {
5715 pmap_pde_attr(pdpe, cache_bits_pde);
5718 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5719 if (pa_start == pa_end) {
5720 /* Start physical address run. */
5721 pa_start = *pdpe & PG_PS_FRAME;
5722 pa_end = pa_start + NBPDP;
5723 } else if (pa_end == (*pdpe & PG_PS_FRAME))
5726 /* Run ended, update direct map. */
5727 error = pmap_change_attr_locked(
5728 PHYS_TO_DMAP(pa_start),
5729 pa_end - pa_start, mode);
5732 /* Start physical address run. */
5733 pa_start = *pdpe & PG_PS_FRAME;
5734 pa_end = pa_start + NBPDP;
5737 tmpva = trunc_1gpage(tmpva) + NBPDP;
5740 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5742 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5743 pmap_pde_attr(pde, cache_bits_pde);
5746 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5747 if (pa_start == pa_end) {
5748 /* Start physical address run. */
5749 pa_start = *pde & PG_PS_FRAME;
5750 pa_end = pa_start + NBPDR;
5751 } else if (pa_end == (*pde & PG_PS_FRAME))
5754 /* Run ended, update direct map. */
5755 error = pmap_change_attr_locked(
5756 PHYS_TO_DMAP(pa_start),
5757 pa_end - pa_start, mode);
5760 /* Start physical address run. */
5761 pa_start = *pde & PG_PS_FRAME;
5762 pa_end = pa_start + NBPDR;
5765 tmpva = trunc_2mpage(tmpva) + NBPDR;
5767 pte = pmap_pde_to_pte(pde, tmpva);
5768 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5769 pmap_pte_attr(pte, cache_bits_pte);
5772 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5773 if (pa_start == pa_end) {
5774 /* Start physical address run. */
5775 pa_start = *pte & PG_FRAME;
5776 pa_end = pa_start + PAGE_SIZE;
5777 } else if (pa_end == (*pte & PG_FRAME))
5778 pa_end += PAGE_SIZE;
5780 /* Run ended, update direct map. */
5781 error = pmap_change_attr_locked(
5782 PHYS_TO_DMAP(pa_start),
5783 pa_end - pa_start, mode);
5786 /* Start physical address run. */
5787 pa_start = *pte & PG_FRAME;
5788 pa_end = pa_start + PAGE_SIZE;
5794 if (error == 0 && pa_start != pa_end)
5795 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
5796 pa_end - pa_start, mode);
5799 * Flush CPU caches if required to make sure any data isn't cached that
5800 * shouldn't be, etc.
5803 pmap_invalidate_range(kernel_pmap, base, tmpva);
5804 pmap_invalidate_cache_range(base, tmpva);
5810 * Demotes any mapping within the direct map region that covers more than the
5811 * specified range of physical addresses. This range's size must be a power
5812 * of two and its starting address must be a multiple of its size. Since the
5813 * demotion does not change any attributes of the mapping, a TLB invalidation
5814 * is not mandatory. The caller may, however, request a TLB invalidation.
5817 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
5826 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
5827 KASSERT((base & (len - 1)) == 0,
5828 ("pmap_demote_DMAP: base is not a multiple of len"));
5829 if (len < NBPDP && base < dmaplimit) {
5830 va = PHYS_TO_DMAP(base);
5832 PMAP_LOCK(kernel_pmap);
5833 pdpe = pmap_pdpe(kernel_pmap, va);
5834 if ((*pdpe & PG_V) == 0)
5835 panic("pmap_demote_DMAP: invalid PDPE");
5836 if ((*pdpe & PG_PS) != 0) {
5837 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
5838 panic("pmap_demote_DMAP: PDPE failed");
5842 pde = pmap_pdpe_to_pde(pdpe, va);
5843 if ((*pde & PG_V) == 0)
5844 panic("pmap_demote_DMAP: invalid PDE");
5845 if ((*pde & PG_PS) != 0) {
5846 if (!pmap_demote_pde(kernel_pmap, pde, va))
5847 panic("pmap_demote_DMAP: PDE failed");
5851 if (changed && invalidate)
5852 pmap_invalidate_page(kernel_pmap, va);
5853 PMAP_UNLOCK(kernel_pmap);
5858 * perform the pmap work for mincore
5861 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5870 pdep = pmap_pde(pmap, addr);
5871 if (pdep != NULL && (*pdep & PG_V)) {
5872 if (*pdep & PG_PS) {
5874 /* Compute the physical address of the 4KB page. */
5875 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5877 val = MINCORE_SUPER;
5879 pte = *pmap_pde_to_pte(pdep, addr);
5880 pa = pte & PG_FRAME;
5888 if ((pte & PG_V) != 0) {
5889 val |= MINCORE_INCORE;
5890 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5891 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5892 if ((pte & PG_A) != 0)
5893 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5895 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5896 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5897 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5898 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5899 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5902 PA_UNLOCK_COND(*locked_pa);
5908 pmap_activate(struct thread *td)
5910 pmap_t pmap, oldpmap;
5914 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5915 oldpmap = PCPU_GET(curpmap);
5916 cpuid = PCPU_GET(cpuid);
5918 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5919 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5920 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
5922 CPU_CLR(cpuid, &oldpmap->pm_active);
5923 CPU_SET(cpuid, &pmap->pm_active);
5924 CPU_SET(cpuid, &pmap->pm_save);
5926 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
5927 load_cr3(pmap->pm_cr3);
5928 PCPU_SET(curpmap, pmap);
5933 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5938 * Increase the starting virtual address of the given mapping if a
5939 * different alignment might result in more superpage mappings.
5942 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5943 vm_offset_t *addr, vm_size_t size)
5945 vm_offset_t superpage_offset;
5949 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5950 offset += ptoa(object->pg_color);
5951 superpage_offset = offset & PDRMASK;
5952 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5953 (*addr & PDRMASK) == superpage_offset)
5955 if ((*addr & PDRMASK) < superpage_offset)
5956 *addr = (*addr & ~PDRMASK) + superpage_offset;
5958 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5961 #include "opt_ddb.h"
5963 #include <ddb/ddb.h>
5965 DB_SHOW_COMMAND(pte, pmap_print_pte)
5975 va = (vm_offset_t)addr;
5976 pmap = PCPU_GET(curpmap); /* XXX */
5978 db_printf("show pte addr\n");
5981 pml4 = pmap_pml4e(pmap, va);
5982 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
5983 if ((*pml4 & PG_V) == 0) {
5987 pdp = pmap_pml4e_to_pdpe(pml4, va);
5988 db_printf(" pdpe %#016lx", *pdp);
5989 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
5993 pde = pmap_pdpe_to_pde(pdp, va);
5994 db_printf(" pde %#016lx", *pde);
5995 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
5999 pte = pmap_pde_to_pte(pde, va);
6000 db_printf(" pte %#016lx\n", *pte);
6003 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
6008 a = (vm_paddr_t)addr;
6009 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
6011 db_printf("show phys2dmap addr\n");