2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmem.h>
119 #include <sys/vmmeter.h>
120 #include <sys/sched.h>
121 #include <sys/sysctl.h>
122 #include <sys/_unrhdr.h>
126 #include <vm/vm_param.h>
127 #include <vm/vm_kern.h>
128 #include <vm/vm_page.h>
129 #include <vm/vm_map.h>
130 #include <vm/vm_object.h>
131 #include <vm/vm_extern.h>
132 #include <vm/vm_pageout.h>
133 #include <vm/vm_pager.h>
134 #include <vm/vm_phys.h>
135 #include <vm/vm_radix.h>
136 #include <vm/vm_reserv.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
141 #include <machine/cpu.h>
142 #include <machine/cputypes.h>
143 #include <machine/md_var.h>
144 #include <machine/pcb.h>
145 #include <machine/specialreg.h>
147 #include <machine/smp.h>
150 static __inline boolean_t
151 pmap_type_guest(pmap_t pmap)
154 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
157 static __inline boolean_t
158 pmap_emulate_ad_bits(pmap_t pmap)
161 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
164 static __inline pt_entry_t
165 pmap_valid_bit(pmap_t pmap)
169 switch (pmap->pm_type) {
175 if (pmap_emulate_ad_bits(pmap))
176 mask = EPT_PG_EMUL_V;
181 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
187 static __inline pt_entry_t
188 pmap_rw_bit(pmap_t pmap)
192 switch (pmap->pm_type) {
198 if (pmap_emulate_ad_bits(pmap))
199 mask = EPT_PG_EMUL_RW;
204 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
210 static __inline pt_entry_t
211 pmap_global_bit(pmap_t pmap)
215 switch (pmap->pm_type) {
224 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
230 static __inline pt_entry_t
231 pmap_accessed_bit(pmap_t pmap)
235 switch (pmap->pm_type) {
241 if (pmap_emulate_ad_bits(pmap))
247 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
253 static __inline pt_entry_t
254 pmap_modified_bit(pmap_t pmap)
258 switch (pmap->pm_type) {
264 if (pmap_emulate_ad_bits(pmap))
270 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
276 extern struct pcpu __pcpu[];
278 #if !defined(DIAGNOSTIC)
279 #ifdef __GNUC_GNU_INLINE__
280 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
282 #define PMAP_INLINE extern inline
289 #define PV_STAT(x) do { x ; } while (0)
291 #define PV_STAT(x) do { } while (0)
294 #define pa_index(pa) ((pa) >> PDRSHIFT)
295 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
297 #define NPV_LIST_LOCKS MAXCPU
299 #define PHYS_TO_PV_LIST_LOCK(pa) \
300 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
302 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
303 struct rwlock **_lockp = (lockp); \
304 struct rwlock *_new_lock; \
306 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
307 if (_new_lock != *_lockp) { \
308 if (*_lockp != NULL) \
309 rw_wunlock(*_lockp); \
310 *_lockp = _new_lock; \
315 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
316 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
318 #define RELEASE_PV_LIST_LOCK(lockp) do { \
319 struct rwlock **_lockp = (lockp); \
321 if (*_lockp != NULL) { \
322 rw_wunlock(*_lockp); \
327 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
328 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
330 struct pmap kernel_pmap_store;
332 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
333 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
336 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
337 "Number of kernel page table pages allocated on bootup");
340 vm_paddr_t dmaplimit;
341 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
344 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
346 static int pat_works = 1;
347 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
348 "Is page attribute table fully functional?");
350 static int pg_ps_enabled = 1;
351 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
352 &pg_ps_enabled, 0, "Are large page mappings enabled?");
354 #define PAT_INDEX_SIZE 8
355 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
357 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
358 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
359 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
360 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
362 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
363 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
364 static int ndmpdpphys; /* number of DMPDPphys pages */
367 * pmap_mapdev support pre initialization (i.e. console)
369 #define PMAP_PREINIT_MAPPING_COUNT 8
370 static struct pmap_preinit_mapping {
375 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
376 static int pmap_initialized;
378 static struct rwlock_padalign pvh_global_lock;
381 * Data for the pv entry allocation mechanism
383 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
384 static struct mtx pv_chunks_mutex;
385 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
386 static struct md_page *pv_table;
389 * All those kernel PT submaps that BSD is so fond of
391 pt_entry_t *CMAP1 = 0;
393 static vm_offset_t qframe = 0;
394 static struct mtx qframe_mtx;
396 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
398 int pmap_pcid_enabled = 1;
399 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
400 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
401 int invpcid_works = 0;
402 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
403 "Is the invpcid instruction available ?");
406 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
413 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
415 return (sysctl_handle_64(oidp, &res, 0, req));
417 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
418 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
419 "Count of saved TLB context on switch");
424 static caddr_t crashdumpmap;
426 static void free_pv_chunk(struct pv_chunk *pc);
427 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
428 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
429 static int popcnt_pc_map_elem_pq(uint64_t elem);
430 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
431 static void reserve_pv_entries(pmap_t pmap, int needed,
432 struct rwlock **lockp);
433 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
434 struct rwlock **lockp);
435 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
436 struct rwlock **lockp);
437 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
438 struct rwlock **lockp);
439 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
440 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
443 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
444 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
445 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
446 vm_offset_t va, struct rwlock **lockp);
447 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
449 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
450 vm_prot_t prot, struct rwlock **lockp);
451 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
452 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
453 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
454 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
455 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
456 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
457 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
458 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
459 struct rwlock **lockp);
460 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
462 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
463 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
464 struct spglist *free, struct rwlock **lockp);
465 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
466 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
467 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
468 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
469 struct spglist *free);
470 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
471 vm_page_t m, struct rwlock **lockp);
472 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
474 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
476 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
477 struct rwlock **lockp);
478 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
479 struct rwlock **lockp);
480 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
481 struct rwlock **lockp);
483 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
484 struct spglist *free);
485 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
486 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
489 * Move the kernel virtual free pointer to the next
490 * 2MB. This is used to help improve performance
491 * by using a large (2MB) page for much of the kernel
492 * (.text, .data, .bss)
495 pmap_kmem_choose(vm_offset_t addr)
497 vm_offset_t newaddr = addr;
499 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
503 /********************/
504 /* Inline functions */
505 /********************/
507 /* Return a non-clipped PD index for a given VA */
508 static __inline vm_pindex_t
509 pmap_pde_pindex(vm_offset_t va)
511 return (va >> PDRSHIFT);
515 /* Return various clipped indexes for a given VA */
516 static __inline vm_pindex_t
517 pmap_pte_index(vm_offset_t va)
520 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
523 static __inline vm_pindex_t
524 pmap_pde_index(vm_offset_t va)
527 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
530 static __inline vm_pindex_t
531 pmap_pdpe_index(vm_offset_t va)
534 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
537 static __inline vm_pindex_t
538 pmap_pml4e_index(vm_offset_t va)
541 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
544 /* Return a pointer to the PML4 slot that corresponds to a VA */
545 static __inline pml4_entry_t *
546 pmap_pml4e(pmap_t pmap, vm_offset_t va)
549 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
552 /* Return a pointer to the PDP slot that corresponds to a VA */
553 static __inline pdp_entry_t *
554 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
558 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
559 return (&pdpe[pmap_pdpe_index(va)]);
562 /* Return a pointer to the PDP slot that corresponds to a VA */
563 static __inline pdp_entry_t *
564 pmap_pdpe(pmap_t pmap, vm_offset_t va)
569 PG_V = pmap_valid_bit(pmap);
570 pml4e = pmap_pml4e(pmap, va);
571 if ((*pml4e & PG_V) == 0)
573 return (pmap_pml4e_to_pdpe(pml4e, va));
576 /* Return a pointer to the PD slot that corresponds to a VA */
577 static __inline pd_entry_t *
578 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
582 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
583 return (&pde[pmap_pde_index(va)]);
586 /* Return a pointer to the PD slot that corresponds to a VA */
587 static __inline pd_entry_t *
588 pmap_pde(pmap_t pmap, vm_offset_t va)
593 PG_V = pmap_valid_bit(pmap);
594 pdpe = pmap_pdpe(pmap, va);
595 if (pdpe == NULL || (*pdpe & PG_V) == 0)
597 return (pmap_pdpe_to_pde(pdpe, va));
600 /* Return a pointer to the PT slot that corresponds to a VA */
601 static __inline pt_entry_t *
602 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
606 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
607 return (&pte[pmap_pte_index(va)]);
610 /* Return a pointer to the PT slot that corresponds to a VA */
611 static __inline pt_entry_t *
612 pmap_pte(pmap_t pmap, vm_offset_t va)
617 PG_V = pmap_valid_bit(pmap);
618 pde = pmap_pde(pmap, va);
619 if (pde == NULL || (*pde & PG_V) == 0)
621 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
622 return ((pt_entry_t *)pde);
623 return (pmap_pde_to_pte(pde, va));
627 pmap_resident_count_inc(pmap_t pmap, int count)
630 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
631 pmap->pm_stats.resident_count += count;
635 pmap_resident_count_dec(pmap_t pmap, int count)
638 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
639 KASSERT(pmap->pm_stats.resident_count >= count,
640 ("pmap %p resident count underflow %ld %d", pmap,
641 pmap->pm_stats.resident_count, count));
642 pmap->pm_stats.resident_count -= count;
645 PMAP_INLINE pt_entry_t *
646 vtopte(vm_offset_t va)
648 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
650 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
652 return (PTmap + ((va >> PAGE_SHIFT) & mask));
655 static __inline pd_entry_t *
656 vtopde(vm_offset_t va)
658 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
660 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
662 return (PDmap + ((va >> PDRSHIFT) & mask));
666 allocpages(vm_paddr_t *firstaddr, int n)
671 bzero((void *)ret, n * PAGE_SIZE);
672 *firstaddr += n * PAGE_SIZE;
676 CTASSERT(powerof2(NDMPML4E));
678 /* number of kernel PDP slots */
679 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
682 nkpt_init(vm_paddr_t addr)
689 pt_pages = howmany(addr, 1 << PDRSHIFT);
690 pt_pages += NKPDPE(pt_pages);
693 * Add some slop beyond the bare minimum required for bootstrapping
696 * This is quite important when allocating KVA for kernel modules.
697 * The modules are required to be linked in the negative 2GB of
698 * the address space. If we run out of KVA in this region then
699 * pmap_growkernel() will need to allocate page table pages to map
700 * the entire 512GB of KVA space which is an unnecessary tax on
703 * Secondly, device memory mapped as part of setting up the low-
704 * level console(s) is taken from KVA, starting at virtual_avail.
705 * This is because cninit() is called after pmap_bootstrap() but
706 * before vm_init() and pmap_init(). 20MB for a frame buffer is
709 pt_pages += 32; /* 64MB additional slop. */
715 create_pagetables(vm_paddr_t *firstaddr)
717 int i, j, ndm1g, nkpdpe;
723 /* Allocate page table pages for the direct map */
724 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
725 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
727 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
728 if (ndmpdpphys > NDMPML4E) {
730 * Each NDMPML4E allows 512 GB, so limit to that,
731 * and then readjust ndmpdp and ndmpdpphys.
733 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
734 Maxmem = atop(NDMPML4E * NBPML4);
735 ndmpdpphys = NDMPML4E;
736 ndmpdp = NDMPML4E * NPDEPG;
738 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
740 if ((amd_feature & AMDID_PAGE1GB) != 0)
741 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
743 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
744 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
747 KPML4phys = allocpages(firstaddr, 1);
748 KPDPphys = allocpages(firstaddr, NKPML4E);
751 * Allocate the initial number of kernel page table pages required to
752 * bootstrap. We defer this until after all memory-size dependent
753 * allocations are done (e.g. direct map), so that we don't have to
754 * build in too much slop in our estimate.
756 * Note that when NKPML4E > 1, we have an empty page underneath
757 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
758 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
760 nkpt_init(*firstaddr);
761 nkpdpe = NKPDPE(nkpt);
763 KPTphys = allocpages(firstaddr, nkpt);
764 KPDphys = allocpages(firstaddr, nkpdpe);
766 /* Fill in the underlying page table pages */
767 /* Nominally read-only (but really R/W) from zero to physfree */
768 /* XXX not fully used, underneath 2M pages */
769 pt_p = (pt_entry_t *)KPTphys;
770 for (i = 0; ptoa(i) < *firstaddr; i++)
771 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
773 /* Now map the page tables at their location within PTmap */
774 pd_p = (pd_entry_t *)KPDphys;
775 for (i = 0; i < nkpt; i++)
776 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
778 /* Map from zero to end of allocations under 2M pages */
779 /* This replaces some of the KPTphys entries above */
780 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
781 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
784 /* And connect up the PD to the PDP (leaving room for L4 pages) */
785 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
786 for (i = 0; i < nkpdpe; i++)
787 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
791 * Now, set up the direct map region using 2MB and/or 1GB pages. If
792 * the end of physical memory is not aligned to a 1GB page boundary,
793 * then the residual physical memory is mapped with 2MB pages. Later,
794 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
795 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
796 * that are partially used.
798 pd_p = (pd_entry_t *)DMPDphys;
799 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
800 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
801 /* Preset PG_M and PG_A because demotion expects it. */
802 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
805 pdp_p = (pdp_entry_t *)DMPDPphys;
806 for (i = 0; i < ndm1g; i++) {
807 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
808 /* Preset PG_M and PG_A because demotion expects it. */
809 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
812 for (j = 0; i < ndmpdp; i++, j++) {
813 pdp_p[i] = DMPDphys + ptoa(j);
814 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
817 /* And recursively map PML4 to itself in order to get PTmap */
818 p4_p = (pml4_entry_t *)KPML4phys;
819 p4_p[PML4PML4I] = KPML4phys;
820 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
822 /* Connect the Direct Map slot(s) up to the PML4. */
823 for (i = 0; i < ndmpdpphys; i++) {
824 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
825 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
828 /* Connect the KVA slots up to the PML4 */
829 for (i = 0; i < NKPML4E; i++) {
830 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
831 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
836 * Bootstrap the system enough to run with virtual memory.
838 * On amd64 this is called after mapping has already been enabled
839 * and just syncs the pmap module with what has already been done.
840 * [We can't call it easily with mapping off since the kernel is not
841 * mapped with PA == VA, hence we would have to relocate every address
842 * from the linked base (virtual) address "KERNBASE" to the actual
843 * (physical) address starting relative to 0]
846 pmap_bootstrap(vm_paddr_t *firstaddr)
853 * Create an initial set of page tables to run the kernel in.
855 create_pagetables(firstaddr);
858 * Add a physical memory segment (vm_phys_seg) corresponding to the
859 * preallocated kernel page table pages so that vm_page structures
860 * representing these pages will be created. The vm_page structures
861 * are required for promotion of the corresponding kernel virtual
862 * addresses to superpage mappings.
864 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
866 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
867 virtual_avail = pmap_kmem_choose(virtual_avail);
869 virtual_end = VM_MAX_KERNEL_ADDRESS;
872 /* XXX do %cr0 as well */
873 load_cr4(rcr4() | CR4_PGE);
875 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
876 load_cr4(rcr4() | CR4_SMEP);
879 * Initialize the kernel pmap (which is statically allocated).
881 PMAP_LOCK_INIT(kernel_pmap);
882 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
883 kernel_pmap->pm_cr3 = KPML4phys;
884 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
885 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
886 kernel_pmap->pm_flags = pmap_flags;
889 * Initialize the global pv list lock.
891 rw_init(&pvh_global_lock, "pmap pv global");
894 * Reserve some special page table entries/VA space for temporary
897 #define SYSMAP(c, p, v, n) \
898 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
904 * Crashdump maps. The first page is reused as CMAP1 for the
907 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
908 CADDR1 = crashdumpmap;
912 /* Initialize the PAT MSR. */
915 /* Initialize TLB Context Id. */
916 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
917 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
918 /* Check for INVPCID support */
919 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
921 for (i = 0; i < MAXCPU; i++) {
922 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
923 kernel_pmap->pm_pcids[i].pm_gen = 1;
925 __pcpu[0].pc_pcid_next = PMAP_PCID_KERN + 1;
926 __pcpu[0].pc_pcid_gen = 1;
928 * pcpu area for APs is zeroed during AP startup.
929 * pc_pcid_next and pc_pcid_gen are initialized by AP
932 load_cr4(rcr4() | CR4_PCIDE);
934 pmap_pcid_enabled = 0;
944 int pat_table[PAT_INDEX_SIZE];
949 /* Bail if this CPU doesn't implement PAT. */
950 if ((cpu_feature & CPUID_PAT) == 0)
953 /* Set default PAT index table. */
954 for (i = 0; i < PAT_INDEX_SIZE; i++)
956 pat_table[PAT_WRITE_BACK] = 0;
957 pat_table[PAT_WRITE_THROUGH] = 1;
958 pat_table[PAT_UNCACHEABLE] = 3;
959 pat_table[PAT_WRITE_COMBINING] = 3;
960 pat_table[PAT_WRITE_PROTECTED] = 3;
961 pat_table[PAT_UNCACHED] = 3;
963 /* Initialize default PAT entries. */
964 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
965 PAT_VALUE(1, PAT_WRITE_THROUGH) |
966 PAT_VALUE(2, PAT_UNCACHED) |
967 PAT_VALUE(3, PAT_UNCACHEABLE) |
968 PAT_VALUE(4, PAT_WRITE_BACK) |
969 PAT_VALUE(5, PAT_WRITE_THROUGH) |
970 PAT_VALUE(6, PAT_UNCACHED) |
971 PAT_VALUE(7, PAT_UNCACHEABLE);
975 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
976 * Program 5 and 6 as WP and WC.
977 * Leave 4 and 7 as WB and UC.
979 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
980 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
981 PAT_VALUE(6, PAT_WRITE_COMBINING);
982 pat_table[PAT_UNCACHED] = 2;
983 pat_table[PAT_WRITE_PROTECTED] = 5;
984 pat_table[PAT_WRITE_COMBINING] = 6;
987 * Just replace PAT Index 2 with WC instead of UC-.
989 pat_msr &= ~PAT_MASK(2);
990 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
991 pat_table[PAT_WRITE_COMBINING] = 2;
996 load_cr4(cr4 & ~CR4_PGE);
998 /* Disable caches (CD = 1, NW = 0). */
1000 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1002 /* Flushes caches and TLBs. */
1006 /* Update PAT and index table. */
1007 wrmsr(MSR_PAT, pat_msr);
1008 for (i = 0; i < PAT_INDEX_SIZE; i++)
1009 pat_index[i] = pat_table[i];
1011 /* Flush caches and TLBs again. */
1015 /* Restore caches and PGE. */
1021 * Initialize a vm_page's machine-dependent fields.
1024 pmap_page_init(vm_page_t m)
1027 TAILQ_INIT(&m->md.pv_list);
1028 m->md.pat_mode = PAT_WRITE_BACK;
1032 * Initialize the pmap module.
1033 * Called by vm_init, to initialize any structures that the pmap
1034 * system needs to map virtual memory.
1039 struct pmap_preinit_mapping *ppim;
1042 int error, i, pv_npg;
1045 * Initialize the vm page array entries for the kernel pmap's
1048 for (i = 0; i < nkpt; i++) {
1049 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1050 KASSERT(mpte >= vm_page_array &&
1051 mpte < &vm_page_array[vm_page_array_size],
1052 ("pmap_init: page table page is out of range"));
1053 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1054 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1058 * If the kernel is running on a virtual machine, then it must assume
1059 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1060 * be prepared for the hypervisor changing the vendor and family that
1061 * are reported by CPUID. Consequently, the workaround for AMD Family
1062 * 10h Erratum 383 is enabled if the processor's feature set does not
1063 * include at least one feature that is only supported by older Intel
1064 * or newer AMD processors.
1066 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1067 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1068 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1070 workaround_erratum383 = 1;
1073 * Are large page mappings enabled?
1075 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1076 if (pg_ps_enabled) {
1077 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1078 ("pmap_init: can't assign to pagesizes[1]"));
1079 pagesizes[1] = NBPDR;
1083 * Initialize the pv chunk list mutex.
1085 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1088 * Initialize the pool of pv list locks.
1090 for (i = 0; i < NPV_LIST_LOCKS; i++)
1091 rw_init(&pv_list_locks[i], "pmap pv list");
1094 * Calculate the size of the pv head table for superpages.
1096 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1099 * Allocate memory for the pv head table for superpages.
1101 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1103 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1105 for (i = 0; i < pv_npg; i++)
1106 TAILQ_INIT(&pv_table[i].pv_list);
1108 pmap_initialized = 1;
1109 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1110 ppim = pmap_preinit_mapping + i;
1113 /* Make the direct map consistent */
1114 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz < dmaplimit) {
1115 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1116 ppim->sz, ppim->mode);
1120 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1121 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1124 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1125 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1126 (vmem_addr_t *)&qframe);
1128 panic("qframe allocation failed");
1131 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1132 "2MB page mapping counters");
1134 static u_long pmap_pde_demotions;
1135 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1136 &pmap_pde_demotions, 0, "2MB page demotions");
1138 static u_long pmap_pde_mappings;
1139 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1140 &pmap_pde_mappings, 0, "2MB page mappings");
1142 static u_long pmap_pde_p_failures;
1143 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1144 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1146 static u_long pmap_pde_promotions;
1147 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1148 &pmap_pde_promotions, 0, "2MB page promotions");
1150 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1151 "1GB page mapping counters");
1153 static u_long pmap_pdpe_demotions;
1154 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1155 &pmap_pdpe_demotions, 0, "1GB page demotions");
1157 /***************************************************
1158 * Low level helper routines.....
1159 ***************************************************/
1162 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1164 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1166 switch (pmap->pm_type) {
1169 /* Verify that both PAT bits are not set at the same time */
1170 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1171 ("Invalid PAT bits in entry %#lx", entry));
1173 /* Swap the PAT bits if one of them is set */
1174 if ((entry & x86_pat_bits) != 0)
1175 entry ^= x86_pat_bits;
1179 * Nothing to do - the memory attributes are represented
1180 * the same way for regular pages and superpages.
1184 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1191 * Determine the appropriate bits to set in a PTE or PDE for a specified
1195 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1197 int cache_bits, pat_flag, pat_idx;
1199 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1200 panic("Unknown caching mode %d\n", mode);
1202 switch (pmap->pm_type) {
1205 /* The PAT bit is different for PTE's and PDE's. */
1206 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1208 /* Map the caching mode to a PAT index. */
1209 pat_idx = pat_index[mode];
1211 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1214 cache_bits |= pat_flag;
1216 cache_bits |= PG_NC_PCD;
1218 cache_bits |= PG_NC_PWT;
1222 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1226 panic("unsupported pmap type %d", pmap->pm_type);
1229 return (cache_bits);
1233 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1237 switch (pmap->pm_type) {
1240 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1243 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1246 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1252 static __inline boolean_t
1253 pmap_ps_enabled(pmap_t pmap)
1256 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1260 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1263 switch (pmap->pm_type) {
1270 * This is a little bogus since the generation number is
1271 * supposed to be bumped up when a region of the address
1272 * space is invalidated in the page tables.
1274 * In this case the old PDE entry is valid but yet we want
1275 * to make sure that any mappings using the old entry are
1276 * invalidated in the TLB.
1278 * The reason this works as expected is because we rendezvous
1279 * "all" host cpus and force any vcpu context to exit as a
1282 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1285 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1287 pde_store(pde, newpde);
1291 * After changing the page size for the specified virtual address in the page
1292 * table, flush the corresponding entries from the processor's TLB. Only the
1293 * calling processor's TLB is affected.
1295 * The calling thread must be pinned to a processor.
1298 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1302 if (pmap_type_guest(pmap))
1305 KASSERT(pmap->pm_type == PT_X86,
1306 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1308 PG_G = pmap_global_bit(pmap);
1310 if ((newpde & PG_PS) == 0)
1311 /* Demotion: flush a specific 2MB page mapping. */
1313 else if ((newpde & PG_G) == 0)
1315 * Promotion: flush every 4KB page mapping from the TLB
1316 * because there are too many to flush individually.
1321 * Promotion: flush every 4KB page mapping from the TLB,
1322 * including any global (PG_G) mappings.
1330 * For SMP, these functions have to use the IPI mechanism for coherence.
1332 * N.B.: Before calling any of the following TLB invalidation functions,
1333 * the calling processor must ensure that all stores updating a non-
1334 * kernel page table are globally performed. Otherwise, another
1335 * processor could cache an old, pre-update entry without being
1336 * invalidated. This can happen one of two ways: (1) The pmap becomes
1337 * active on another processor after its pm_active field is checked by
1338 * one of the following functions but before a store updating the page
1339 * table is globally performed. (2) The pmap becomes active on another
1340 * processor before its pm_active field is checked but due to
1341 * speculative loads one of the following functions stills reads the
1342 * pmap as inactive on the other processor.
1344 * The kernel page table is exempt because its pm_active field is
1345 * immutable. The kernel page table is always active on every
1350 * Interrupt the cpus that are executing in the guest context.
1351 * This will force the vcpu to exit and the cached EPT mappings
1352 * will be invalidated by the host before the next vmresume.
1354 static __inline void
1355 pmap_invalidate_ept(pmap_t pmap)
1360 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1361 ("pmap_invalidate_ept: absurd pm_active"));
1364 * The TLB mappings associated with a vcpu context are not
1365 * flushed each time a different vcpu is chosen to execute.
1367 * This is in contrast with a process's vtop mappings that
1368 * are flushed from the TLB on each context switch.
1370 * Therefore we need to do more than just a TLB shootdown on
1371 * the active cpus in 'pmap->pm_active'. To do this we keep
1372 * track of the number of invalidations performed on this pmap.
1374 * Each vcpu keeps a cache of this counter and compares it
1375 * just before a vmresume. If the counter is out-of-date an
1376 * invept will be done to flush stale mappings from the TLB.
1378 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1381 * Force the vcpu to exit and trap back into the hypervisor.
1383 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1384 ipi_selected(pmap->pm_active, ipinum);
1389 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1394 if (pmap_type_guest(pmap)) {
1395 pmap_invalidate_ept(pmap);
1399 KASSERT(pmap->pm_type == PT_X86,
1400 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1403 if (pmap == kernel_pmap) {
1407 cpuid = PCPU_GET(cpuid);
1408 if (pmap == PCPU_GET(curpmap))
1410 else if (pmap_pcid_enabled)
1411 pmap->pm_pcids[cpuid].pm_gen = 0;
1412 if (pmap_pcid_enabled) {
1415 pmap->pm_pcids[i].pm_gen = 0;
1418 mask = &pmap->pm_active;
1420 smp_masked_invlpg(*mask, va);
1424 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1425 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1428 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1434 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1435 pmap_invalidate_all(pmap);
1439 if (pmap_type_guest(pmap)) {
1440 pmap_invalidate_ept(pmap);
1444 KASSERT(pmap->pm_type == PT_X86,
1445 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1448 cpuid = PCPU_GET(cpuid);
1449 if (pmap == kernel_pmap) {
1450 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1454 if (pmap == PCPU_GET(curpmap)) {
1455 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1457 } else if (pmap_pcid_enabled) {
1458 pmap->pm_pcids[cpuid].pm_gen = 0;
1460 if (pmap_pcid_enabled) {
1463 pmap->pm_pcids[i].pm_gen = 0;
1466 mask = &pmap->pm_active;
1468 smp_masked_invlpg_range(*mask, sva, eva);
1473 pmap_invalidate_all(pmap_t pmap)
1476 struct invpcid_descr d;
1479 if (pmap_type_guest(pmap)) {
1480 pmap_invalidate_ept(pmap);
1484 KASSERT(pmap->pm_type == PT_X86,
1485 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1488 if (pmap == kernel_pmap) {
1489 if (pmap_pcid_enabled && invpcid_works) {
1490 bzero(&d, sizeof(d));
1491 invpcid(&d, INVPCID_CTXGLOB);
1497 cpuid = PCPU_GET(cpuid);
1498 if (pmap == PCPU_GET(curpmap)) {
1499 if (pmap_pcid_enabled) {
1500 if (invpcid_works) {
1501 d.pcid = pmap->pm_pcids[cpuid].pm_pcid;
1504 invpcid(&d, INVPCID_CTX);
1506 load_cr3(pmap->pm_cr3 | pmap->pm_pcids
1507 [PCPU_GET(cpuid)].pm_pcid);
1512 } else if (pmap_pcid_enabled) {
1513 pmap->pm_pcids[cpuid].pm_gen = 0;
1515 if (pmap_pcid_enabled) {
1518 pmap->pm_pcids[i].pm_gen = 0;
1521 mask = &pmap->pm_active;
1523 smp_masked_invltlb(*mask, pmap);
1528 pmap_invalidate_cache(void)
1538 cpuset_t invalidate; /* processors that invalidate their TLB */
1543 u_int store; /* processor that updates the PDE */
1547 pmap_update_pde_action(void *arg)
1549 struct pde_action *act = arg;
1551 if (act->store == PCPU_GET(cpuid))
1552 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1556 pmap_update_pde_teardown(void *arg)
1558 struct pde_action *act = arg;
1560 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1561 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1565 * Change the page size for the specified virtual address in a way that
1566 * prevents any possibility of the TLB ever having two entries that map the
1567 * same virtual address using different page sizes. This is the recommended
1568 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1569 * machine check exception for a TLB state that is improperly diagnosed as a
1573 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1575 struct pde_action act;
1576 cpuset_t active, other_cpus;
1580 cpuid = PCPU_GET(cpuid);
1581 other_cpus = all_cpus;
1582 CPU_CLR(cpuid, &other_cpus);
1583 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1586 active = pmap->pm_active;
1588 if (CPU_OVERLAP(&active, &other_cpus)) {
1590 act.invalidate = active;
1594 act.newpde = newpde;
1595 CPU_SET(cpuid, &active);
1596 smp_rendezvous_cpus(active,
1597 smp_no_rendevous_barrier, pmap_update_pde_action,
1598 pmap_update_pde_teardown, &act);
1600 pmap_update_pde_store(pmap, pde, newpde);
1601 if (CPU_ISSET(cpuid, &active))
1602 pmap_update_pde_invalidate(pmap, va, newpde);
1608 * Normal, non-SMP, invalidation functions.
1611 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1614 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1618 KASSERT(pmap->pm_type == PT_X86,
1619 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
1621 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
1623 else if (pmap_pcid_enabled)
1624 pmap->pm_pcids[0].pm_gen = 0;
1628 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1632 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1636 KASSERT(pmap->pm_type == PT_X86,
1637 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
1639 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
1640 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1642 } else if (pmap_pcid_enabled) {
1643 pmap->pm_pcids[0].pm_gen = 0;
1648 pmap_invalidate_all(pmap_t pmap)
1650 struct invpcid_descr d;
1652 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
1656 KASSERT(pmap->pm_type == PT_X86,
1657 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
1659 if (pmap == kernel_pmap) {
1660 if (pmap_pcid_enabled && invpcid_works) {
1661 bzero(&d, sizeof(d));
1662 invpcid(&d, INVPCID_CTXGLOB);
1666 } else if (pmap == PCPU_GET(curpmap)) {
1667 if (pmap_pcid_enabled) {
1668 if (invpcid_works) {
1669 d.pcid = pmap->pm_pcids[0].pm_pcid;
1672 invpcid(&d, INVPCID_CTX);
1674 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[0].
1680 } else if (pmap_pcid_enabled) {
1681 pmap->pm_pcids[0].pm_gen = 0;
1686 pmap_invalidate_cache(void)
1693 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1696 pmap_update_pde_store(pmap, pde, newpde);
1697 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
1698 pmap_update_pde_invalidate(pmap, va, newpde);
1700 pmap->pm_pcids[0].pm_gen = 0;
1704 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1707 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1711 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1713 KASSERT((sva & PAGE_MASK) == 0,
1714 ("pmap_invalidate_cache_range: sva not page-aligned"));
1715 KASSERT((eva & PAGE_MASK) == 0,
1716 ("pmap_invalidate_cache_range: eva not page-aligned"));
1719 if ((cpu_feature & CPUID_SS) != 0 && !force)
1720 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1721 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1722 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1724 * XXX: Some CPUs fault, hang, or trash the local APIC
1725 * registers if we use CLFLUSH on the local APIC
1726 * range. The local APIC is always uncached, so we
1727 * don't need to flush for that range anyway.
1729 if (pmap_kextract(sva) == lapic_paddr)
1733 * Otherwise, do per-cache line flush. Use the mfence
1734 * instruction to insure that previous stores are
1735 * included in the write-back. The processor
1736 * propagates flush to other processors in the cache
1740 for (; sva < eva; sva += cpu_clflush_line_size)
1743 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1744 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1745 if (pmap_kextract(sva) == lapic_paddr)
1748 * Writes are ordered by CLFLUSH on Intel CPUs.
1750 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1752 for (; sva < eva; sva += cpu_clflush_line_size)
1754 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1759 * No targeted cache flush methods are supported by CPU,
1760 * or the supplied range is bigger than 2MB.
1761 * Globally invalidate cache.
1763 pmap_invalidate_cache();
1768 * Remove the specified set of pages from the data and instruction caches.
1770 * In contrast to pmap_invalidate_cache_range(), this function does not
1771 * rely on the CPU's self-snoop feature, because it is intended for use
1772 * when moving pages into a different cache domain.
1775 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1777 vm_offset_t daddr, eva;
1781 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
1782 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1783 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
1784 pmap_invalidate_cache();
1786 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
1788 for (i = 0; i < count; i++) {
1789 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1790 eva = daddr + PAGE_SIZE;
1791 for (; daddr < eva; daddr += cpu_clflush_line_size) {
1798 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
1804 * Routine: pmap_extract
1806 * Extract the physical page address associated
1807 * with the given map/virtual_address pair.
1810 pmap_extract(pmap_t pmap, vm_offset_t va)
1814 pt_entry_t *pte, PG_V;
1818 PG_V = pmap_valid_bit(pmap);
1820 pdpe = pmap_pdpe(pmap, va);
1821 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1822 if ((*pdpe & PG_PS) != 0)
1823 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1825 pde = pmap_pdpe_to_pde(pdpe, va);
1826 if ((*pde & PG_V) != 0) {
1827 if ((*pde & PG_PS) != 0) {
1828 pa = (*pde & PG_PS_FRAME) |
1831 pte = pmap_pde_to_pte(pde, va);
1832 pa = (*pte & PG_FRAME) |
1843 * Routine: pmap_extract_and_hold
1845 * Atomically extract and hold the physical page
1846 * with the given pmap and virtual address pair
1847 * if that mapping permits the given protection.
1850 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1852 pd_entry_t pde, *pdep;
1853 pt_entry_t pte, PG_RW, PG_V;
1859 PG_RW = pmap_rw_bit(pmap);
1860 PG_V = pmap_valid_bit(pmap);
1863 pdep = pmap_pde(pmap, va);
1864 if (pdep != NULL && (pde = *pdep)) {
1866 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1867 if (vm_page_pa_tryrelock(pmap, (pde &
1868 PG_PS_FRAME) | (va & PDRMASK), &pa))
1870 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1875 pte = *pmap_pde_to_pte(pdep, va);
1877 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1878 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1881 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1892 pmap_kextract(vm_offset_t va)
1897 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1898 pa = DMAP_TO_PHYS(va);
1902 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1905 * Beware of a concurrent promotion that changes the
1906 * PDE at this point! For example, vtopte() must not
1907 * be used to access the PTE because it would use the
1908 * new PDE. It is, however, safe to use the old PDE
1909 * because the page table page is preserved by the
1912 pa = *pmap_pde_to_pte(&pde, va);
1913 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1919 /***************************************************
1920 * Low level mapping routines.....
1921 ***************************************************/
1924 * Add a wired page to the kva.
1925 * Note: not SMP coherent.
1928 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1933 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1936 static __inline void
1937 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1943 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1944 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1948 * Remove a page from the kernel pagetables.
1949 * Note: not SMP coherent.
1952 pmap_kremove(vm_offset_t va)
1961 * Used to map a range of physical addresses into kernel
1962 * virtual address space.
1964 * The value passed in '*virt' is a suggested virtual address for
1965 * the mapping. Architectures which can support a direct-mapped
1966 * physical to virtual region can return the appropriate address
1967 * within that region, leaving '*virt' unchanged. Other
1968 * architectures should map the pages starting at '*virt' and
1969 * update '*virt' with the first usable address after the mapped
1973 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1975 return PHYS_TO_DMAP(start);
1980 * Add a list of wired pages to the kva
1981 * this routine is only used for temporary
1982 * kernel mappings that do not need to have
1983 * page modification or references recorded.
1984 * Note that old mappings are simply written
1985 * over. The page *must* be wired.
1986 * Note: SMP coherent. Uses a ranged shootdown IPI.
1989 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1991 pt_entry_t *endpte, oldpte, pa, *pte;
1997 endpte = pte + count;
1998 while (pte < endpte) {
2000 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2001 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2002 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2004 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
2008 if (__predict_false((oldpte & X86_PG_V) != 0))
2009 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2014 * This routine tears out page mappings from the
2015 * kernel -- it is meant only for temporary mappings.
2016 * Note: SMP coherent. Uses a ranged shootdown IPI.
2019 pmap_qremove(vm_offset_t sva, int count)
2024 while (count-- > 0) {
2025 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2029 pmap_invalidate_range(kernel_pmap, sva, va);
2032 /***************************************************
2033 * Page table page management routines.....
2034 ***************************************************/
2035 static __inline void
2036 pmap_free_zero_pages(struct spglist *free)
2040 while ((m = SLIST_FIRST(free)) != NULL) {
2041 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2042 /* Preserve the page's PG_ZERO setting. */
2043 vm_page_free_toq(m);
2048 * Schedule the specified unused page table page to be freed. Specifically,
2049 * add the page to the specified list of pages that will be released to the
2050 * physical memory manager after the TLB has been updated.
2052 static __inline void
2053 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2054 boolean_t set_PG_ZERO)
2058 m->flags |= PG_ZERO;
2060 m->flags &= ~PG_ZERO;
2061 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2065 * Inserts the specified page table page into the specified pmap's collection
2066 * of idle page table pages. Each of a pmap's page table pages is responsible
2067 * for mapping a distinct range of virtual addresses. The pmap's collection is
2068 * ordered by this virtual address range.
2071 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2074 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2075 return (vm_radix_insert(&pmap->pm_root, mpte));
2079 * Looks for a page table page mapping the specified virtual address in the
2080 * specified pmap's collection of idle page table pages. Returns NULL if there
2081 * is no page table page corresponding to the specified virtual address.
2083 static __inline vm_page_t
2084 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2087 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2088 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2092 * Removes the specified page table page from the specified pmap's collection
2093 * of idle page table pages. The specified page table page must be a member of
2094 * the pmap's collection.
2096 static __inline void
2097 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2100 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2101 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2105 * Decrements a page table page's wire count, which is used to record the
2106 * number of valid page table entries within the page. If the wire count
2107 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2108 * page table page was unmapped and FALSE otherwise.
2110 static inline boolean_t
2111 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2115 if (m->wire_count == 0) {
2116 _pmap_unwire_ptp(pmap, va, m, free);
2123 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2126 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2128 * unmap the page table page
2130 if (m->pindex >= (NUPDE + NUPDPE)) {
2133 pml4 = pmap_pml4e(pmap, va);
2135 } else if (m->pindex >= NUPDE) {
2138 pdp = pmap_pdpe(pmap, va);
2143 pd = pmap_pde(pmap, va);
2146 pmap_resident_count_dec(pmap, 1);
2147 if (m->pindex < NUPDE) {
2148 /* We just released a PT, unhold the matching PD */
2151 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2152 pmap_unwire_ptp(pmap, va, pdpg, free);
2154 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2155 /* We just released a PD, unhold the matching PDP */
2158 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2159 pmap_unwire_ptp(pmap, va, pdppg, free);
2163 * This is a release store so that the ordinary store unmapping
2164 * the page table page is globally performed before TLB shoot-
2167 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
2170 * Put page on a list so that it is released after
2171 * *ALL* TLB shootdown is done
2173 pmap_add_delayed_free_list(m, free, TRUE);
2177 * After removing a page table entry, this routine is used to
2178 * conditionally free the page, and manage the hold/wire counts.
2181 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2182 struct spglist *free)
2186 if (va >= VM_MAXUSER_ADDRESS)
2188 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2189 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2190 return (pmap_unwire_ptp(pmap, va, mpte, free));
2194 pmap_pinit0(pmap_t pmap)
2198 PMAP_LOCK_INIT(pmap);
2199 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2200 pmap->pm_cr3 = KPML4phys;
2201 pmap->pm_root.rt_root = 0;
2202 CPU_ZERO(&pmap->pm_active);
2203 TAILQ_INIT(&pmap->pm_pvchunk);
2204 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2205 pmap->pm_flags = pmap_flags;
2207 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2208 pmap->pm_pcids[i].pm_gen = 0;
2210 PCPU_SET(curpmap, kernel_pmap);
2211 pmap_activate(curthread);
2212 CPU_FILL(&kernel_pmap->pm_active);
2216 * Initialize a preallocated and zeroed pmap structure,
2217 * such as one in a vmspace structure.
2220 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2223 vm_paddr_t pml4phys;
2227 * allocate the page directory page
2229 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2230 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2233 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2234 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2236 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
2237 pmap->pm_pcids[i].pm_gen = 0;
2239 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2241 if ((pml4pg->flags & PG_ZERO) == 0)
2242 pagezero(pmap->pm_pml4);
2245 * Do not install the host kernel mappings in the nested page
2246 * tables. These mappings are meaningless in the guest physical
2249 if ((pmap->pm_type = pm_type) == PT_X86) {
2250 pmap->pm_cr3 = pml4phys;
2252 /* Wire in kernel global address entries. */
2253 for (i = 0; i < NKPML4E; i++) {
2254 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2255 X86_PG_RW | X86_PG_V | PG_U;
2257 for (i = 0; i < ndmpdpphys; i++) {
2258 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2259 X86_PG_RW | X86_PG_V | PG_U;
2262 /* install self-referential address mapping entry(s) */
2263 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2264 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2267 pmap->pm_root.rt_root = 0;
2268 CPU_ZERO(&pmap->pm_active);
2269 TAILQ_INIT(&pmap->pm_pvchunk);
2270 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2271 pmap->pm_flags = flags;
2272 pmap->pm_eptgen = 0;
2278 pmap_pinit(pmap_t pmap)
2281 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2285 * This routine is called if the desired page table page does not exist.
2287 * If page table page allocation fails, this routine may sleep before
2288 * returning NULL. It sleeps only if a lock pointer was given.
2290 * Note: If a page allocation fails at page table level two or three,
2291 * one or two pages may be held during the wait, only to be released
2292 * afterwards. This conservative approach is easily argued to avoid
2296 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2298 vm_page_t m, pdppg, pdpg;
2299 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2301 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2303 PG_A = pmap_accessed_bit(pmap);
2304 PG_M = pmap_modified_bit(pmap);
2305 PG_V = pmap_valid_bit(pmap);
2306 PG_RW = pmap_rw_bit(pmap);
2309 * Allocate a page table page.
2311 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2312 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2313 if (lockp != NULL) {
2314 RELEASE_PV_LIST_LOCK(lockp);
2316 rw_runlock(&pvh_global_lock);
2318 rw_rlock(&pvh_global_lock);
2323 * Indicate the need to retry. While waiting, the page table
2324 * page may have been allocated.
2328 if ((m->flags & PG_ZERO) == 0)
2332 * Map the pagetable page into the process address space, if
2333 * it isn't already there.
2336 if (ptepindex >= (NUPDE + NUPDPE)) {
2338 vm_pindex_t pml4index;
2340 /* Wire up a new PDPE page */
2341 pml4index = ptepindex - (NUPDE + NUPDPE);
2342 pml4 = &pmap->pm_pml4[pml4index];
2343 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2345 } else if (ptepindex >= NUPDE) {
2346 vm_pindex_t pml4index;
2347 vm_pindex_t pdpindex;
2351 /* Wire up a new PDE page */
2352 pdpindex = ptepindex - NUPDE;
2353 pml4index = pdpindex >> NPML4EPGSHIFT;
2355 pml4 = &pmap->pm_pml4[pml4index];
2356 if ((*pml4 & PG_V) == 0) {
2357 /* Have to allocate a new pdp, recurse */
2358 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2361 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2362 vm_page_free_zero(m);
2366 /* Add reference to pdp page */
2367 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2368 pdppg->wire_count++;
2370 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2372 /* Now find the pdp page */
2373 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2374 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2377 vm_pindex_t pml4index;
2378 vm_pindex_t pdpindex;
2383 /* Wire up a new PTE page */
2384 pdpindex = ptepindex >> NPDPEPGSHIFT;
2385 pml4index = pdpindex >> NPML4EPGSHIFT;
2387 /* First, find the pdp and check that its valid. */
2388 pml4 = &pmap->pm_pml4[pml4index];
2389 if ((*pml4 & PG_V) == 0) {
2390 /* Have to allocate a new pd, recurse */
2391 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2394 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2395 vm_page_free_zero(m);
2398 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2399 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2401 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2402 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2403 if ((*pdp & PG_V) == 0) {
2404 /* Have to allocate a new pd, recurse */
2405 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2408 atomic_subtract_int(&vm_cnt.v_wire_count,
2410 vm_page_free_zero(m);
2414 /* Add reference to the pd page */
2415 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2419 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2421 /* Now we know where the page directory page is */
2422 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2423 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2426 pmap_resident_count_inc(pmap, 1);
2432 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2434 vm_pindex_t pdpindex, ptepindex;
2435 pdp_entry_t *pdpe, PG_V;
2438 PG_V = pmap_valid_bit(pmap);
2441 pdpe = pmap_pdpe(pmap, va);
2442 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2443 /* Add a reference to the pd page. */
2444 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2447 /* Allocate a pd page. */
2448 ptepindex = pmap_pde_pindex(va);
2449 pdpindex = ptepindex >> NPDPEPGSHIFT;
2450 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2451 if (pdpg == NULL && lockp != NULL)
2458 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2460 vm_pindex_t ptepindex;
2461 pd_entry_t *pd, PG_V;
2464 PG_V = pmap_valid_bit(pmap);
2467 * Calculate pagetable page index
2469 ptepindex = pmap_pde_pindex(va);
2472 * Get the page directory entry
2474 pd = pmap_pde(pmap, va);
2477 * This supports switching from a 2MB page to a
2480 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2481 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2483 * Invalidation of the 2MB page mapping may have caused
2484 * the deallocation of the underlying PD page.
2491 * If the page table page is mapped, we just increment the
2492 * hold count, and activate it.
2494 if (pd != NULL && (*pd & PG_V) != 0) {
2495 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2499 * Here if the pte page isn't mapped, or if it has been
2502 m = _pmap_allocpte(pmap, ptepindex, lockp);
2503 if (m == NULL && lockp != NULL)
2510 /***************************************************
2511 * Pmap allocation/deallocation routines.
2512 ***************************************************/
2515 * Release any resources held by the given physical map.
2516 * Called when a pmap initialized by pmap_pinit is being released.
2517 * Should only be called if the map contains no valid mappings.
2520 pmap_release(pmap_t pmap)
2525 KASSERT(pmap->pm_stats.resident_count == 0,
2526 ("pmap_release: pmap resident count %ld != 0",
2527 pmap->pm_stats.resident_count));
2528 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2529 ("pmap_release: pmap has reserved page table page(s)"));
2530 KASSERT(CPU_EMPTY(&pmap->pm_active),
2531 ("releasing active pmap %p", pmap));
2533 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2535 for (i = 0; i < NKPML4E; i++) /* KVA */
2536 pmap->pm_pml4[KPML4BASE + i] = 0;
2537 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2538 pmap->pm_pml4[DMPML4I + i] = 0;
2539 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2542 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2543 vm_page_free_zero(m);
2547 kvm_size(SYSCTL_HANDLER_ARGS)
2549 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2551 return sysctl_handle_long(oidp, &ksize, 0, req);
2553 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2554 0, 0, kvm_size, "LU", "Size of KVM");
2557 kvm_free(SYSCTL_HANDLER_ARGS)
2559 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2561 return sysctl_handle_long(oidp, &kfree, 0, req);
2563 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2564 0, 0, kvm_free, "LU", "Amount of KVM free");
2567 * grow the number of kernel page table entries, if needed
2570 pmap_growkernel(vm_offset_t addr)
2574 pd_entry_t *pde, newpdir;
2577 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2580 * Return if "addr" is within the range of kernel page table pages
2581 * that were preallocated during pmap bootstrap. Moreover, leave
2582 * "kernel_vm_end" and the kernel page table as they were.
2584 * The correctness of this action is based on the following
2585 * argument: vm_map_insert() allocates contiguous ranges of the
2586 * kernel virtual address space. It calls this function if a range
2587 * ends after "kernel_vm_end". If the kernel is mapped between
2588 * "kernel_vm_end" and "addr", then the range cannot begin at
2589 * "kernel_vm_end". In fact, its beginning address cannot be less
2590 * than the kernel. Thus, there is no immediate need to allocate
2591 * any new kernel page table pages between "kernel_vm_end" and
2594 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2597 addr = roundup2(addr, NBPDR);
2598 if (addr - 1 >= kernel_map->max_offset)
2599 addr = kernel_map->max_offset;
2600 while (kernel_vm_end < addr) {
2601 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2602 if ((*pdpe & X86_PG_V) == 0) {
2603 /* We need a new PDP entry */
2604 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2605 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2606 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2608 panic("pmap_growkernel: no memory to grow kernel");
2609 if ((nkpg->flags & PG_ZERO) == 0)
2610 pmap_zero_page(nkpg);
2611 paddr = VM_PAGE_TO_PHYS(nkpg);
2612 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2613 X86_PG_A | X86_PG_M);
2614 continue; /* try again */
2616 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2617 if ((*pde & X86_PG_V) != 0) {
2618 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2619 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2620 kernel_vm_end = kernel_map->max_offset;
2626 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2627 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2630 panic("pmap_growkernel: no memory to grow kernel");
2631 if ((nkpg->flags & PG_ZERO) == 0)
2632 pmap_zero_page(nkpg);
2633 paddr = VM_PAGE_TO_PHYS(nkpg);
2634 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2635 pde_store(pde, newpdir);
2637 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2638 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2639 kernel_vm_end = kernel_map->max_offset;
2646 /***************************************************
2647 * page management routines.
2648 ***************************************************/
2650 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2651 CTASSERT(_NPCM == 3);
2652 CTASSERT(_NPCPV == 168);
2654 static __inline struct pv_chunk *
2655 pv_to_chunk(pv_entry_t pv)
2658 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2661 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2663 #define PC_FREE0 0xfffffffffffffffful
2664 #define PC_FREE1 0xfffffffffffffffful
2665 #define PC_FREE2 0x000000fffffffffful
2667 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2670 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2672 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2673 "Current number of pv entry chunks");
2674 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2675 "Current number of pv entry chunks allocated");
2676 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2677 "Current number of pv entry chunks frees");
2678 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2679 "Number of times tried to get a chunk page but failed.");
2681 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2682 static int pv_entry_spare;
2684 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2685 "Current number of pv entry frees");
2686 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2687 "Current number of pv entry allocs");
2688 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2689 "Current number of pv entries");
2690 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2691 "Current number of spare pv entries");
2695 * We are in a serious low memory condition. Resort to
2696 * drastic measures to free some pages so we can allocate
2697 * another pv entry chunk.
2699 * Returns NULL if PV entries were reclaimed from the specified pmap.
2701 * We do not, however, unmap 2mpages because subsequent accesses will
2702 * allocate per-page pv entries until repromotion occurs, thereby
2703 * exacerbating the shortage of free pv entries.
2706 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2708 struct pch new_tail;
2709 struct pv_chunk *pc;
2710 struct md_page *pvh;
2713 pt_entry_t *pte, tpte;
2714 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2718 struct spglist free;
2720 int bit, field, freed;
2722 rw_assert(&pvh_global_lock, RA_LOCKED);
2723 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2724 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2727 PG_G = PG_A = PG_M = PG_RW = 0;
2729 TAILQ_INIT(&new_tail);
2730 mtx_lock(&pv_chunks_mutex);
2731 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2732 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2733 mtx_unlock(&pv_chunks_mutex);
2734 if (pmap != pc->pc_pmap) {
2736 pmap_invalidate_all(pmap);
2737 if (pmap != locked_pmap)
2741 /* Avoid deadlock and lock recursion. */
2742 if (pmap > locked_pmap) {
2743 RELEASE_PV_LIST_LOCK(lockp);
2745 } else if (pmap != locked_pmap &&
2746 !PMAP_TRYLOCK(pmap)) {
2748 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2749 mtx_lock(&pv_chunks_mutex);
2752 PG_G = pmap_global_bit(pmap);
2753 PG_A = pmap_accessed_bit(pmap);
2754 PG_M = pmap_modified_bit(pmap);
2755 PG_RW = pmap_rw_bit(pmap);
2759 * Destroy every non-wired, 4 KB page mapping in the chunk.
2762 for (field = 0; field < _NPCM; field++) {
2763 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2764 inuse != 0; inuse &= ~(1UL << bit)) {
2766 pv = &pc->pc_pventry[field * 64 + bit];
2768 pde = pmap_pde(pmap, va);
2769 if ((*pde & PG_PS) != 0)
2771 pte = pmap_pde_to_pte(pde, va);
2772 if ((*pte & PG_W) != 0)
2774 tpte = pte_load_clear(pte);
2775 if ((tpte & PG_G) != 0)
2776 pmap_invalidate_page(pmap, va);
2777 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2778 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2780 if ((tpte & PG_A) != 0)
2781 vm_page_aflag_set(m, PGA_REFERENCED);
2782 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2783 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2785 if (TAILQ_EMPTY(&m->md.pv_list) &&
2786 (m->flags & PG_FICTITIOUS) == 0) {
2787 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2788 if (TAILQ_EMPTY(&pvh->pv_list)) {
2789 vm_page_aflag_clear(m,
2793 pc->pc_map[field] |= 1UL << bit;
2794 pmap_unuse_pt(pmap, va, *pde, &free);
2799 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2800 mtx_lock(&pv_chunks_mutex);
2803 /* Every freed mapping is for a 4 KB page. */
2804 pmap_resident_count_dec(pmap, freed);
2805 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2806 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2807 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2808 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2809 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2810 pc->pc_map[2] == PC_FREE2) {
2811 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2812 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2813 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2814 /* Entire chunk is free; return it. */
2815 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2816 dump_drop_page(m_pc->phys_addr);
2817 mtx_lock(&pv_chunks_mutex);
2820 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2821 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2822 mtx_lock(&pv_chunks_mutex);
2823 /* One freed pv entry in locked_pmap is sufficient. */
2824 if (pmap == locked_pmap)
2827 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2828 mtx_unlock(&pv_chunks_mutex);
2830 pmap_invalidate_all(pmap);
2831 if (pmap != locked_pmap)
2834 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2835 m_pc = SLIST_FIRST(&free);
2836 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2837 /* Recycle a freed page table page. */
2838 m_pc->wire_count = 1;
2839 atomic_add_int(&vm_cnt.v_wire_count, 1);
2841 pmap_free_zero_pages(&free);
2846 * free the pv_entry back to the free list
2849 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2851 struct pv_chunk *pc;
2852 int idx, field, bit;
2854 rw_assert(&pvh_global_lock, RA_LOCKED);
2855 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2856 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2857 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2858 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2859 pc = pv_to_chunk(pv);
2860 idx = pv - &pc->pc_pventry[0];
2863 pc->pc_map[field] |= 1ul << bit;
2864 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2865 pc->pc_map[2] != PC_FREE2) {
2866 /* 98% of the time, pc is already at the head of the list. */
2867 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2868 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2869 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2873 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2878 free_pv_chunk(struct pv_chunk *pc)
2882 mtx_lock(&pv_chunks_mutex);
2883 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2884 mtx_unlock(&pv_chunks_mutex);
2885 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2886 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2887 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2888 /* entire chunk is free, return it */
2889 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2890 dump_drop_page(m->phys_addr);
2891 vm_page_unwire(m, PQ_NONE);
2896 * Returns a new PV entry, allocating a new PV chunk from the system when
2897 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2898 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2901 * The given PV list lock may be released.
2904 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2908 struct pv_chunk *pc;
2911 rw_assert(&pvh_global_lock, RA_LOCKED);
2912 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2913 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2915 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2917 for (field = 0; field < _NPCM; field++) {
2918 if (pc->pc_map[field]) {
2919 bit = bsfq(pc->pc_map[field]);
2923 if (field < _NPCM) {
2924 pv = &pc->pc_pventry[field * 64 + bit];
2925 pc->pc_map[field] &= ~(1ul << bit);
2926 /* If this was the last item, move it to tail */
2927 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2928 pc->pc_map[2] == 0) {
2929 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2930 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2933 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2934 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2938 /* No free items, allocate another chunk */
2939 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2942 if (lockp == NULL) {
2943 PV_STAT(pc_chunk_tryfail++);
2946 m = reclaim_pv_chunk(pmap, lockp);
2950 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2951 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2952 dump_add_page(m->phys_addr);
2953 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2955 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2956 pc->pc_map[1] = PC_FREE1;
2957 pc->pc_map[2] = PC_FREE2;
2958 mtx_lock(&pv_chunks_mutex);
2959 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2960 mtx_unlock(&pv_chunks_mutex);
2961 pv = &pc->pc_pventry[0];
2962 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2963 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2964 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2969 * Returns the number of one bits within the given PV chunk map element.
2971 * The erratas for Intel processors state that "POPCNT Instruction May
2972 * Take Longer to Execute Than Expected". It is believed that the
2973 * issue is the spurious dependency on the destination register.
2974 * Provide a hint to the register rename logic that the destination
2975 * value is overwritten, by clearing it, as suggested in the
2976 * optimization manual. It should be cheap for unaffected processors
2979 * Reference numbers for erratas are
2980 * 4th Gen Core: HSD146
2981 * 5th Gen Core: BDM85
2984 popcnt_pc_map_elem_pq(uint64_t elem)
2988 __asm __volatile("xorl %k0,%k0;popcntq %1,%0"
2989 : "=&r" (result) : "rm" (elem));
2994 * Ensure that the number of spare PV entries in the specified pmap meets or
2995 * exceeds the given count, "needed".
2997 * The given PV list lock may be released.
3000 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3002 struct pch new_tail;
3003 struct pv_chunk *pc;
3007 rw_assert(&pvh_global_lock, RA_LOCKED);
3008 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3009 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3012 * Newly allocated PV chunks must be stored in a private list until
3013 * the required number of PV chunks have been allocated. Otherwise,
3014 * reclaim_pv_chunk() could recycle one of these chunks. In
3015 * contrast, these chunks must be added to the pmap upon allocation.
3017 TAILQ_INIT(&new_tail);
3020 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3021 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
3022 free = bitcount64(pc->pc_map[0]);
3023 free += bitcount64(pc->pc_map[1]);
3024 free += bitcount64(pc->pc_map[2]);
3026 free = popcnt_pc_map_elem_pq(pc->pc_map[0]);
3027 free += popcnt_pc_map_elem_pq(pc->pc_map[1]);
3028 free += popcnt_pc_map_elem_pq(pc->pc_map[2]);
3033 if (avail >= needed)
3036 for (; avail < needed; avail += _NPCPV) {
3037 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3040 m = reclaim_pv_chunk(pmap, lockp);
3044 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3045 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3046 dump_add_page(m->phys_addr);
3047 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3049 pc->pc_map[0] = PC_FREE0;
3050 pc->pc_map[1] = PC_FREE1;
3051 pc->pc_map[2] = PC_FREE2;
3052 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3053 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3054 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3056 if (!TAILQ_EMPTY(&new_tail)) {
3057 mtx_lock(&pv_chunks_mutex);
3058 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3059 mtx_unlock(&pv_chunks_mutex);
3064 * First find and then remove the pv entry for the specified pmap and virtual
3065 * address from the specified pv list. Returns the pv entry if found and NULL
3066 * otherwise. This operation can be performed on pv lists for either 4KB or
3067 * 2MB page mappings.
3069 static __inline pv_entry_t
3070 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3074 rw_assert(&pvh_global_lock, RA_LOCKED);
3075 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3076 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3077 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3086 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3087 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3088 * entries for each of the 4KB page mappings.
3091 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3092 struct rwlock **lockp)
3094 struct md_page *pvh;
3095 struct pv_chunk *pc;
3097 vm_offset_t va_last;
3101 rw_assert(&pvh_global_lock, RA_LOCKED);
3102 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3103 KASSERT((pa & PDRMASK) == 0,
3104 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3105 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3108 * Transfer the 2mpage's pv entry for this mapping to the first
3109 * page's pv list. Once this transfer begins, the pv list lock
3110 * must not be released until the last pv entry is reinstantiated.
3112 pvh = pa_to_pvh(pa);
3113 va = trunc_2mpage(va);
3114 pv = pmap_pvh_remove(pvh, pmap, va);
3115 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3116 m = PHYS_TO_VM_PAGE(pa);
3117 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3119 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3120 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3121 va_last = va + NBPDR - PAGE_SIZE;
3123 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3124 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3125 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3126 for (field = 0; field < _NPCM; field++) {
3127 while (pc->pc_map[field]) {
3128 bit = bsfq(pc->pc_map[field]);
3129 pc->pc_map[field] &= ~(1ul << bit);
3130 pv = &pc->pc_pventry[field * 64 + bit];
3134 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3135 ("pmap_pv_demote_pde: page %p is not managed", m));
3136 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3142 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3143 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3146 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3147 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3148 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3150 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3151 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3155 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3156 * replace the many pv entries for the 4KB page mappings by a single pv entry
3157 * for the 2MB page mapping.
3160 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3161 struct rwlock **lockp)
3163 struct md_page *pvh;
3165 vm_offset_t va_last;
3168 rw_assert(&pvh_global_lock, RA_LOCKED);
3169 KASSERT((pa & PDRMASK) == 0,
3170 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3171 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3174 * Transfer the first page's pv entry for this mapping to the 2mpage's
3175 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3176 * a transfer avoids the possibility that get_pv_entry() calls
3177 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3178 * mappings that is being promoted.
3180 m = PHYS_TO_VM_PAGE(pa);
3181 va = trunc_2mpage(va);
3182 pv = pmap_pvh_remove(&m->md, pmap, va);
3183 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3184 pvh = pa_to_pvh(pa);
3185 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3187 /* Free the remaining NPTEPG - 1 pv entries. */
3188 va_last = va + NBPDR - PAGE_SIZE;
3192 pmap_pvh_free(&m->md, pmap, va);
3193 } while (va < va_last);
3197 * First find and then destroy the pv entry for the specified pmap and virtual
3198 * address. This operation can be performed on pv lists for either 4KB or 2MB
3202 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3206 pv = pmap_pvh_remove(pvh, pmap, va);
3207 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3208 free_pv_entry(pmap, pv);
3212 * Conditionally create the PV entry for a 4KB page mapping if the required
3213 * memory can be allocated without resorting to reclamation.
3216 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3217 struct rwlock **lockp)
3221 rw_assert(&pvh_global_lock, RA_LOCKED);
3222 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3223 /* Pass NULL instead of the lock pointer to disable reclamation. */
3224 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3226 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3227 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3235 * Conditionally create the PV entry for a 2MB page mapping if the required
3236 * memory can be allocated without resorting to reclamation.
3239 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3240 struct rwlock **lockp)
3242 struct md_page *pvh;
3245 rw_assert(&pvh_global_lock, RA_LOCKED);
3246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3247 /* Pass NULL instead of the lock pointer to disable reclamation. */
3248 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3250 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3251 pvh = pa_to_pvh(pa);
3252 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3260 * Fills a page table page with mappings to consecutive physical pages.
3263 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3267 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3269 newpte += PAGE_SIZE;
3274 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3275 * mapping is invalidated.
3278 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3280 struct rwlock *lock;
3284 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3291 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3292 struct rwlock **lockp)
3294 pd_entry_t newpde, oldpde;
3295 pt_entry_t *firstpte, newpte;
3296 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3299 struct spglist free;
3302 PG_G = pmap_global_bit(pmap);
3303 PG_A = pmap_accessed_bit(pmap);
3304 PG_M = pmap_modified_bit(pmap);
3305 PG_RW = pmap_rw_bit(pmap);
3306 PG_V = pmap_valid_bit(pmap);
3307 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3309 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3311 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3312 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3313 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3315 pmap_remove_pt_page(pmap, mpte);
3317 KASSERT((oldpde & PG_W) == 0,
3318 ("pmap_demote_pde: page table page for a wired mapping"
3322 * Invalidate the 2MB page mapping and return "failure" if the
3323 * mapping was never accessed or the allocation of the new
3324 * page table page fails. If the 2MB page mapping belongs to
3325 * the direct map region of the kernel's address space, then
3326 * the page allocation request specifies the highest possible
3327 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3328 * normal. Page table pages are preallocated for every other
3329 * part of the kernel address space, so the direct map region
3330 * is the only part of the kernel address space that must be
3333 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3334 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3335 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3336 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3338 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3340 pmap_invalidate_page(pmap, trunc_2mpage(va));
3341 pmap_free_zero_pages(&free);
3342 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3343 " in pmap %p", va, pmap);
3346 if (va < VM_MAXUSER_ADDRESS)
3347 pmap_resident_count_inc(pmap, 1);
3349 mptepa = VM_PAGE_TO_PHYS(mpte);
3350 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3351 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3352 KASSERT((oldpde & PG_A) != 0,
3353 ("pmap_demote_pde: oldpde is missing PG_A"));
3354 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3355 ("pmap_demote_pde: oldpde is missing PG_M"));
3356 newpte = oldpde & ~PG_PS;
3357 newpte = pmap_swap_pat(pmap, newpte);
3360 * If the page table page is new, initialize it.
3362 if (mpte->wire_count == 1) {
3363 mpte->wire_count = NPTEPG;
3364 pmap_fill_ptp(firstpte, newpte);
3366 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3367 ("pmap_demote_pde: firstpte and newpte map different physical"
3371 * If the mapping has changed attributes, update the page table
3374 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3375 pmap_fill_ptp(firstpte, newpte);
3378 * The spare PV entries must be reserved prior to demoting the
3379 * mapping, that is, prior to changing the PDE. Otherwise, the state
3380 * of the PDE and the PV lists will be inconsistent, which can result
3381 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3382 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3383 * PV entry for the 2MB page mapping that is being demoted.
3385 if ((oldpde & PG_MANAGED) != 0)
3386 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3389 * Demote the mapping. This pmap is locked. The old PDE has
3390 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3391 * set. Thus, there is no danger of a race with another
3392 * processor changing the setting of PG_A and/or PG_M between
3393 * the read above and the store below.
3395 if (workaround_erratum383)
3396 pmap_update_pde(pmap, va, pde, newpde);
3398 pde_store(pde, newpde);
3401 * Invalidate a stale recursive mapping of the page table page.
3403 if (va >= VM_MAXUSER_ADDRESS)
3404 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3407 * Demote the PV entry.
3409 if ((oldpde & PG_MANAGED) != 0)
3410 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3412 atomic_add_long(&pmap_pde_demotions, 1);
3413 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3414 " in pmap %p", va, pmap);
3419 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3422 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3428 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3429 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3430 mpte = pmap_lookup_pt_page(pmap, va);
3432 panic("pmap_remove_kernel_pde: Missing pt page.");
3434 pmap_remove_pt_page(pmap, mpte);
3435 mptepa = VM_PAGE_TO_PHYS(mpte);
3436 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3439 * Initialize the page table page.
3441 pagezero((void *)PHYS_TO_DMAP(mptepa));
3444 * Demote the mapping.
3446 if (workaround_erratum383)
3447 pmap_update_pde(pmap, va, pde, newpde);
3449 pde_store(pde, newpde);
3452 * Invalidate a stale recursive mapping of the page table page.
3454 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3458 * pmap_remove_pde: do the things to unmap a superpage in a process
3461 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3462 struct spglist *free, struct rwlock **lockp)
3464 struct md_page *pvh;
3466 vm_offset_t eva, va;
3468 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3470 PG_G = pmap_global_bit(pmap);
3471 PG_A = pmap_accessed_bit(pmap);
3472 PG_M = pmap_modified_bit(pmap);
3473 PG_RW = pmap_rw_bit(pmap);
3475 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3476 KASSERT((sva & PDRMASK) == 0,
3477 ("pmap_remove_pde: sva is not 2mpage aligned"));
3478 oldpde = pte_load_clear(pdq);
3480 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3483 * Machines that don't support invlpg, also don't support
3487 pmap_invalidate_page(kernel_pmap, sva);
3488 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3489 if (oldpde & PG_MANAGED) {
3490 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3491 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3492 pmap_pvh_free(pvh, pmap, sva);
3494 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3495 va < eva; va += PAGE_SIZE, m++) {
3496 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3499 vm_page_aflag_set(m, PGA_REFERENCED);
3500 if (TAILQ_EMPTY(&m->md.pv_list) &&
3501 TAILQ_EMPTY(&pvh->pv_list))
3502 vm_page_aflag_clear(m, PGA_WRITEABLE);
3505 if (pmap == kernel_pmap) {
3506 pmap_remove_kernel_pde(pmap, pdq, sva);
3508 mpte = pmap_lookup_pt_page(pmap, sva);
3510 pmap_remove_pt_page(pmap, mpte);
3511 pmap_resident_count_dec(pmap, 1);
3512 KASSERT(mpte->wire_count == NPTEPG,
3513 ("pmap_remove_pde: pte page wire count error"));
3514 mpte->wire_count = 0;
3515 pmap_add_delayed_free_list(mpte, free, FALSE);
3516 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
3519 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3523 * pmap_remove_pte: do the things to unmap a page in a process
3526 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3527 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3529 struct md_page *pvh;
3530 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3533 PG_A = pmap_accessed_bit(pmap);
3534 PG_M = pmap_modified_bit(pmap);
3535 PG_RW = pmap_rw_bit(pmap);
3537 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3538 oldpte = pte_load_clear(ptq);
3540 pmap->pm_stats.wired_count -= 1;
3541 pmap_resident_count_dec(pmap, 1);
3542 if (oldpte & PG_MANAGED) {
3543 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3544 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3547 vm_page_aflag_set(m, PGA_REFERENCED);
3548 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3549 pmap_pvh_free(&m->md, pmap, va);
3550 if (TAILQ_EMPTY(&m->md.pv_list) &&
3551 (m->flags & PG_FICTITIOUS) == 0) {
3552 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3553 if (TAILQ_EMPTY(&pvh->pv_list))
3554 vm_page_aflag_clear(m, PGA_WRITEABLE);
3557 return (pmap_unuse_pt(pmap, va, ptepde, free));
3561 * Remove a single page from a process address space
3564 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3565 struct spglist *free)
3567 struct rwlock *lock;
3568 pt_entry_t *pte, PG_V;
3570 PG_V = pmap_valid_bit(pmap);
3571 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3572 if ((*pde & PG_V) == 0)
3574 pte = pmap_pde_to_pte(pde, va);
3575 if ((*pte & PG_V) == 0)
3578 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3581 pmap_invalidate_page(pmap, va);
3585 * Remove the given range of addresses from the specified map.
3587 * It is assumed that the start and end are properly
3588 * rounded to the page size.
3591 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3593 struct rwlock *lock;
3594 vm_offset_t va, va_next;
3595 pml4_entry_t *pml4e;
3597 pd_entry_t ptpaddr, *pde;
3598 pt_entry_t *pte, PG_G, PG_V;
3599 struct spglist free;
3602 PG_G = pmap_global_bit(pmap);
3603 PG_V = pmap_valid_bit(pmap);
3606 * Perform an unsynchronized read. This is, however, safe.
3608 if (pmap->pm_stats.resident_count == 0)
3614 rw_rlock(&pvh_global_lock);
3618 * special handling of removing one page. a very
3619 * common operation and easy to short circuit some
3622 if (sva + PAGE_SIZE == eva) {
3623 pde = pmap_pde(pmap, sva);
3624 if (pde && (*pde & PG_PS) == 0) {
3625 pmap_remove_page(pmap, sva, pde, &free);
3631 for (; sva < eva; sva = va_next) {
3633 if (pmap->pm_stats.resident_count == 0)
3636 pml4e = pmap_pml4e(pmap, sva);
3637 if ((*pml4e & PG_V) == 0) {
3638 va_next = (sva + NBPML4) & ~PML4MASK;
3644 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3645 if ((*pdpe & PG_V) == 0) {
3646 va_next = (sva + NBPDP) & ~PDPMASK;
3653 * Calculate index for next page table.
3655 va_next = (sva + NBPDR) & ~PDRMASK;
3659 pde = pmap_pdpe_to_pde(pdpe, sva);
3663 * Weed out invalid mappings.
3669 * Check for large page.
3671 if ((ptpaddr & PG_PS) != 0) {
3673 * Are we removing the entire large page? If not,
3674 * demote the mapping and fall through.
3676 if (sva + NBPDR == va_next && eva >= va_next) {
3678 * The TLB entry for a PG_G mapping is
3679 * invalidated by pmap_remove_pde().
3681 if ((ptpaddr & PG_G) == 0)
3683 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3685 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3687 /* The large page mapping was destroyed. */
3694 * Limit our scan to either the end of the va represented
3695 * by the current page table page, or to the end of the
3696 * range being removed.
3702 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3705 if (va != va_next) {
3706 pmap_invalidate_range(pmap, va, sva);
3711 if ((*pte & PG_G) == 0)
3713 else if (va == va_next)
3715 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3722 pmap_invalidate_range(pmap, va, sva);
3728 pmap_invalidate_all(pmap);
3729 rw_runlock(&pvh_global_lock);
3731 pmap_free_zero_pages(&free);
3735 * Routine: pmap_remove_all
3737 * Removes this physical page from
3738 * all physical maps in which it resides.
3739 * Reflects back modify bits to the pager.
3742 * Original versions of this routine were very
3743 * inefficient because they iteratively called
3744 * pmap_remove (slow...)
3748 pmap_remove_all(vm_page_t m)
3750 struct md_page *pvh;
3753 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3756 struct spglist free;
3758 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3759 ("pmap_remove_all: page %p is not managed", m));
3761 rw_wlock(&pvh_global_lock);
3762 if ((m->flags & PG_FICTITIOUS) != 0)
3763 goto small_mappings;
3764 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3765 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3769 pde = pmap_pde(pmap, va);
3770 (void)pmap_demote_pde(pmap, pde, va);
3774 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3777 PG_A = pmap_accessed_bit(pmap);
3778 PG_M = pmap_modified_bit(pmap);
3779 PG_RW = pmap_rw_bit(pmap);
3780 pmap_resident_count_dec(pmap, 1);
3781 pde = pmap_pde(pmap, pv->pv_va);
3782 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3783 " a 2mpage in page %p's pv list", m));
3784 pte = pmap_pde_to_pte(pde, pv->pv_va);
3785 tpte = pte_load_clear(pte);
3787 pmap->pm_stats.wired_count--;
3789 vm_page_aflag_set(m, PGA_REFERENCED);
3792 * Update the vm_page_t clean and reference bits.
3794 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3796 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3797 pmap_invalidate_page(pmap, pv->pv_va);
3798 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3800 free_pv_entry(pmap, pv);
3803 vm_page_aflag_clear(m, PGA_WRITEABLE);
3804 rw_wunlock(&pvh_global_lock);
3805 pmap_free_zero_pages(&free);
3809 * pmap_protect_pde: do the things to protect a 2mpage in a process
3812 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3814 pd_entry_t newpde, oldpde;
3815 vm_offset_t eva, va;
3817 boolean_t anychanged;
3818 pt_entry_t PG_G, PG_M, PG_RW;
3820 PG_G = pmap_global_bit(pmap);
3821 PG_M = pmap_modified_bit(pmap);
3822 PG_RW = pmap_rw_bit(pmap);
3824 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3825 KASSERT((sva & PDRMASK) == 0,
3826 ("pmap_protect_pde: sva is not 2mpage aligned"));
3829 oldpde = newpde = *pde;
3830 if (oldpde & PG_MANAGED) {
3832 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3833 va < eva; va += PAGE_SIZE, m++)
3834 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3837 if ((prot & VM_PROT_WRITE) == 0)
3838 newpde &= ~(PG_RW | PG_M);
3839 if ((prot & VM_PROT_EXECUTE) == 0)
3841 if (newpde != oldpde) {
3842 if (!atomic_cmpset_long(pde, oldpde, newpde))
3845 pmap_invalidate_page(pmap, sva);
3849 return (anychanged);
3853 * Set the physical protection on the
3854 * specified range of this map as requested.
3857 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3859 vm_offset_t va_next;
3860 pml4_entry_t *pml4e;
3862 pd_entry_t ptpaddr, *pde;
3863 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3864 boolean_t anychanged, pv_lists_locked;
3866 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3867 if (prot == VM_PROT_NONE) {
3868 pmap_remove(pmap, sva, eva);
3872 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3873 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3876 PG_G = pmap_global_bit(pmap);
3877 PG_M = pmap_modified_bit(pmap);
3878 PG_V = pmap_valid_bit(pmap);
3879 PG_RW = pmap_rw_bit(pmap);
3880 pv_lists_locked = FALSE;
3885 for (; sva < eva; sva = va_next) {
3887 pml4e = pmap_pml4e(pmap, sva);
3888 if ((*pml4e & PG_V) == 0) {
3889 va_next = (sva + NBPML4) & ~PML4MASK;
3895 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3896 if ((*pdpe & PG_V) == 0) {
3897 va_next = (sva + NBPDP) & ~PDPMASK;
3903 va_next = (sva + NBPDR) & ~PDRMASK;
3907 pde = pmap_pdpe_to_pde(pdpe, sva);
3911 * Weed out invalid mappings.
3917 * Check for large page.
3919 if ((ptpaddr & PG_PS) != 0) {
3921 * Are we protecting the entire large page? If not,
3922 * demote the mapping and fall through.
3924 if (sva + NBPDR == va_next && eva >= va_next) {
3926 * The TLB entry for a PG_G mapping is
3927 * invalidated by pmap_protect_pde().
3929 if (pmap_protect_pde(pmap, pde, sva, prot))
3933 if (!pv_lists_locked) {
3934 pv_lists_locked = TRUE;
3935 if (!rw_try_rlock(&pvh_global_lock)) {
3937 pmap_invalidate_all(
3940 rw_rlock(&pvh_global_lock);
3944 if (!pmap_demote_pde(pmap, pde, sva)) {
3946 * The large page mapping was
3957 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3959 pt_entry_t obits, pbits;
3963 obits = pbits = *pte;
3964 if ((pbits & PG_V) == 0)
3967 if ((prot & VM_PROT_WRITE) == 0) {
3968 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3969 (PG_MANAGED | PG_M | PG_RW)) {
3970 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3973 pbits &= ~(PG_RW | PG_M);
3975 if ((prot & VM_PROT_EXECUTE) == 0)
3978 if (pbits != obits) {
3979 if (!atomic_cmpset_long(pte, obits, pbits))
3982 pmap_invalidate_page(pmap, sva);
3989 pmap_invalidate_all(pmap);
3990 if (pv_lists_locked)
3991 rw_runlock(&pvh_global_lock);
3996 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3997 * single page table page (PTP) to a single 2MB page mapping. For promotion
3998 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3999 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4000 * identical characteristics.
4003 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4004 struct rwlock **lockp)
4007 pt_entry_t *firstpte, oldpte, pa, *pte;
4008 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4012 PG_A = pmap_accessed_bit(pmap);
4013 PG_G = pmap_global_bit(pmap);
4014 PG_M = pmap_modified_bit(pmap);
4015 PG_V = pmap_valid_bit(pmap);
4016 PG_RW = pmap_rw_bit(pmap);
4017 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4019 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4022 * Examine the first PTE in the specified PTP. Abort if this PTE is
4023 * either invalid, unused, or does not map the first 4KB physical page
4024 * within a 2MB page.
4026 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4029 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4030 atomic_add_long(&pmap_pde_p_failures, 1);
4031 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4032 " in pmap %p", va, pmap);
4035 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4037 * When PG_M is already clear, PG_RW can be cleared without
4038 * a TLB invalidation.
4040 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4046 * Examine each of the other PTEs in the specified PTP. Abort if this
4047 * PTE maps an unexpected 4KB physical page or does not have identical
4048 * characteristics to the first PTE.
4050 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4051 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4054 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4055 atomic_add_long(&pmap_pde_p_failures, 1);
4056 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4057 " in pmap %p", va, pmap);
4060 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4062 * When PG_M is already clear, PG_RW can be cleared
4063 * without a TLB invalidation.
4065 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4068 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4069 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
4070 (va & ~PDRMASK), pmap);
4072 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4073 atomic_add_long(&pmap_pde_p_failures, 1);
4074 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4075 " in pmap %p", va, pmap);
4082 * Save the page table page in its current state until the PDE
4083 * mapping the superpage is demoted by pmap_demote_pde() or
4084 * destroyed by pmap_remove_pde().
4086 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4087 KASSERT(mpte >= vm_page_array &&
4088 mpte < &vm_page_array[vm_page_array_size],
4089 ("pmap_promote_pde: page table page is out of range"));
4090 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4091 ("pmap_promote_pde: page table page's pindex is wrong"));
4092 if (pmap_insert_pt_page(pmap, mpte)) {
4093 atomic_add_long(&pmap_pde_p_failures, 1);
4095 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4101 * Promote the pv entries.
4103 if ((newpde & PG_MANAGED) != 0)
4104 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4107 * Propagate the PAT index to its proper position.
4109 newpde = pmap_swap_pat(pmap, newpde);
4112 * Map the superpage.
4114 if (workaround_erratum383)
4115 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4117 pde_store(pde, PG_PS | newpde);
4119 atomic_add_long(&pmap_pde_promotions, 1);
4120 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4121 " in pmap %p", va, pmap);
4125 * Insert the given physical page (p) at
4126 * the specified virtual address (v) in the
4127 * target physical map with the protection requested.
4129 * If specified, the page will be wired down, meaning
4130 * that the related pte can not be reclaimed.
4132 * NB: This is the only routine which MAY NOT lazy-evaluate
4133 * or lose information. That is, this routine must actually
4134 * insert this page into the given map NOW.
4137 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4138 u_int flags, int8_t psind __unused)
4140 struct rwlock *lock;
4142 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4143 pt_entry_t newpte, origpte;
4149 PG_A = pmap_accessed_bit(pmap);
4150 PG_G = pmap_global_bit(pmap);
4151 PG_M = pmap_modified_bit(pmap);
4152 PG_V = pmap_valid_bit(pmap);
4153 PG_RW = pmap_rw_bit(pmap);
4155 va = trunc_page(va);
4156 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4157 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4158 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4160 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4161 va >= kmi.clean_eva,
4162 ("pmap_enter: managed mapping within the clean submap"));
4163 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4164 VM_OBJECT_ASSERT_LOCKED(m->object);
4165 pa = VM_PAGE_TO_PHYS(m);
4166 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4167 if ((flags & VM_PROT_WRITE) != 0)
4169 if ((prot & VM_PROT_WRITE) != 0)
4171 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4172 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4173 if ((prot & VM_PROT_EXECUTE) == 0)
4175 if ((flags & PMAP_ENTER_WIRED) != 0)
4177 if (va < VM_MAXUSER_ADDRESS)
4179 if (pmap == kernel_pmap)
4181 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4184 * Set modified bit gratuitously for writeable mappings if
4185 * the page is unmanaged. We do not want to take a fault
4186 * to do the dirty bit accounting for these mappings.
4188 if ((m->oflags & VPO_UNMANAGED) != 0) {
4189 if ((newpte & PG_RW) != 0)
4196 rw_rlock(&pvh_global_lock);
4200 * In the case that a page table page is not
4201 * resident, we are creating it here.
4204 pde = pmap_pde(pmap, va);
4205 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4206 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4207 pte = pmap_pde_to_pte(pde, va);
4208 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4209 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4212 } else if (va < VM_MAXUSER_ADDRESS) {
4214 * Here if the pte page isn't mapped, or if it has been
4217 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4218 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4219 nosleep ? NULL : &lock);
4220 if (mpte == NULL && nosleep) {
4223 rw_runlock(&pvh_global_lock);
4225 return (KERN_RESOURCE_SHORTAGE);
4229 panic("pmap_enter: invalid page directory va=%#lx", va);
4234 * Is the specified virtual address already mapped?
4236 if ((origpte & PG_V) != 0) {
4238 * Wiring change, just update stats. We don't worry about
4239 * wiring PT pages as they remain resident as long as there
4240 * are valid mappings in them. Hence, if a user page is wired,
4241 * the PT page will be also.
4243 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4244 pmap->pm_stats.wired_count++;
4245 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4246 pmap->pm_stats.wired_count--;
4249 * Remove the extra PT page reference.
4253 KASSERT(mpte->wire_count > 0,
4254 ("pmap_enter: missing reference to page table page,"
4259 * Has the physical page changed?
4261 opa = origpte & PG_FRAME;
4264 * No, might be a protection or wiring change.
4266 if ((origpte & PG_MANAGED) != 0) {
4267 newpte |= PG_MANAGED;
4268 if ((newpte & PG_RW) != 0)
4269 vm_page_aflag_set(m, PGA_WRITEABLE);
4271 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4277 * Increment the counters.
4279 if ((newpte & PG_W) != 0)
4280 pmap->pm_stats.wired_count++;
4281 pmap_resident_count_inc(pmap, 1);
4285 * Enter on the PV list if part of our managed memory.
4287 if ((m->oflags & VPO_UNMANAGED) == 0) {
4288 newpte |= PG_MANAGED;
4289 pv = get_pv_entry(pmap, &lock);
4291 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4292 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4294 if ((newpte & PG_RW) != 0)
4295 vm_page_aflag_set(m, PGA_WRITEABLE);
4301 if ((origpte & PG_V) != 0) {
4303 origpte = pte_load_store(pte, newpte);
4304 opa = origpte & PG_FRAME;
4306 if ((origpte & PG_MANAGED) != 0) {
4307 om = PHYS_TO_VM_PAGE(opa);
4308 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4311 if ((origpte & PG_A) != 0)
4312 vm_page_aflag_set(om, PGA_REFERENCED);
4313 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4314 pmap_pvh_free(&om->md, pmap, va);
4315 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4316 TAILQ_EMPTY(&om->md.pv_list) &&
4317 ((om->flags & PG_FICTITIOUS) != 0 ||
4318 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4319 vm_page_aflag_clear(om, PGA_WRITEABLE);
4321 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4322 PG_RW)) == (PG_M | PG_RW)) {
4323 if ((origpte & PG_MANAGED) != 0)
4327 * Although the PTE may still have PG_RW set, TLB
4328 * invalidation may nonetheless be required because
4329 * the PTE no longer has PG_M set.
4331 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4333 * This PTE change does not require TLB invalidation.
4337 if ((origpte & PG_A) != 0)
4338 pmap_invalidate_page(pmap, va);
4340 pte_store(pte, newpte);
4345 * If both the page table page and the reservation are fully
4346 * populated, then attempt promotion.
4348 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4349 pmap_ps_enabled(pmap) &&
4350 (m->flags & PG_FICTITIOUS) == 0 &&
4351 vm_reserv_level_iffullpop(m) == 0)
4352 pmap_promote_pde(pmap, pde, va, &lock);
4356 rw_runlock(&pvh_global_lock);
4358 return (KERN_SUCCESS);
4362 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4363 * otherwise. Fails if (1) a page table page cannot be allocated without
4364 * blocking, (2) a mapping already exists at the specified virtual address, or
4365 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4368 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4369 struct rwlock **lockp)
4371 pd_entry_t *pde, newpde;
4374 struct spglist free;
4376 PG_V = pmap_valid_bit(pmap);
4377 rw_assert(&pvh_global_lock, RA_LOCKED);
4378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4380 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4381 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4382 " in pmap %p", va, pmap);
4385 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4386 pde = &pde[pmap_pde_index(va)];
4387 if ((*pde & PG_V) != 0) {
4388 KASSERT(mpde->wire_count > 1,
4389 ("pmap_enter_pde: mpde's wire count is too low"));
4391 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4392 " in pmap %p", va, pmap);
4395 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4397 if ((m->oflags & VPO_UNMANAGED) == 0) {
4398 newpde |= PG_MANAGED;
4401 * Abort this mapping if its PV entry could not be created.
4403 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4406 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4407 pmap_invalidate_page(pmap, va);
4408 pmap_free_zero_pages(&free);
4410 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4411 " in pmap %p", va, pmap);
4415 if ((prot & VM_PROT_EXECUTE) == 0)
4417 if (va < VM_MAXUSER_ADDRESS)
4421 * Increment counters.
4423 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4426 * Map the superpage.
4428 pde_store(pde, newpde);
4430 atomic_add_long(&pmap_pde_mappings, 1);
4431 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4432 " in pmap %p", va, pmap);
4437 * Maps a sequence of resident pages belonging to the same object.
4438 * The sequence begins with the given page m_start. This page is
4439 * mapped at the given virtual address start. Each subsequent page is
4440 * mapped at a virtual address that is offset from start by the same
4441 * amount as the page is offset from m_start within the object. The
4442 * last page in the sequence is the page with the largest offset from
4443 * m_start that can be mapped at a virtual address less than the given
4444 * virtual address end. Not every virtual page between start and end
4445 * is mapped; only those for which a resident page exists with the
4446 * corresponding offset from m_start are mapped.
4449 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4450 vm_page_t m_start, vm_prot_t prot)
4452 struct rwlock *lock;
4455 vm_pindex_t diff, psize;
4457 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4459 psize = atop(end - start);
4463 rw_rlock(&pvh_global_lock);
4465 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4466 va = start + ptoa(diff);
4467 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4468 m->psind == 1 && pmap_ps_enabled(pmap) &&
4469 pmap_enter_pde(pmap, va, m, prot, &lock))
4470 m = &m[NBPDR / PAGE_SIZE - 1];
4472 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4474 m = TAILQ_NEXT(m, listq);
4478 rw_runlock(&pvh_global_lock);
4483 * this code makes some *MAJOR* assumptions:
4484 * 1. Current pmap & pmap exists.
4487 * 4. No page table pages.
4488 * but is *MUCH* faster than pmap_enter...
4492 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4494 struct rwlock *lock;
4497 rw_rlock(&pvh_global_lock);
4499 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4502 rw_runlock(&pvh_global_lock);
4507 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4508 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4510 struct spglist free;
4511 pt_entry_t *pte, PG_V;
4514 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4515 (m->oflags & VPO_UNMANAGED) != 0,
4516 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4517 PG_V = pmap_valid_bit(pmap);
4518 rw_assert(&pvh_global_lock, RA_LOCKED);
4519 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4522 * In the case that a page table page is not
4523 * resident, we are creating it here.
4525 if (va < VM_MAXUSER_ADDRESS) {
4526 vm_pindex_t ptepindex;
4530 * Calculate pagetable page index
4532 ptepindex = pmap_pde_pindex(va);
4533 if (mpte && (mpte->pindex == ptepindex)) {
4537 * Get the page directory entry
4539 ptepa = pmap_pde(pmap, va);
4542 * If the page table page is mapped, we just increment
4543 * the hold count, and activate it. Otherwise, we
4544 * attempt to allocate a page table page. If this
4545 * attempt fails, we don't retry. Instead, we give up.
4547 if (ptepa && (*ptepa & PG_V) != 0) {
4550 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4554 * Pass NULL instead of the PV list lock
4555 * pointer, because we don't intend to sleep.
4557 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4562 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4563 pte = &pte[pmap_pte_index(va)];
4577 * Enter on the PV list if part of our managed memory.
4579 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4580 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4583 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4584 pmap_invalidate_page(pmap, va);
4585 pmap_free_zero_pages(&free);
4593 * Increment counters
4595 pmap_resident_count_inc(pmap, 1);
4597 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4598 if ((prot & VM_PROT_EXECUTE) == 0)
4602 * Now validate mapping with RO protection
4604 if ((m->oflags & VPO_UNMANAGED) != 0)
4605 pte_store(pte, pa | PG_V | PG_U);
4607 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4612 * Make a temporary mapping for a physical address. This is only intended
4613 * to be used for panic dumps.
4616 pmap_kenter_temporary(vm_paddr_t pa, int i)
4620 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4621 pmap_kenter(va, pa);
4623 return ((void *)crashdumpmap);
4627 * This code maps large physical mmap regions into the
4628 * processor address space. Note that some shortcuts
4629 * are taken, but the code works.
4632 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4633 vm_pindex_t pindex, vm_size_t size)
4636 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4637 vm_paddr_t pa, ptepa;
4641 PG_A = pmap_accessed_bit(pmap);
4642 PG_M = pmap_modified_bit(pmap);
4643 PG_V = pmap_valid_bit(pmap);
4644 PG_RW = pmap_rw_bit(pmap);
4646 VM_OBJECT_ASSERT_WLOCKED(object);
4647 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4648 ("pmap_object_init_pt: non-device object"));
4649 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4650 if (!pmap_ps_enabled(pmap))
4652 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4654 p = vm_page_lookup(object, pindex);
4655 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4656 ("pmap_object_init_pt: invalid page %p", p));
4657 pat_mode = p->md.pat_mode;
4660 * Abort the mapping if the first page is not physically
4661 * aligned to a 2MB page boundary.
4663 ptepa = VM_PAGE_TO_PHYS(p);
4664 if (ptepa & (NBPDR - 1))
4668 * Skip the first page. Abort the mapping if the rest of
4669 * the pages are not physically contiguous or have differing
4670 * memory attributes.
4672 p = TAILQ_NEXT(p, listq);
4673 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4675 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4676 ("pmap_object_init_pt: invalid page %p", p));
4677 if (pa != VM_PAGE_TO_PHYS(p) ||
4678 pat_mode != p->md.pat_mode)
4680 p = TAILQ_NEXT(p, listq);
4684 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4685 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4686 * will not affect the termination of this loop.
4689 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4690 pa < ptepa + size; pa += NBPDR) {
4691 pdpg = pmap_allocpde(pmap, addr, NULL);
4694 * The creation of mappings below is only an
4695 * optimization. If a page directory page
4696 * cannot be allocated without blocking,
4697 * continue on to the next mapping rather than
4703 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4704 pde = &pde[pmap_pde_index(addr)];
4705 if ((*pde & PG_V) == 0) {
4706 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4707 PG_U | PG_RW | PG_V);
4708 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4709 atomic_add_long(&pmap_pde_mappings, 1);
4711 /* Continue on if the PDE is already valid. */
4713 KASSERT(pdpg->wire_count > 0,
4714 ("pmap_object_init_pt: missing reference "
4715 "to page directory page, va: 0x%lx", addr));
4724 * Clear the wired attribute from the mappings for the specified range of
4725 * addresses in the given pmap. Every valid mapping within that range
4726 * must have the wired attribute set. In contrast, invalid mappings
4727 * cannot have the wired attribute set, so they are ignored.
4729 * The wired attribute of the page table entry is not a hardware feature,
4730 * so there is no need to invalidate any TLB entries.
4733 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4735 vm_offset_t va_next;
4736 pml4_entry_t *pml4e;
4739 pt_entry_t *pte, PG_V;
4740 boolean_t pv_lists_locked;
4742 PG_V = pmap_valid_bit(pmap);
4743 pv_lists_locked = FALSE;
4746 for (; sva < eva; sva = va_next) {
4747 pml4e = pmap_pml4e(pmap, sva);
4748 if ((*pml4e & PG_V) == 0) {
4749 va_next = (sva + NBPML4) & ~PML4MASK;
4754 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4755 if ((*pdpe & PG_V) == 0) {
4756 va_next = (sva + NBPDP) & ~PDPMASK;
4761 va_next = (sva + NBPDR) & ~PDRMASK;
4764 pde = pmap_pdpe_to_pde(pdpe, sva);
4765 if ((*pde & PG_V) == 0)
4767 if ((*pde & PG_PS) != 0) {
4768 if ((*pde & PG_W) == 0)
4769 panic("pmap_unwire: pde %#jx is missing PG_W",
4773 * Are we unwiring the entire large page? If not,
4774 * demote the mapping and fall through.
4776 if (sva + NBPDR == va_next && eva >= va_next) {
4777 atomic_clear_long(pde, PG_W);
4778 pmap->pm_stats.wired_count -= NBPDR /
4782 if (!pv_lists_locked) {
4783 pv_lists_locked = TRUE;
4784 if (!rw_try_rlock(&pvh_global_lock)) {
4786 rw_rlock(&pvh_global_lock);
4791 if (!pmap_demote_pde(pmap, pde, sva))
4792 panic("pmap_unwire: demotion failed");
4797 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4799 if ((*pte & PG_V) == 0)
4801 if ((*pte & PG_W) == 0)
4802 panic("pmap_unwire: pte %#jx is missing PG_W",
4806 * PG_W must be cleared atomically. Although the pmap
4807 * lock synchronizes access to PG_W, another processor
4808 * could be setting PG_M and/or PG_A concurrently.
4810 atomic_clear_long(pte, PG_W);
4811 pmap->pm_stats.wired_count--;
4814 if (pv_lists_locked)
4815 rw_runlock(&pvh_global_lock);
4820 * Copy the range specified by src_addr/len
4821 * from the source map to the range dst_addr/len
4822 * in the destination map.
4824 * This routine is only advisory and need not do anything.
4828 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4829 vm_offset_t src_addr)
4831 struct rwlock *lock;
4832 struct spglist free;
4834 vm_offset_t end_addr = src_addr + len;
4835 vm_offset_t va_next;
4836 pt_entry_t PG_A, PG_M, PG_V;
4838 if (dst_addr != src_addr)
4841 if (dst_pmap->pm_type != src_pmap->pm_type)
4845 * EPT page table entries that require emulation of A/D bits are
4846 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4847 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4848 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4849 * implementations flag an EPT misconfiguration for exec-only
4850 * mappings we skip this function entirely for emulated pmaps.
4852 if (pmap_emulate_ad_bits(dst_pmap))
4856 rw_rlock(&pvh_global_lock);
4857 if (dst_pmap < src_pmap) {
4858 PMAP_LOCK(dst_pmap);
4859 PMAP_LOCK(src_pmap);
4861 PMAP_LOCK(src_pmap);
4862 PMAP_LOCK(dst_pmap);
4865 PG_A = pmap_accessed_bit(dst_pmap);
4866 PG_M = pmap_modified_bit(dst_pmap);
4867 PG_V = pmap_valid_bit(dst_pmap);
4869 for (addr = src_addr; addr < end_addr; addr = va_next) {
4870 pt_entry_t *src_pte, *dst_pte;
4871 vm_page_t dstmpde, dstmpte, srcmpte;
4872 pml4_entry_t *pml4e;
4874 pd_entry_t srcptepaddr, *pde;
4876 KASSERT(addr < UPT_MIN_ADDRESS,
4877 ("pmap_copy: invalid to pmap_copy page tables"));
4879 pml4e = pmap_pml4e(src_pmap, addr);
4880 if ((*pml4e & PG_V) == 0) {
4881 va_next = (addr + NBPML4) & ~PML4MASK;
4887 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4888 if ((*pdpe & PG_V) == 0) {
4889 va_next = (addr + NBPDP) & ~PDPMASK;
4895 va_next = (addr + NBPDR) & ~PDRMASK;
4899 pde = pmap_pdpe_to_pde(pdpe, addr);
4901 if (srcptepaddr == 0)
4904 if (srcptepaddr & PG_PS) {
4905 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4907 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4908 if (dstmpde == NULL)
4910 pde = (pd_entry_t *)
4911 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4912 pde = &pde[pmap_pde_index(addr)];
4913 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4914 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4915 PG_PS_FRAME, &lock))) {
4916 *pde = srcptepaddr & ~PG_W;
4917 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4918 atomic_add_long(&pmap_pde_mappings, 1);
4920 dstmpde->wire_count--;
4924 srcptepaddr &= PG_FRAME;
4925 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4926 KASSERT(srcmpte->wire_count > 0,
4927 ("pmap_copy: source page table page is unused"));
4929 if (va_next > end_addr)
4932 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4933 src_pte = &src_pte[pmap_pte_index(addr)];
4935 while (addr < va_next) {
4939 * we only virtual copy managed pages
4941 if ((ptetemp & PG_MANAGED) != 0) {
4942 if (dstmpte != NULL &&
4943 dstmpte->pindex == pmap_pde_pindex(addr))
4944 dstmpte->wire_count++;
4945 else if ((dstmpte = pmap_allocpte(dst_pmap,
4946 addr, NULL)) == NULL)
4948 dst_pte = (pt_entry_t *)
4949 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4950 dst_pte = &dst_pte[pmap_pte_index(addr)];
4951 if (*dst_pte == 0 &&
4952 pmap_try_insert_pv_entry(dst_pmap, addr,
4953 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4956 * Clear the wired, modified, and
4957 * accessed (referenced) bits
4960 *dst_pte = ptetemp & ~(PG_W | PG_M |
4962 pmap_resident_count_inc(dst_pmap, 1);
4965 if (pmap_unwire_ptp(dst_pmap, addr,
4967 pmap_invalidate_page(dst_pmap,
4969 pmap_free_zero_pages(&free);
4973 if (dstmpte->wire_count >= srcmpte->wire_count)
4983 rw_runlock(&pvh_global_lock);
4984 PMAP_UNLOCK(src_pmap);
4985 PMAP_UNLOCK(dst_pmap);
4989 * pmap_zero_page zeros the specified hardware page by mapping
4990 * the page into KVM and using bzero to clear its contents.
4993 pmap_zero_page(vm_page_t m)
4995 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4997 pagezero((void *)va);
5001 * pmap_zero_page_area zeros the specified hardware page by mapping
5002 * the page into KVM and using bzero to clear its contents.
5004 * off and size may not cover an area beyond a single hardware page.
5007 pmap_zero_page_area(vm_page_t m, int off, int size)
5009 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5011 if (off == 0 && size == PAGE_SIZE)
5012 pagezero((void *)va);
5014 bzero((char *)va + off, size);
5018 * pmap_zero_page_idle zeros the specified hardware page by mapping
5019 * the page into KVM and using bzero to clear its contents. This
5020 * is intended to be called from the vm_pagezero process only and
5024 pmap_zero_page_idle(vm_page_t m)
5026 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5028 pagezero((void *)va);
5032 * pmap_copy_page copies the specified (machine independent)
5033 * page by mapping the page into virtual memory and using
5034 * bcopy to copy the page, one machine dependent page at a
5038 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5040 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5041 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5043 pagecopy((void *)src, (void *)dst);
5046 int unmapped_buf_allowed = 1;
5049 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5050 vm_offset_t b_offset, int xfersize)
5054 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
5058 while (xfersize > 0) {
5059 a_pg_offset = a_offset & PAGE_MASK;
5060 pages[0] = ma[a_offset >> PAGE_SHIFT];
5061 b_pg_offset = b_offset & PAGE_MASK;
5062 pages[1] = mb[b_offset >> PAGE_SHIFT];
5063 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5064 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5065 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
5066 a_cp = (char *)vaddr[0] + a_pg_offset;
5067 b_cp = (char *)vaddr[1] + b_pg_offset;
5068 bcopy(a_cp, b_cp, cnt);
5069 if (__predict_false(mapped))
5070 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
5078 * Returns true if the pmap's pv is one of the first
5079 * 16 pvs linked to from this page. This count may
5080 * be changed upwards or downwards in the future; it
5081 * is only necessary that true be returned for a small
5082 * subset of pmaps for proper page aging.
5085 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5087 struct md_page *pvh;
5088 struct rwlock *lock;
5093 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5094 ("pmap_page_exists_quick: page %p is not managed", m));
5096 rw_rlock(&pvh_global_lock);
5097 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5099 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5100 if (PV_PMAP(pv) == pmap) {
5108 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5109 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5110 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5111 if (PV_PMAP(pv) == pmap) {
5121 rw_runlock(&pvh_global_lock);
5126 * pmap_page_wired_mappings:
5128 * Return the number of managed mappings to the given physical page
5132 pmap_page_wired_mappings(vm_page_t m)
5134 struct rwlock *lock;
5135 struct md_page *pvh;
5139 int count, md_gen, pvh_gen;
5141 if ((m->oflags & VPO_UNMANAGED) != 0)
5143 rw_rlock(&pvh_global_lock);
5144 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5148 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5150 if (!PMAP_TRYLOCK(pmap)) {
5151 md_gen = m->md.pv_gen;
5155 if (md_gen != m->md.pv_gen) {
5160 pte = pmap_pte(pmap, pv->pv_va);
5161 if ((*pte & PG_W) != 0)
5165 if ((m->flags & PG_FICTITIOUS) == 0) {
5166 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5167 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5169 if (!PMAP_TRYLOCK(pmap)) {
5170 md_gen = m->md.pv_gen;
5171 pvh_gen = pvh->pv_gen;
5175 if (md_gen != m->md.pv_gen ||
5176 pvh_gen != pvh->pv_gen) {
5181 pte = pmap_pde(pmap, pv->pv_va);
5182 if ((*pte & PG_W) != 0)
5188 rw_runlock(&pvh_global_lock);
5193 * Returns TRUE if the given page is mapped individually or as part of
5194 * a 2mpage. Otherwise, returns FALSE.
5197 pmap_page_is_mapped(vm_page_t m)
5199 struct rwlock *lock;
5202 if ((m->oflags & VPO_UNMANAGED) != 0)
5204 rw_rlock(&pvh_global_lock);
5205 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5207 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5208 ((m->flags & PG_FICTITIOUS) == 0 &&
5209 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5211 rw_runlock(&pvh_global_lock);
5216 * Destroy all managed, non-wired mappings in the given user-space
5217 * pmap. This pmap cannot be active on any processor besides the
5220 * This function cannot be applied to the kernel pmap. Moreover, it
5221 * is not intended for general use. It is only to be used during
5222 * process termination. Consequently, it can be implemented in ways
5223 * that make it faster than pmap_remove(). First, it can more quickly
5224 * destroy mappings by iterating over the pmap's collection of PV
5225 * entries, rather than searching the page table. Second, it doesn't
5226 * have to test and clear the page table entries atomically, because
5227 * no processor is currently accessing the user address space. In
5228 * particular, a page table entry's dirty bit won't change state once
5229 * this function starts.
5232 pmap_remove_pages(pmap_t pmap)
5235 pt_entry_t *pte, tpte;
5236 pt_entry_t PG_M, PG_RW, PG_V;
5237 struct spglist free;
5238 vm_page_t m, mpte, mt;
5240 struct md_page *pvh;
5241 struct pv_chunk *pc, *npc;
5242 struct rwlock *lock;
5244 uint64_t inuse, bitmask;
5245 int allfree, field, freed, idx;
5246 boolean_t superpage;
5250 * Assert that the given pmap is only active on the current
5251 * CPU. Unfortunately, we cannot block another CPU from
5252 * activating the pmap while this function is executing.
5254 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5257 cpuset_t other_cpus;
5259 other_cpus = all_cpus;
5261 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5262 CPU_AND(&other_cpus, &pmap->pm_active);
5264 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5269 PG_M = pmap_modified_bit(pmap);
5270 PG_V = pmap_valid_bit(pmap);
5271 PG_RW = pmap_rw_bit(pmap);
5274 rw_rlock(&pvh_global_lock);
5276 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5279 for (field = 0; field < _NPCM; field++) {
5280 inuse = ~pc->pc_map[field] & pc_freemask[field];
5281 while (inuse != 0) {
5283 bitmask = 1UL << bit;
5284 idx = field * 64 + bit;
5285 pv = &pc->pc_pventry[idx];
5288 pte = pmap_pdpe(pmap, pv->pv_va);
5290 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5292 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5295 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5297 pte = &pte[pmap_pte_index(pv->pv_va)];
5301 * Keep track whether 'tpte' is a
5302 * superpage explicitly instead of
5303 * relying on PG_PS being set.
5305 * This is because PG_PS is numerically
5306 * identical to PG_PTE_PAT and thus a
5307 * regular page could be mistaken for
5313 if ((tpte & PG_V) == 0) {
5314 panic("bad pte va %lx pte %lx",
5319 * We cannot remove wired pages from a process' mapping at this time
5327 pa = tpte & PG_PS_FRAME;
5329 pa = tpte & PG_FRAME;
5331 m = PHYS_TO_VM_PAGE(pa);
5332 KASSERT(m->phys_addr == pa,
5333 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5334 m, (uintmax_t)m->phys_addr,
5337 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5338 m < &vm_page_array[vm_page_array_size],
5339 ("pmap_remove_pages: bad tpte %#jx",
5345 * Update the vm_page_t clean/reference bits.
5347 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5349 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5355 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5358 pc->pc_map[field] |= bitmask;
5360 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5361 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5362 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5364 if (TAILQ_EMPTY(&pvh->pv_list)) {
5365 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5366 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5367 TAILQ_EMPTY(&mt->md.pv_list))
5368 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5370 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5372 pmap_remove_pt_page(pmap, mpte);
5373 pmap_resident_count_dec(pmap, 1);
5374 KASSERT(mpte->wire_count == NPTEPG,
5375 ("pmap_remove_pages: pte page wire count error"));
5376 mpte->wire_count = 0;
5377 pmap_add_delayed_free_list(mpte, &free, FALSE);
5378 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
5381 pmap_resident_count_dec(pmap, 1);
5382 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5384 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5385 TAILQ_EMPTY(&m->md.pv_list) &&
5386 (m->flags & PG_FICTITIOUS) == 0) {
5387 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5388 if (TAILQ_EMPTY(&pvh->pv_list))
5389 vm_page_aflag_clear(m, PGA_WRITEABLE);
5392 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5396 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5397 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5398 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5400 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5406 pmap_invalidate_all(pmap);
5407 rw_runlock(&pvh_global_lock);
5409 pmap_free_zero_pages(&free);
5413 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5415 struct rwlock *lock;
5417 struct md_page *pvh;
5418 pt_entry_t *pte, mask;
5419 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5421 int md_gen, pvh_gen;
5425 rw_rlock(&pvh_global_lock);
5426 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5429 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5431 if (!PMAP_TRYLOCK(pmap)) {
5432 md_gen = m->md.pv_gen;
5436 if (md_gen != m->md.pv_gen) {
5441 pte = pmap_pte(pmap, pv->pv_va);
5444 PG_M = pmap_modified_bit(pmap);
5445 PG_RW = pmap_rw_bit(pmap);
5446 mask |= PG_RW | PG_M;
5449 PG_A = pmap_accessed_bit(pmap);
5450 PG_V = pmap_valid_bit(pmap);
5451 mask |= PG_V | PG_A;
5453 rv = (*pte & mask) == mask;
5458 if ((m->flags & PG_FICTITIOUS) == 0) {
5459 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5460 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5462 if (!PMAP_TRYLOCK(pmap)) {
5463 md_gen = m->md.pv_gen;
5464 pvh_gen = pvh->pv_gen;
5468 if (md_gen != m->md.pv_gen ||
5469 pvh_gen != pvh->pv_gen) {
5474 pte = pmap_pde(pmap, pv->pv_va);
5477 PG_M = pmap_modified_bit(pmap);
5478 PG_RW = pmap_rw_bit(pmap);
5479 mask |= PG_RW | PG_M;
5482 PG_A = pmap_accessed_bit(pmap);
5483 PG_V = pmap_valid_bit(pmap);
5484 mask |= PG_V | PG_A;
5486 rv = (*pte & mask) == mask;
5494 rw_runlock(&pvh_global_lock);
5501 * Return whether or not the specified physical page was modified
5502 * in any physical maps.
5505 pmap_is_modified(vm_page_t m)
5508 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5509 ("pmap_is_modified: page %p is not managed", m));
5512 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5513 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5514 * is clear, no PTEs can have PG_M set.
5516 VM_OBJECT_ASSERT_WLOCKED(m->object);
5517 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5519 return (pmap_page_test_mappings(m, FALSE, TRUE));
5523 * pmap_is_prefaultable:
5525 * Return whether or not the specified virtual address is eligible
5529 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5532 pt_entry_t *pte, PG_V;
5535 PG_V = pmap_valid_bit(pmap);
5538 pde = pmap_pde(pmap, addr);
5539 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5540 pte = pmap_pde_to_pte(pde, addr);
5541 rv = (*pte & PG_V) == 0;
5548 * pmap_is_referenced:
5550 * Return whether or not the specified physical page was referenced
5551 * in any physical maps.
5554 pmap_is_referenced(vm_page_t m)
5557 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5558 ("pmap_is_referenced: page %p is not managed", m));
5559 return (pmap_page_test_mappings(m, TRUE, FALSE));
5563 * Clear the write and modified bits in each of the given page's mappings.
5566 pmap_remove_write(vm_page_t m)
5568 struct md_page *pvh;
5570 struct rwlock *lock;
5571 pv_entry_t next_pv, pv;
5573 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5575 int pvh_gen, md_gen;
5577 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5578 ("pmap_remove_write: page %p is not managed", m));
5581 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5582 * set by another thread while the object is locked. Thus,
5583 * if PGA_WRITEABLE is clear, no page table entries need updating.
5585 VM_OBJECT_ASSERT_WLOCKED(m->object);
5586 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5588 rw_rlock(&pvh_global_lock);
5589 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5590 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5593 if ((m->flags & PG_FICTITIOUS) != 0)
5594 goto small_mappings;
5595 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5597 if (!PMAP_TRYLOCK(pmap)) {
5598 pvh_gen = pvh->pv_gen;
5602 if (pvh_gen != pvh->pv_gen) {
5608 PG_RW = pmap_rw_bit(pmap);
5610 pde = pmap_pde(pmap, va);
5611 if ((*pde & PG_RW) != 0)
5612 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5613 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5614 ("inconsistent pv lock %p %p for page %p",
5615 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5619 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5621 if (!PMAP_TRYLOCK(pmap)) {
5622 pvh_gen = pvh->pv_gen;
5623 md_gen = m->md.pv_gen;
5627 if (pvh_gen != pvh->pv_gen ||
5628 md_gen != m->md.pv_gen) {
5634 PG_M = pmap_modified_bit(pmap);
5635 PG_RW = pmap_rw_bit(pmap);
5636 pde = pmap_pde(pmap, pv->pv_va);
5637 KASSERT((*pde & PG_PS) == 0,
5638 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5640 pte = pmap_pde_to_pte(pde, pv->pv_va);
5643 if (oldpte & PG_RW) {
5644 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5647 if ((oldpte & PG_M) != 0)
5649 pmap_invalidate_page(pmap, pv->pv_va);
5654 vm_page_aflag_clear(m, PGA_WRITEABLE);
5655 rw_runlock(&pvh_global_lock);
5658 static __inline boolean_t
5659 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5662 if (!pmap_emulate_ad_bits(pmap))
5665 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5668 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
5669 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5670 * if the EPT_PG_WRITE bit is set.
5672 if ((pte & EPT_PG_WRITE) != 0)
5676 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5678 if ((pte & EPT_PG_EXECUTE) == 0 ||
5679 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5685 #define PMAP_TS_REFERENCED_MAX 5
5688 * pmap_ts_referenced:
5690 * Return a count of reference bits for a page, clearing those bits.
5691 * It is not necessary for every reference bit to be cleared, but it
5692 * is necessary that 0 only be returned when there are truly no
5693 * reference bits set.
5695 * XXX: The exact number of bits to check and clear is a matter that
5696 * should be tested and standardized at some point in the future for
5697 * optimal aging of shared pages.
5700 pmap_ts_referenced(vm_page_t m)
5702 struct md_page *pvh;
5705 struct rwlock *lock;
5706 pd_entry_t oldpde, *pde;
5707 pt_entry_t *pte, PG_A;
5710 int cleared, md_gen, not_cleared, pvh_gen;
5711 struct spglist free;
5714 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5715 ("pmap_ts_referenced: page %p is not managed", m));
5718 pa = VM_PAGE_TO_PHYS(m);
5719 lock = PHYS_TO_PV_LIST_LOCK(pa);
5720 pvh = pa_to_pvh(pa);
5721 rw_rlock(&pvh_global_lock);
5725 if ((m->flags & PG_FICTITIOUS) != 0 ||
5726 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5727 goto small_mappings;
5733 if (!PMAP_TRYLOCK(pmap)) {
5734 pvh_gen = pvh->pv_gen;
5738 if (pvh_gen != pvh->pv_gen) {
5743 PG_A = pmap_accessed_bit(pmap);
5745 pde = pmap_pde(pmap, pv->pv_va);
5747 if ((*pde & PG_A) != 0) {
5749 * Since this reference bit is shared by 512 4KB
5750 * pages, it should not be cleared every time it is
5751 * tested. Apply a simple "hash" function on the
5752 * physical page number, the virtual superpage number,
5753 * and the pmap address to select one 4KB page out of
5754 * the 512 on which testing the reference bit will
5755 * result in clearing that reference bit. This
5756 * function is designed to avoid the selection of the
5757 * same 4KB page for every 2MB page mapping.
5759 * On demotion, a mapping that hasn't been referenced
5760 * is simply destroyed. To avoid the possibility of a
5761 * subsequent page fault on a demoted wired mapping,
5762 * always leave its reference bit set. Moreover,
5763 * since the superpage is wired, the current state of
5764 * its reference bit won't affect page replacement.
5766 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5767 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5768 (*pde & PG_W) == 0) {
5769 if (safe_to_clear_referenced(pmap, oldpde)) {
5770 atomic_clear_long(pde, PG_A);
5771 pmap_invalidate_page(pmap, pv->pv_va);
5773 } else if (pmap_demote_pde_locked(pmap, pde,
5774 pv->pv_va, &lock)) {
5776 * Remove the mapping to a single page
5777 * so that a subsequent access may
5778 * repromote. Since the underlying
5779 * page table page is fully populated,
5780 * this removal never frees a page
5784 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5786 pte = pmap_pde_to_pte(pde, va);
5787 pmap_remove_pte(pmap, pte, va, *pde,
5789 pmap_invalidate_page(pmap, va);
5795 * The superpage mapping was removed
5796 * entirely and therefore 'pv' is no
5804 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5805 ("inconsistent pv lock %p %p for page %p",
5806 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5811 /* Rotate the PV list if it has more than one entry. */
5812 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5813 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5814 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5817 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5819 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5821 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5828 if (!PMAP_TRYLOCK(pmap)) {
5829 pvh_gen = pvh->pv_gen;
5830 md_gen = m->md.pv_gen;
5834 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5839 PG_A = pmap_accessed_bit(pmap);
5840 pde = pmap_pde(pmap, pv->pv_va);
5841 KASSERT((*pde & PG_PS) == 0,
5842 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5844 pte = pmap_pde_to_pte(pde, pv->pv_va);
5845 if ((*pte & PG_A) != 0) {
5846 if (safe_to_clear_referenced(pmap, *pte)) {
5847 atomic_clear_long(pte, PG_A);
5848 pmap_invalidate_page(pmap, pv->pv_va);
5850 } else if ((*pte & PG_W) == 0) {
5852 * Wired pages cannot be paged out so
5853 * doing accessed bit emulation for
5854 * them is wasted effort. We do the
5855 * hard work for unwired pages only.
5857 pmap_remove_pte(pmap, pte, pv->pv_va,
5858 *pde, &free, &lock);
5859 pmap_invalidate_page(pmap, pv->pv_va);
5864 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5865 ("inconsistent pv lock %p %p for page %p",
5866 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5871 /* Rotate the PV list if it has more than one entry. */
5872 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5873 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5874 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5877 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5878 not_cleared < PMAP_TS_REFERENCED_MAX);
5881 rw_runlock(&pvh_global_lock);
5882 pmap_free_zero_pages(&free);
5883 return (cleared + not_cleared);
5887 * Apply the given advice to the specified range of addresses within the
5888 * given pmap. Depending on the advice, clear the referenced and/or
5889 * modified flags in each mapping and set the mapped page's dirty field.
5892 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5894 struct rwlock *lock;
5895 pml4_entry_t *pml4e;
5897 pd_entry_t oldpde, *pde;
5898 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5899 vm_offset_t va_next;
5901 boolean_t anychanged, pv_lists_locked;
5903 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5907 * A/D bit emulation requires an alternate code path when clearing
5908 * the modified and accessed bits below. Since this function is
5909 * advisory in nature we skip it entirely for pmaps that require
5910 * A/D bit emulation.
5912 if (pmap_emulate_ad_bits(pmap))
5915 PG_A = pmap_accessed_bit(pmap);
5916 PG_G = pmap_global_bit(pmap);
5917 PG_M = pmap_modified_bit(pmap);
5918 PG_V = pmap_valid_bit(pmap);
5919 PG_RW = pmap_rw_bit(pmap);
5921 pv_lists_locked = FALSE;
5925 for (; sva < eva; sva = va_next) {
5926 pml4e = pmap_pml4e(pmap, sva);
5927 if ((*pml4e & PG_V) == 0) {
5928 va_next = (sva + NBPML4) & ~PML4MASK;
5933 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5934 if ((*pdpe & PG_V) == 0) {
5935 va_next = (sva + NBPDP) & ~PDPMASK;
5940 va_next = (sva + NBPDR) & ~PDRMASK;
5943 pde = pmap_pdpe_to_pde(pdpe, sva);
5945 if ((oldpde & PG_V) == 0)
5947 else if ((oldpde & PG_PS) != 0) {
5948 if ((oldpde & PG_MANAGED) == 0)
5950 if (!pv_lists_locked) {
5951 pv_lists_locked = TRUE;
5952 if (!rw_try_rlock(&pvh_global_lock)) {
5954 pmap_invalidate_all(pmap);
5956 rw_rlock(&pvh_global_lock);
5961 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5966 * The large page mapping was destroyed.
5972 * Unless the page mappings are wired, remove the
5973 * mapping to a single page so that a subsequent
5974 * access may repromote. Since the underlying page
5975 * table page is fully populated, this removal never
5976 * frees a page table page.
5978 if ((oldpde & PG_W) == 0) {
5979 pte = pmap_pde_to_pte(pde, sva);
5980 KASSERT((*pte & PG_V) != 0,
5981 ("pmap_advise: invalid PTE"));
5982 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
5991 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5993 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
5996 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5997 if (advice == MADV_DONTNEED) {
5999 * Future calls to pmap_is_modified()
6000 * can be avoided by making the page
6003 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6006 atomic_clear_long(pte, PG_M | PG_A);
6007 } else if ((*pte & PG_A) != 0)
6008 atomic_clear_long(pte, PG_A);
6011 if ((*pte & PG_G) != 0)
6012 pmap_invalidate_page(pmap, sva);
6018 pmap_invalidate_all(pmap);
6019 if (pv_lists_locked)
6020 rw_runlock(&pvh_global_lock);
6025 * Clear the modify bits on the specified physical page.
6028 pmap_clear_modify(vm_page_t m)
6030 struct md_page *pvh;
6032 pv_entry_t next_pv, pv;
6033 pd_entry_t oldpde, *pde;
6034 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6035 struct rwlock *lock;
6037 int md_gen, pvh_gen;
6039 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6040 ("pmap_clear_modify: page %p is not managed", m));
6041 VM_OBJECT_ASSERT_WLOCKED(m->object);
6042 KASSERT(!vm_page_xbusied(m),
6043 ("pmap_clear_modify: page %p is exclusive busied", m));
6046 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6047 * If the object containing the page is locked and the page is not
6048 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6050 if ((m->aflags & PGA_WRITEABLE) == 0)
6052 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6053 rw_rlock(&pvh_global_lock);
6054 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6057 if ((m->flags & PG_FICTITIOUS) != 0)
6058 goto small_mappings;
6059 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6061 if (!PMAP_TRYLOCK(pmap)) {
6062 pvh_gen = pvh->pv_gen;
6066 if (pvh_gen != pvh->pv_gen) {
6071 PG_M = pmap_modified_bit(pmap);
6072 PG_V = pmap_valid_bit(pmap);
6073 PG_RW = pmap_rw_bit(pmap);
6075 pde = pmap_pde(pmap, va);
6077 if ((oldpde & PG_RW) != 0) {
6078 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6079 if ((oldpde & PG_W) == 0) {
6081 * Write protect the mapping to a
6082 * single page so that a subsequent
6083 * write access may repromote.
6085 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6087 pte = pmap_pde_to_pte(pde, va);
6089 if ((oldpte & PG_V) != 0) {
6090 while (!atomic_cmpset_long(pte,
6092 oldpte & ~(PG_M | PG_RW)))
6095 pmap_invalidate_page(pmap, va);
6103 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6105 if (!PMAP_TRYLOCK(pmap)) {
6106 md_gen = m->md.pv_gen;
6107 pvh_gen = pvh->pv_gen;
6111 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6116 PG_M = pmap_modified_bit(pmap);
6117 PG_RW = pmap_rw_bit(pmap);
6118 pde = pmap_pde(pmap, pv->pv_va);
6119 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6120 " a 2mpage in page %p's pv list", m));
6121 pte = pmap_pde_to_pte(pde, pv->pv_va);
6122 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6123 atomic_clear_long(pte, PG_M);
6124 pmap_invalidate_page(pmap, pv->pv_va);
6129 rw_runlock(&pvh_global_lock);
6133 * Miscellaneous support routines follow
6136 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6137 static __inline void
6138 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6143 * The cache mode bits are all in the low 32-bits of the
6144 * PTE, so we can just spin on updating the low 32-bits.
6147 opte = *(u_int *)pte;
6148 npte = opte & ~mask;
6150 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6153 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6154 static __inline void
6155 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6160 * The cache mode bits are all in the low 32-bits of the
6161 * PDE, so we can just spin on updating the low 32-bits.
6164 opde = *(u_int *)pde;
6165 npde = opde & ~mask;
6167 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6171 * Map a set of physical memory pages into the kernel virtual
6172 * address space. Return a pointer to where it is mapped. This
6173 * routine is intended to be used for mapping device memory,
6177 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6179 struct pmap_preinit_mapping *ppim;
6180 vm_offset_t va, offset;
6184 offset = pa & PAGE_MASK;
6185 size = round_page(offset + size);
6186 pa = trunc_page(pa);
6188 if (!pmap_initialized) {
6190 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6191 ppim = pmap_preinit_mapping + i;
6192 if (ppim->va == 0) {
6196 ppim->va = virtual_avail;
6197 virtual_avail += size;
6203 panic("%s: too many preinit mappings", __func__);
6206 * If we have a preinit mapping, re-use it.
6208 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6209 ppim = pmap_preinit_mapping + i;
6210 if (ppim->pa == pa && ppim->sz == size &&
6212 return ((void *)(ppim->va + offset));
6215 * If the specified range of physical addresses fits within
6216 * the direct map window, use the direct map.
6218 if (pa < dmaplimit && pa + size < dmaplimit) {
6219 va = PHYS_TO_DMAP(pa);
6220 if (!pmap_change_attr(va, size, mode))
6221 return ((void *)(va + offset));
6223 va = kva_alloc(size);
6225 panic("%s: Couldn't allocate KVA", __func__);
6227 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6228 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6229 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6230 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6231 return ((void *)(va + offset));
6235 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6238 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6242 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6245 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6249 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6251 struct pmap_preinit_mapping *ppim;
6255 /* If we gave a direct map region in pmap_mapdev, do nothing */
6256 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6258 offset = va & PAGE_MASK;
6259 size = round_page(offset + size);
6260 va = trunc_page(va);
6261 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
6262 ppim = pmap_preinit_mapping + i;
6263 if (ppim->va == va && ppim->sz == size) {
6264 if (pmap_initialized)
6270 if (va + size == virtual_avail)
6275 if (pmap_initialized)
6280 * Tries to demote a 1GB page mapping.
6283 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6285 pdp_entry_t newpdpe, oldpdpe;
6286 pd_entry_t *firstpde, newpde, *pde;
6287 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6291 PG_A = pmap_accessed_bit(pmap);
6292 PG_M = pmap_modified_bit(pmap);
6293 PG_V = pmap_valid_bit(pmap);
6294 PG_RW = pmap_rw_bit(pmap);
6296 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6298 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6299 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6300 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6301 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6302 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6303 " in pmap %p", va, pmap);
6306 mpdepa = VM_PAGE_TO_PHYS(mpde);
6307 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6308 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6309 KASSERT((oldpdpe & PG_A) != 0,
6310 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6311 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6312 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6316 * Initialize the page directory page.
6318 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6324 * Demote the mapping.
6329 * Invalidate a stale recursive mapping of the page directory page.
6331 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6333 pmap_pdpe_demotions++;
6334 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6335 " in pmap %p", va, pmap);
6340 * Sets the memory attribute for the specified page.
6343 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6346 m->md.pat_mode = ma;
6349 * If "m" is a normal page, update its direct mapping. This update
6350 * can be relied upon to perform any cache operations that are
6351 * required for data coherence.
6353 if ((m->flags & PG_FICTITIOUS) == 0 &&
6354 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6356 panic("memory attribute change on the direct map failed");
6360 * Changes the specified virtual address range's memory type to that given by
6361 * the parameter "mode". The specified virtual address range must be
6362 * completely contained within either the direct map or the kernel map. If
6363 * the virtual address range is contained within the kernel map, then the
6364 * memory type for each of the corresponding ranges of the direct map is also
6365 * changed. (The corresponding ranges of the direct map are those ranges that
6366 * map the same physical pages as the specified virtual address range.) These
6367 * changes to the direct map are necessary because Intel describes the
6368 * behavior of their processors as "undefined" if two or more mappings to the
6369 * same physical page have different memory types.
6371 * Returns zero if the change completed successfully, and either EINVAL or
6372 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6373 * of the virtual address range was not mapped, and ENOMEM is returned if
6374 * there was insufficient memory available to complete the change. In the
6375 * latter case, the memory type may have been changed on some part of the
6376 * virtual address range or the direct map.
6379 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6383 PMAP_LOCK(kernel_pmap);
6384 error = pmap_change_attr_locked(va, size, mode);
6385 PMAP_UNLOCK(kernel_pmap);
6390 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6392 vm_offset_t base, offset, tmpva;
6393 vm_paddr_t pa_start, pa_end;
6397 int cache_bits_pte, cache_bits_pde, error;
6400 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6401 base = trunc_page(va);
6402 offset = va & PAGE_MASK;
6403 size = round_page(offset + size);
6406 * Only supported on kernel virtual addresses, including the direct
6407 * map but excluding the recursive map.
6409 if (base < DMAP_MIN_ADDRESS)
6412 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6413 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6417 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6418 * into 4KB pages if required.
6420 for (tmpva = base; tmpva < base + size; ) {
6421 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6422 if (pdpe == NULL || *pdpe == 0)
6424 if (*pdpe & PG_PS) {
6426 * If the current 1GB page already has the required
6427 * memory type, then we need not demote this page. Just
6428 * increment tmpva to the next 1GB page frame.
6430 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6431 tmpva = trunc_1gpage(tmpva) + NBPDP;
6436 * If the current offset aligns with a 1GB page frame
6437 * and there is at least 1GB left within the range, then
6438 * we need not break down this page into 2MB pages.
6440 if ((tmpva & PDPMASK) == 0 &&
6441 tmpva + PDPMASK < base + size) {
6445 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6448 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6453 * If the current 2MB page already has the required
6454 * memory type, then we need not demote this page. Just
6455 * increment tmpva to the next 2MB page frame.
6457 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6458 tmpva = trunc_2mpage(tmpva) + NBPDR;
6463 * If the current offset aligns with a 2MB page frame
6464 * and there is at least 2MB left within the range, then
6465 * we need not break down this page into 4KB pages.
6467 if ((tmpva & PDRMASK) == 0 &&
6468 tmpva + PDRMASK < base + size) {
6472 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6475 pte = pmap_pde_to_pte(pde, tmpva);
6483 * Ok, all the pages exist, so run through them updating their
6484 * cache mode if required.
6486 pa_start = pa_end = 0;
6487 for (tmpva = base; tmpva < base + size; ) {
6488 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6489 if (*pdpe & PG_PS) {
6490 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6491 pmap_pde_attr(pdpe, cache_bits_pde,
6495 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6496 (*pdpe & PG_PS_FRAME) < dmaplimit) {
6497 if (pa_start == pa_end) {
6498 /* Start physical address run. */
6499 pa_start = *pdpe & PG_PS_FRAME;
6500 pa_end = pa_start + NBPDP;
6501 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6504 /* Run ended, update direct map. */
6505 error = pmap_change_attr_locked(
6506 PHYS_TO_DMAP(pa_start),
6507 pa_end - pa_start, mode);
6510 /* Start physical address run. */
6511 pa_start = *pdpe & PG_PS_FRAME;
6512 pa_end = pa_start + NBPDP;
6515 tmpva = trunc_1gpage(tmpva) + NBPDP;
6518 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6520 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6521 pmap_pde_attr(pde, cache_bits_pde,
6525 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6526 (*pde & PG_PS_FRAME) < dmaplimit) {
6527 if (pa_start == pa_end) {
6528 /* Start physical address run. */
6529 pa_start = *pde & PG_PS_FRAME;
6530 pa_end = pa_start + NBPDR;
6531 } else if (pa_end == (*pde & PG_PS_FRAME))
6534 /* Run ended, update direct map. */
6535 error = pmap_change_attr_locked(
6536 PHYS_TO_DMAP(pa_start),
6537 pa_end - pa_start, mode);
6540 /* Start physical address run. */
6541 pa_start = *pde & PG_PS_FRAME;
6542 pa_end = pa_start + NBPDR;
6545 tmpva = trunc_2mpage(tmpva) + NBPDR;
6547 pte = pmap_pde_to_pte(pde, tmpva);
6548 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6549 pmap_pte_attr(pte, cache_bits_pte,
6553 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
6554 (*pte & PG_PS_FRAME) < dmaplimit) {
6555 if (pa_start == pa_end) {
6556 /* Start physical address run. */
6557 pa_start = *pte & PG_FRAME;
6558 pa_end = pa_start + PAGE_SIZE;
6559 } else if (pa_end == (*pte & PG_FRAME))
6560 pa_end += PAGE_SIZE;
6562 /* Run ended, update direct map. */
6563 error = pmap_change_attr_locked(
6564 PHYS_TO_DMAP(pa_start),
6565 pa_end - pa_start, mode);
6568 /* Start physical address run. */
6569 pa_start = *pte & PG_FRAME;
6570 pa_end = pa_start + PAGE_SIZE;
6576 if (error == 0 && pa_start != pa_end)
6577 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6578 pa_end - pa_start, mode);
6581 * Flush CPU caches if required to make sure any data isn't cached that
6582 * shouldn't be, etc.
6585 pmap_invalidate_range(kernel_pmap, base, tmpva);
6586 pmap_invalidate_cache_range(base, tmpva, FALSE);
6592 * Demotes any mapping within the direct map region that covers more than the
6593 * specified range of physical addresses. This range's size must be a power
6594 * of two and its starting address must be a multiple of its size. Since the
6595 * demotion does not change any attributes of the mapping, a TLB invalidation
6596 * is not mandatory. The caller may, however, request a TLB invalidation.
6599 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6608 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6609 KASSERT((base & (len - 1)) == 0,
6610 ("pmap_demote_DMAP: base is not a multiple of len"));
6611 if (len < NBPDP && base < dmaplimit) {
6612 va = PHYS_TO_DMAP(base);
6614 PMAP_LOCK(kernel_pmap);
6615 pdpe = pmap_pdpe(kernel_pmap, va);
6616 if ((*pdpe & X86_PG_V) == 0)
6617 panic("pmap_demote_DMAP: invalid PDPE");
6618 if ((*pdpe & PG_PS) != 0) {
6619 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6620 panic("pmap_demote_DMAP: PDPE failed");
6624 pde = pmap_pdpe_to_pde(pdpe, va);
6625 if ((*pde & X86_PG_V) == 0)
6626 panic("pmap_demote_DMAP: invalid PDE");
6627 if ((*pde & PG_PS) != 0) {
6628 if (!pmap_demote_pde(kernel_pmap, pde, va))
6629 panic("pmap_demote_DMAP: PDE failed");
6633 if (changed && invalidate)
6634 pmap_invalidate_page(kernel_pmap, va);
6635 PMAP_UNLOCK(kernel_pmap);
6640 * perform the pmap work for mincore
6643 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6646 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6650 PG_A = pmap_accessed_bit(pmap);
6651 PG_M = pmap_modified_bit(pmap);
6652 PG_V = pmap_valid_bit(pmap);
6653 PG_RW = pmap_rw_bit(pmap);
6657 pdep = pmap_pde(pmap, addr);
6658 if (pdep != NULL && (*pdep & PG_V)) {
6659 if (*pdep & PG_PS) {
6661 /* Compute the physical address of the 4KB page. */
6662 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6664 val = MINCORE_SUPER;
6666 pte = *pmap_pde_to_pte(pdep, addr);
6667 pa = pte & PG_FRAME;
6675 if ((pte & PG_V) != 0) {
6676 val |= MINCORE_INCORE;
6677 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6678 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6679 if ((pte & PG_A) != 0)
6680 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6682 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6683 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6684 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6685 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6686 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6689 PA_UNLOCK_COND(*locked_pa);
6695 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
6697 uint32_t gen, new_gen, pcid_next;
6699 CRITICAL_ASSERT(curthread);
6700 gen = PCPU_GET(pcid_gen);
6701 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN ||
6702 pmap->pm_pcids[cpuid].pm_gen == gen)
6703 return (CR3_PCID_SAVE);
6704 pcid_next = PCPU_GET(pcid_next);
6705 KASSERT(pcid_next <= PMAP_PCID_OVERMAX, ("cpu %d pcid_next %#x",
6707 if (pcid_next == PMAP_PCID_OVERMAX) {
6711 PCPU_SET(pcid_gen, new_gen);
6712 pcid_next = PMAP_PCID_KERN + 1;
6716 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
6717 pmap->pm_pcids[cpuid].pm_gen = new_gen;
6718 PCPU_SET(pcid_next, pcid_next + 1);
6723 pmap_activate_sw(struct thread *td)
6725 pmap_t oldpmap, pmap;
6726 uint64_t cached, cr3;
6729 oldpmap = PCPU_GET(curpmap);
6730 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6731 if (oldpmap == pmap)
6733 cpuid = PCPU_GET(cpuid);
6735 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6737 CPU_SET(cpuid, &pmap->pm_active);
6740 if (pmap_pcid_enabled) {
6741 cached = pmap_pcid_alloc(pmap, cpuid);
6742 KASSERT(pmap->pm_pcids[cpuid].pm_pcid >= 0 &&
6743 pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
6744 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
6745 pmap->pm_pcids[cpuid].pm_pcid));
6746 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
6747 pmap == kernel_pmap,
6748 ("non-kernel pmap thread %p pmap %p cpu %d pcid %#x",
6749 td, pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
6750 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3) {
6751 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
6754 PCPU_INC(pm_save_cnt);
6756 } else if (cr3 != pmap->pm_cr3) {
6757 load_cr3(pmap->pm_cr3);
6759 PCPU_SET(curpmap, pmap);
6761 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6763 CPU_CLR(cpuid, &oldpmap->pm_active);
6768 pmap_activate(struct thread *td)
6772 pmap_activate_sw(td);
6777 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6782 * Increase the starting virtual address of the given mapping if a
6783 * different alignment might result in more superpage mappings.
6786 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6787 vm_offset_t *addr, vm_size_t size)
6789 vm_offset_t superpage_offset;
6793 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6794 offset += ptoa(object->pg_color);
6795 superpage_offset = offset & PDRMASK;
6796 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6797 (*addr & PDRMASK) == superpage_offset)
6799 if ((*addr & PDRMASK) < superpage_offset)
6800 *addr = (*addr & ~PDRMASK) + superpage_offset;
6802 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6806 static unsigned long num_dirty_emulations;
6807 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6808 &num_dirty_emulations, 0, NULL);
6810 static unsigned long num_accessed_emulations;
6811 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6812 &num_accessed_emulations, 0, NULL);
6814 static unsigned long num_superpage_accessed_emulations;
6815 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6816 &num_superpage_accessed_emulations, 0, NULL);
6818 static unsigned long ad_emulation_superpage_promotions;
6819 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6820 &ad_emulation_superpage_promotions, 0, NULL);
6821 #endif /* INVARIANTS */
6824 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6827 struct rwlock *lock;
6830 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6831 boolean_t pv_lists_locked;
6833 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6834 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6836 if (!pmap_emulate_ad_bits(pmap))
6839 PG_A = pmap_accessed_bit(pmap);
6840 PG_M = pmap_modified_bit(pmap);
6841 PG_V = pmap_valid_bit(pmap);
6842 PG_RW = pmap_rw_bit(pmap);
6846 pv_lists_locked = FALSE;
6850 pde = pmap_pde(pmap, va);
6851 if (pde == NULL || (*pde & PG_V) == 0)
6854 if ((*pde & PG_PS) != 0) {
6855 if (ftype == VM_PROT_READ) {
6857 atomic_add_long(&num_superpage_accessed_emulations, 1);
6865 pte = pmap_pde_to_pte(pde, va);
6866 if ((*pte & PG_V) == 0)
6869 if (ftype == VM_PROT_WRITE) {
6870 if ((*pte & PG_RW) == 0)
6873 * Set the modified and accessed bits simultaneously.
6875 * Intel EPT PTEs that do software emulation of A/D bits map
6876 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
6877 * An EPT misconfiguration is triggered if the PTE is writable
6878 * but not readable (WR=10). This is avoided by setting PG_A
6879 * and PG_M simultaneously.
6881 *pte |= PG_M | PG_A;
6886 /* try to promote the mapping */
6887 if (va < VM_MAXUSER_ADDRESS)
6888 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6892 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6894 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6895 pmap_ps_enabled(pmap) &&
6896 (m->flags & PG_FICTITIOUS) == 0 &&
6897 vm_reserv_level_iffullpop(m) == 0) {
6898 if (!pv_lists_locked) {
6899 pv_lists_locked = TRUE;
6900 if (!rw_try_rlock(&pvh_global_lock)) {
6902 rw_rlock(&pvh_global_lock);
6906 pmap_promote_pde(pmap, pde, va, &lock);
6908 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6912 if (ftype == VM_PROT_WRITE)
6913 atomic_add_long(&num_dirty_emulations, 1);
6915 atomic_add_long(&num_accessed_emulations, 1);
6917 rv = 0; /* success */
6921 if (pv_lists_locked)
6922 rw_runlock(&pvh_global_lock);
6928 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6933 pt_entry_t *pte, PG_V;
6937 PG_V = pmap_valid_bit(pmap);
6940 pml4 = pmap_pml4e(pmap, va);
6942 if ((*pml4 & PG_V) == 0)
6945 pdp = pmap_pml4e_to_pdpe(pml4, va);
6947 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6950 pde = pmap_pdpe_to_pde(pdp, va);
6952 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6955 pte = pmap_pde_to_pte(pde, va);
6964 * Get the kernel virtual address of a set of physical pages. If there are
6965 * physical addresses not covered by the DMAP perform a transient mapping
6966 * that will be removed when calling pmap_unmap_io_transient.
6968 * \param page The pages the caller wishes to obtain the virtual
6969 * address on the kernel memory map.
6970 * \param vaddr On return contains the kernel virtual memory address
6971 * of the pages passed in the page parameter.
6972 * \param count Number of pages passed in.
6973 * \param can_fault TRUE if the thread using the mapped pages can take
6974 * page faults, FALSE otherwise.
6976 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6977 * finished or FALSE otherwise.
6981 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6982 boolean_t can_fault)
6985 boolean_t needs_mapping;
6987 int cache_bits, error, i;
6990 * Allocate any KVA space that we need, this is done in a separate
6991 * loop to prevent calling vmem_alloc while pinned.
6993 needs_mapping = FALSE;
6994 for (i = 0; i < count; i++) {
6995 paddr = VM_PAGE_TO_PHYS(page[i]);
6996 if (__predict_false(paddr >= dmaplimit)) {
6997 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6998 M_BESTFIT | M_WAITOK, &vaddr[i]);
6999 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
7000 needs_mapping = TRUE;
7002 vaddr[i] = PHYS_TO_DMAP(paddr);
7006 /* Exit early if everything is covered by the DMAP */
7011 * NB: The sequence of updating a page table followed by accesses
7012 * to the corresponding pages used in the !DMAP case is subject to
7013 * the situation described in the "AMD64 Architecture Programmer's
7014 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
7015 * Coherency Considerations". Therefore, issuing the INVLPG right
7016 * after modifying the PTE bits is crucial.
7020 for (i = 0; i < count; i++) {
7021 paddr = VM_PAGE_TO_PHYS(page[i]);
7022 if (paddr >= dmaplimit) {
7025 * Slow path, since we can get page faults
7026 * while mappings are active don't pin the
7027 * thread to the CPU and instead add a global
7028 * mapping visible to all CPUs.
7030 pmap_qenter(vaddr[i], &page[i], 1);
7032 pte = vtopte(vaddr[i]);
7033 cache_bits = pmap_cache_bits(kernel_pmap,
7034 page[i]->md.pat_mode, 0);
7035 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
7042 return (needs_mapping);
7046 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
7047 boolean_t can_fault)
7054 for (i = 0; i < count; i++) {
7055 paddr = VM_PAGE_TO_PHYS(page[i]);
7056 if (paddr >= dmaplimit) {
7058 pmap_qremove(vaddr[i], 1);
7059 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
7065 pmap_quick_enter_page(vm_page_t m)
7069 paddr = VM_PAGE_TO_PHYS(m);
7070 if (paddr < dmaplimit)
7071 return (PHYS_TO_DMAP(paddr));
7072 mtx_lock_spin(&qframe_mtx);
7073 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
7074 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
7075 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
7080 pmap_quick_remove_page(vm_offset_t addr)
7085 pte_store(vtopte(qframe), 0);
7087 mtx_unlock_spin(&qframe_mtx);
7090 #include "opt_ddb.h"
7092 #include <ddb/ddb.h>
7094 DB_SHOW_COMMAND(pte, pmap_print_pte)
7100 pt_entry_t *pte, PG_V;
7104 va = (vm_offset_t)addr;
7105 pmap = PCPU_GET(curpmap); /* XXX */
7107 db_printf("show pte addr\n");
7110 PG_V = pmap_valid_bit(pmap);
7111 pml4 = pmap_pml4e(pmap, va);
7112 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
7113 if ((*pml4 & PG_V) == 0) {
7117 pdp = pmap_pml4e_to_pdpe(pml4, va);
7118 db_printf(" pdpe %#016lx", *pdp);
7119 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
7123 pde = pmap_pdpe_to_pde(pdp, va);
7124 db_printf(" pde %#016lx", *pde);
7125 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
7129 pte = pmap_pde_to_pte(pde, va);
7130 db_printf(" pte %#016lx\n", *pte);
7133 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
7138 a = (vm_paddr_t)addr;
7139 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
7141 db_printf("show phys2dmap addr\n");